CD74HCT574-Q1 TI | Alldatasheet
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/C0067/C0068/C0055/C0052/C0072/C0067/C0084/C0053/C0055/C0052/C0262/C0081/C0049 /C0072/C0073/C0071/C0072/C0262/C0083/C0080/C0069/C0069/C0068 /C0067/C0077/C0079/C0083 /C0076/C0079/C0071/C0073/C0067 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080 /C0051/C0262/C0083/C0084/C0065/C0084/C0069/C0044 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069 /C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 SCLS570 − FEBRUARY 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Qualification in Accordance With AEC-Q100 † /C0068Qualified for Automotive Applications /C0068Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval /C0068Buffered Inputs /C0068Common 3-State Output-Enable Control /C00683-State Outputs /C0068Bus-Line Driving Capability /C0068Typical Propagation Delay (Clock to Q): 15 ns at V CC = 5 V, CL = 15 pF, TA = 25/C0053C /C0068Fanout (Over Temperature Range) − Standard Outputs ... 1 0 LSTTL Loads − Bus Driver Outputs ... 1 5 LSTTL Loads /C0068Balanced Propagation Delay and Transition Times † Contact factory for details. Q100 qualification data available on request. /C0068Significant Power Reduction Compared to LSTTL Logic ICs /C0068VCC Voltage = 4.5 V to 5.5 V /C0068Direct LSTTL Input Logic Compatibility, V IL = 0.8 V (Max), VIH = 2 V (Min) /C0068CMOS Input Compatibility, Il /C0118 1 /C0109A at VOL , VOH description/ordering information The CD74HCT574 is an octal D-type flip-flop with 3-state outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered flip-flops enter data into their registers on the low-to-high transition of the clock (CP). The output enable (OE ) controls the 3-state outputs and is independent of the register operation. When OE is high, the outputs are in the high-impedance state.
ORDERING INFORMATION
TA PACKAGE ‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 125°C SOIC − M Tape and reel CD74HCT574QM96Q1 HCT574Q −40°C to 125°C TSSOP − PW Tape and reel CD74HCT574QPWRQ1 HCT574Q ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2004, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. M OR PW PACKAGE (TOP VIEW) OE GND V CC CP
/C0067/C0068/C0055/C0052/C0072/C0067/C0084/C0053/C0055/C0052/C0262/C0081/C0049 /C0072/C0073/C0071/C0072/C0262/C0083/C0080/C0069/C0069/C0068 /C0067/C0077/C0079/C0083 /C0076/C0079/C0071/C0073/C0067 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080 /C0051/C0262/C0083/C0084/C0065/C0084/C0069/C0044 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069 /C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 SCLS570 − FEBRUARY 2004
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Q L ↑ H H L ↑ L L L L X Q 0 H X X Z NOTE: H = High voltage level (steady state) L = Low voltage level (steady state) X = Don’t care ↑ = Transition from low to high level Q 0 = Level before the indicated steady-state conditions were established Z = High-impedance state logic diagram (positive logic) CP D CP D CP D CP D CP D CP D CP D CP D CP D 2D 1 D 4D 3 D 5 D 6 D 7D 0 Q 1Q 0 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 QQQQQQQQ OE
/C0067/C0068/C0055/C0052/C0072/C0067/C0084/C0053/C0055/C0052/C0262/C0081/C0049 /C0072/C0073/C0071/C0072/C0262/C0083/C0080/C0069/C0069/C0068 /C0067/C0077/C0079/C0083 /C0076/C0079/C0071/C0073/C0067 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080 /C0051/C0262/C0083/C0084/C0065/C0084/C0069/C0044 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069 /C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 SCLS570 − FEBRUARY 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Lead temperature (during soldering): † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages referenced to GND unless otherwise specified. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 4.5 5.5 V VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 V VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 2 V 0 1000 tt Input transition (rise and fall) time VCC = 4.5 V 0 500 nstt Input transition (rise and fall) time VCC = 6 V 0 400 ns TA Operating free-air temperature −40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
/C0067/C0068/C0055/C0052/C0072/C0067/C0084/C0053/C0055/C0052/C0262/C0081/C0049 /C0072/C0073/C0071/C0072/C0262/C0083/C0080/C0069/C0069/C0068 /C0067/C0077/C0079/C0083 /C0076/C0079/C0071/C0073/C0067 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080 /C0051/C0262/C0083/C0084/C0065/C0084/C0069/C0044 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069 /C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 SCLS570 − FEBRUARY 2004
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IO (mA) VCC TA = 25°C TA = −40°C TO 125°C UNITPARAMETER TEST CONDITIONS O (mA) VCC MIN TYP MAX MIN MAX UNIT VOH VI = VIH or VIL CMOS loads −0.02 4.5 V 4.4 4.4 VVOH VI = VIH or VIL TTL loads −6 4.5 V 3.98 3.7 V VOL VI = VIH or VIL CMOS loads 0.02 4.5 V 0.1 0.1 VVOL VI = VIH or VIL TTL loads 6 4.5 V 0.26 0.4 V II VI = VCC or GND 0 5.5 V ±0.1 ±1 µA IOZ VI = VIL or VIH, VO = VCC or GND 6 V ±0.5 ±10 µA ICC VI = VCC or GND 0 5.5 V 8 160 µA ∆ICC VI = VCC − 2.1 V, See Note 4 4.5 V to 5.5 V 100 360 490 µA C IN C L = 50 pF 10 10 pF C OUT 3-state 20 20 pF NOTE 4: For dual-supply systems, theoretical worst-case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. HCT input loading TYPE INPUT UNIT LOADS † D0−D7 0.4 ’574 CP 0.75’574 OE 0.6 † Unit load is ∆ICC limit specified in electrical characteristics table, e.g., 360 µA max at 25°C. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER VCC TA = 25°C TA = −40°C TO 125°C UNITPARAMETER VCC MIN MAX MIN MAX UNIT fmax Maximum clock frequency 4.5 V 30 20 MHz tw Clock pulse duration 4.5 V 16 24 ns tsu Setup time, data before clock↑ 4.5 V 12 18 ns th Hold time, data after clock↑ 4.5 V 5 5 ns
/C0067/C0068/C0055/C0052/C0072/C0067/C0084/C0053/C0055/C0052/C0262/C0081/C0049 /C0072/C0073/C0071/C0072/C0262/C0083/C0080/C0069/C0069/C0068 /C0067/C0077/C0079/C0083 /C0076/C0079/C0071/C0073/C0067 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080 /C0051/C0262/C0083/C0084/C0065/C0084/C0069/C0044 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069 /C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 SCLS570 − FEBRUARY 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE VCC TA = 25°C TA = −40°C TO 125°C UNITPARAMETER (INPUT) (OUTPUT) CAPACITANCE VCC MIN TYP MAX MIN MAX UNIT tpd CP Q C L = 50 pF 4.5 V 33 50 nstpd CP Q C L = 15 pF 5 V 15 ns tdis OE Q C L = 50 pF 4.5 V 28 42 nstdis OE Q C L = 15 pF 5 V 11 ns ten OE Q C L = 50 pF 4.5 V 30 45 nsten OE Q C L = 15 pF 5 V 12 ns tt Q C L = 50 pF 4.5 V 12 18 ns fmax CP C L = 15 pF 5 V 60 MHz operating characteristics, VCC = 5 V, TA = 25°C, input tr, tf = 6 ns PARAMETER TYP UNIT C pd Power dissipation capacitance (see Note 5) 47 pF NOTE 5: C pd is used to determine the dynamic power consumption (PD ), per package. PD = (CPD × VCC 2 × fI) + Σ (CL × VCC 2 × fO ) fI = input frequency fO = output frequency C L = output load capacitance VCC = supply voltage
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1.3 V 10%
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. F. tPLH and tPHL are the same as tpd. G. tPLZ and tPHZ are the same as tdis. H. tPZH and tPZL are the same as ten. Figure 1. Load Circuit and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CD74HCT574QM96Q1 ACTIVE SOIC DW 20 2000 TBD CU NIPDAU Level-1-235C-UNLIM CD74HCT574QPWRQ1 ACTIVE TSSOP PW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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