HCSXXX

HCSXXX MICROCHIP | Alldatasheet

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 2004 Microchip Technology Inc. Preliminary DS41256A-page 1 HCSXXX This document includes the programming specifications for the following devices:

1.0 PROGRAMMING THE HCSXXX

All of the KEE LOQ ® devices are programmed using a serial method. This Serial mode allows KEE LOQ devices to be programmed while in users' systems, which increases the flexibility of designing cryptographic encoders, decoders and transponders into electronic systems. While some of the devices are capable of being programmed through wireless communications, the subject of this document is focused on wired programmers that make contact with the K EE LOQ products while the components are in- circuit or in a programmer socket. Additionally, this programming specification only applies to all KEE LOQ devices listed above in all packages.

1.1 Programming Algorithm

Depending on the device being programmed, the method for entering Programming mode can be achieved through the use of a combination of logic level signals applied to the programming pins. One or two pins are capable of accepting clock signals, while another pin is dedicated to bidirectional data. These pins are detailed in Table 1-1. Additionally, the programming voltage range for V DD is +5V ± 10% for all the KEE LOQ devices. There is not a requirement to apply high voltages to any of the pins beyond the level of VDD in order to enter the Programming mode. For more details about pin configurations during programming, refer to Table 1-1.

1.2 Program/Verify Mode

The Program/Verify mode for the KEE LOQ devices allows programming for all memory locations within the device being programmed. With the exception of the decoders, these pins are also used to verify the memory arrays.  HCS200  HCS360  HCS500  HCS201  HCS361  HCS512  HCS300  HCS362  HCS515  HCS301  HCS410  HCS320  HCS412Note: For the purpose of this document, “KEE LOQ devices” and “KEE LOQ products” refers to all of the components listed above. HCSXXX Memory Programming Specification

DS41256A-page 2 Preliminary  2004 Microchip Technology Inc. Pin Diagrams NC VDD NC PWM VSS PDIP, SOIC HCS200 SHIFT VDD LED PWM VSS HCS320 VDDB VDD STEP DATA VSS HCS201 VDD LED PWM VSS HCS300/301 VDD LED DATA VSS HCS360/361 S3/RFEN VDD LED /SHIFT DATA VSS HCS362 S2/LED LC1 VDD LC0 PWM GND HCS410 S2/RFEN/LC1 LC0 VDD LED DATA GND HCS412 VDD EE_CLK EE_DAT MCLR VSS RFIN S_CLK S_DAT HCS500

 2004 Microchip Technology Inc. Preliminary DS41256A-page 3 HCSXXX Pin Diagrams (Continued) NC NC VDD NC NC HCS5155 MCLR NC VSS RF_IN S_CLK S_DAT NC HCS512 PDIP , SOIC LRNIN LRNOUT NC MCLR GND RFIN NC OSCIN OSC OUT VDD DATA CLK SLEEP V LOW S2/LED LC1 GND PWM VDD LC0 HCS410 S3/RFEN VSS DATA VDD LED /SHIFT HCS362 TSSOP

DS41256A-page 4 Preliminary  2004 Microchip Technology Inc. TABLE 1-1: PIN DESCRIPTIONS (DURING PROGRAMMING) Device Pin Number CommentsPower Supply Ground Clock Data Other HCS200 8 5 3 6 — HCS201 8 5 3 6 — (Notes 1) HCS300 8 5 3, 4 6 — (Notes 2) HCS301 8 5 3, 4 6 — (Notes 2) HCS320 8 5 3 6 — (Notes 2) HCS360 8 5 3, 4 6 2 (Notes 2) HCS361 8 5 3, 4 6 2 (Notes 2) HCS362 8 5 3, 4 6 — (Notes 2) HCS410 8 5 3 6 — HCS412 8 5 3 6 — (Note 1) HCS500 1 8 6 5 — (Notes 2, 3, 4, 7, 8) HCS512 14 5 12 13 4 (Notes 5, 6, 8, 9) HCS515 3 12 10 9 — (Notes 7, 8) Note 1: Sends calibration pulse during ACK periods. 2: VDD pin must be driven low after a Program/Verify cycle. 3: In-circuit programming recommended. 4: Used in conjunction with a Microchip Technology 24LC02B device. 5: MCLR , pin 4, is used to enter Program mode. 6: Must apply external clock source to OSCIN while programming. 7: Requires command byte preceding data packet. 8: Verify function not available. 9: Uses checksum in data packet.

 2004 Microchip Technology Inc. Preliminary DS41256A-page 5 HCSXXX

2.0 MEMORY MAPPING

The program memory maps for KEE LOQ products begin at 0x000 and extend as shown in the tables that follow. As a device is being programmed, the address counter automatically increments to the next word location after receiving a data word. The memory maps for all K EE LOQ encoders and transponders were designed so that each word is 16 bits wide. Decoder memory maps are 8 bits wide.

2.1 Encoder Memory Maps

TABLE 2-1: HCS200 12 X 16-BIT EEPROM MEMORY MAP TABLE 2-2: HCS201 12 X 16-BIT EEPROM MEMORY MAP Word Address Mnemonic Description 0x00 KEY_0 Word 0 (LSb's) of 64-bit crypt key 0x01 KEY_1 Word 1 of 64-bit crypt key 0x02 KEY_2 Word 2 of 64-bit crypt key 0x03 KEY_3 Word 3 (MSb's) of 64-bit crypt key 0x04 SYNC 16-bit synchronization value 0x05 Reserved Set to 0x0000 0x06 SER_0 Word 0 (LSb's) of 32-bit serial number 0x07 SER_1 Word 1 (MSb's) of 32-bit serial number 0x08 SEED_0 Word 0 (LSb's) of 32-bit seed value 0x09 SEED_1 Word 1 (MSb's) of 32-bit seed value 0x0A Reserved Set to 0x0000 0x0B CONFIG Configuration Word Word Address Mnemonic Description 0x00 KEY_0 Word 0 (LSb's) of 64-bit crypt key 0x01 KEY_1 Word 1 of 64-bit crypt key 0x02 KEY_2 Word 2 of 64-bit crypt key 0x03 KEY_3 Word 3 (MSb's) of 64-bit crypt key 0x04 SYNC 16-bit synchronization value 0x05 Reserved Set to 0x0000 0x06 SER_0 Word 0 (LSb's) of 32-bit serial number 0x07 SER_1 Word 1 (MSb's) of 32-bit serial number 0x08 SEED_0 Word 0 (LSb's) of 32-bit seed value 0x09 SEED_1 Word 1 (MSb's) of 32-bit seed value 0x0A DISC Discrimination Word 0x0B CONFIG Configuration Word

DS41256A-page 6 Preliminary  2004 Microchip Technology Inc. TABLE 2-3: HCS300 12 X 16-BIT EEPROM MEMORY MAP TABLE 2-4: HCS301 12 X 16-BIT EEPROM MEMORY MAP TABLE 2-5: HCS320 12 X 16-BIT EEPROM MEMORY MAP Word Address Mnemonic Description 0x00 KEY_0 Word 0 (LSb's) of 64-bit crypt key 0x01 KEY_1 Word 1 of 64-bit crypt key 0x02 KEY_2 Word 2 of 64-bit crypt key 0x03 KEY_3 Word 3 (MSb's) of 64-bit crypt key 0x04 SYNC 16-bit synchronization value 0x05 Reserved Set to 0x0000 0x06 SER_0 Word 0 (LSb's) of 32-bit serial number 0x07 SER_1 (1) Word 1 (MSb's) of 32-bit serial number 0x08 SEED_0 Word 0 (LSb's) of 32-bit seed value 0x09 SEED_1 Word 1 (MSb's) of 32-bit seed value 0x0A Reserved Set to 0x0000 0x0B CONFIG Configuration Word Note 1: MSb of this word is used for auto-shutoff timer. Word Address Mnemonic Description 0x00 KEY_0 Word 0 (LSb's) of 64-bit crypt key 0x01 KEY_1 Word 1 of 64-bit crypt key 0x02 KEY_2 Word 2 of 64-bit crypt key 0x03 KEY_3 Word 3 (MSb's) of 64-bit crypt key 0x04 SYNC 16-bit synchronization value 0x05 Reserved Set to 0x0000 0x06 SER_0 Word 0 (LSb's) of 32-bit serial number 0x07 SER_1 (1) Word 1 (MSb's) of 32-bit serial number 0x08 SEED_0 Word 0 (LSb's) of 32-bit seed value 0x09 SEED_1 Word 1 (MSb's) of 32-bit seed value 0x0A Reserved Set to 0x0000 0x0B CONFIG Configuration Word Note 1: MSb of this word is used for auto-shutoff timer. Word Address Mnemonic Description 0x00 KEY_0 Word 0 (LSb's) of 64-bit crypt key 0x01 KEY_1 Word 1 of 64-bit crypt key 0x02 KEY_2 Word 2 of 64-bit crypt key 0x03 KEY_3 Word 3 (MSb's) of 64-bit crypt key 0x04 SYNC 16-bit synchronization value 0x05 Reserved Set to 0x0000 0x06 SER_0 Word 0 (LSb's) of 32-bit serial number 0x07 SER_1 (1) Word 1 (MSb's) of 32-bit serial number 0x08 — Not used 0x09 — Not used 0x0A Reserved Set to 0x0000 0x0B CONFIG Configuration Word Note 1: MSb of this word is used for auto-shutoff timer.

 2004 Microchip Technology Inc. Preliminary DS41256A-page 7 HCSXXX TABLE 2-6: HCS360 12 X 16-BIT EEPROM MEMORY MAP TABLE 2-7: HCS361 12 X 16-BIT EEPROM MEMORY MAP Word Address Mnemonic Description 0x00 KEY_0 Word 0 (LSb's) of 64-bit crypt key 0x01 KEY_1 Word 1 of 64-bit crypt key 0x02 KEY_2 Word 2 of 64-bit crypt key 0x03 KEY_3 Word 3 (MSb's) of 64-bit crypt key 0x04 SYNC_A 16-bit synchronization value A 0x05 SYNC_B 16-bit synchronization value B or Seed Value (Word 2) 0x06 Reserved Set to 0x0000 0x07 SEED_0 Word 0 (LSb's) of 32-bit seed value 0x08 SEED_1 Word 1 (MSb's) of 32-bit seed value 0x09 SER_0 Word 0 (LSb's) of 32-bit serial number 0x0A SER_1 Word 1 (MSb's) of 32-bit serial number 0x0B CONFIG Configuration Word Word Address Mnemonic Description 0x00 KEY_0 Word 0 (LSb's) of 64-bit crypt key 0x01 KEY_1 Word 1 of 64-bit crypt key 0x02 KEY_2 Word 2 of 64-bit crypt key 0x03 KEY_3 Word 3 (MSb's) of 64-bit crypt key 0x04 SYNC_A 16-bit synchronization value A 0x05 SYNC_B/SEED_2 16-bit synchronization value B or Seed Value (Word 2) 0x06 Reserved Set to 0x0000 0x07 SEED_0 Word 0 (LSb's) of 32-bit seed value 0x08 SEED_1 Word 1 (MSb's) of 32-bit seed value 0x09 SER_0 Word 0 (LSb's) of 32-bit serial number 0x0A SER_1 Word 1 (MSb's) of 32-bit serial number 0x0B CONFIG Configuration Word

DS41256A-page 8 Preliminary  2004 Microchip Technology Inc. TABLE 2-8: HCS362 18 X 16-BIT EEPROM MEMORY MAP TABLE 2-9: HCS500 9 X 8-BIT EEPROM MEMORY MAP TABLE 2-10: HCS512 10 X 8-BIT EEPROM MEMORY MAP Word Address Mnemonic Description 0x00 KEY1_0 Word 0 (LSb's) of 64-bit crypt key 1 0x01 KEY1_1 Word 1 of 64-bit crypt key 1 0x02 KEY1_2 Word 2 of 64-bit crypt key 1 0x03 KEY1_3 Word 3 (MSb's) of 64-bit crypt key 1 0x04 KEY2_0 Word 0 (LSb's) of 64-bit crypt key 2 0x05 KEY2_1 Word 1 of 64-bit crypt key 2 0x06 KEY2_2 Word 2 of 64-bit crypt key 2 0x07 KEY2_3 Word 3 (MSb's) of 64-bit crypt key 2 0x08 SEED_0 Word 0 (LSb's) of 64-bit seed value 0x09 SEED_1 Word 1 of 64-bit seed value 0x0A SEED_2 Word 2 of 64-bit seed value 0x0B SEED_3 Word 3 (MSb's) of 64-bit seed value 0x0C CONFIG_0 Configuration Word (LSb's) 0x0D CONFIG_1 Configuration Word (MSb's) 0x0E SERIAL_0 Word 0 (LSb's) of 32-bit serial number 0x0F SERIAL_0 Word 1 (MSb's) of 32-bit serial number 0x10 SYNC 16-bit synchronization value 0x11 Reserved Set to 0x0000 Word Address Mnemonic Description 0x00 CONFIG Configuration Word 0x01 KEY0 Byte 0 (LSb’s) of 64-bit manufacturer key 0x02 KEY1 Byte 1 of 64-bit manufacturer key 0x03 KEY2 Byte 2 of 64-bit manufacturer key 0x04 KEY3 Byte 3 of 64-bit manufacturer key 0x05 KEY4 Byte 4 of 64-bit manufacturer key 0x06 KEY5 Byte 5 of 64-bit manufacturer key 0x07 KEY6 Byte 6 of 64-bit manufacturer key 0x08 KEY7 Byte 7 (MSb’s) of 64-bit manufacturer key Word Address Mnemonic Description 0x00 KEY0 Byte 0 (LSb’s) of 64-bit manufacturer key 0x01 KEY1 Byte 1 of 64-bit manufacturer key 0x02 KEY2 Byte 2 of 64-bit manufacturer key 0x03 KEY3 Byte 3 of 64-bit manufacturer key 0x04 KEY4 Byte 4 of 64-bit manufacturer key 0x05 KEY5 Byte 5 of 64-bit manufacturer key 0x06 KEY6 Byte 6 of 64-bit manufacturer key 0x07 KEY7 Byte 7 (MSb’s) of 64-bit manufacturer key 0x08 CONFIG Configuration byte 0x09 Checksum Checksum byte

 2004 Microchip Technology Inc. Preliminary DS41256A-page 9 HCSXXX TABLE 2-11: HCS515 9 X 8-BIT EEPROM MEMORY MAP

2.2 Transponder Memory Maps

TABLE 2-12: HCS410 16 X 16-BIT EEPROM MEMORY MAP Word Address Mnemonic Description 0x00 CONFIG Configuration byte 0x01 KEY0 Byte 0 (LSb’s) of 64-bit manufacturer key 0x02 KEY1 Byte 1 of 64-bit manufacturer key 0x03 KEY2 Byte 2 of 64-bit manufacturer key 0x04 KEY3 Byte 3 of 64-bit manufacturer key 0x05 KEY4 Byte 4 of 64-bit manufacturer key 0x06 KEY5 Byte 5 of 64-bit manufacturer key 0x07 KEY6 Byte 6 of 64-bit manufacturer key 0x08 KEY7 Byte 7 (MSb’s) of 64-bit manufacturer key Word Address Mnemonic Description 0x00 KEY_0 Word 0 (LSb's) of 64-bit crypt key 0x01 KEY_1 Word 1 of 64-bit crypt key 0x02 KEY_2 Word 2 of 64-bit crypt key 0x03 KEY_3 Word 3 (MSb's) of 64-bit crypt key 0x04 DISC Ext. Config. Word/10-bit Discriminator 0x05 CONFIG 16-bit Configuration Word 0x06 SER_0 Word 0 (LSb's) of 32-bit serial number 0x07 SER_1 Word 1 (MSb's) of 32-bit serial number 0x08 SEED_0 Word 0 (LSb's) of 64-bit seed value 0x09 SEED_1 Word 1 of 64-bit seed value 0x0A SEED_2 Word 2 of 64-bit seed value 0x0B SEED_3 Word 3 (MSb's) of 64-bit seed value 0x0C USR_0 Word 0 (LSb's) of 64-bit user area 0x0D USR_1 Word 1 of 64-bit user area 0x0E USR_2 Word 2 of 64-bit user area 0x0F USR_3 Word 3 (MSb's) of 64-bit user area SYNC

DS41256A-page 10 Preliminary  2004 Microchip Technology Inc. TABLE 2-13: HCS412 18 X 16-BIT EEPROM MEMORY MAP

2.3 Entering Program Mode

Entering the Program/Verify mode will be dependent upon the type of device in use. Most KEE LOQ devices use a serial clock and bidirectional data line to access the chips' memory maps. In order to enter the Programming mode, a Start condition is sent to the target device, where the clock and data lines must be held high and low for specified periods of time. That is, all lines are held low while the clock line is driven high. After a short delay, the data line is driven high. At this point, both lines must remain high for another delay period prior to dropping back to ground. After dropping both lines low and providing another delay, the state machine for the K EE LOQ device will enter the Programming mode and begin to wait for data, or depending on the component, a bulk erase is performed on the memory array. For the HCS360 and HCS361 devices, the Programming mode is entered by providing a clock source on the clock line and a Start pulse on the data line, as described in the previous paragraph. However, the difference is with driving the S1 pin, as shown in Figure 5-5. Bit 0 of the data packet must be driven on the S1 pin and kept at that level throughout the programming cycles and through verification. The HCS512 is another device that does not conform to the 2-wire protocol described above. For this device, the MCLR pin is driven high while data is held low. After the minimum setup time has been realized, the clock pin is driven high and then low for a minimum amount of time in order to send the HCS512 a Start condition and complete the Entry mode for the next programming sequence. The associated waveform is detailed in Section 5.0 “Program/Verify Mode Electrical Characteristics”. The HCS512 is also the only device that requires a checksum be sent to the target device while it is being programmed. See the Checksum Section in the HCS512 Data Sheet, “K EE LOQ ® Code Hopping Decoder“ (DS40151), for details on calculating the checksum. Word Address Mnemonic Description 0x00 KEY0 Word 0 (LSb’s) of 64-bit crypt key 1 0x01 KEY1 Word 1 of 64-bit crypt key 1 0x02 KEY2 Word 2 of 64-bit crypt key 1 0x03 KEY3 Word 3 (MSb’s) of 64-bit crypt key 1 0x04 SEED0 Word 0 (LSb’s) of 60-bit seed value 0x05 SEED1 Word 1 of 60-bit seed value 0x06 SEED2 Word 2 of 60-bit seed value 0x07 CFG/SEED3 Word 3 of 60-bit seed value/Configuration in top nibble 0x08 CONFIG1 Configuration Word 1 (security options) 0x09 CONFIG2 Configuration Word 2 0x0A SER0 Word 0 (LSb’s) of 32-bit serial number 0x0B SER1 Word 1 (MSb’s) of 32-bit serial number 0x0C USR0 Word 0 (LSb’s) of 64-bit user area 0x0D USR1 Word 1 of 64-bit user area 0x0E USR2 Word 2 of 64-bit user area 0x0F USR3 Word 3 (MSb’s) of 64-bit user area Note: The HCS512 requires an external clock signal for the OSCIN pin. This signal is necessary throughout the Programming mode.

 2004 Microchip Technology Inc. Preliminary DS41256A-page 11 HCSXXX

2.4 Bulk Write Device

All transponders and encoders are bulk erased and programmed with zeros following the Start condition. The bulk erase/write time frame is specified as T PBW , which is minimally 4.0 ms. After the bulk function is complete, the programming state machine continues into the Program mode where it begins to wait for data and clock signals.

2.5 Serial Program/Verify Operation

For all of the encoders and transponders, the memory maps have been designed to be in 16-bit format, which means that each address location contains 16 bits of information including “don't care” bits that are read as zeros. Details relating to the designated pins for clock and data signals are outlined in Table 1-1. The decoders, on the other hand, were designed with memory maps in 8-bit format, so they are discussed separately in the next couple of paragraphs. For specific information relating to the size of the memory maps for a given family of devices, be sure to review the tables in Section 2.1 “Encoder Memory Maps” . The following paragraphs were written with the assumption that the target device has been placed into the Programming mode and is now waiting for data or a command byte to continue programming the memory array.

2.5.1 ENCODERS/TRANSPONDERS

To input data to the target KEE LOQ encoder or transponder, 16 clock cycles are applied to the clock pin of the target device while data is driven into the data pin. Data is clocked into the target device on the falling edge of the clock signal. Also, the minimum high time and low time for the clock signals are 50µs. During verification, data must be sampled on the rising edge of the clock.

2.5.2 DECODERS

To input data to the target KEE LOQ decoder, 8 clock cycles are applied to the clock pin of the target device while data is driven into the data pin. Data is clocked into the target device on the falling edge of the clock signals. Also, the minimum high time and minimum low time for the clock signals are 50µs. For the decoder family, there are no verification functions.

2.6 Begin Programming

Write cycles are performed a bit-at-a-time throughout the entire programming sequence for K EE LOQ products. The total write cycle, which includes internal processing and programming time, is specified to take a minimum of 50 ms. As a result, programmers can include a delay for the minimum write cycle time or they can poll the target device as discussed in Section 2.7 “Polling Write Cycle”.

2.7 Polling Write Cycle

2.7.1 HCS201 AND HCS412

Once the 16th clock cycle for the data word has been generated and the next minimum low time for the clock passes, the clock pin can be driven high to poll the completion of the write cycle. Before the write cycle is complete, the data pin for the target K EE LOQ device will be low. After the write cycle is complete, the data pin on the HCS201 and the HCS412 will begin to provide pulses to the programmer in order to signal the completion of the write cycle. As a result, the programmer data pin should be set to high-impedance (input) so that it can read the pulses. After reading the pulses on the data pin, the programmer should drive the clock pin low and make the data pin an output so that data can continue to be driven into the target device. These pulses can be used for calibration sequences for the HCS201 and the HCS412. For information relating to oscillator calibration refer to Section 5.0 “Program/Verify Mode Electrical Characteristics”, which discusses oscillator tuning. If the programmer polls the target device for the end of a write cycle, these two devices will continue to emit calibration pulses until their clock lines are driven low. In order to measure the calibration pulses, the clock pin must be driven high prior to the end of the write cycle, otherwise the calibration pulses will not appear.

2.7.2 ALL OTHER K EE LOQ DEVICES

Once the 16th clock cycle for the data word has been generated for any of the encoders or transponders or the last clock cycle for a decoder data packet is generated, the clock pin can be driven high to poll for the completion of the write cycle. Before the write cycle is complete, the data pin for the target K EE LOQ device will be low. As a result, the programmer data pin should be set to high-impedance (input) so that it can sense the rising edge of data. After the write cycle is complete, the data pin will be driven high until the clock line is driven low again.

DS41256A-page 12 Preliminary  2004 Microchip Technology Inc.

2.8 Verify Mode

In terms of verify operations, all KEE LOQ encoders and transponders incorporate a security feature that only allows one verify operation to be completed, and it must be completed at the end of the programming sequence before exiting the Programming mode. When implementing polling routines to sense the end of the last write cycle and after driving the clock line low, the programmer can begin to read data by continuing to provide clock cycles to the target device. Note that there is not an Acknowledge bit from K EE LOQ devices during the Verify mode. In the case where the programmer provides a time delay to allow for write cycle completion, the programmer can provide clock cycles after the delay to begin reading data.

3.0 CONFIGURATION WORD

For detailed descriptions of bit functions for the configuration words of the KEE LOQ devices, be sure to download the latest Data Sheet for the respective device from the Microchip Technology web site (www.microchip.com). Configuration word architectures are also shown earlier in Section 2.0 “Memory Mapping”.

4.0 OSCILLATOR TUNING

Calibrating the oscillator of select devices can be completed a number of ways. For the purpose of this document, calibration will be completed using the Two- Point Calibration Algorithm, which is described in EE LOQ ® Encoders Oscillator Calibration” (DS00824). The algorithm is as follows:  OSCCAL = -8  Program target device  Measure oscillator frequency F HIGH  OSCCAL = +7  Program target device  Measure oscillator frequency F LOW  Interpolate: - OSCCAL = 16*(FIDEAL - FLOW )/(FHIGH - FLOW )  Program target device For a better understanding of how to implement this algorithm, the following flow charts are being provided: Note: Decoders do not incorporate a verify function.

 2004 Microchip Technology Inc. Preliminary DS41256A-page 13 HCSXXX FIGURE 4-1: HCS201 AND HCS412 OSCILLATOR TUNING Preload Datastream with 0x7 for OSCCAL(1) Preload Datastream with 400 µs Time Element Program Target Reset Target(2) Preload Datastream with 0x8 for OSCCAL(1) Preload Datastream with 400 µs Time Element Program First Word of Target Poll Target for End of Write Cycle Measure Calibration Pulses as Time Elements Store Average Value as FLOW Measure Calibration Pulses as Time Elements Poll Target for End of Write Cycle Program First Word of Target Reset Target(2) Program Remaining Target Store Average Value as FHIGH Reset Target(2) Preload Datastream with Interpolated OSCCAL Interpolate OSCCAL Preload Desired Baud Rate Program Target Note 1: -8d = 0x7, and +7d = 0x8 2: Cycle Power

DS41256A-page 14 Preliminary  2004 Microchip Technology Inc. FIGURE 4-2: HCS362 AND HCS410 OSCILLATOR TUNING Preload Datastream with 0x7 for OSCCAL(1) Preload Datastream with 400 µs Time Element Program Target Reset Target(2) Activate Button Input on Target Measure Preamble Time Elements Store Average Value as F HIGH Reset Target(2) Store Average Value as FLOW Measure Preamble Time Elements Activate Button Input on Target Reset Target(2) Preload Datastream With 400 µs Time Element Preload Datastream Preload Datastream with Interpolated OSCCAL Interpolate OSCCAL Preload Desired Baud Rate Program Target Note 1: -8d = 0x7, and +7d = 0x8 2: Cycle Power Device Program Target Device With 0x8 for OSCCAL

 2004 Microchip Technology Inc. Preliminary DS41256A-page 15 HCSXXX KEE LOQ devices that are capable of oscillator tuning include the HCS201, HCS362, HCS410 and the HCS412. Though, only the HCS201 and HCS412 transmit calibration pulses when polling the chips at the end of write cycles. The other two devices must be tuned according to the preamble pulses that they transmit at the beginning of a data packet. For the best accuracy, use multiple time elements to achieve an average time element value. Typically, a number that is a power of 2 n is used in order to simplify the resultant quotient (i.e., 4 or 8). In order to obtain the most accurate time element measurement, the widest possible baud rate should be chosen. For simplifying the two flow diagrams below, a common time element was chosen to the devices that share algorithms. The HCS362 and the HCS410 oscillator tuning register can also be tuned as shown in the algorithm above, but with the caveat that after the device is programmed, the programmer must activate the target device in order to measure the time element in the communication preamble. A typical preamble is shown in Figure 4-3. FIGURE 4-3: PWM CODE WORD TRANSMISSION TIMINGS Preamble = 23 TE Header = 10 TE bit 0 bit 1 TETE TE TE TE

DS41256A-page 16 Preliminary  2004 Microchip Technology Inc.

4.1 Programming Flow Charts

FIGURE 4-4: PROGRAMMING FLOW CHART 1 FIGURE 4-5: PROGRAMMING FLOW CHART 2 Set VDD = All LocationsNo Yes Start 5.0V ± 10% Send Start Sequence Device Bulk Erase Load 16-Bits of Data Wait TWC or Poll Rising Pulse Programmed? Begin Verify Read 16-Bits of Data All Locations Verified? Program/Verify Complete No Yes Note: Applies to HCS200, HCS201, HCS300, HCS301, HCS320, HCS362, HCS410 and HCS412 only. Set VDD = All LocationsNo Yes Start 5.0V ± 10% Send Start Sequence Wait TWC or Poll Calibration Pulse Programmed? Begin Verify Read 16-Bits of Data All Locations Verified? Program/Verify Complete No Yes Note: Applies to HCS360 and HCS361 only. If Data Bit 0 = 0 Then S1 = 0 Else S1 = 1 Load 16 Bits of Data (LSb first) Complemented Data Load 16 Bits of (LSb first)

DS41256A-page 18 Preliminary  2004 Microchip Technology Inc.

5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS

5.1 Timing Requirements for Program/Verify Mode – Encoders

Standard Operating Conditions (unless otherwise stated) Operating Temperature +25°C ± 5°C Operating Voltage 4.5V ≤ V DD ≤ 5.5V Sym Characteristics Min Max Units Conditions/Comments HCS200, HCS300, HCS301, HCS320 and HCS362 TCLKH Clock high time 50 — µs TCLKL Clock low time 50 — µs TDH Data hold time 30 — µs TDS Data setup time 0 — µs TDV Data out valid time — 30 µs TPBW Bulk Write time 4.0 — ms TPH 1 Hold Time 1 3.5 — ms TPH 2 Hold Time 2 50 — µs TPROG Program delay time 4.0 — ms TPS Program mode setup time 3.5 4.5 ms TWC Program cycle time 50 — ms HCS201 T ACKH Data out valid time 800 — µs TACKL Data hold time 800 — µs TCLKH Clock high time 50 — µs TCLKL Clock low time 50 — µs TDH Data hold time 18 — µs TDS Data setup time 0 — µs TDV Data out valid time — 30 µs TPBW Bulk Write time 4.0 — ms TPH 1 Hold Time 1 4.0 — ms TPH 2 Hold Time 2 50 — µs TPHOLD Hold time 100 — µs TPROG Program delay time 4.0 — ms TPS Program mode setup time 2.0 5.0 ms TWC Program cycle time 50 — ms HCS360, HCS361 T 1 Hold Time 1 9.0 — ms T2 Program mode setup time 0 4.0 ms TCLKH Clock high time 50 — µs TCLKL Clock low time 50 — µs TDH Data hold time 30 — µs TDS Data setup time 0 — µs TDV Data out valid time — 30 µs TWC Program cycle time 50 — ms

 2004 Microchip Technology Inc. Preliminary DS41256A-page 19 HCSXXX

5.2 Timing Requirements for Program/Verify Mode – Transponders

Standard Operating Conditions (unless otherwise stated) Operating Temperature +25°C ± 5°C Operating Voltage 4.5V ≤ VDD ≤ 5.5V Sym Characteristics Min Max Units Conditions/Comments HCS410, HCS412 TAS ACK start time 100 — µs TCLKH Clock high time 50 — µs TCLKL Clock low time 50 — µs TDH Data hold time 20 — µs TDS Data stable time 20 — µs TDV Data valid time — 20 µs TPH 1 Program Hold Time 1 4 — ms TPH 2 Program Hold Time 2 100 — µs TPROG Bulk write time 2.2 — ms TPS Program mode setup time 3 5 ms TWC EEPROM write time 36 — ms

DS41256A-page 20 Preliminary  2004 Microchip Technology Inc.

5.3 Timing Requirements for Program/Verify Mode – Decoders

Standard Operating Conditions (unless otherwise stated) Operating Temperature +25°C ± 5°C Operating Voltage 4.5V ≤ VDD ≤ 5.5V Sym Characteristics Sugg. Value Min Max Units Conditions/Comments HCS500 FCLK Clock frequency — 500 25000 Hz TACK Decoder acknowledge time — 30 µs TADDR Address validate time — — 10 µs TCLKH Clock high time — 20 1000 µs TCLKL Clock low time — 20 1000 µs TCMD Command validate time — — 10 µs TDATA Command last bit to data first bit — — 10 µs TDS Data hold time — 14 — µs TREQ Command request time — 0.015 500 ms TRESP Acknowledge time — — 1 ms TSTART Command request to first command bit — 20 1000 µs HCS512 TACK Acknowledge time — — 80 ms F OSC = 4 MHZ TACKH Acknowledge duration — 1 — µsF OSC = 4 MHZ TCLKH Clock high time — 0.05 320 µsF OSC = 4 MHZ TCLKL Clock low time — 0.05 320 µsF OSC = 4 MHZ TPH 1 Hold Time 1 — 8 128 ms F OSC = 4 MHZ TPH 2 Hold Time 2 — 0.05 320 µsF OSC = 4 MHZ TPS Program mode setup time — 1 64 ms F OSC = 4 MHZ HCS515 TACK Command acknowledge time * 30 240 ms TCLKH Clock high time 100 20 1000 µs TCLKL Clock low time 100 20 1000 µs TDATA Command last bit to data first bit 100 10 1000 µs TDS Data hold time 50 14 1000 µs TREQ Command request time * 0.005 500 ms TRESP Acknowledge time 100 10 1000 µs TSTART Command request to first command bit 100 20 1000 µs TWTH Acknowledge respond time 100 20 1000 µs TWTL Clock low to next command 100 10 — µs * Depends on decoder status.

 2004 Microchip Technology Inc. Preliminary DS41256A-page 21 HCSXXX

5.4 Programming Waveforms (HCS200, HCS300, HCS301, HCS320, HCS362)

FIGURE 5-1: PROGRAMMING WAVEFORMS FIGURE 5-2: VERIFY WAVEFORMS PWM Enter Program Mode (Data) (Clock) Note 1: Unused button inputs to be held to ground during the entire programming sequence. bit 0 bit 1 bit 2 bit 3 bit 14bit 15 bit 16bit 17 TPH 1 TPBW TPS Repeat for each word (12 times) TPH 2 TCLKH TCLKL TWC TDS Data for Word 0 (KEY_0) Data for Word 1 (KEY_1) TDH TAS Ack Pulse PWM (Clock) (Data) Note: If a Verify operation is to be done, then it must immediately follow the Program cycle. End of Programming Cycle Beginning of Verify Cycle bit 1bit 2bit 3 bit 15bit 14 bit 16 bit 17 bit 190bit 191 TWC Data from Word 0 TDV S2 (S3) bit 0bit 191bit 190

DS41256A-page 22 Preliminary  2004 Microchip Technology Inc.

5.5 Programming Waveforms (HCS201)

FIGURE 5-3: PROGRAMMING WAVEFORMS (HCS201) FIGURE 5-4: VERIFY WAVEFORMS DATA Enter Program Mode (Data) (Clock) bit 0bit 1bit 2bit 3 bit 14bit 15 bit 16bit 17 TPH 1 TPBW TPS Repeat for each word (12 times) TPH 2 TCLKH TCLKL TWC TDS Data for Word 1 TDH TCLKL Initiate Data Polling Here Write Cycle Complete Here TACKL TACKH Calibration Pulses TPHOLD Ack Ack Ack Note: S0 and S1 button inputs to be held to ground during the entire programming sequence. DATA (Clock) (Data) End of Programming Cycle Beginning of Verify Cycle bit 1bit 2bit 3 bit 15bit 14 bit 16 bit 17 bit 190bit 191 TWC Data from Word 0 TDV bit 0bit 191bit 190 Ack Note: If a Verify operation is to be done, then it must immediately follow the Program cycle.

 2004 Microchip Technology Inc. Preliminary DS41256A-page 23 HCSXXX

5.6 Programming Waveforms (HCS360, HCS361)

FIGURE 5-5: PROGRAMMING WAVEFORMS FIGURE 5-6: VERIFY WAVEFORMS The VDD pin must be taken to ground after a program/verify cycle. DATA Enter Program Mode (Data) (Clock) bit 1bit 2bit 3 bit 14 bit 15 bit 16 bit 17 Repeat for each word TCLKHTCLKL TWC TDS S2/S3 Data for Word 0 (KEY_0) Data for Word 1 TDH bit 0bit 1bit 2bit 3 bit 14bit 15 bit 0 bit 0 of Word 0 Note 1: Unused button inputs to be held to ground during the entire programming sequence. 2: The VDD pin must be taken to ground after a Program/Verify cycle. Acknowledge Pulse DATA (Clock) (Data) End of Programming Cycle Beginning of Verify Cycle bit 1bit 2 bit 3 bit 15bit 14 bit 16 bit 17 bit 190bit 191 TWC Data from Word0 TDV S2/S3 bit 0bit 191bit 190 Ack Note 1: A Verify sequence is performed only once immediately after the Program cycle.

DS41256A-page 24 Preliminary  2004 Microchip Technology Inc.

5.7 Programming Waveforms (HCS410, HCS412)

FIGURE 5-7: PROGRAMMING WAVEFORMS FIGURE 5-8: VERIFY WAVEFORMS PWM Enter Program Mode (Data) (Clock) bit 0 bit 1 bit 2 bit 3 bit 14 bit 15 bit 16bit 17 TPH 1 TPBW TPS Repeat for each word (18 times) TPH 2 TCLKH TCLKL TWC TDS Data for Word 0 (KEY_0) Data for Word 1 (KEY_1) TDH TAS Ack Pulse Note 1: Unused button inputs to be held to ground during the entire programming sequence. 2: The VDD pin must be taken to ground after a Program/Verify cycle. PWM (Clock) (Data) Note: If a Verify operation is to be done, then it must immediately follow the Program cycle. End of Programming Cycle Beginning of Verify Cycle bit 1bit 2bit 3 bit 15bit 14 bit 16bit 17 bit 206bit 207 TWC Data from Word 0 TDV S2 (S3) bit 0bit 207bit 206

 2004 Microchip Technology Inc. Preliminary DS41256A-page 25 HCSXXX

5.8 Programming Waveforms (HCS500)

FIGURE 5-9: PROGRAMMING WAVEFORMS

5.9 Programming Waveforms (HCS512)

FIGURE 5-10: PROGRAMMING WAVEFORMS Decoder MSb MSb A Command ByteStart Command TCLKL TCLKHTPP 1 TDS BC LSb TPP 3 TPP 2 TCMD D LSb LSb Configuration Byte CLK µC Data MSb TDATA G Most Significant Byte H TACK TWT 2 TAW Acknowledge MSb E Least Significant Byte F TDATATADDR TPP 4 Data bit 1bit 0 bit 78 bit 79 Ack MCLR CLK (Clock) DAT (Data) Enter Program Mode Acknowledge pulse TPS TPH 1 TCLKL TCLKH TACKTPH 2 80-bit Data Package TACKH

DS41256A-page 26 Preliminary  2004 Microchip Technology Inc.

5.10 Programming Waveforms (HCS515)

FIGURE 5-11: PROGRAMMING WAVEFORMS MSb A Command ByteStart Command TCLKL TCLKH TDS BC LSb TSTART TDATA D TDATA E Configuration Byte LSb TDATA TREQ TRESP CLK µC Data MSbLSb MSbLSb HCS515 Data TDATA G MSb H TACK TWTH Acknowledge F TWTL LSb MSb Note: The programming command consists of the following:  Command Request Sequence (A to B)  Command Byte (B to C)  Configuration Byte (C to D)  Manufacturer’s Code Eight Data Bytes (D to G)  Activation and Acknowledge Sequence (G to H)

 2004 Microchip Technology Inc. Preliminary DS41256A-page 27 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEE LOQ , microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices:  Microchip products meet the specification contained in their particular Microchip Data Sheet.  Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.  There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  Microchip is willing to work with the customer who is concerned about the integrity of their code.  Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEE LOQ ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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