HCS373T INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • QML Class T, Per MIL-PRF-38535
  • Radiation Performance - Gamma Dose (γ) 1 x 105 RAD(Si) - Latch-Up Free Under Any Conditions - SEP Effective LET No Upsets: >100 MEV-cm 2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)
  • 3 Micron Radiation Hardened CMOS SOS
  • Significant Power Reduction Compared to LSTTL ICs
  • DC Operating Voltage Range: 4.5V to 5.5V
  • Input Logic Levels IL = 0.3 VCC Max -V IH = 0.7 VCC Min
  • Input Current Levels Ii≤ 5mA at VOL , VOH Pinouts HCS373DTR (SBDIP), CDIP2-T20 TOP VIEW HCS373KTR (FLATPACK), CDFP4-F20 TOP VIEW

Ordering Information

TEMP. RANGE (oC) 5962R9579201TRC HCS373DTR -55 to 125 5962R9579201TXC HCS373KTR -55 to 125 NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct. 1OE GND V CC LE 12 0 OE GND V CC LE Data Sheet July 1999 File Number 4617.1

D LE Q OE LATCH COMMON CONTROLS OE

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(3, 4, 7, 8, 13, 14, 17, 18) (2, 5, 6, 9, 12, 15, 16, 19) (1) (11) TRUTH TABLE OE LE D Q LHHH LHLL L LIL LLhH HXXZ H = High Level, L = Low Level. X = Immaterial, Z =High Impedance. I = Low voltage level prior to the high-to-low latch enable transition. h = High voltage level prior to the high-to-low latch enable transition. HCS373T

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Die Characteristics DIE DIMENSIONS: (2747µm x 2693µm x 533µm ±51.0µm) 108 x 106 x 21mils±2mil METALLIZATION: Type: Al Si Thickness: 11kÅ ±1kÅ SUBSTRATE POTENTIAL: Unbiased Silicon on Sapphire BACKSIDE FINISH: Sapphire PASSIVATION: Type: Silox (SiO 2) Thickness: 13kÅ ±2.6kÅ WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: 376 PROCESS: CMOS SOS Metallization Mask Layout HCS373T OE (1) (2) D1 (4) Q1 (5) D2 (7) (9) GND (10) (12) (15) Q5 (16) Q6 (17) D6 (18) D7 (19) VCC (20) (14) D5 (3) Q2 (6) (8) (11) (13) NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCS373 is TA14303A. HCS373T