HCS245MS RENESAS | Alldatasheet
Document overview
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- PDF pages: 8
Technical content
Features
- 3 Micron Radiation Hardened CMOS SOS
- Total Dose 200K or 1 Mega-RAD(Si)
- Latch-Up Free Under Any Conditions
- Fanout (Over Temperature Range) - Bus Driver Outputs - 15 LSTTL Loads
- Military Temperature Range: -55oC to +125oC
- Significant Power Reduction Compared to LSTTL ICs
- DC Operating Voltage Range: 4.5V to 5.5V
- LSTTL Input Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min
- Input Current Levels Ii 5A at VOL, VOH
Description
The Intersil HCS245MS is a Radiation Hardened Non-Invert- ing Octal Bidirectional Bus Transceiver, Three-State, intended for two-way asynchronous communication between data busses. The HCS245MS allows data transmission from the A bus to the B bus or from the B bus to the A bus. The logic level at the direction input (DIR) determines the data direction. The output enable input (OE ) puts the I/O port in the high-impedance state when high. The HCS245MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS245MS is supplied in a 20 lead Weld Seal Ceramic flatpack (K suffix) or a Weld Seal Ceramic Dual-In-Line Package (D suffix). Truth Table Pinouts
20 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T20, LEAD FINISH C TOP VIEW
20 PIN CERAMIC FLAT PACK
MIL-STD-1835 DESIGNATOR CDFP4-F20, LEAD FINISH C TOP VIEW Functional Diagram CONTROL INPUTS OPERATIONOE DIR L L B Data to A Bus L H A Data to B Bus H X Isolation H = High Voltage Level, L = Low Voltage Level, X = Immaterial To prevent excess currents in the High-Z (Isolation) modes, all I/O terminals should be terminated with 10k to 1M resistors. 1DIR GND VCC OE 12 0 DIR GND VCC OE B7ONE OF 8 TRANSCEIVERS B DATA (18, 17, 16, 15, 14, 13, 12) DIR OUTPUT ENABLE A DATA (2, 3, 4, 5, 6, 7, 8) TO OTHER
7 BUFFERS
cal Performance Characteristics” are the only conditions recommended for satisfactory device operation. TABLE 1. DC. ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages reference to device GND.
- For functional tests, VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages referenced to device GND.
- AC measurements assume RL = 500 , CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
- The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages referenced to device GND.
- AC measurements assume RL = 500 , CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
- For functional tests, VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 TABLE 6. APPLICABLE SUBGROUPS
- Alternate Group A testing in accordance with Method 5005 of MIL-STD-883 may be exercised.
TABLE 7. TOTAL DOSE IRRADIATION
- Except FN test which will be performed 100% Go/No-Go.
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
TABLE 8. STATIC BURN-IN AND DYNAMIC BURN-IN TEST CONNECTIONS
- Each pin except VCC and GND will have a resistor of 10K 5% for static burn-in.
- Each pin except VCC and GND will have a resistor of 680 5% for dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS group 2, sample size is 4 dice/wafer 0 failures.
FN2468 Rev 1.00 Page 6 of 8 December 1992 Three-State Low Timing Diagrams Three-State High Timing Diagrams Three-State Low Load Circuit Three-State High Load Circuit TRI-STATE LOW VOLTAGE LEVELS PARAMETER HCS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VT 2.25 V VW 0.90 V GND 0 V TRI-STATE HIGH VOLTAGE LEVELS PARAMETER HCS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VT 2.25 V VW 3.60 V GND 0 V VS INPUT OUTPUT VIH VIL VOZ VOL TPZL TPLZ VT VW VS INPUT OUTPUT VIH VIL VOH VOZ TPZH TPHZ VT VW DUT TEST CL RL POINT CL = 50pF RL = 500 VCC DUT TEST RL POINT CL = 50pF RL = 500 File Number
FN2468 Rev 1.00 Page 7 of 8 December 1992 Die Characteristics DIE DIMENSIONS: 124 x 110 mils METALLIZATION: Type: AlSi Metal Thickness: 11k Å 1kÅ GLASSIVATION: Type: SiO2 Thickness: 13kÅ -2.6kÅ DIE ATTACH: Material: Silver Epoxy WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100m x 100m 4 mils x 4 mils Metallization Mask Layout HCS245MS DIR (1) A0 (2) (8) (13) B5 VCC (20)NC NC NC NC OE (19) A1 (3) A2 (4) A3 (5) A4 (6) A5 (7) (9) GND (10) (11) (12) (14) B4 (15) B3 (16) B2 (17) B1 (18) B0
FN2468 Rev 1.00 Page 8 of 8 December 1992 HCS245MS Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1999. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners.