HCS244MS RENESAS | Alldatasheet

Document overview

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Technical content

Features

  • 3 Micron Radiation Hardened CMOS SOS
  • Total Dose 200K RAD (Si)/s
  • SEP Effective LET No Upsets: >100 MEV-cm 2/mg
  • Single Event Upset (SEU) Immunity < 2 x 10 -9 Errors/ Bit-Day (Typ)
  • Dose Rate Survivability: >1 x 1012 RAD (Si)/s
  • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
  • Latch-Up Free Under Any Conditions
  • Fanout (Over Temperature Range) - Bus Driver Outputs - 15 LSTTL Loads
  • Military Temperature Range: -55 oC to +125oC
  • Significant Power Reduction Compared to LSTTL ICs
  • DC Operating Voltage Range: 4.5V to 5.5V
  • Input Logic Levels - VIL = 0.3 VCC Max - VIH = 0.7 VCC Min
  • Input Current Levels Ii  5A at VOL, VOH

Description

The Intersil HCS244MS is a Radiation Hardened Non- Inverting Octal Buffer/Line Driver, Three-State, with two active-low output enables. The HCS244MS utilizes advan ced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS244MS is supplied in a 20 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). Pinouts

20 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T20 TOP VIEW

20 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F20 TOP VIEW 1OE GND VCC OE 12 0 OE GND VCC OE

Ordering Information

PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE HCS244DMSR -55 oC to +125oC Intersil Class S Equivalent 20 Lead SBDIP HCS244KMSR -55 oC to +125oC Intersil Class S Equivalent 20 Lead Ceramic Flatpack HCS244D/Sample +25 oC Sample 20 Lead SBDIP HCS244K/Sample +25 oC Sample 20 Lead Ceramic Flatpack HCS244HMSR +25 oCD i e D i e DB NA

FN2132 Rev 2.00 Page 2 of 10 September 1995 Functional Diagram NP N P N P N P P N P N P N P N 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 357912141618 1OE 2OE 2 4 6 8 11 13 15 17 1A0 1A1 1A2 1A3 2A0 2A1 2A2 2A3 TRUTH TABLE INPUTS OUTPUT 1OE, 2OE AY LLL LHH HXZ H = High Voltage Level L = Low Voltage Level X = Immaterial Z = High Impedance

under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages reference to device GND.
  2. For functional tests, VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages referenced to device GND.
  2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly

tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages referenced to device GND.
  2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
  3. For functional tests, VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.

TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

TABLE 6. APPLICABLE SUBGROUPS

  1. Alternate group A testing in accordance with Method 5005 of Mil-Std-883 may be exercised.

TABLE 7. TOTAL DOSE IRRADIATION

  1. Except FN test which will be performed 100% go/no-go.

TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS

  1. Each pin except VCC and GND will have a resistor of 10K  5% for static burn-in
  2. Each pin except VCC and GND will have a resistor of 680  5% for dynamic burn-in

TABLE 9. IRRADIATION TEST CONNECTIONS Subgroup 2, sample size is 4 dice/wafer 0 failures.

FN2132 Rev 2.00 Page 7 of 10 September 1995 Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019,

4 Samples/Wafer, 0 Rejects

100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C,

10 Cycles

100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125 oC min., Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Interim Electrical Test 2 (T2) 100% Delta Calculation (T0-T2) 100% PDA 1, Method 5004 (Notes 1and 2) 100% Dynamic Burn-In, Condition D, 240 hrs., +125 oC or Equivalent, Method 1015 100% Interim Electrical Test 3 (T3) 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic, Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents:

  • Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quan- tity).
  • Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
  • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil.
  • X-Ray report and film. Includes penetrometer measurements.
  • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
  • Lot Serial Number Sheet (Good units serial number and lot number).
  • Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
  • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.

FN2132 Rev 2.00 Page 8 of 10 September 1995 AC Timing Diagrams Three-State Low Timing Diagrams AC Load Circuit Three-State Low Load Circuit AC VOLTAGE LEVELS PARAMETER HCS UNITS VCC 4.50 V VIH 3.00 V VS 1.30 V VIL 0 V GND 0 V THREE-STATE LOW VOLTAGE LEVELS PARAMETER HCS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VT 2.25 V VW 0.90 V GND 0 V VS INPUT OUTPUT OUTPUT TTHL 80% 20% 80% 20% VIH VIL VOH VOL VOH VOL TPLH TPHL VS TTLH VS INPUT OUTPUT VIH VIL VOZ VOL TPZL TPLZ VT VW DUT TEST CL RL POINT CL = 50pF RL = 500 DUT TEST CL RL POINT CL = 50pF RL = 500

FN2132 Rev 2.00 Page 9 of 10 September 1995 HCS244MS Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1999. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Three-State High Timing Diagrams Three-State High Load Circuit TRI-STATE HIGH VOLTAGE LEVELS PARAMETER HCS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VT 2.25 V VW 3.60 V GND 0 V VS INPUT OUTPUT VIH VIL VOH VOZ TPZH TPHZ VT VW DUT TEST CL RL POINT CL = 50pF RL = 500

FN2132 Rev 2.00 Page 10 of 10 September 1995 Die Characteristics DIE DIMENSIONS: 108 x 106 mils METALLIZATION: Type: Al/Sil Metal Thickness: 11k Å 1kÅ GLASSIVATION: Type: SiO2 Thickness: 13kÅ  2.6kÅ WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100m x 100m 4 mils x 4 mils Metallization Mask Layout HCS244MS (18) Y0 1 (17) A3 2 (16) Y1 1 (15) A2 2 (14) Y2 1 (13)(12) A1 2Y3 1 (11) A0 2 (10) GND (9) Y0 2 (8) A3 1 VCC (20) OE 2 (19) OE (1) A0 1 (2) Y3 2 (3) A1 1 (4) Y2 2 (5) A2 1 (6) Y1 2 (7)