HCS160MS RENESAS | Alldatasheet
Document overview
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Technical content
Features
- 3 Micron Radiation Hardened SOS CMOS
- Total Dose 200K RAD (Si)
- SEP Effective LET No Upsets: >100 MEV-cm2/mg
- Single Event Upset (SEU) Immunity < 2 x 10 -9 Errors/ Bit-Day (Typ)
- Dose Rate Survivability: >1 x 1012 RAD (Si)/s
- Dose Rate Upset: >1010 RAD (Si)/s 20ns Pulse
- Latch-Up Free Under Any Conditions
- Fanout (Over Temperature Range) -Standard Outputs: 10 LSTTL Loads -Bus Driver Outputs: 15 LSTTL Loads
- Military Temperature Range: -55oC to +125oC
- Significant Power Reduction Compared to LSTTL ICs
- DC Operating Voltage Range: 4.5V to 5.5V
- Input Logic Levels -VIL = 30% of VCC Max -VIH = 70% of VCC Min
- Input Current Levels Ii 5A @ VOL, VOH
Description
The Intersil HCS160MS is a Radiation Hardened high speed presettable BCD decade synch ronous counter that features an asynchronous reset and look-ahead carry logic. Counting and parallel presetting are accomplished synchronously with the low-to-high transition of the clock. A low level on the syn- chronous parallel enable input, SPE , disables counting and allows data at the preset inputs, P0 - P3, to be loaded into the counter. The counter is reset by a low on the master reset input, MR . Two count enables, PE and TE are provided for n-bit cascading. TE also controls the terminal count out- put, TC. The terminal count output indicates a maximum count for one clock pulse and is used to enable the next cas- caded stage to count. The HCS160MS utilizes advan ced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS160MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix.) Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW MR CP GND PE VCC TE SPE TC MR CP PE GND 11 6 VCC TC TE SPE
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE HCS160DMSR -55 oC to +125oC Intersil Class S Equivalent 16 Lead SBDIP HCS160KMSR -55 oC to +125oC Intersil Class S Equivalent 16 Lead Ceramic Flatpack HCS160D/Sample +25 oC Sample 16 Lead SBDIP HCS160K/Sample +25 oC Sample 16 Lead Ceramic Flatpack HCS160HMSR +25 oCD i e D i e DB NA
FN2296 Rev 2.00 Page 2 of 9 September 1995 Functional Block Diagram SPE MR CP PE TE MR CP P 14 15 TC MR CP P MR CP P MR CP P Q3 Q3 Q3 Q0 Q3 Q0 Q0 Q1Q2 Q3 Q0 Q3Q0 P3P2P1P0 34 56 GND VCC 168 TRUTH TABLE OPERATING MODE INPUTS OUTPUTS MR CP PE TE SPE Pn Qn TC R e s e t ( C l e a r ) LXXXXXLL Parallel Load H X X l l L L H X X l h H (Note 1) Count H h h h (Note 3) X Count (Note 1) Inhibit H X l (Note 2) X h (Note 3) X qn (Note 1) H X X l (Note 2) h (Note 3) X qn L H = HIGH Voltage Level L = LOW Voltage Level h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial q = Lower case letterindicate the state of the referenced output prior to the LOW-to-HIGH clock transition = LOW-to-HIGH clock transition NOTES: 1. The TC output is HIGH when TE is HIGH and the counter is at terminal count (HHHH for 161 and HLLH for 160) 2. The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation 3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages referenced to device GND.
- For functional tests, VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages referenced to device GND.
- AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
- The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages referenced to device GND.
- AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC
- For functional tests VO 4.0V is recognized as a logic “1”, and VO 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) TABLE 6. APPLICABLE SUBGROUPS TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
- Alternate Group A testing in accordance with Method 5005 of Mil-Std-883 may be exercised.
TABLE 7. TOTAL DOSE IRRADIATION
- Except FN test which will be performed 100% go/no-go.
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
- Each pin except VCC and GND will have a resistor of 10K 5% for static burn-in
- Each pin except VCC and GND will have a resistor of 1K 5% for dynamic burn-in
TABLE 9. IRRADIATION TEST CONNECTIONS NOTE: Each pin except VCC and GN D will have a resistor of 47K 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. TABLE 6. APPLICABLE SUBGROUPS
FN2296 Rev 2.00 Page 7 of 9 September 1995 Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125 oC min., Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125 oC min., Method 1015 100% Interim Electrical Test 2 (T2) 100% Delta Calculation (T0-T2) 100% PDA 1, Method 5004 (Notes 1and 2) 100% Dynamic Burn-In, Condition D, 240 hrs., +125 oC or Equivalent, Method 1015 100% Interim Electrical Test 3 (T3) 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic, Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents:
- Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
- Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
- GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil.
- X-Ray report and film. Includes penetrometer measurements.
- Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
- Lot Serial Number Sheet (Good units serial number and lot number).
- Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
- The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
FN2296 Rev 2.00 Page 8 of 9 September 1995 AC Timing Diagrams AC Load Circuit AC VOLTAGE LEVELS PARAMETER HCS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VIL 0 V GND 0 V VS INPUT OUTPUT OUTPUT TTHL 80% 20% 80% 20% VIH VIL VOH VOL VOH VOL TPLH TPHL VS TTLH DUT TEST CL RL POINT CL = 50pF RL = 500
FN2296 Rev 2.00 Page 9 of 9 September 1995 Die Characteristics DIE DIMENSIONS: 104 x 86 mils METALLIZATION: Type: AlSi Metal Thickness: 11k Å 1kÅ GLASSIVATION: Type: SiO2 Thickness: 13kÅ 2.6kÅ WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100m x 100m 4 mils x 4 mils Metallization Mask Layout HCS160MS MR (1) CP (2) P0 (3) P1 (4) P2 (5) P3 (6) PE (7) (8) (9) SPE (10) TE (11) Q3 (12) Q2 (13) Q1 (14) Q0 (15) TC VCC GND (16)