HCS138T INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • QML Class T, Per MIL-PRF-38535
  • Radiation Performance - Gamma Dose (γ) 1 x 105 RAD(Si) - Latch-Up Free Under Any Conditions - SEP Effective LET No Upsets: >100 MEV-cm 2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)
  • 3 Micron Radiation Hardened SOS CMOS
  • Fanout (Over Temperature Range) - Standard Outputs - 10 LSTTL Loads
  • Significant Power Reduction Compared to LSTTL ICs
  • DC Operating Voltage Range: 4.5V to 5.5V
  • Input Logic Levels IL = 0.3 VCC Max -V IH = 0.7 VCC Min
  • Input Current Levels Ii≤ 5mA at VOL , VOH Pinouts HCS138DTR (SBDIP), CDIP2-T16 TOP VIEW HCS138KTR (FLATPACK), CDFP4-F16 TOP VIEW

Ordering Information

TEMP. RANGE (oC) 5962R9572701TEC HCS138DTR -55 to 125 5962R9572701TXC HCS138KTR -55 to 125 NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct. GND VCC GND VCC 11 6 Data Sheet July 1999 File Number 4614.1

E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 XXHXXXHHHHHHHH LXXXXXHHHHHHHH XHXXXXHHHHHHHH HL L L L L LHHHHHHH HLLLLHHLHHHHHH HLLLHLHHLHHHH H HL L LHHHHHLHHHH HLLHLLHHHHLHHH HLLHLHHHHHHLHH HLLHHLHHHHHHLH HL LHHHHHHHHHHL H = High Level, L = Low Level, X = Don’t Care HCS138T

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Die Characteristics DIE DIMENSIONS: (2159µm x 2565µm x 533µm ±51µm) 85 x 101 x 21mils±2mil METALLIZATION: Type: Al Si Thickness: 11.0kÅ ±1kÅ SUBSTRATE POTENTIAL: Unbiased Silicon on Sapphire BACKSIDE FINISH: Sapphire PASSIVATION: Type: Silox (SiO 2) Thickness: 13.0kÅ ±2.6kÅ WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: 264 PROCESS: CMOS SOS Metallization Mask Layout HCS138T A1 A0 VCC A2 (3) E1 (4) E2 (5) E3 (6) (8) (9) (10) (11)Y4 (12)Y3 (13)Y2 (14)Y1 (2) (1) (16) GND Y6 Y5 (7) (15) NC NC NC NC NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCS138 is TA14361A. HCS138T