HCS12X

MC9S12XHZ512 NXP | Alldatasheet

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Technical content

freescale.com MC9S12XHZ512 Data Sheet Covers MC9S12XHZ384, MC9S12XHZ256 MC9S12XHZ512 Rev. 1.06

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. This document contains information for all constituent modules, with the exception of the S12X CPU. For S12X CPU information please refer to CPU12XV2 in the CPU12/CPU12X Reference Manual.

Revision History

January 5, 2006 01.00 New Book April 20, 2006 01.01 Updated block guide versions July 28, 2006 01.02 Made minor corrections January 8, 2007 01.03 Added MC9S12XHZ384 and MC9S12XHZ256 August 20, 2007 01.04 Updated slew rates November 4, 2008 01.05 Corrected typos on pinout diagram October 14, 2010 01.06 Added PartID. Minor updates to ECT, SCI, IIC and XGATE sections.

MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 3 List of Chapters Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3).507

MC9S12XHZ512 Data Sheet, Rev. 1.06

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MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 5 Table of Contents Chapter 1 MC9S12XHZ Family Device Overview Chapter 2 Port Integration Module (S12XHZPIMV1)

MC9S12XHZ512 Data Sheet, Rev. 1.06

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512 Kbyte Flash Module (S12XFTX512K4V3)

MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 7 Chapter 4

4 Kbyte EEPROM Module (S12XEETX4KV2)

XGATE (S12XGATEV2)

MC9S12XHZ512 Data Sheet, Rev. 1.06

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Security (S12X9SECV2)

MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 9 Chapter 7 Clocks and Reset Generator (S12CRGV6) 7.2.3 Chapter 8 Pierce Oscillator (S12XOSCLCPV1)

MC9S12XHZ512 Data Sheet, Rev. 1.06

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Analog-to-Digital Converter (ATD10B16CV4) Block Description

9.2.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Channel x Pins

9.2.3 V Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description

MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 11 Chapter 11 Motor Controller (MC10B12CV2) Block Description Chapter 12 Stepper Stall Detector (SSDV1) Block Description

MC9S12XHZ512 Data Sheet, Rev. 1.06

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Inter-Integrated Circuit (IICV3) Block Description Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 13 Chapter 15 Serial Communication Interface (S12SCIV5)

MC9S12XHZ512 Data Sheet, Rev. 1.06

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Serial Peripheral Interface (S12SPIV4) 16.2.3 Chapter 17 Periodic Interrupt Timer (S12PIT24B4CV1)

MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 15 Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) Chapter 19 Enhanced Capture Timer (ECT16B8CV3)

MC9S12XHZ512 Data Sheet, Rev. 1.06

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Voltage Regulator (S12VREG3V3V5) 20.2.5 V Chapter 21 Background Debug Module (S12XBDMV2)

MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 17 Chapter 22 S12X Debug (S12XDBGV3) Module

MC9S12XHZ512 Data Sheet, Rev. 1.06

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External Bus Interface (S12XEBIV3) Chapter 24 Interrupt (S12XINTV1)

MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 19 Chapter 25 Memory Mapping Control (S12XMMCV3) Appendix A

Electrical Characteristics

Package Information

MC9S12XHZ512 Data Sheet, Rev. 1.06

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Ordering Information

MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 21 Chapter 1 MC9S12XHZ Family Device Overview

1.1 Introduction

Targeted at automotive instrumentation applications, the MC912XHZ family of microcontrollers is a fully pin-compatible extension to the existing MC9S12HZ family. It offers not only a larger memory but also incorporates all the architectural benefits of the new S12X-based family to deliver significantly higher performance. The MC9S12XHZ family retains the low cost, power consumption, EMC and code-size efficiency advantages currently associated with the MC9S12 products. Based around S12X core, the MC912XHZ family runs 16-bit wide accesses without wait states for all peripherals and memories. The MC912XHZ family also features a new flexible interrupt handler, which allows multilevel nested interrupts. The MC912XHZ family features the performance boosting XGATE co-processor. The XGATE is programmable in “C” language and runs at twice the bus frequency of the S12. Its instruction set is optimized for data movement, logic and bit manipulation instructions. Any peripheral module can be serviced by the XGATE. The MC912XHZ family contains up to 512K bytes of Freescale Semiconductor’s industry leading, full automotive qualified Split-Gate Flash memory, with 4K bytes of additional integrated data EEPROM and up to 32K bytes of static RAM. The MC912XHZ family features a 32x4 liquid crystal display (LCD) controller/driver and a motor pulse width modulator (MC) consisting of up to 24 high current outputs suited to drive six stepper motors with stall detectors (SSD) to simultaneously calibrate the pointer reset position of each motor. It also features two MSCAN modules, each with a FIFO receiver buffer arrangement, and input filters optimized for Gateway applications handling numerous message identifiers. In addition, the MC912XHZ family is composed of standard on-chip peripherals including two asynchronous serial communications interfaces (SCI0 and SCI1), one serial peripheral interface (SPI), two IIC-bus interface (IIC0 and IIC1), an 8-channel 16-bit enhanced capture timer (ECT), a 16-channel, 10-bit analog-to-digital converter (ADC), and one 8-channel pulse width modulator (PWM). The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. The new fast-exit from STOP mode feature can further improve system power consumption. In addition to the I/O ports available in each module, 8 general-purpose I/O pins are available with interrupt and wake-up capability from stop or wait mode. The MC912XHZ family is available in 112-pin LQFP and 144-pin LQFP packages. The 144-pin LQFP package option provides a full 16-bit wide non-multiplexed external bus interface.

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1.1.1 Features

• HCS12X Core — 16-bit HCS12X CPU – Upward compatible with MC9S12 instruction set – Interrupt stacking and programmer’s model identical to MC9S12 – Instruction queue – Enhanced indexed addressing – Enhanced instruction set — EBI (external bus interface) — MMC (module mapping control) — INT (interrupt controller) — DBG (debug module to monitor HCS12X CPU and XGATE bus activity) — BDM (background debug mode)
• XGATE (peripheral coprocessor) — Parallel processing module off loads the CPU by providing high-speed data processing and transfer — Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports
• Memory – 512K, 384K, 256K byte Flash EEPROM – 4K byte EEPROM – 32K, 28K, 16K byte RAM
• CRG (clock and reset generator) — Low noise/low power Pierce oscillator — PLL — COP watchdog — Real time interrupt — Clock monitor — Fast wake-up from stop mode
• Analog-to-digital converter — 16 channels, 10-bit resolution — External conversion trigger capability
• ECT (enhanced capture timer) — 16-bit main counter with 8-bit prescaler — 8 programmable input capture or output compare channels — Four 8-bit or two 16-bit pulse accumulators
• PIT (periodic interrupt timer) — Four timers with independent time-out periods — Time-out periods selectable between 1 and 2 24 bus clock cycles

Chapter 1 MC9S12XHZ Family Device Overview MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 23

• 8 PWM (pulse-width modulator) channels — Programmable period and duty cycle — 8-bit 8-channel or 16-bit 4-channel — Separate control for each pulse width and duty cycle — Center-aligned or left-aligned outputs — Programmable clock select logic with a wide range of frequencies — Fast emergency shutdown input
• Two 1-Mbps, CAN 2.0 A, B software compatible modules — Five receive and three transmit buffers — Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8x8b i t — Four separate interrupt channels for Rx, Tx, error, and wake-up — Low-pass filter wake-up function — Loop-back for self-test operation
• Two IIC (Inter-IC bus) Modules — Compatible with IIC bus standard — Multi-master operation — Broadcast mode
• Serial interfaces — Two asynchronous serial communication interfaces (SCI) with additional LIN support and selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width — Synchronous Serial Peripheral Interface (SPI)
• Liquid crystal display (LCD) driver with variable input voltage — Configurable for up to 32 frontplanes and 4 backplanes or general-purpose input or output — 5 modes of operation allow for different display sizes to meet application requirements — Unused frontplane and backplane pins can be used as general-purpose I/O
• PWM motor controller (MC) with 24 high current drivers — Each PWM channel switchable between two drivers in an H-bridge configuration — Left, right and center aligned outputs — Support for sine and cosine drive — Dithering — Output slew rate control
• Six stepper stall detectors (SSD) — Full step control during return to zero — Voltage detector and integrator / sigma delta converter circuit — 16-bit accumulator register — 16-bit modulus down counter

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• On-Chip V oltage Regulator — Two parallel, linear voltage regulators with bandgap reference — Low-voltage detect (LVD) with low-voltage interrupt (LVI) — Power-on reset (POR) circuit — 3.3-V–5.5-V operation — Low-voltage reset (LVR) — Ultra low-power wake-up timer
• 144-pin LQFP and 112-pin LQFP packages — I/O lines with 5-V input and drive capability — Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation — 5-V A/D converter inputs — 8 key wake up interrupts with digital filtering and programmable rising/falling edge trigger
• Operation at 80 MHz equivalent to 40-MHz bus speed
• Development support — Single-wire background debug™ mode (BDM) — Four on-chip hardware breakpoints

1.1.2 Modes of Operation

User modes:

• Normal and emulation operating modes — Normal single-chip mode — Normal expanded mode — Emulation of single-chip mode — Emulation of expanded mode
• Special Operating Modes — Special single-chip mode with active background debug mode — Special test mode ( Freescale use only) Low-power modes:
• System stop modes — Pseudo stop mode — Full stop mode
• System wait mode

1.1.3 Block Diagram

Figure 1-1 shows a block diagram of the MC912XHZ family.

Chapter 1 MC9S12XHZ Family Device Overview MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 25 Figure 1-1. MC9S12XHZ Family Block Diagram EXTAL XTAL BKGD XIRQ PLL XFC IRQ ECLK PA4 PA3 PA2 PA1 PA0 PA7 PA6 PA5 TEST PB4 PB0 PB7 PB6 FP4 FP3 FP2 FP1 FP0 FP7 FP6 PE4 PE5 PE6 PE0 PE1 MISO MOSI PS4 PS5 PS0 PS1 PK3 PK0 PK1 SCK SS PS6 PS7 SPI RXCAN0 TXCAN0 PM2 PM3 DDRA DDRB PTA PTB DDRE PTEPTK DDRK PTS DDRS PTM DDRM PK2 FP12 FP11 FP10 FP9 FP8 FP15 FP14 BP0 BP1 BP2 BP3 PL3 PL2 PL1 PL0 DDRL PTL FP19 FP18 FP17 FP16 FP22 FP21 FP20 VLCDVLCD LCD Driver CAN0 MODB/TAGHI MODA/TAGLO/RE RESET VDDPLL VSSPLL Clock and Reset Generation Module FP13 PB5 PB3 PB2 PB1 FP5 ADDR16/IQSTAT0 ADDR17/IQSTAT1 ADDR18/IQSTAT2 ADDR19/IQSTAT3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 FP24 FP25 FP26 FP27 AN2 AN6 AN0 AN7 AN1 AN3 AN4 AN5 PAD3 PAD4 PAD5 PAD6 PAD7 PAD0 PAD1 PAD2 VRH VRL VDDA VSSA Analog to Digital Converter DDRAD VRH VRL VDDA VSSA 512K, 384K, 256K Bytes Flash EEPROM 4k Bytes EEPROM 32K, 28K, 16K Bytes RAM EWAIT/ROMCTL VDDR VDD1 VSS1,2 Voltage Regulator Enahanced Capture Timer PL7 PL6 PL5 PL4 FP31 FP30 FP29 FP28 Single-Wire Background Debug Module RXCAN1 TXCAN1 PM4 PM5 CAN1 M0C0M M0C0P PU0 PU1 PTU DDRU PWM0 SSD0 M0C1M M0C1P PU2 PU3PWM1 M1C0M M1C0P PU4 PU5PWM2 SSD1 M1C1M M1C1P PU6 PU7PWM3 Pulse Width Modulator PW2 PW0 PW1 PW3 PW4 PW5 PP3 PP4 PP5 PP0 PP1 PP2 PTP DDRP RXD0 TXD0SCI0 AN10 AN14 AN8 AN15 AN9 AN11 AN12 AN13 AN10 AN14 AN8 AN15 AN9 AN11 AN12 AN13 KWAD2 KWAD6 KWAD0 KWAD7 KWAD1 KWAD3 KWAD4 KWAD5 M0COSM M0COSP M0SINM M0SINP M1COSM M1COSP M1SINM M1SINP PTAD M2C0M M2C0P PV0 PV1 PTV DDRV PWM4 SSD2 M2C1M M2C1P PV2 PV3PWM5 M3C0M M3C0P PV4 PV5PWM6 SSD3 M3C1M M3C1P PV6 PV7PWM7 M2COSM M2COSP M2SINM M2SINP M3COSM M3COSP M3SINM M3SINP RXD1 TXD1SCI1 PS2 PS3 SDA0 SCL0 PM1 IIC0 PP6 PP7 A/D Converter & VDDA VSSA PLL Supply 2.5V VDDPLL VSSPLL I/O Supply 5V VDDX1,2 VSSX1,2 Internal 2.5V VDD1 VSS1,2 Voltage Regulator 5V VDDR Voltage Regulator 5V PK7 FP23 PC4 PC0 PC7 PC6 DDRC PTC PC5 PC3 PC2 PC1 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 PD4 PD0 PD7 PD6 DDRD PTD PD5 PD3 PD2 PD1 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 PE7 PE2 PE3 XCLKS/ECLKX2 LSTRB/LDS/EROMCTL RW/WE PT4 PT3 PT2 PT1 PT0 PT7 PT6 PT5 DDRT PTT IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 Non-Multiplexed External Bus Interface SDA1 SCL1IIC1 SDA0 SCL0 SDA1 SCL1 CPU12X Periodic Interrupt COP Watchdog Clock Monitor Breakpoints XGATE Peripheral 4-Channel Motor Supplies VDDM1,2,3 VSSM1,2,3 M4C0M M4C0P PW0 PW1 PTW DDRW PWM8 SSD4 M4C1M M4C1P PW2 PW3PWM9 M5C0M M5C0P PW4 PW5PWM10 SSD5 M5C1M M5C1P PW6 PW7PWM11 M4COSM M4COSP M4SINM M4SINP M5COSM M5COSP M5SINM M5SINP Pins and signals shown in BOLD are not available in the 112 QFP package Co-Processor Programmable Interrupt Timer (PIT) for internal timebases Enhanced Multilevel Interrupt Module PK4 ADDR20/ACC0 PK5 ADDR21/ACC1 PK6 ADDR22/ACC2 CS1 CS3 CS0 CS2 PW6 PW7 Module-to-Port-Routing

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1.1.4 Device Memory Map

Table 1-1 shows the device memory map for the MC912XHZ family. Unimplemented register space shown in Table 1-1 is not allocated to any module. Writing to these locations have no effect. Read access to these locations returns zero. Table 1-1. Device Register Memory Map Address Offset Module Size (Bytes) 0x0000–0x0009 PIM (port integration module ) 10 0x000A–0x000B MMC (memory map control) 2 0x000C–0x000D PIM (port integration module) 2 0x000E–0x000F EBI (external bus interface) 2 0x0010–0x0017 MMC (memory map control) 8 0x0018–0x0019 Unimplemented 2 0x001A–0x001B Device ID register 2 0x001C–0x001F PIM (port integration module) 4 0x0020–0x002F DBG (debug module) 16 0x0030–0x0031 MMC (memory map control) 2 0x0032–0x0033 PIM (port integration module) 2 0x0034–0x003F CRG (clock and reset generator) 12 0x0040–0x007F ECT (enhanced capture timer 16-bit 8-channel) 64 0x0080–0x00AF ATD (analog-to-digital converter 10-bit 16-channel) 48 0x00B0–0x00BF INT (interrupt module) 16 0x00C0–0x00C7 IIC0 (inter IC bus) 8 0x00C8–0x00CF SCI0 (serial communications interface) 8 0x00D0–0x00D7 SCI1 (serial communications interface) 8 0x00D8–0x00DF SPI (serial peripheral interface) 8 0x00E0–0x00FF Unimplemented 32 0x0100–0x010F Flash control registers 16 0x0110–0x011B EEPROM control registers 12 0x011C–0x011F MMC (memory map control) 4 0x0120–0x0137 Liquid Crystal Display Driver 32x4 (LCD) 24 0x0138–0x013F IIC1 (inter IC bus) 8 0x0140–0x017F CAN0 (scalable CAN) 64 0x0180–0x01BF CAN1 (scalable CAN) 64 0x01C0–0x01FF MC (motor controller) 64 0x0200–0x027F PIM (port integration module) 128 0x0280–0x0287 SSD4 (stepper stall detector) 8 0x0288–0x028F SSD0 (stepper stall detector) 8 0x0290–0x0297 SSD1 (stepper stall detector) 8 0x0298–0x029F SSD2 (stepper stall detector) 8

Chapter 1 MC9S12XHZ Family Device Overview MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 27 Figure 1-2 shows the CPU & BDM local address translation to the global memory map. It indicates also the location of the internal resources in the memory map. Table 1-2. Device Internal Resources Figure 1-3 shows XGATE local address translation to the global memory map. It indicates also the location of used internal resources in the memory map. 0x02A0–0x02A7 SSD3 (stepper stall detector) 8 0x02A8–0x02AF SSD5 (stepper stall detector) 8 0x02B0–0x02EF Unimplemented 64 0x02F0–0x02F7 Voltage regulator 8 0x02F8–0x02FF Unimplemented 8 0x0300–0x0327 PWM (pulse-width modulator 8 channels) 40 0x0328–0x033F Unimplemented 24 0x0340–0x0367 PIT (periodic interrupt timer) 40 0x0368–0x037F Unimplemented 24 0x0380–0x03BF XGATE 64 0x03C0–0x03FF Unimplemented 64 0x0400–0x07FF Unimplemented 1024 Device RAMSIZE / RAM_LOW EEPROMSIZE / EEPROM_LOW FLASHSIZE0 / FLASH0_LOW FLASHSIZE1 / FLASH1_HIGH MC9S12XHZ512 32K / 0x0F_8000 4K / 0x13_F000 256K / 0x7B_FFFF 256K / 0x7C_0000 MC9S12XHZ384 28K / 0x0F_9000 4K / 0x13_F000 128K / 0x79_FFFF 256K / 0x7C_0000 MC9S12XHZ256 16K / 0x0F_C000 4K / 0x13_F000 128K / 0x79_FFFF 128K / 0x7E_0000 Table 1-3. XGATE Resources Device XGRAMSIZE / XGRAMLOW XGFLASHSIZE / XGFLASH_HIGH MC9S12XHZ512 32K / 0x0F_8000 30K 1 / 0x78_7FFF

1 This value is calculated by the following formula: (64K - 2K - XGRAMSIZE)

MC9S12XHZ384 28K / 0x0F_9000 MC9S12XHZ256 16K / 0x0F_C000 Table 1-1. Device Register Memory Map Address Offset Module Size (Bytes)

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Figure 1-2. MC9S12XHZ Family Global Memory Map 0x7F_FFFF 0x00_0000 0x13_FFFF 0x0F_FFFF EEPROM RAM 0x00_07FF EPAGE RPAGE PPAGE 0x3F_FFFF CPU and BDM Local Memory Map Global Memory Map FLASHSIZE EEPROMSIZE RAMSIZE Unimplemented EEPROM Unimplemented FLASH CS3CS2CS1CS0 0x1F_FFFF CS2 0xFFFF Reset Vectors 0xC000 0x8000 Unpaged 0x4000 0x1000 0x0000 16K FLASH window 0x0C00 0x2000 0x0800 8K RAM 4K RAM window 1K EEPROM 2K REGISTERS 1K EEPROM window 16K FLASH Unpaged 16K FLASH 2K REGISTERS Unimplemented RAM External Space RAM_LOW EEPROM_LOW 0x78_0000 FLASH1 FLASH0_LOW FLASH1_HIGH FLASH0 Unimplemented FLASH CS0 FLASHSIZE0FLASHSIZE1

Chapter 1 MC9S12XHZ Family Device Overview MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 29 Figure 1-3. XGATE Global Address Mapping 0x7F_FFFF 0x00_0000 0x0F_FFFF 0xFFFF 0x0000 Registers FLASH RAM 0x0800 Registers 0x00_07FF XGATE Local Memory Map Global Memory Map FLASHSIZE XGRAMSIZE RAMSIZE 0x78_0800 FLASH RAM XGRAM_LOW XGFLASH_HIGH

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1.1.5 Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0X001B). The read-only value is a unique part ID for each revision of the chip.Table 1-4 shows the assigned part ID number and mask set number.

1.2 Signal Description

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals.

1.2.1 Device Pinout

The MC912XHZ family is offered in the following package options:

• 144-pin LQFP with an external bus interface (address/data bus)
• 112-pin LQFP without an external bus interface Figure 1-4 and Figure 1-5 show the pin assignments. Table 1-4. Assigned Part ID Numbers Device Mask Set Number Part ID

1 The coding is as follows:

Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision including fab transfers Bit 3-0: Minor non-full mask set revision MC9S12XHZ512 0M80F 1M80F 0xE400 0xE401MC9S12XHZ384 MC9S12XHZ256

Chapter 1 MC9S12XHZ Family Device Overview MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 31 Figure 1-4. MC9S12XHZ Family 144 LQFP Pin Assignment FP28/AN12/PL4 FP29AN13/PL5 FP30/AN14/PL6 FP31/AN15/PL7 M4C0M/M4COSM/PW0 M4C0P/M4COSP/PW1 M4C1M/M4SINM/PW2 M4C1P/M4SINP/PW3 VDDM1 VSSM1 M0C0M/M0COSM/PU0 M0C0P/M0COSP/PU1 M0C1M/M0SINM/PU2 M0C1P/M0SINP/PU3 M1C0M/M1COSM/PU4 M1C0P/M1COSP/PU5 M1C1M/M1SINM/PU6 M1C1P/M1SINP/PU7 VDDM2 VSSM2 M2C0M/M2COSM/PV0 M2C0P/M2COSP/PV1 M2C1M/M2SINM/PV2 M2C1P/M2SINP/PV3 M3C0M/M3COSM/PV4 M3C0P/M3COSP/PV5 M3C1M/M3SINM/PV6 M3C1P/M3SINP/PV7 VDDM3 VSSM3 M5C0M/M5COSM/PW4 M5C0P/M5COSP/PW5 M5C1M/M5SINM/PW6 M5C1P/M5SINP/PW7 SCL0/PWM5/PP5 SDA0/PWM4/PP4 PWM3/PP3 RXD1/PWM2/PP2 TXD1/PWM0/PP0 PWM1/PP1 CS0/SDA1/PWM6/PP6 CS2/SCL1/PWM7/PP7 ACC0/ADDR20/PK4 ACC1/ADDR21/PK5 RXD0/PS0 TXD0/PS1 CS3/RXD1/PS2 TXD1/PS3 VSS2 VDDR VDDX2 VSSX2 MODC/BKGD RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST ACC2/ADDR22/PK6 CS1/PM1 RXCAN0/PM2 TXCAN0/PM3 RXCAN1/PM4 TXCAN1/PM5 TAGLO/RE/MODA/PE5 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 IRQ/PE1 PB5/ADDR5/FP5 PB4/ADDR4/FP4 PB3/ADDR3/FP3 PB2/ADDR2/FP2 PB1/ADDR1/FP1 PB0/ADDR0/FP0 PK0/ADDR16/BP0 PK1/ADDR17/BP1 PK2/ADDR18/BP2 PK3/ADDR19/BP3 VLCD VSS1 VDD1 PD7/DATA7 PD6/DATA6 PD5/DATA5 PD4/DATA4 PD3/DATA3 PD2/DATA2 PD1/DATA1 PD0/DATA0 PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 VDDA VRH VRL VSSA PE0/ XIRQ PE4/ECLK PE6/MODB/ TAGHI PT7/IOC7/SCL1 PT6/IOC6/SDA1 PT5/IOC5/SCL0 PT4/IOC4/SDA0 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 PC7/DATA15 PC6/DATA14 PC5/DATA13 PC4/DATA12 VSSX1 VDDX1 PK7/ EWAIT/ROMCTL/FP23 PE7/ECLKX2/XCLKS/FP22 PE3/LSTRB/LDS/EROMCTL/FP21 PE2/RW/WE/FP20 PC3/DATA11 PC2/DATA10 PC1/DATA9 PC0/DATA8 PL3/AN11/FP19 PL2/AN10/FP18 PL1/AN9/FP17 PL0/AN8/FP16 PA7/ADDR15/FP15 PA6/ADDR14/FP14 PA5/ADDR13/FP13 PA4/ADDR12/FP12 PA3/ADDR11/FP11 PA2/ADDR10/FP10 PA1/ADDR9/FP9 PA0/ADDR8/FP8 PB7/ADDR7/FP7 PB6/ADDR6/FP6 MC9S12XHZ Family

144 LQFP

Pins shown in BOLD are not available in the 112 QFP package 108 107 106 105 104 103 102 101 100 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109

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Figure 1-5. MC9S12XHZ Family 112 LQFP Pin Assignment 112 111 110 109 108 107 106 105 104 103 102 101 100 MC9S12XHZ Family

112 LQFP

Chapter 1 MC9S12XHZ Family Device Overview MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 33

1.2.2 Signal Properties Summary

Table 1-5 summarizes all pin functions. Table 1-5. Signal Properties Pin Name Function 1 Pin Name Function 2 Pin Name Function 3 Pin Name Function 4 Pin Name Function 5 Powered by Internal Pull Up Resistor

Description

EXTAL — — — — V DDPLL NA NA Oscillator pins XTAL — — — — V DDPLL NA NA RESET — — — — V DDX2 PULL UP External reset TEST — — — — NA NA NA Test input - must be tied to VSS in all applications XFC — — — — V DDPLL NA NA PLL loop Filter BKGD MODC — — — V DDX2 Always on Up Background debug, mode input PAD[7:0] AN[7:0] KWAD[7:0] — — V DDA PERAD/ PPSAD Disabled Port AD I/O, Analog inputs (ATD), interrupts PA[7:0] FP[15:8] ADDR[15:8] IVD[15:8] — V DDX1 PUCR Down Port A I/O, address bus, internal visibility data PB[7:1] FP[7:1] ADDR[7:1] IVD[7:1] — V DDX1 PUCR Down Port B I/O, address bus, internal visibility data PB0 FP0 ADDR0 IVD0 UDS V DDX1 PUCR Down Port B I/O, address bus, internal visibility data, upper data strobe PC[7:0] — DATA[15:8] — — V DDX1 PUCR Disabled Port C I/O, data bus PD[7:0] — DATA[7:0] — — V DDX1 PUCR Disabled Port D I/O, data bus PE7 FP22 ECLKX2 XCLKS — V DDX1 PUCR Down Port E I/O, LCD driver, system clock output, clock select PE6 TAGHI MODB — — V DDX2 While RESET pin is low: Down Port E I/O, tag high, mode input PE5 TAGLO MODA RE — V DDX2 While RESET pin is low: Down Port E I/O, tag low, mode input, read enable PE4 ECLK — — — V DDX2 PUCR Down Port E I/O, bus clock output PE3 FP21 LSTRB LDS EROMCTL V DDX1 PUCR Down Port E I/O, LCD driver, low byte strobe, EROMON control PE2 FP20 R/ W WE — V DDX1 PUCR Down Port E I/O, read/write, write enable PE1 IRQ — — — V DDX2 PUCR Up Port E input, maskable interrupt PE0 XIRQ — — — V DDX2 PUCR Up Port E input, non-maskable interrupt

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PK7 FP23 ECS ROMCTL ROMCTL V DDX1 PUCR Down Port K I/O, emulation chip select, ROM on enable PK[6:4] — ADDR[22:20] ACC[2:0] — V DDX2 Port K I/O, extended address, access source PK[3:0] BP[3:0] ADDR[19:16] IQSTAT[3:0] — V DDX1 Port K I/O, LCD driver, extended address, pipe status PL[7:4] FP[31:28] AN[15:12] — — V DDA PERL/ PPSL Down Port L I/O, LCD drivers, analog inputs (ATD) PL[3:0] FP[19:16] AN[11:8] — — V DDX1 Port L I/O, LCD drivers, analog inputs (ATD) PM5 TXCAN1 — — — V DDX2 PERM/ PPSM Disabled Port M I/O, TX of CAN1 PM4 RXCAN1 — — — V DDX2 Port M I/O, RX of CAN1 PM3 TXCAN0 — — — V DDX2 Port M I/O, TX of CAN0 PM2 RXCAN0 — — — V DDX2 Port M I/O, RX of CAN0 PM1 — — CS1 — V DDX2 Port M I/O, chip select 1 PP7 PWM7 SCL1 CS2 — V DDX2 PERP/ PPSP Disabled Port P I/O, PWM channel, SCL of IIC1, chip select 2 PP6 PWM6 SDA1 CS0 — V DDX2 Port P I/O, PWM channel, SDA of IIC1, chip select 0 PP5 PWM5 SCL0 — — V DDX2 Port P I/O, PWM channel, SCL of IIC0 PP4 PWM4 SDA0 — — V DDX2 Port P I/O, PWM channel, SDA of IIC0 PP3 PWM3 — — — V DDX2 Port P I/O, PWM channel PP2 PWM2 RXD1 — — V DDX2 Port P I/O, PWM channel, RXD of SCI1 PP1 PWM1 — — — V DDX2 Port P I/O, PWM channel PP0 PWM0 TXD1 — — V DDX2 Port P I/O, PWM channel, TXD of SCI1 PS7 SS — — — V DDX2 PERS/ PPSS Disabled Port S I/O, SS of SPI PS6 SCK — — — V DDX2 Port S I/O, SCK of SPI PS5 MOSI — — — V DDX2 Port S I/O, MOSI of SPI PS4 MISO — — — V DDX2 Port S I/O, MISO of SPI PS3 TXD1 — — — V DDX2 Port S I/O, TXD of SCI1 PS2 RXD1 — CS3 — V DDX2 Port S I/O, RXD of SCI1, chip select 3 PS1 TXD0 — — — V DDX2 Port S I/O, TXD of SCI0 PS0 RXD0 — — — V DDX2 Port S I/O, RXD of SCI0 Table 1-5. Signal Properties Pin Name Function 1 Pin Name Function 2 Pin Name Function 3 Pin Name Function 4 Pin Name Function 5 Powered by Internal Pull Up Resistor

Chapter 1 MC9S12XHZ Family Device Overview MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 35 PT7 IOC7 SCL1 — — V DDX1 PERT/ PPST Disabled Port T I/O, Timer channels, SCL of IIC1 PT6 IOC6 SDA1 — — V DDX1 Port T I/O, Timer channels, SDA of IIC1 PT5 IOC5 SCL0 — — V DDX1 Port T I/O, Timer channels, SCL of IIC0 PT4 IOC4 SDA0 — — V DDX1 Port T I/O, Timer channels, SDA of IIC0 PT[3:0] IOC[3:0] FP[27:24] — — V DDX1 PERT/ PPST Down Port T I/O, Timer channels, LCD driver PU7 M1C1P M1SINP — — V DDM1,2,3 PERU/ PPSU Disabled Port U I/O, motor1 coil nodes of MC or SSD1PU6 M1C1M M1SINM — — V DDM1,2,3 PU5 M1C0P M1COSP — — V DDM1,2,3 PU4 M1C0M M1COSM — — V DDM1,2,3 PU3 M0C1P M0SINP — — V DDM1,2,3 Port U I/O, motor 0 coil nodes of MC or SSD0PU2 M0C1M M0SINM — — V DDM1,2,3 PU1 M0C0P M0COSP — — V DDM1,2,3 PU0 M0C0M M0COSM — — V DDM1,2,3 PV7 M3C1P M3SINP — — V DDM1,2,3 PERV/ PPSV Disabled Port V I/O, motor 3 coil nodes of MC or SSD3PV6 M3C1M M3SINM — — V DDM1,2,3 PV5 M3C0P M3COSP — — V DDM1,2,3 PV4 M3C0M M3COSM — — V DDM1,2,3 PV3 M2C1P M2SINP — — V DDM1,2,3 Port V I/O, motor 2 coil nodes of MC or SSD2PV2 M2C1M M2SINM — — V DDM1,2,3 PV1 M2C0P M2COSP — — V DDM1,2,3 PV0 M2C0M M2COSM — — V DDM1,2,3 PW7 M5C1P M5SINP — — V DDM1,2,3 PERW/ PPSW Disabled Port W I/O, motor 5 coil nodes of MC or SSD5PW6 M5C1M M5SINM — — V DDM1,2,3 PW5 M5C0P M5COSP — — V DDM1,2,3 PW4 M5C0M M5COSM — — V DDM1,2,3 PW3 M4C1P M4SINP — — V DDM1,2,3 Port W I/O, motor 4 coil nodes of MC or SSD4PW2 M4C1M M4SINM — — V DDM1,2,3 PW1 M4C0P M4COSP — — V DDM1,2,3 PW0 M4C0M M4COSM — — V DDM1,2,3 Table 1-5. Signal Properties Pin Name Function 1 Pin Name Function 2 Pin Name Function 3 Pin Name Function 4 Pin Name Function 5 Powered by Internal Pull Up Resistor

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All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on MCU pin load.

1.2.3 Detailed Signal Descriptions

1.2.3.1 EXTAL, XTAL — Oscillator Pins

EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output.

1.2.3.2 RESET — External Reset Pin

The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset.TheRESET pin has an internal pullup device. Table 1-6. Power and Ground Mnemonic Nominal Voltage Description VLCD 5.0 V Voltage reference pin for the LCD driver. VDD1 2.5 V Internal power and ground generated by internal regulator. These also allow an external source to supply the core VDD/VSS voltages and bypass the internal voltage regulator.VSS1 VSS2 VDDR 5.0 V External power and ground, supply to pin drivers and internal voltage regulator. VSSR 0 V VDDX1 VDDX2 5.0 V External power and ground, supply to pin drivers. VSSX1 VSSX2 0 V VDDA 5.0 V Operating voltage and ground for the analog-to-digital converter and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently.VSSA 0 V VRH 5.0 V Reference voltage high for the ATD converter. VRL 0 V Reference voltage low for the ATD converter. VDDPLL 2.5 V Provides operating voltage and ground for the phased-locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator.V SSPLL 0 V VDDM1,2,3 5.0 V Provides operating voltage and ground for motor 0, 1, 2 and 3. VSSM1,2,3 0 V

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1.2.3.3 TEST — Test Pin

This input only pin is reserved for test. This pin has a pulldown device. NOTE The TEST pin must be tied to VSS in all applications.

1.2.3.4 XFC — PLL Loop Filter Pin

Please ask your Freescale representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided. Figure 1-6. PLL Loop Filter Connections

1.2.3.5 BKGD / MODC — Background Debug and Mode Pin

The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. The BKGD pin has a pullup device.

1.2.3.6 PAD[7:0] / AN[7:0] / KWAD[7:0] — Port AD I/O Pins [7:0]

PAD7–PAD0 are general-purpose input or output pins and analog inputs for the analog-to-digital converter. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.

1.2.3.7 PA[7:0] / ADDR[15:8] / IVD[15:8] — Port A I/O Pins

PA[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external address bus. In MCU emulation modes of operation, these pins are used for external address bus and internal visibility read data.

1.2.3.8 PB[7:1] / ADDR[7:1] / IVD[7:1] — Port B I/O Pins

PB[7:1] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external address bus. In MCU emulation modes of operation, these pins are used for external address bus and internal visibility read data. MCU XFC CS CP VDDPLLVDDPLL

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1.2.3.9 PB0 / ADDR0 / UDS / IVD[0] — Port B I/O Pin 0

PB0 is a general-purpose input or output pin. In MCU expanded modes of operation, this pin is used for the external address bus ADDR0 or as upper data strobe signal. In MCU emulation modes of operation, this pin is used for external address bus ADDR0 and internal visibility read data IVD0.

1.2.3.10 PC[7:0] / DATA [15:8] — Port C I/O Pins

PC[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external data bus. The input voltage thresholds for PC[7:0] can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V . The input voltage thresholds for PC[7:0] are configured to reduced levels out of reset in expanded and emulation modes. The input voltage thresholds for PC[7:0] are configured to 5-V levels out of reset in normal modes.

1.2.3.11 PD[7:0] / DATA [7:0] — Port D I/O Pins

PD[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external data bus. The input voltage thresholds for PD[7:0] can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V . The input voltage thresholds for PD[7:0] are configured to reduced levels out of reset in expanded and emulation modes. The input voltage thresholds for PC[7:0] are configured to 5-V levels out of reset in normal modes.

1.2.3.12 PE7 / FP22 / ECLKX2 / XCLKS — Port E I/O Pin 7

PE7 is a general-purpose input or output pin. The pin can be configured as frontplane segment driver output FP22 of the LCD module or as the internal system clock ECLKX2. The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check is ongoing. This is the case for:

• Power on reset or low-voltage reset
• Clock monitor reset
• Any reset while in self-clock mode or full stop mode The selected oscillator configuration is frozen with the rising edge of reset.

Chapter 1 MC9S12XHZ Family Device Overview MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 39 Figure 1-7. Loop Controlled Pierce Oscillator Connections (PE7 = 0) Figure 1-8. Full Swing Pierce Oscillator Connections (PE7 = 1) Figure 1-9. External Clock Connections (PE7 = 1)

1.2.3.13 PE6 / MODB / TAGHI — Port E I/O Pin 6

PE6 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a pull-down device which is only active when RESET is low. TAGHI is used to tag the high half of the instruction word being read into the instruction queue. The input voltage threshold for PE6 can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V . The input voltage threshold for PE6 is configured to reduced levels out of reset in expanded and emulation modes. MCU EXTAL XTAL VSSPLL Crystal or Ceramic Resonator MCU EXTAL XTAL RS RB VSSPLL Crystal or Ceramic Resonator MCU EXTAL XTAL CMOS-Compatible External Oscillator Not Connected

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1.2.3.14 PE5 / MODA / TAGLO / RE — Port E I/O Pin 5

PE5 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the read enable RE output. This pin is an input with a pull-down device which is only active whenRESET is low. TAGLO is used to tag the low half of the instruction word being read into the instruction queue. The input voltage threshold for PE5 can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V . The input voltage threshold for PE5 is configured to reduced levels out of reset in expanded and emulation modes.

1.2.3.15 PE4 / ECLK — Port E I/O Pin 4

PE4 is a general-purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference.

1.2.3.16 PE3 / FP21 / LSTRB / LDS / EROMCTL— Port E I/O Pin 3

PE3 is a general-purpose input or output pin. It can be configured as frontplane segment driver output FP21 of the LCD module. In MCU expanded modes of operation, LSTRB or LDS can be used for the low byte strobe function to indicate the type of bus access. At the rising edge of RESET the state of this pin is latched to the EROMON bit.

1.2.3.17 PE2 / FP20 / R/ W / WE— Port E I/O Pin 2

PE2 is a general-purpose input or output pin. It can be configured as frontplane segment driver output FP20 of the LCD module. In MCU expanded modes of operations, this pin drives the read/write output signal or write enable output signal for the external bus. It indicates the direction of data on the external bus.

1.2.3.18 PE1 / IRQ — Port E Input Pin 1

PE1 is a general-purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode.

1.2.3.19 PE0 / XIRQ — Port E Input Pin 0

PE0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode.

1.2.3.20 PK7 / FP23 / EWAIT / ROMCTL — Port K I/O Pin 7

PK7 is a general-purpose input or output pin. It can be configured as frontplane segment driver output FP23 of the LCD module. During MCU emulation modes and normal expanded modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. TheEWAIT input signal maintains the external bus access until the external device is ready to capture data (write) or provide data (read).

Chapter 1 MC9S12XHZ Family Device Overview MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 41 The input voltage threshold for PK7 can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V . The input voltage threshold for PK7 is configured to reduced levels out of reset in expanded and emulation modes.

1.2.3.21 PK[6:4] / ADDR[22:20] / ACC[2:0] — Port K I/O Pin [6:4]

PK[6:4] are general-purpose input or output pins. During MCU expanded modes of operation, the ACC[2:0] signals are used to indicate the access source of the bus cycle. This pins also provide the expanded addresses ADDR[22:20] for the external bus. In Emulation modes ACC[2:0] is available and is time multiplexed with the high addresses

1.2.3.22 PK[3:0] / BP[3:0] / ADDR[19:16] / IQSTAT[3:0] — Port K I/O Pins [3:0]

PK3-PK0 are general-purpose input or output pins. The pins can be configured as backplane segment driver outputs BP3–BP0 of the LCD module. In MCU expanded modes of operation, these pins provide the expanded address ADDR[19:16] for the external bus and carry instruction pipe information.

1.2.3.23 PL[7:4] / FP[31:28] / AN[15:12] — Port L I/O Pins [7:4]

PL7–PL4 are general-purpose input or output pins. They can be configured as frontplane segment driver outputs FP31–FP28 of the LCD module or analog inputs for the analog-to-digital converter.

1.2.3.24 PL[3:0] / FP[19:16] / AN[11:8] — Port L I/O Pins [3:0]

PL3–PL0 are general-purpose input or output pins. They can be configured as frontplane segment driver outputs FP19–FP16 of the LCD module or analog inputs for the analog-to-digital converter.

1.2.3.25 PM5 / TXCAN1 — Port M I/O Pin 5

PM5 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN1 of the scalable controller area network controller 1 (CAN1)

1.2.3.26 PM4 / RXCAN1 — Port M I/O Pin 4

PM4 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN1 of the scalable controller area network controller 1 (CAN1)

1.2.3.27 PM3 / TXCAN0 — Port M I/O Pin 3

PM3 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN0 of the scalable controller area network controller 0 (CAN0)

1.2.3.28 PM2 / RXCAN0 — Port M I/O Pin 2

PM2 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN0 of the scalable controller area network controller 0 (CAN0).

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1.2.3.29 PM1 / CS1 — Port M I/O Pin 1

PM1 is a general-purpose input or output pin. It can be configured to provide a chip-select output.

1.2.3.30 PP7 / PWM7 / SCL1 / CS2 — Port P I/O Pin 7

PP7 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM7 or the serial clock pin SCL1 of the inter-IC bus interface 1 (IIC1). It can be configured to provide a chip-select output.

1.2.3.31 PP6 / PWM6 / SDA1 / CS0 — Port P I/O Pin 6

PP6 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM6 or the serial data pin SDA1 of the inter-IC bus interface 1 (IIC1). It can be configured to provide a chip-select output.

1.2.3.32 PP5 / PWM5 / SCL0 — Port P I/O Pin 5

PP5 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM5 or the serial clock pin SCL0 of the inter-IC bus interface 0 (IIC0).

1.2.3.33 PP4 / PWM4 / SDA0 — Port P I/O Pin 4

PP4 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM4 or the serial data pin SDA0 of the inter-IC bus interface 0 (IIC0).

1.2.3.34 PP3 / PWM3 — Port P I/O Pin 3

PP3 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM3.

1.2.3.35 PP2 / PWM2 / RXD1 — Port P I/O Pin 2

PP2 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM2 or the receive pin RXD1 of the serial communication interface 1 (SCI1).

1.2.3.36 PP1 / PWM1 — Port P I/O Pin 1

PP1 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM1.

1.2.3.37 PP0 / PWM0 / TXD1 — Port P I/O Pin 0

PP0 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM0 or the transmit pin TXD1 of the serial communication interface 1 (SCI1).

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1.2.3.38 PS7 / SS — Port S I/O Pin 7

PS7 is a general-purpose input or output pin. It can be configured as slave select pin SS of the serial peripheral interface (SPI).

1.2.3.39 PS6 / SCK — Port S I/O Pin 6

PS6 is a general-purpose input or output pin. It can be configured as serial clock pin SCK of the serial peripheral interface (SPI).

1.2.3.40 PS5 / MOSI — Port S I/O Pin 5

PS5 is a general-purpose input or output pin. It can be configured as the master output (during master mode) or slave input (during slave mode) pin MOSI of the serial peripheral interface (SPI).

1.2.3.41 PS4 / MISO — Port S I/O Pin 4

PS4 is a general-purpose input or output pin. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO for the serial peripheral interface (SPI).

1.2.3.42 PS3 / TXD1 — Port S I/O Pin 3

PS3 is a general-purpose input or output pin. It can be configured as transmit pin TXD1 of the serial communication interface 1 (SCI1).

1.2.3.43 PS2 / RXD1 / CS2 — Port S I/O Pin 2

PS2 is a general-purpose input or output pin. It can be configured as receive pin RXD1 of the serial communication interface 1 (SCI1). It can be configured to provide a chip-select output.

1.2.3.44 PS1 / TXD0 — Port S I/O Pin 1

PS1 is a general-purpose input or output pin. It can be configured as transmit pin TXD0 of the serial communication interface 0 (SCI0).

1.2.3.45 PS0 / RXD0 — Port S I/O Pin 0

PS0 is a general-purpose input or output pin. It can be configured as receive pin RXD0 of the serial communication interface 0 (SCI0).

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1.2.3.46 PT7 / IOC7 / SCL1 — Port T I/O Pin 7

PT7 is a general-purpose input or output pin. It can be configured as input capture or output compare pin IOC7 of the enhanced capture timer (ECT) or the serial clock pin SCL1 of the inter-IC bus interface 1 (IIC1).

1.2.3.47 PT6 / IOC6 / SDA1 — Port T I/O Pin 6

PT6 is a general-purpose input or output pin. It can be configured as input capture or output compare pin IOC6 of the enhanced capture timer (ECT) or the serial data pin SDA1 of the inter-IC bus interface 1 (IIC1).

1.2.3.48 PT5 / IOC5 / SCL0 — Port T I/O Pin 5

PT5 is a general-purpose input or output pin. It can be configured as input capture or output compare pin IOC5 of the enhanced capture timer (ECT) or the serial clock pin SCL0 of the inter-IC bus interface 0 (IIC0).

1.2.3.49 PT4 / IOC4 / SDA0 — Port T I/O Pin 4

PT4 is a general-purpose input or output pin. It can be configured as input capture or output compare pin IOC4 of the enhanced capture timer (ECT) or the serial data pin SDA0 of the inter-IC bus interface 0 (IIC0).

1.2.3.50 PT[3:0] / IOC[3:0] / FP[27:24] — Port T I/O Pins [3:0]

PT3–PT0 are general-purpose input or output pins. They can be configured as input capture or output compare pins IOC3–IOC0 of the enhanced capture timer (ECT). They can be configured as frontplane segment driver outputs FP27–FP24 of the LCD module.

1.2.3.51 PU[7:4] / M1C1(SIN)P, M1C1(SIN)M, M1C0(COS)P, M1C0(COS)M — Port U

I/O Pins [7:4] PU7–PU4 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 1.

1.2.3.52 PU[3:0] / M0C1(SIN)P, M0C1(SIN)M, M0C0(COS)P, M0C0(COS)M — Port U

I/O Pins [3:0] PU3–PU0 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 0.

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1.2.3.53 PV[7:4] / M3C1(SIN)P, M3C1(SIN)M, M3C0(COS)P, M3C0(COS)M — Port V

I/O Pins [7:4] PV7–PV4 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 3.

1.2.3.54 PV[3:0] / M2C1(SIN)P, M2C1(SIN)M, M2C0(COS)P, M2C0(COS)M — Port V

I/O Pins [3:0] PV3–PV0 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 2.

1.2.3.55 PW[7:4] / M5C1(SIN)P, M5C1(SIN)M, M5C0(COS)P, M5C0(COS)M — Port

W I/O Pins [7:4] PW7–PW4 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 5.

1.2.3.56 PW[3:0] / M4C1(SIN)P, M4C1(SIN)M, M4C0(COS)P, M4C0(COS)M — Port

W I/O Pins [3:0] PW3–PW0 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 4.

1.2.4 Power Supply Pins

Power and ground pins are described below. NOTE All VSS pins must be connected together in the application.

1.2.4.1 V DDR — External Power Pin

VDDR is the power supply pin for the internal voltage regulator.

1.2.4.2 V DDX1, VDDX2, VSSX1, VSSX2 — External Power and Ground Pins

External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. V DDX1 and VDDX2 as well as VSSX1 and VSSX2 are not internally connected.

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1.2.4.3 V DD1, VSS1, VSS2 — Internal Logic Power Pins

Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5-V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. V SS1 and VSS2 are internally connected.

1.2.4.4 V DDA, VSSA — Power Supply Pins for ATD and VREG

VDDA, VSSA are the power supply and ground pins for the voltage regulator and the analog-to-digital converter.

1.2.4.5 V RH, VRL — ATD Reference Voltage Input Pins

VRH and VRL are the voltage reference pins for the analog-to-digital converter.

1.2.4.6 V DDPLL, VSSPLL — Power Supply Pins for PLL

Provides operating voltage and ground for the oscillator and the phased-locked loop. This allows the supply voltage to the oscillator and PLL to be bypassed independently. This 2.5-V voltage is generated by the internal voltage regulator.

1.2.4.7 V DDM1, VDDM2, VDDM3 — Power Supply Pins for Motor 0 to 3

VDDM1, VDDM2 and VDDM3 are the supply pins for the ports U, V and W. VDDM1, VDDM2 and VDDM3 are internally connected.

1.2.4.8 V SSM1, VSSM2, VSSM3 — Ground Pins for Motor 0 to 3

VSSM1, VSSM2 and VSSM3 are the ground pins for the ports U, V and W. VSSM1, VSSM2 and VSSM3 are internally connected.

1.2.4.9 V LCD — Power Supply Reference Pin for LCD driver

VLCD is the voltage reference pin for the LCD driver. Adjusting the voltage on this pin will change the display contrast.

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1.3 System Clock Description

The clock and reset generator module (CRG) provides the internal clock signals for the core and all peripheral modules. Figure 1-10 shows the clock connections from the CRG to all modules. Consult the CRG block description chapter for details on clock generation. Figure 1-10. Clock Connections The MCU’s system clock can be supplied in several ways enabling a range of system operating frequencies to be supported:

• The on-chip phase locked loop (PLL)
• the PLL self clocking
• the oscillator The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and bus clock. As shown inFigure 1-10, this system clocks are used throughout the MCU to drive the core, the memories, and the peripherals. SSD0 . . SSD5 IIC0 & IIC1 SCI0 & SCI1 CRG Bus Clock EXTAL XTAL Core Clock Oscillator Clock RAM S12X XGATE EEPROM FLASH PIT ECT PIM CAN0 & CAN1 SPILCDMC

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The program Flash memory and the EEPROM are supplied by the bus clock and the oscillator clock.The oscillator clock is used as a time base to derive the program and erase times for the NVM’s. Consult the FTX512k4 and EETX4K block description chapters for more details on the operation of the NVM’s. The CAN modules may be configured to have their clock sources derived either from the bus clock or directly from the oscillator clock. This allows the user to select its clock based on the required jitter performance. Consult MSCAN block description for more details on the operation and configuration of the CAN blocks. In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the output of the oscillator. The clock monitor can be configured to invoke the PLL self-clocking mode or to generate a system reset if it is allowed to time out as a result of no oscillator clock being present. In addition to the clock monitor, the MCU also provides a clock quality checker which performs a more accurate check of the clock. The clock quality checker counts a predetermined number of clock edges within a defined time window to insure that the clock is running. The checker can be invoked following specific events such as on wake-up or clock monitor failure.

1.4 Chip Configuration Summary

The MCU can operate in six different modes. The different modes, the state of ROMCTL and EROMCTL signal on rising edge of RESET, and the security state of the MCU affects the following device characteristics:

• External bus interface configuration
• Flash in memory map, or not
• Debug features enabled or disabled The operating mode out of reset is determined by the states of the MODC, MODB, and MODA signals during reset (seeTable 1-7). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA signals are latched into these bits on the rising edge of RESET. In normal expanded mode and in emulation modes the ROMON bit and the EROMON bit in the MMCCTL1 register defines if the on chip flash memory is the memory map, or not. (See Table 1-7.) For a detailed description of the ROMON and EROMON bits refer to the S12X_MMC Bblock description chapter. The state of the ROMCTL signal is latched into the ROMON bit in the MMCCTL1 register on the rising edge of RESET. The state of the EROMCTL signal is latched into the EROMON bit in the MISC register on the rising edge of RESET.

Chapter 1 MC9S12XHZ Family Device Overview MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 49 The configuration of the oscillator can be selected using the XCLKS signal (seeTable 1-8). For a detailed description please refer to the CRG block description chapter.

1.5 Modes of Operation

1.5.1 User Modes

1.5.1.1 Normal Expanded Mode

Ports K, A, and B are configured as a 23-bit address bus, ports C and D are configured as a 16-bit data bus, and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system. The fastest external bus rate is divide by 2 from the internal bus rate.

1.5.1.2 Normal Single-Chip Mode

There is no external bus in this mode. The processor program is executed from internal memory. Ports A, B,C,D, K, and most pins of port E are available as general-purpose I/O. Table 1-7. Chip Modes and Data Sources Chip Modes BKGD = MODC PE6 = MODB PE5 = MODA PK7 = ROMCTL PE3 = EROMCTL Data Source1 1 Internal means resources inside the MCU are read/written. Internal Flash means Flash resources inside the MCU are read/written. Emulation memory means resources inside the emulator are read/written (PRU registers, Flash replacement, RAM, EEPROM, and register space are always considered internal). External application means resources residing outside the MCU are read/written. Normal single chip 1 0 0 X X Internal Special single chip 0 0 0 Emulation single chip 0 0 1 X 0 Emulation memory X 1 Internal Flash Normal expanded 1 0 1 0 X External application

1 X Internal Flash

Emulation expanded 0 1 1 0 X External application 1 0 Emulation memory 1 1 Internal Flash Special test 0 1 0 0 X External application Table 1-8. Clock Selection Based on PE7 PE7 = XCLKS Description

0 Loop controlled Pierce oscillator selected

1 Full swing Pierce oscillator or external clock source selected

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1.5.1.3 Special Single-Chip Mode

This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug module BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external bus after reset in this mode.

1.5.1.4 Emulation of Expanded Mode

Developers use this mode for emulation systems in which the users target application is normal expanded mode. Code is executed from external memory or from internal memory depending on the state of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.

1.5.1.5 Emulation of Single-Chip Mode

Developers use this mode for emulation systems in which the user’s target application is normal single-chip mode. Code is executed from external memory or from internal memory depending on the state of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.

1.5.1.6 Special Test Mode

Freescale internal use only.

1.5.2 Low-Power Modes

The microcontroller features two main low-power modes. Consult the respective block description chapter for information on the module behavior in system stop, system pseudo stop, and system wait mode. An important source of information about the clock system is the Clock and Reset Generator (CRG) block description chapter.

1.5.2.1 System Stop Modes

The system stop modes are entered if the CPU executes the STOP instruction and the XGATE doesn’t execute a thread and the XGFACT bit in the XGMCTL register is cleared. Depending on the state of the PSTP bit in the CLKSEL register the MCU goes into pseudo stop mode or full stop mode. Please refer to CRG block description chapter. Asserting RESET, XIRQ, IRQ or any other interrupt ends the system stop modes.

1.5.2.2 Pseudo Stop Mode

In this mode the clocks are stopped but the oscillator is still running and the real time interrupt (RTI) or watchdog (COP) submodule can stay active. Other peripherals are turned off. This mode consumes more current than the system stop mode, but the wake up time from this mode is significantly shorter.

1.5.2.3 Full Stop Mode

The oscillator is stopped in this mode. All clocks are switched off. All counters and dividers remain frozen.

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1.5.2.4 System Wait Mode

This mode is entered when the CPU executes the W AI instruction. In this mode the CPU will not execute instructions. The internal CPU clock is switched off. All peripherals and the XGATE can be active in system wait mode. For further power consumption savings, the peripherals can individually turn off their local clocks. Asserting RESET, XIRQ, IRQ or any other interrupt that has not been masked ends system wait mode.

1.5.3 Freeze Mode

The enhanced capture timer, pulse width modulator, analog-to-digital converter, the periodic interrupt timer and the XGATE module provide a software programmable option to freeze the module status during the background debug module is active. This is useful when debugging application software. For detailed description of the behavior of the ATD, ECT, PWM, XGATE and PIT when the background debug module is active consult the corresponding module block description chapters.

1.6 Resets and Interrupts

Consult the S12XCPU block description chapter for information on exception processing.

1.6.1 Vectors

Table 1-9 lists all interrupt sources and vectors in the default order of priority. The interrupt module (S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each I-bit maskable service request is a configuration register. It selects if the service request is enabled, the service request priority level and whether the service request is handled either by the S12X CPU or by the XGATE module.

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Table 1-9. Interrupt Vector Locations (Sheet 1 of 3) Vector Address1 XGATE Channel ID2 Interrupt Source CCR Mask Local Enable 0xFFFE — System reset or illegal access reset None None 0xFFFC — Clock monitor reset None PLLCTL (CME, SCME) 0xFFFA — COP watchdog reset None COP rate select Vector base + 0xF8 — Unimplemented instruction trap None None Vector base+ 0xF6 — SWI None None Vector base+ 0xF4 — XIRQ X Bit None Vector base+ 0xF2 — IRQ I bit IRQCR (IRQEN) Vector base+ 0xF0 0x78 Real time interrupt I bit CRGINT (RTIE) Vector base+ 0xEE 0x77 Enhanced capture timer channel 0 I bit TIE (C0I) Vector base + 0xEC 0x76 Enhanced capture timer channel 1 I bit TIE (C1I) Vector base+ 0xEA 0x75 Enhanced capture timer channel 2 I bit TIE (C2I) Vector base+ 0xE8 0x74 Enhanced capture timer channel 3 I bit TIE (C3I) Vector base+ 0xE6 0x73 Enhanced capture timer channel 4 I bit TIE (C4I) Vector base+ 0xE4 0x72 Enhanced capture timer channel 5 I bit TIE (C5I) Vector base + 0xE2 0x71 Enhanced capture timer channel 6 I bit TIE (C6I) Vector base+ 0xE0 0x70 Enhanced capture timer channel 7 I bit TIE (C7I) Vector base+ 0xDE 0x6F Enhanced capture timer overflow I bit TSRC2 (TOF) Vector base+ 0xDC 0x6E Pulse accumulator A overflow I bit PACTL (PAOVI) Vector base + 0xDA 0x6D Pulse accumulator input edge I bit PACTL (PAI) Vector base + 0xD8 0x6C SPI I bit SPCR1 (SPIE, SPTIE) Vector base+ 0xD6 0x6B SCI0 I bit SCI0CR2 (TIE, TCIE, RIE, ILIE) Vector base + 0xD4 0x6A SCI1 I bit SCI1CR2 (TIE, TCIE, RIE, ILIE) Vector base + 0xD2 0x69 ATD I bit ATDCTL2 (ASCIE) Vector base + 0xD0 0x68 Reserved I bit Reserved Vector base + 0xCE 0x67 Port AD I bit PIEAD (PIEAD7 - PIEAD0) Vector base + 0xCC 0x66 Reserved I bit Reserved Vector base + 0xCA 0x65 Modulus down counter underflow I bit MCCTL(MCZI) Vector base + 0xC8 0x64 Pulse accumulator B overflow I bit PBCTL(PBOVI) Vector base + 0xC6 0x63 CRG PLL lock I bit CRGINT(LOCKIE) Vector base + 0xC4 0x62 CRG self-clock mode I bit CRGINT (SCMIE) Vector base + 0xC2 0x61 Reserved I bit Reserved Vector base + 0xC0 0x60 IIC0 bus I bit IB0CR (IBIE) Vector base + 0xBE 0x5F Reserved I bit Reserved

Chapter 1 MC9S12XHZ Family Device Overview MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 53 Vector base + 0xBC 0x5E Reserved I bit Reserved Vector base + 0xBA 0x5D EEPROM I bit ECNFG (CCIE, CBEIE) Vector base + 0xB8 0x5C FLASH I bit FCNFG (CCIE, CBEIE) Vector base + 0xB6 0x5B CAN0 wake-up I bit CAN0RIER (WUPIE) Vector base + 0xB4 0x5A CAN0 errors I bit CAN0RIER (CSCIE, OVRIE) Vector base + 0xB2 0x59 CAN0 receive I bit CAN0RIER (RXFIE) Vector base + 0xB0 0x58 CAN0 transmit I bit CAN0TIER (TXEIE[2:0]) Vector base + 0xAE 0x57 CAN1 wake-up I bit CAN1RIER (WUPIE) Vector base + 0xAC 0x56 CAN1 errors I bit CAN1RIER (CSCIE, OVRIE) Vector base + 0xAA 0x55 CAN1 receive I bit CAN1RIER (RXFIE) Vector base + 0xA8 0x54 CAN1 transmit I bit CAN1TIER (TXEIE[2:0]) Vector base + 0xA6 0x53 Reserved I bit Reserved Vector base + 0xA4 0x52 Reserved I bit Reserved Vector base + 0xA2 0x51 SSD4 I bit MDC4CTL (MCZIE, AOVIE) Vector base + 0xA0 0x50 SSD0 I bit MDC0CTL (MCZIE, AOVIE) Vector base + 0x9E 0x4F SSD1 I bit MDC1CTL (MCZIE, AOVIE) Vector base+ 0x9C 0x4E SSD2 I bit MDC2CTL (MCZIE, AOVIE) Vector base+ 0x9A 0x4D SSD3 I bit MDC3CTL (MCZIE, AOVIE) Vector base + 0x98 0x4C SSD5 I bit MDC5CTL (MCZIE, AOVIE) Vector base + 0x96 0x4B Motor Control Timer Overflow I bit MCCTL1 (MCOCIE) Vector base + 0x94 0x4A Reserved I bit Reserved Vector base + 0x92 0x49 Reserved I bit Reserved Vector base + 0x90 0x48 Reserved I bit Reserved Vector base + 0x8E 0x47 Reserved I bit Reserved Vector base+ 0x8C 0x46 PWM emergency shutdown I bit PWMSDN (PWMIE) Vector base + 0x8A 0x45 Reserved I bit Reserved Vector base + 0x88 0x44 Reserved I bit Reserved Vector base + 0x86 0x43 Reserved I bit Reserved Vector base + 0x84 0x42 Reserved I bit Reserved Vector base + 0x82 0x41 IIC1 Bus I bit IB1CR (IBIE) Vector base + 0x80 0x40 Low-voltage interrupt (LVI) I bit VREGCTRL (LVIE) Vector base + 0x7E 0x3F Autonomous periodical interrupt (API) I bit VREGAPICTRL (APIE) Vector base + 0x7C 0x3E Reserved I bit Reserved Vector base + 0x7A 0x3D Periodic interrupt timer channel 0 I bit PITINTE (PINTE0) Table 1-9. Interrupt Vector Locations (Sheet 2 of 3) Vector Address1 XGATE Channel ID2 Interrupt Source CCR Mask Local Enable

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1.6.2 Effects of Reset

When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module block description chapters for register reset states.

1.6.2.1 I/O Pins

Refer to the PIM block description chapter for reset configurations of all peripheral module ports.

1.6.2.2 Memory

The RAM array is not initialized out of reset.

1.7 COP Configuration

The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge of RESET from the Flash control register FCTL (0x0107) located in the Flash EEPROM block. See Table 1-10 and Table 1-11 for coding. The FCTL register is loaded from the Flash configuration field byte at global address 0x7FFF0E during the reset sequence Vector base + 0x78 0x3C Periodic interrupt timer channel 1 I bit PITINTE (PINTE1) Vector base + 0x76 0x3B Periodic interrupt timer channel 2 I bit PITINTE (PINTE2) Vector base + 0x74 0x3A Periodic interrupt timer channel 3 I bit PITINTE (PINTE3) Vector base + 0x72 0x39 XGATE software trigger 0 I bit XGMCTL (XGIE) Vector base + 0x70 0x38 XGATE software trigger 1 I bit XGMCTL (XGIE) Vector base + 0x6E 0x37 XGATE software trigger 2 I bit XGMCTL (XGIE) Vector base + 0x6C 0x36 XGATE software trigger 3 I bit XGMCTL (XGIE) Vector base + 0x6A 0x35 XGATE software trigger 4 I bit XGMCTL (XGIE) Vector base + 0x68 0x34 XGATE software trigger 5 I bit XGMCTL (XGIE) Vector base + 0x66 0x33 XGATE software trigger 6 I bit XGMCTL (XGIE) Vector base + 0x64 0x32 XGATE software trigger 7 I bit XGMCTL (XGIE) Vector base + 0x62 — XGATE software error interrupt I bit XGMCTL (XGIE) Vector base + 0x60 — S12XCPU RAM access violation I bit RAMWPC (AVIE) Vector base+ 0x12 to Vector base + 0x5E — Reserved — Reserved Vector base + 0x10 — Spurious interrupt — None 1 16 bits vector address based

2 For detailed description of XGATE channel ID refer to XGATE block description chapter

Table 1-9. Interrupt Vector Locations (Sheet 3 of 3) Vector Address1 XGATE Channel ID2 Interrupt Source CCR Mask Local Enable

Chapter 1 MC9S12XHZ Family Device Overview MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 55 NOTE If the MCU is secured the COP timeout rate is always set to the longest period (CR[2:0] = 111) after COP reset.

1.8 ATD External Trigger Input Connection

The ATD_10B16C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The external trigger feature allows the user to synchronize ATD conversion to external trigger events. Table 1-12 shows the connection of the external trigger inputs on MC9S12XHZ Family. Consult the ATD_10B16C block description chapter for information about the analog-to-digital converter module. Table 1-10. Initial COP Rate Configuration NV[2:0] in FCTL Register CR[2:0] in COPCTL Register 000 111 001 110 010 101 011 100 100 011 101 010 110 001 111 000 Table 1-11. Initial WCOP Configuration NV[3] in FCTL Register WCOP in COPCTL Register Table 1-12. ATD External Trigger Sources External Trigger Input Connectivity ETRIG0 Pulse width modulator channel 1 ETRIG1 Pulse width modulator channel 3 ETRIG2 Periodic interrupt timer hardware trigger 0 ETRIG3 Periodic interrupt timer hardware trigger 1

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MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 57 Chapter 2 Port Integration Module (S12XHZPIMV1) 2.1 lntroduction The port integration module establishes the interface between the peripheral modules including the non-multiplexed external bus interface module (S12X_EBI) and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins. This section covers:

• Port A, B and K associated with S12X_EBI module and the LCD driver
• Port C and D associated with S12X_EBI module
• Port E associated with S12X_EBI module, the IRQ, XIRQ interrupt inputs, and the LCD driver
• Port AD associated with ATD module (channels 7 through 0) and keyboard wake-up interrupts
• Port L connected to the LCD driver and ATD (channels 15 through 8) modules
• Port M connected to 2 CAN modules
• Port P connected to 1 SCI, 2 IIC and PWM modules
• Port S connected to 2 SCI and 1 SPI modules
• Port T connected to 2 IIC, 1 ECT and LCD driver modules
• Port U, V and W associated with PWM motor control and stepper stall detect modules Each I/O pin can be configured by several registers: input/output selection, drive strength reduction, enable and select of pull resistors, wired-or mode selection, interrupt enable, and/or status flags.

2.1.1 Features

A standard port has the following minimum features:

• Input/output selection
• 5-V output drive with two selectable drive strength (or slew rates)
• 5-V digital and analog input
• Input with selectable pull-up or pull-down device Optional features:
• Open drain for wired-OR connections
• Interrupt input with glitch filtering

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2.1.2 Block Diagram

Figure 2-1 is a block diagram of the S12XHZPIM Figure 2-1. S12XHZPIM Block Diagram BKGD XIRQ IRQ ECLK PA4 PA3 PA2 PA1 PA0 PA7 PA6 PA5 PB4 PB0 PB7 PB6 FP4 FP3 FP2 FP1 FP0 FP7 FP6 PE4 PE5 PE6 PE0 PE1 MISO MOSI PS4 PS5 PS0 PS1 PK3 PK0 PK1 SCK SS PS6 PS7 SPI RXCAN0 TXCAN0 PM2 PM3 DDRA DDRB PTA PTB DDRE PTEPTK DDRK PTS DDRS PTM DDRM PK2 FP12 FP11 FP10 FP9 FP8 FP15 FP14 BP0 BP1 BP2 BP3 PL3 PL2 PL1 PL0 DDRL PTL FP19 FP18 FP17 FP16 FP22 FP21 FP20 LCD Driver CAN0 MODB/TAGHI MODA/TAGLO/RE FP13 PB5 PB3 PB2 PB1 FP5 ADDR16/IQSTAT0 ADDR17/IQSTAT1 ADDR18/IQSTAT2 ADDR19/IQSTAT3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 FP24 FP25 FP26 FP27 AN2 AN6 AN0 AN7 AN1 AN3 AN4 AN5 PAD3 PAD4 PAD5 PAD6 PAD7 PAD0 PAD1 PAD2 Analog to Digital Converter DDRAD EWAIT/ROMCTL Enhanced Capture Timer PL7 PL6 PL5 PL4 FP31 FP30 FP29 FP28 Single-Wire Background Debug Module RXCAN1 TXCAN1 PM4 PM5CAN1 M0C0M M0C0P PU0 PU1 PTU DDRU PWM0 SSD0 M0C1M M0C1P PU2 PU3PWM1 M1C0M M1C0P PU4 PU5PWM2 SSD1 M1C1M M1C1P PU6 PU7PWM3 Pulse Width Modulator PW2 PW0 PW1 PW3 PW4 PW5 PP3 PP4 PP5 PP0 PP1 PP2 PTP DDRP RXD0 TXD0SCI0 AN10 AN14 AN8 AN15 AN9 AN11 AN12 AN13 AN10 AN14 AN8 AN15 AN9 AN11 AN12 AN13 KWAD2 KWAD6 KWAD0 KWAD7 KWAD1 KWAD3 KWAD4 KWAD5 M0COSM M0COSP M0SINM M0SINP M1COSM M1COSP M1SINM M1SINP PTAD M2C0M M2C0P PV0 PV1 PTV DDRV PWM4 SSD2 M2C1M M2C1P PV2 PV3PWM5 M3C0M M3C0P PV4 PV5PWM6 SSD3 M3C1M M3C1P PV6 PV7PWM7 M2COSM M2COSP M2SINM M2SINP M3COSM M3COSP M3SINM M3SINP RXD1 TXD1SCI1 PS2 PS3 SDA0 SCL0 PM1 IIC0 PP6 PP7 PK7 FP23 PC4 PC0 PC7 PC6 DDRC PTC PC5 PC3 PC2 PC1 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 PD4 PD0 PD7 PD6 DDRD PTD PD5 PD3 PD2 PD1 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 PE7 PE2 PE3 XCLKS/ECLKX2 LSTRB/LDS/EROMCTL RW/WE PT4 PT3 PT2 PT1 PT0 PT7 PT6 PT5 DDRT PTT IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 Non-Multiplexed External Bus Interface SDA1 SCL1IIC1 SDA0 SCL0 SDA1 SCL1 M4C0M M4C0P PW0 PW1 PTW DDRW PWM8 SSD4 M4C1M M4C1P PW2 PW3PWM9 M5C0M M5C0P PW4 PW5PWM10 SSD5 M5C1M M5C1P PW6 PW7PWM11 M4COSM M4COSP M4SINM M4SINP M5COSM M5COSP M5SINM M5SINP PK4 ADDR20/ACC0 PK5 ADDR21/ACC1 PK6 ADDR22/ACC2 CS1 CS3 CS0 CS2 Port Integration Module PW6 PW7 Module-to-Port-Routing

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2.2 External Signal Description

This section lists and describes the signals that connect off chip. Table 2-1 shows all the pins and their functions that are controlled by the S12XHZPIM. The order in which the pin functions are listed represents the functions priority (top – highest priority, bottom – lowest priority). Table 2-1. Detailed Signal Descriptions (Sheet 1 of 6) Port Pin Name Pin Function and Priority I/O Description Pin Function after Reset — BKGD MODC I MODC input during RESET BKGD BKGD I/O S12X_BDM communication pin A PA[7:0] ADDR[15:8] mux IVD[15:8] O High-order external bus address output (multiplexed with IVIS data) Mode dependent FP[15:8] O LCD frontplane driver GPIO I/O General-purpose I/O B PB[7:1] ADDR[7:1] mux IVD[7:1] O Low-order external bus address output (multiplexed with IVIS data) Mode dependent FP[7:1] O LCD frontplane driver GPIO I/O General-purpose I/O PB[0] ADDR0 mux IVD0 O Low-order external bus address output (multiplexed with IVIS data) UDS O Upper data strobe FP[0] O LCD frontplane driver GPIO I/O General-purpose I/O C PC[7:0] DATA[15:8] I/O High-order bidirectional data input/output Configurable for reduced input threshold Mode dependent GPIO I/O General-purpose I/O D PD[7:0] DATA[7:0] I/O Low-order bidirectional data input/output Configurable for reduced input threshold Mode dependent GPIO I/O General-purpose I/O

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E PE[7] XCLKS I External clock selection input during RESET Mode dependent ECLKX2 O Free-running clock output at Core Clock rate (ECLK x 2) FP[22] O LCD frontplane driver GPIO I/O General-purpose I/O PE[6] MODB I MODB input during RESET TAGHI I Instruction tagging low pin Configurable for reduced input threshold GPIO I/O General-purpose I/O PE[5] MODA I MODA input during RESET RE O Read enable signal TAGLO I Instruction tagging low pin Configurable for reduced input threshold GPIO I/O General-purpose I/O PE[4] ECLK O Free-running clock output at the Bus Clock rate or programmable divided in normal modes GPIO I/O General-purpose I/O PE[3] EROMCTL I EROMON bit control input during RESET LSTRB O Low strobe bar output LDS O Lower data strobe FP[21] O LCD frontplane driver GPIO I/O General-purpose I/O PE[2] R/ W O Read/write output for external bus WE O Write enable FP[20] O LCD frontplane driver GPIO I/O General-purpose I/O PE[1] IRQ I Maskable level or falling edge-sensitive interrupt input GPIO I/O General-purpose I/O PE[0] XIRQ I Non-maskable level-sensitive interrupt input GPIO I/O General-purpose I/O K PK[7] ROMCTL I ROMON bit control input during RESET Mode dependent EWAIT I External Wait signal Configurable for reduced input threshold FP[23] O LCD frontplane driver GPIO I/O General-purpose I/O PK[6:4] ADDR[22:20] mux ACC[2:0] O Extended external bus address output (multiplexed with master access output) GPIO I/O General-purpose I/O PK[3:0] ADDR[19:16] mux IQSTAT[3:0] O Extended external bus address output (multiplexed with instruction pipe status bits) BP[3:0] O LCD backplane driver GPIO I/O General-purpose I/O AD PAD[7:0] AN[7:0] I Analog-to-digital converter input channel GPIO KWAD[7:0] I Keyboard wake-up interrupt GPIO I/O General-purpose I/O Table 2-1. Detailed Signal Descriptions (Sheet 2 of 6) Port Pin Name Pin Function and Priority I/O Description Pin Function after Reset

Chapter 2 Port Integration Module (S12XHZPIMV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 61 L PL[7:4] FP[31:28] O LCD frontplane driver GPIO AN[15:12] I Analog-to-digital converter input channel GPIO I/O General-purpose I/O PL[3:0] FP[19:16] O LCD frontplane driver AN[11:8] I Analog-to-digital converter input channel GPIO I/O General-purpose I/O M PM[5] TXCAN1 O MSCAN1 transmit pin GPIO GPIO I/O General-purpose I/O PM[4] RXCAN1 I MSCAN1 receive pin GPIO I/O General-purpose I/O PM[3] TXCAN0 O MSCAN0 transmit pin GPIO I/O General-purpose I/O PM[2] RXCAN0 I MSCAN0 receive pin GPIO O General-purpose I/O PM[1] CS1 O Chip select 1 GPIO I/O General-purpose I/O P PP[7] CS2 O Chip select 2 GPIO PWM7 I/O Pulse-width modulator channel 7 and emergency shutdown input SCL1 I/O Inter-integrated circuit 1 serial clock line GPIO I/O General-purpose I/O PP[6] CS0 O Chip select 0 PWM6 O Pulse-width modulator channel 6 SDA1 I/O Inter-integrated circuit 1 serial data line GPIO I/O General-purpose I/O PP[5] PWM5 I/O Pulse-width modulator channel 5 and emergency shutdown input SCL0 I/O Inter-integrated circuit 0 serial clock line GPIO I/O General-purpose I/O PP[4] PWM4 O Pulse-width modulator channel 4 SDA0 I/O Inter-integrated circuit 0 serial data line GPIO I/O General-purpose I/O PP[3] PWM3 O Pulse-width modulator channel 3 GPIO I/O General-purpose I/O PP[2] PWM2 O Pulse-width modulator channel 2 RXD1 I Serial communication interface 1 receive pin GPIO I/O General-purpose I/O PP[1] PWM1 O Pulse-width modulator channel 1 GPIO I/O General-purpose I/O PP[0] PWM0 O Pulse-width modulator channel 0 TXD1 O Serial communication interface 1 transmit pin GPIO I/O General-purpose I/O Table 2-1. Detailed Signal Descriptions (Sheet 3 of 6) Port Pin Name Pin Function and Priority I/O Description Pin Function after Reset

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S PS[7] SS I/O Serial peripheral interface slave select input/output in master mode, input in slave mode GPIO GPIO I/O General-purpose I/O PS[6] SCK I/O Serial peripheral interface serial clock pin GPIO I/O General-purpose I/O PS[5] MOSI I/O Serial peripheral interface master out/slave in pin GPIO I/O General-purpose I/O PS[4] MISO I/O Serial peripheral interface master in/slave out pin GPIO I/O General-purpose I/O PS[3] TXD1 O Serial communication interface 1 transmit pin GPIO I/O General-purpose I/O PS[2] CS3 O Chip select 3 RXD1 I Serial communication interface 1 receive pin GPIO I/O General-purpose I/O PS[1] TXD0 O Serial communication interface 0 transmit pin GPIO I/O General-purpose I/O PS[0] RXD0 I Serial communication interface 0 receive pin GPIO I/O General-purpose I/O T PT[7] IOC7 I/O Timer channel GPIO SCL1 I/O Inter-integrated circuit 1 serial clock line GPIO I/O General-purpose I/O PT[6] IOC7 I/O Timer channel SDA1 I/O Inter-integrated circuit 1 serial data line GPIO I/O General-purpose I/O PT[5] IOC5 I/O Timer channel SCL0 I/O Inter-integrated circuit 0 serial clock line GPIO I/O General-purpose I/O PT[4] IOC4 I/O Timer channel SDA0 I/O Inter-integrated circuit 0 serial data line GPIO I/O General-purpose I/O PT[3:0] FP[27:24] I/O LCD frontplane driver IOC[3:0] I/O Timer channel GPIO I/O General-purpose I/O Table 2-1. Detailed Signal Descriptions (Sheet 4 of 6) Port Pin Name Pin Function and Priority I/O Description Pin Function after Reset

Chapter 2 Port Integration Module (S12XHZPIMV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 63 U PU[7] M1SINP O SSD1 Sine+ Node GPIO M1C1P O PWM motor controller channel 3 GPIO I/O General-purpose I/O PU[6] M1SINM O SSD1 Sine- Node M1C1M O PWM motor controller channel 3 GPIO I/O General-purpose I/O PU[5] M1COSP O SSD1 Cosine+ Node M1C0P O PWM motor controller channel 2 GPIO I/O General-purpose I/O PU[4] M1COSM O SSD1 Cosine- Node M1C0M O PWM motor controller channel 2 GPIO I/O General-purpose I/O PU[3] M0SINP O SSD0 Sine+ Node M0C1P O PWM motor controller channel 1 GPIO I/O General-purpose I/O PU[2] M0SINM O SSD0 Sine- Node M0C1M O PWM motor controller channel 1 GPIO I/O General-purpose I/O PU[1] M0COSP O SSD0 Cosine+ Node M0C0P O PWM motor controller channel 0 GPIO I/O General-purpose I/O PU[0] M0COSM O SSD0 Cosine- Node M0C0M O PWM motor controller channel 0 GPIO I/O General-purpose I/O V PV[7] M3SINP O SSD3 sine+ node GPIO M3C1P O PWM motor controller channel 7 GPIO I/O General-purpose I/O PV[6] M3SINM O SSD3 sine- node M3C1M O PWM motor controller channel 7 GPIO I/O General-purpose I/O PV[5] M3COSP O SSD3 cosine+ node M3C0P O PWM motor controller channel 6 GPIO I/O General-purpose I/O PV[4] M3COSM O SSD3 cosine- node M3C0M O PWM motor controller channel 6 GPIO I/O General-purpose I/O PV[3] M2SINP O SSD2 sine+ node M2C1P O PWM motor controller channel 5 GPIO I/O General-purpose I/O PV[2] M2SINM O SSD2 sine- node M2C1M O PWM motor controller channel 5 GPIO I/O General-purpose I/O PV[1] M2COSP O SSD2 cosine+ node M2C0P O PWM motor controller channel 4 GPIO I/O General-purpose I/O PV[0] M2COSM O SSD2 cosine- node M2C0M O PWM motor controller channel 4 GPIO I/O General-purpose I/O Table 2-1. Detailed Signal Descriptions (Sheet 5 of 6) Port Pin Name Pin Function and Priority I/O Description Pin Function after Reset

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W PW[7] M5SINP O SSD5 sine+ node GPIO M5C1P O PWM motor controller channel 11 GPIO I/O General-purpose I/O PW[6] M5SINM O SSD5 sine- node M5C1M O PWM motor controller channel 11 GPIO I/O General-purpose I/O PW[5] M5COSP O SSD5 cosine+ node M5C0P O PWM motor controller channel 10 GPIO I/O General-purpose I/O PW[4] M5COSM O SSD5 cosine- node M5C0M O PWM motor controller channel 10 GPIO I/O General-purpose I/O PW[3] M4SINP O SSD4 sine+ node M4C1P O PWM motor controller channel 9 GPIO I/O General-purpose I/O PW[2] M4SINM O SSD4 sine- node M4C1M O PWM motor controller channel 9 GPIO I/O General-purpose I/O PW[1] M4COSP O SSD4 cosine+ node M4C0P O PWM motor controller channel 8 GPIO I/O General-purpose I/O PW[0] M4COSM O SSD4 cosine- node M4C0M O PWM motor controller channel 8 GPIO I/O General-purpose I/O Table 2-1. Detailed Signal Descriptions (Sheet 6 of 6) Port Pin Name Pin Function and Priority I/O Description Pin Function after Reset

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2.3 Memory Map and Register Definition

This section provides a detailed description of all registers. Table 2-2 is a standard memory map of port integration module. Table 2-2. S12XHZPIM Memory Map Address Offset Use Access 0x0000 Port A I/O Register (PTA) R/W 0x0001 Port B I/O Register (PTB) R/W 0x0002 Port A Data Direction Register (DDRA) R/W 0x0003 Port B Data Direction Register (DDRB) R/W 0x0004 Port C I/O Register (PTC) R/W 0x0005 Port D I/O Register (PTD) R/W 0x0006 Port C Data Direction Register (DDRC) R/W 0x0007 Port D Data Direction Register (DDRD) R/W 0x0008 Port E I/O Register (PTE) R/W 0x0009 Port E Data Direction Register (DDRE) R/W 0x000A - 0x000B Non-PIM address range — 0x000C Pull Up/Down Control Register (PUCR) R/W 0x000D Reduced Drive Register (RDRIV) R/W 0x000E - 0x001B Non-PIM address range — 0x001C ECLK Control Register (ECLKCR) R/W 0x001D Reserved — 0x001E IRQ Control Register (IRQCR) R/W 0x001F Slew Rate Control Register (SRCR) R/W 0x0020 - 0x0031 Non-PIM address range — 0x0032 Port K I/O Register (PTK) R/W 0x0033 Port K Data Direction Register (DDRK) R/W 0x0034 - 0x01FF Non-PIM address range — 0x0200 Port T I/O Register (PTT) R/W 0x0201 Port T Input Register (PTIT) R 0x0202 Port T Data Direction Register (DDRT) R/W 0x0203 Port T Reduced Drive Register (RDRT) R/W 0x0204 Port T Pull Device Enable Register (PERT) R/W 0x0205 Port T Polarity Select Register (PPST) R/W 0x0206 Port T Wired-OR Mode Register (WOMT) R/W 0x0207 Port T Slew Rate Register (SRRT) R/W

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0x0208 Port S I/O Register (PTS) R/W 0x0209 Port S Input Register (PTIS) R 0x020A Port S Data Direction Register (DDRS) R/W 0x020B Port S Reduced Drive Register (RDRS) R/W 0x020C Port S Pull Device Enable Register (PERS) R/W 0x020D Port S Polarity Select Register (PPSS) R/W 0x020E Port S Wired-OR Mode Register (WOMS) R/W 0x020F Port S Slew Rate Register (SRRS) R/W 0x0210 Port M I/O Register (PTM) R/W 0x0211 Port M Input Register (PTIM) R 0x0212 Port M Data Direction Register (DDRM) R/W 0x0213 Port M Reduced Drive Register (RDRM) R/W 0x0214 Port M Pull Device Enable Register (PERM) R/W 0x0215 Port M Polarity Select Register (PPSM) R/W 0x0216 Port M Wired-OR Mode Register (WOMM) R/W 0x0217 Port M Slew Rate Register (SRRM) R/W 0x0218 Port P I/O Register (PTP) R/W 0x0219 Port P Input Register (PTIP) R 0x021A Port P Data Direction Register (DDRP) R/W 0x021B Port P Reduced Drive Register (RDRP) R/W 0x021C Port P Pull Device Enable Register (PERP) R/W 0x021D Port P Polarity Select Register (PPSP) R/W 0x021E Port P Wired-OR Mode Register (WOMP) R/W 0x021F Port P Slew Rate Register (SRRP) R/W 0x0220 - 0x022F Reserved — 0x0230 Port L I/O Register (PTL) R/W 0x0231 Port L Input Register (PTIL) R 0x0232 Port L Data Direction Register (DDRL) R/W 0x0233 Port L Reduced Drive Register (RDRL) R/W 0x0234 Port L Pull Device Enable Register (PERL) R/W 0x0235 Port L Polarity Select Register (PPSL) R/W 0x0236 Reserved — 0x0237 Port L Slew Rate Register (SRRL) R/W 0x0238 Port U I/O Register (PTU) R/W 0x0239 Port U Input Register (PTIU) R 0x023A Port U Data Direction Register (DDRU) R/W 0x023B Port U Slew Rate Register (SRRU) R/W 0x023C Port U Pull Device Enable Register (PERU) R/W 0x023D Port U Polarity Select Register (PPSU) R/W 0x023E - 0x023F Reserved — Table 2-2. S12XHZPIM Memory Map (continued) Address Offset Use Access

Chapter 2 Port Integration Module (S12XHZPIMV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 67 0x0240 Port V I/O Register (PTV) R/W 0x0241 Port V Input Register (PTIV) R 0x0242 Port V Data Direction Register (DDRV) R/W 0x0243 Port V Slew Rate Register (SRRV) R/W 0x0244 Port V Pull Device Enable Register (PERV) R/W 0x0245 Port V Polarity Select Register (PPSV) R/W 0x0246 - 0x0247 Reserved — 0x0248 Port W I/O Register (PTW) R/W 0x0249 Port W Input Register (PTIW) R 0x024A Port W Data Direction Register (DDRW) R/W 0x024B Port W Slew Rate Register (SRRW) R/W 0x024C Port W Pull Device Enable Register (PERW) R/W 0x024D Port W Polarity Select Register (PPSW) R/W 0x024E - 0x0250 Reserved — 0x0251 Port AD I/O Register (PTAD) R/W 0x0252 Reserved — 0x0253 Port AD Input Register (PTIAD) R 0x0254 Reserved — 0x0255 Port AD Data Direction Register (DDRAD) R/W 0x0256 Reserved — 0x0257 Port AD Reduced Drive Register (RDRAD) R/W 0x0258 Reserved — 0x0259 Port AD Pull Device Enable Register (PERAD) R/W 0x025A Reserved — 0x025B Port AD Polarity Select Register (PPSAD) R/W 0x025C Reserved — 0x025D Port AD Interrupt Enable Register (PIEAD) R/W 0x025E Reserved — 0x025F Port AD Interrupt Flag Register (PIFAD) R/W 0x0260 - 0x027F Reserved — Table 2-2. S12XHZPIM Memory Map (continued) Address Offset Use Access

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2.3.1 Port A and Port B

Port A and port B are associated with the external address bus outputs ADDR15-ADDR0, the external read visibility IVD15-IVD0 and the liquid crystal display (LCD) driver. Each pin is assigned to these functions according to the following priority: LCD Driver > XEBI > general-purpose I/O. If the corresponding LCD frontplane drivers are enabled (and LCD module is enabled), the FP[15:0] outputs of the LCD module are available on port B and port A pins. Refer to the LCD block description chapter for information on enabling and disabling the LCD and its frontplane drivers.Refer to the S12X_EBI block description chapter for information on external bus. During reset, port A and port B pins are configured as inputs with pull down.

2.3.1.1 Port A I/O Register (PTA)

Read: Anytime. Write: Anytime. If the associated data direction bit (DDRAx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRAx) is set to 0 (input) and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTAx) reads “1”. If the associated data direction bit (DDRAx) is set to 0 (input) and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin. Module Base + 0x0051 76543210 R PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 W XEBI: ADDR15 mux IVD15 ADDR14 mux IVD14 ADDR13 mux IVD13 ADDR12 mux IVD12 ADDR11 mux IVD11 ADDR10 mux IVD10 ADDR9 mux IVD9 ADDR8 mux IVD8 LCD: FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 Reset 0 0 0 00000 Figure 2-2. Port A I/O Register (PTA)

Chapter 2 Port Integration Module (S12XHZPIMV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 69

2.3.1.2 Port B I/O Register (PTB)

Read: Anytime. Write: Anytime. If the associated data direction bit (DDRBx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRBx) is set to 0 (input) and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTBx) reads “1”. If the associated data direction bit (DDRBx) is set to 0 (input) and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin.

2.3.1.3 Port A Data Direction Register (DDRA)

Read: Anytime. Write: Anytime. This register configures port pins PA[7:0] as either input or output.If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. Module Base + 0x0051 76543210 R PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 W XEBI: ADDR7 mux IVD7 ADDR6 mux IVD6 ADDR5 mux IVD5 ADDR4 mux IVD4 ADDR3 mux IVD3 ADDR2 mux IVD2 ADDR1 mux IVD1 ADDR0 mux IVD0 or UDS LCD: FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 Reset 0 0 0 00000 Figure 2-3. Port B I/O Register (PTB) Module Base + 0x0055 76543210 R DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 W Reset 0 0 0 00000 Figure 2-4. Port A Data Direction Register (DDRA)

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2.3.1.4 Port B Data Direction Register (DDRB)

Read: Anytime. Write: Anytime. This register configures port pins PB[7:0] as either input or output.If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. Table 2-3. DDRA Field Descriptions Field Description 7:0 DDRA[7:0] Data Direction Port A 0 Associated pin is configured as input. 1 Associated pin is configured as output. Module Base + 0x0055 76543210 R DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 W Reset 0 0 0 00000 Figure 2-5. Port B Data Direction Register (DDRB) Table 2-4. DDRB Field Descriptions Field Description 7:0 DDRB[7:0] Data Direction Port B 0 Associated pin is configured as input. 1 Associated pin is configured as output.

Chapter 2 Port Integration Module (S12XHZPIMV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 71

2.3.2 Port C and Port D

Port C and port D pins can be used for either general-purpose I/O or the external data bus input/outputs DATA15-DATA0. Refer to the S12X_EBI block description chapter for information on external bus.

2.3.2.1 Port C I/O Register (PTC)

Read: Anytime. Write: Anytime. If the data direction bit of the associated I/O pin (DDRCx) is set to 1 (output), a write to the corresponding I/O Register bit sets the value to be driven to the Port C pin. If the data direction bit of the associated I/O pin (DDRCx) is set to 0 (input), a write to the corresponding I/O Register bit takes place but has no effect on the Port C pin. If the associated data direction bit (DDRCx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRCx) is set to 0 (input), a read returns the value of the pin.

2.3.2.2 Port D I/O Register (PTD)

Read: Anytime. Write: Anytime. If the data direction bit of the associated I/O pin (DDRDx) is set to 1 (output), a write to the corresponding I/O Register bit sets the value to be driven to the Port D pin. If the data direction bit of the associated I/O pin (DDRDx) is set to 0 (input), a write to the corresponding I/O Register bit takes place but has no effect on the Port D pin. If the associated data direction bit (DDRDx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRDx) is set to 0 (input), a read returns the value of the pin. Module Base + 0x0051 76543210 R PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 W XEBI: DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 Reset 0 0 0 00000 Figure 2-6. Port C I/O Register (PTC) Module Base + 0x0051 76543210 R PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 W XEBI: DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Reset 0 0 0 00000 Figure 2-7. Port D I/O Register (PTD)

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2.3.2.3 Port C Data Direction Register (DDRC)

Read: Anytime. Write: Anytime. This register configures port pins PC[7:0] as either input or output.

2.3.2.4 Port D Data Direction Register (DDRD)

Read: Anytime. Write: Anytime. This register configures port pins PD[7:0] as either input or output. Module Base + 0x0055 76543210 R DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 W Reset 0 0 0 00000 Figure 2-8. Port C Data Direction Register (DDRC) Table 2-5. DDRC Field Descriptions Field Description 7:0 DDRC[7:0] Data Direction Port C 0 Associated pin is configured as input. 1 Associated pin is configured as output. Module Base + 0x0055 76543210 R DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 W Reset 0 0 0 00000 Figure 2-9. Port D Data Direction Register (DDRD) Table 2-6. DDRD Field Descriptions Field Description 7:0 DDRD[7:0] Data Direction Port D 0 Associated pin is configured as input. 1 Associated pin is configured as output.

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2.3.3 Port E

Port E pins can be used for either general-purpose I/O, or the liquid crystal display (LCD) driver, or the external bus control outputs R/W, WE, LSTRB, LDS and RE, the free running clock outputs ECLK and ECLKX2, or the inputs TAGHI, TAGLO, MODA, MODB, EROMCTL, XCLKS and interrupts IRQ and XIRQ. Refer to the LCD block description chapter for information on enabling and disabling the LCD and its frontplane drivers. Refer to the S12X_EBI block description chapter for information on external bus. Port E pin PE[7] can be used for either general-purpose I/O, or as the free-running clock ECLKX2 output running at the core clock rate, or the frontplane driver FP22. The clock ECLKX2 output is always enabled in emulation modes. Port E pin PE[4] can be used for either general-purpose I/O or as the free-running clock ECLK output running at the bus clock rate or at the programmed divided clock rate. The clock output is always enabled in emulation modes. Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ interrupt inpu. IRQ will be enabled by setting the IRQEN configuration bit and clearing the I-bit in the CPU’s condition code register. It is inhibited at reset so this pin is initially configured as a simple input with a pull-up. Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ interrupt input. XIRQ can be enabled by clearing the X-bit in the CPU’s condition code register. It is inhibited at reset so this pin is initially configured as a high-impedance input with a pull-up.

2.3.3.1 Port E I/O Register (PTE)

Read: Anytime. Write: Anytime. If the associated data direction bit (DDREx) is set to 1 (output), a read returns the value of the I/O register bit. Module Base + 0x0051 76543210 R PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 W XEBI: XCLKS 1 or ECLKX2 1 Function active when RESET asserted. MODB1 or TAGHI MODA1 or TAGLO or RE ECLK EROMCTL1 or LSTRB or LDS R/W or WE IRQ XIRQ LCD: FP22 FP21 FP20 Reset 0 0 0 0 0 0 — 2 2 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. — 2 Figure 2-10. Port E I/O Register (PTE)

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If the associated data direction bit (DDREx) is set to 0 (input) and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTEx) reads “1”. If the associated data direction bit (DDREx) is set to 0 (input) and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin.

2.3.3.2 Port E Data Direction Register (DDRE)

Read: Anytime. Write: Anytime. This register configures port pins PE[7:0] as either input or output.If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. Module Base + 0x0055 76543210 R DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 W Reset 0 0 0 00000 = Reserved or Unimplemented Figure 2-11. Port E Data Direction Register (DDRE) Table 2-7. DDRE Field Descriptions Field Description 7:2 DDRE[7:2] Data Direction Port E 0 Associated pin is configured as input. 1 Associated pin is configured as output.

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2.3.4 Port K

Port K pins can be used for either general-purpose I/O, or the liquid crystal display (LCD) driver, or the external address bus outputs ADDR22-ADDR16 muxed with master access output ACC2-ACC0 and instruction pipe signals IQSTAT3-IQSTAT0, or inputs EWAIT and ROMCTL. Refer to the LCD block description chapter for information on enabling and disabling the LCD and its frontplane drivers. Refer to the S12X_EBI block description chapter for information on external bus.

2.3.4.1 Port K I/O Register (PTK)

Read: Anytime. Write: Anytime. If the associated data direction bit (DDRKx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRKx) is set to 0 (input) and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTKx) reads “1”. If the associated data direction bit (DDRKx) is set to 0 (input) and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin.

2.3.4.2 Port K Data Direction Register (DDRK)

Read: Anytime. Write: Anytime. Module Base + 0x0051 76543210 R PTK7 PTK6 PTK5 PTK4 PTK3 PTK2 PTK1 PTK0 W XEBI: ROMCTL 1 or EWAIT 1 Function active when RESET asserted. ADDR22 or ACC2 ADDR21 or ACC1 ADDR20 or ACC0 ADDR19 or IQSTAT3 ADDR18 or IQSTAT2 ADDR17 or IQSTAT1 ADDR16 or IQSTAT0 LCD: FP23 BP3 BP2 BP1 BP0 Reset 0 0 0 0 0000 Figure 2-12. Port K I/O Register (PTK) Module Base + 0x0055 76543210 R DDRK7 DDRK6 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0 W Reset 0 0 0 00000 Figure 2-13. Port K Data Direction Register (DDRK)

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This register configures port pins PK[7:0] as either input or output.If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. Table 2-8. DDRK Field Descriptions Field Description 7:0 DDRK[7:0] Data Direction Port K 0 Associated pin is configured as input. 1 Associated pin is configured as output.

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2.3.5 Miscellaneous registers

2.3.5.1 Pull Up/Down Control Register (PUCR)

Read: Anytime. Write: Anytime except BKPUE which is writable in special test mode only. This register is used to enable pull up/down devices for the associated ports A, B, C, D, E and K. Pull up/down devices are assigned on a per-port basis and apply to any pin in the corresponding port currently configured as an input. Module Base + 0x0055 76543210 R PUPKE BKGPE PUPEE PUPDE PUPCE PUPBE PUPAE W Reset 1 1 0 10011 Figure 2-14. Pull Up/Down Control Register (PUCR) Table 2-9. PUCR Field Descriptions Field Description PUPKE Pull-down Port K Enable 0 Port K pull-down devices are disabled. 1 Enable pull-down devices for Port K input pins. BKPUE BKGD Pin Pull-up Enable 0 BKGD pull-up device is disabled. 1 Enable pull-up device on BKGD pin. PUPEE Pull Port E Enable 0 Port E pull-down devices on pins 7, 4–2 are disabled. Port E pull-up devices on pins 1–0 are disabled. 1 Enable pull-down devices for Port E input pins 7, 4–2. Enable pull-up devices for Port E input pins 1–0. Note: Bits 5 and 6 of Port E have pull-down devices which are only enabled during reset. This bit has no effect on these pins. PUPDE Pull-up Port D Enable 0 Port D pull-up devices are disabled. 1 Enable pull-up devices for all Port D input pins. PUPCE Pull-up Port C Enable 0 Port C pull-up devices are disabled. 1 Enable pull-up devices for all Port C. PUPBE Pull-down Port B Enable 0 Port B pull-down devices are disabled. 1 Enable pull-down devices for all Port B input pins. PUPAE Pull-down Port A Enable 0 Port A pull-down devices are disabled. 1 Enable pull-down devices for all Port A input pins.

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2.3.5.2 Reduced Drive Register (RDRIV)

Read: Anytime. Write: Anytime. This register is used to select reduced drive for the pins associated with ports A, B, C, D, E, and K. If enabled, the pins drive at about 1/6 of the full drive strength. The reduced drive function is independent of which function is being used on a particular pin. The reduced drive functionality does not take effect on the pins in emulation modes. Module Base + 0x0055 76543210 R RDPK RDPE RDPD RDPC RDPB RDPA W Reset 0 0 0 00000 = Reserved or Unimplemented Figure 2-15. Reduced Drive Register (RDRIV) Table 2-10. RDRIV Field Descriptions Field Description RDPK Reduced Drive of Port K 0 All port K output pins have full drive enabled. 1 All port K output pins have reduced drive enabled. RDPE Reduced Drive of Port E 0 All port E output pins have full drive enabled. 1 All port E output pins have reduced drive enabled. RDPD Reduced Drive of Port D 0 All port D output pins have full drive enabled. 1 All port D output pins have reduced drive enabled. RDPC Reduced Drive of Port C 0 All Port C output pins have full drive enabled. 1 All port C output pins have reduced drive enabled. RDPB Reduced Drive of Port B 0 All port B output pins have full drive enabled. 1 All port B output pins have reduced drive enabled. RDPA Reduced Drive of Port A 0 All Port A output pins have full drive enabled. 1 All port A output pins have reduced drive enabled.

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2.3.5.3 ECLK Control Register (ECLKCR)

Read: Anytime. Write: Anytime. The ECLKCTL register is used to control the availability of the free-running clocks and the free-running clock divider. Module Base + 0x0055 76543210 R NECLK NCLKX2 0000 EDIV1 EDIV0 W Reset 0 1 1 NECLK reset value is 1 in emulation single-chip and normal single-chip modes. 1000000 = Reserved or Unimplemented Figure 2-16. ECLK Control Register (ECLKCR) Table 2-11. ECLKCTL Field Descriptions Field Description NECLK No ECLK — This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always active in emulation modes and if enabled in all other operating modes.

0 ECLK enabled

1 ECLK disabled

No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other operating modes.

0 ECLKX2 is enabled

1 ECLKX2 is disabled

1–0 EDIV[1:0] Free-Running ECLK Divider — These bits determine the rate of the free-running clock on the ECLK pin r. The usage of the bits is shown in Table 2-12. Divider is always disabled in emulation modes and active as programmed in all other operating modes. Table 2-12. Free-Running ECLK Clock Rate EDIV[1:0] Rate of Free-Running ECLK

00 ECLK = Bus clock rate

01 ECLK = Bus clock rate divided by 2

10 ECLK = Bus clock rate divided by 3

11 ECLK = Bus clock rate divided by 4

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2.3.5.4 IRQ Control Register (IRQCR)

Read: See individual bit descriptions below. Write: See individual bit descriptions below. Module Base + 0x0055 76543210 R IRQE IRQEN 000000 W Reset 0 1 0 00000 = Reserved or Unimplemented Figure 2-17. Port E Data Direction Register (DDRE) Table 2-13. IRQCR Field Descriptions Field Description IRQE IRQ Select Edge Sensitive Only Special modes: Read or write anytime. Normal and emulation modes: Read anytime, write once. IRQ configured for low level recognition. 1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1. The edge detector is cleared only upon the servicing of the IRQ interrupt or a reset . IRQEN External IRQ Enable Read or write anytime.

0 External

IRQ pin is disconnected from interrupt logic. 1 External IRQ pin is connected to interrupt logic.

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2.3.5.5 Slew Rate Control Register (SRCR)

Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for the pins associated with ports A, B, C, D, E, and K. Module Base + 0x0055 76543210 R SRRK SRRE SRRD SRRC SRRB SRRA W Reset 0 0 0 00000 = Reserved or Unimplemented Figure 2-18. Slew Rate Control Register (SRCR) Table 2-14. SRCR Field Descriptions Field Description SRRK Slew Rate of Port K 0 Disables slew rate control and enables digital input buffer for all port K pins. 1 Enables slew rate control and disables digital input buffer for all port K pins. SRRE Slew Rate of Port E 0 Disables slew rate control and enables digital input buffer for all port E pins. 1 Enables slew rate control and disables digital input buffer for all port E pins. SRRD Slew Rate of Port D 0 Disables slew rate control and enables digital input buffer for all port D pins. 1 Enables slew rate control and disables digital input buffer for all port D pins. SRRC Slew Rate of Port C 0 Disables slew rate control and enables digital input buffer for all port C pins. 1 Enables slew rate control and disables digital input buffer for all port C pins. SRRB Slew Rate of Port B 0 Disables slew rate control and enables digital input buffer for all port B pins. 1 Enables slew rate control and disables digital input buffer for all port B pins. SRRA Slew Rate of Port A 0 Disables slew rate control and enables digital input buffer for all port A pins. 1 Enables slew rate control and disables digital input buffer for all port A pins.

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2.3.6 Port AD

Port AD is associated with the analog-to-digital converter (ATD) and keyboard wake-up (KWU) interrupts . Each pin is assigned to these modules according to the following priority: ATD > KWU > general-purpose I/O. For the pins of port AD to be used as inputs, the corresponding bits of the ATDDIEN1 register in the ATD module must be set to 1 (digital input buffer is enabled). The ATDDIEN1 register does not affect the port AD pins when they are configured as outputs. Refer to the ATD block description chapter for information on the ATDDIEN1 register. During reset, port AD pins are configured as high-impedance analog inputs (digital input buffer is disabled).

2.3.6.1 Port AD I/O Register (PTAD)

Read: Anytime. Write: Anytime. If the data direction bit of the associated I/O pin (DDRADx) is set to 1 (output), a write to the corresponding I/O Register bit sets the value to be driven to the Port AD pin. If the data direction bit of the associated I/O pin (DDRADx) is set to 0 (input), a write to the corresponding I/O Register bit takes place but has no effect on the Port AD pin. If the associated data direction bit (DDRADx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN1 bits is set to 0 (digital input buffer is disabled), the associated I/O register bit (PTADx) reads “1”. If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN1 bits is set to 1 (digital input buffer is enabled), a read returns the value of the pin. Module Base + 0x0051 76543210 R PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 W KWU: KWAD7 KWAD6 KWAD5 KWAD4 KWAD3 KWAD2 KWAD1 KWAD0 ATD: AN7 AN6 AN55 AN4 AN3 AN2 AN1 AN0 Reset 0 0 0 00000 Figure 2-19. Port AD I/O Register (PTAD)

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2.3.6.2 Port AD Input Register (PTIAD)

Read: Anytime. Write: Never; writes to these registers have no effect. If the ATDDIEN1 bit of the associated I/O pin is set to 0 (digital input buffer is disabled), a read returns a 1. If the ATDDIEN1 bit of the associated I/O pin is set to 1 (digital input buffer is enabled), a read returns the status of the associated pin.

2.3.6.3 Port AD Data Direction Register (DDRAD)

Read: Anytime. Write: Anytime. This register configures port pins PAD[7:0] as either input or output. If a data direction bit is 0 (pin configured as input), then a read value on PTADx depends on the associated ATDDIEN1 bit. If the associated ATDDIEN1 bit is set to 1 (digital input buffer is enabled), a read on PTADx returns the value on port AD pin. If the associated ATDDIEN1 bit is set to 0 (digital input buffer is disabled), a read on PTADx returns a 1. Module Base + 0x0053 76543210 R PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIAD0 W Reset 1 1 1 11111 = Reserved or Unimplemented Figure 2-20. Port AD Input Register (PTIAD) Module Base + 0x0055 76543210 R DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0 W Reset 0 0 0 00000 Figure 2-21. Port AD Data Direction Register (DDRAD) Table 2-15. DDRAD Field Descriptions Field Description 7:0 DDRAD[7:0] Data Direction Port AD 0 Associated pin is configured as input. 1 Associated pin is configured as output.

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2.3.6.4 Port AD Reduced Drive Register (RDRAD)

Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.

2.3.6.5 Port AD Pull Device Enable Register (PERAD)

Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect. Module Base + 0x0057 76543210 R RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0 W Reset 0 0 0 00000 Figure 2-22. Port AD Reduced Drive Register (RDRAD) Table 2-16. RDRAD Field Descriptions Field Description 7:0 RDRAD[7:0] Reduced Drive Port A 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. Module Base + 0x0059 76543210 R PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0 W Reset 0 0 0 00000 Figure 2-23. Port AD Pull Device Enable Register (PERAD) Table 2-17. PERAD Field Descriptions Field Description 7:0 PERAD[7:0] Pull Device Enable Port AD 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled.

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2.3.6.6 Port AD Polarity Select Register (PPSAD)

Read: Anytime. Write: Anytime. The Port AD Polarity Select Register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled (PERADx = 1). The Port AD Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input). In pull-down mode (PPSADx = 1), a rising edge on a port AD pin sets the corresponding PIFADx bit. In pull-up mode (PPSADx = 0), a falling edge on a port AD pin sets the corresponding PIFADx bit.

2.3.6.7 Port AD Interrupt Enable Register (PIEAD)

Read: Anytime. Write: Anytime. This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port AD. Module Base + 0x005B 76543210 R PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0 W Reset 0 0 0 00000 Figure 2-24. Port AD Polarity Select Register (PPSAD) Table 2-18. PPSAD Field Descriptions Field Description 7:0 PPSAD[7:0] Polarity Select Port AD 0 A pull-up device is connected to the associated port AD pin, and detects falling edge for interrupt generation.

1 A pull-down device is connected to the associated port AD pin, and detects rising edge for interrupt

generation. Module Base + 0x005D 76543210 R PIEAD7 PIEAD6 PIEAD5 PIEAD4 PIEAD3 PIEAD2 PIEAD1 PIEAD0 W Reset 0 0 0 00000 Figure 2-25. Port AD Interrupt Enable Register (PIEAD) Table 2-19. PIEAD Field Descriptions Field Description 7:0 PIEAD[7:0] Interrupt Enable Port AD 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled.

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2.3.6.8 Port AD Interrupt Flag Register (PIFAD)

Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. The active edge could be rising or falling based on the state of the corresponding PPSADx bit. To clear each flag, write “1” to the corresponding PIFADx bit. Writing a “0” has no effect. NOTE If the ATDDIEN1 bit of the associated pin is set to 0 (digital input buffer is disabled), active edges can not be detected. Module Base + 0x005F 76543210 R PIFAD7 PIFAD6 PIFAD5 PIFAD4 PIFAD3 PIFAD2 PIFAD1 PIFAD0 W Reset 0 0 0 00000 Figure 2-26. Port AD Interrupt Flag Register (PIFAD) Table 2-20. PIFAD Field Descriptions Field Description 7:0 PIFAD[7:0] Interrupt Flags Port AD 0 No active edge pending. Writing a “0” has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a “1” clears the associated flag.

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2.3.7 Port L

Port L is associated with the analog-to-digital converter (ATD) and the liquid crystal display (LCD) driver. If the ATD module is enabled, the AN[15:8] inputs of ATD module are available on port L pins PL[7:0]. If the corresponding LCD frontplane drivers are enabled, the FP[31:28] and FP[19:16] outputs of LCD module are available on port L pins PL[7:0] and the general purpose I/Os are disabled. For the pins of port L to be used as inputs, the corresponding LCD frontplane drivers must be disabled and the associated ATDDIEN0 register in the ATD module must be set to 1 (digital input buffer is enabled). The ATDDIEN0 register does not affect the port L pins when they are configured as outputs. Refer to the LCD block description chapter for information on enabling and disabling the LCD and its frontplane drivers. Refer to the ATD block description chapter for information on the ATDDIEN0 register. During reset, port L pins are configured as inputs with pull down.

2.3.7.1 Port L I/O Register (PTL)

Read: Anytime. Write: Anytime. If the data direction bit of the associated I/O pin (DDRLx) is set to 1 (output), a write to the corresponding I/O Register bit sets the value to be driven to the Port L pin. If the data direction bit of the associated I/O pin (DDRLx) is set to 0 (input), a write to the corresponding I/O Register bit takes place but has no effect on the Port L pin. If the associated data direction bit (DDRLx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRLx) is set to 0 (input) and the associated ATDDIEN0 bits is set to 0 (digital input buffer is disabled), the associated I/O register bit (PTLx) reads “1”. If the associated data direction bit (DDRLx) is set to 0 (input), the associated ATDDIEN0 bit is set to 1 (digital input buffer is enabled), and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTLx) reads “1”. If the associated data direction bit (DDRLx) is set to 0 (input), the associated ATDDIEN0 bit is set to 1 (digital input buffer is enabled), and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin. Module Base + 0x0030 76543210 R PTL7 PTL6 PTL5 PTL4 PTL3 PTL2 PTL1 PTL0 W ATD: AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 LCD: 1 1 1 11111 Reset 0 0 0 00000 Figure 2-27. Port L I/O Register (PTL)

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2.3.7.2 Port L Input Register (PTIL)

Read: Anytime. Write: Never, writes to this register have no effect. If the LCD frontplane driver of an associated I/O pin is enabled (and LCD module is enabled) or the associated ATDDIEN0 bit is set to 0 (digital input buffer is disabled), a read returns a 1. If the LCD frontplane driver of an associated I/O pin is disabled (or LCD module is disabled) and the associated ATDDIEN0 bit is set to 1 (digital input buffer is enabled), a read returns the status of the associated pin.

2.3.7.3 Port L Data Direction Register (DDRL)

Read: Anytime. Write: Anytime. This register configures port pins PL[7:0] as either input or output. If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. Module Base + 0x0031 76543210 R PTIL7 PTIL6 PTIL5 PTIL4 PTIL3 PTIL2 PTIL1 PTIL0 W Reset 1 1 1 11111 = Reserved or Unimplemented Figure 2-28. Port L Input Register (PTIL) Module Base + 0x0032 76543210 R DDRL7 DDRL6 DDRL5 DDRL4 DDRL3 DDRL2 DDRL1 DDRL0 W Reset 0 0 0 00000 Figure 2-29. Port L Data Direction Register (DDRL) Table 2-21. DDRL Field Descriptions Field Description 7:0 DDRL[7:0] Data Direction Port L 0 Associated pin is configured as input. 1 Associated pin is configured as output.

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2.3.7.4 Port L Reduced Drive Register (RDRL)

Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.

2.3.7.5 Port L Pull Device Enable Register (PERL)

Read:Anytime. Write:Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect. Module Base + 0x0033 76543210 R RDRL7 RDRL6 RDRL5 RDRL4 RDRL3 RDRL2 RDRL1 RDRL0 W Reset 0 0 0 00000 Figure 2-30. Port L Reduced Drive Register (RDRL) Table 2-22. RDRL Field Descriptions Field Description 7:0 RDRL[7:0] Reduced Drive Port L 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. Module Base + 0x0034 76543210 R PERL7 PERL6 PERL5 PERL4 PERL3 PERL2 PERL1 PERL0 W Reset 1 1 1 11111 Figure 2-31. Port L Pull Device Enable Register (PERL) Table 2-23. PERL Field Descriptions Field Description 7:0 PERL[7:0] Pull Device Enable Port L 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled.

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2.3.7.6 Port L Polarity Select Register (PPSL)

Read: Anytime. Write: Anytime. The Port L Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port L Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.

2.3.7.7 Port L Slew Rate Register (SRRL)

Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PL[7:0]. Module Base + 0x0035 76543210 R PPSL7 PPSL6 PPSL5 PPSL4 PPSL3 PPSL2 PPSL1 PPSL0 W Reset 1 1 1 11111 Figure 2-32. Port L Polarity Select Register (PPSL) Table 2-24. PPSL Field Descriptions Field Description 7:0 PPSL[7:0] Pull Select Port L 0 A pull-up device is connected to the associated port L pin. 1 A pull-down device is connected to the associated port L pin. Module Base + 0x003B 76543210 R SRRL7 SRRL6 SRRL5 SRRL4 SRRL3 SRRL2 SRRL1 SRRL0 W Reset 0 0 0 00000 Figure 2-33. Port L Slew Rate Register (SRRL) Table 2-25. SRRL Field Descriptions Field Description 7:0 SRRL[7:0] Slew Rate Port L 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.

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2.3.8 Port M

Port M is associated with the chip select 1 and the Freescale’s scalable controller area network (CAN1 and CAN0) modules. Each pin is assigned to these modules according to the following priority: CS1/CAN1/CAN0 > general-purpose I/O. When the CAN1 module is enabled, PM[5:4] pins become TXCAN1 (transmitter) and RXCAN1 (receiver) pins for the CAN1 module. When the CAN0 module is enabled, PM[3:2] pins become TXCAN0 (transmitter) and RXCAN0 (receiver) pins for the CAN0 module. Refer to the MSCAN block description chapter for information on enabling and disabling the CAN module. During reset, port M pins are configured as high-impedance inputs.

2.3.8.1 Port M I/O Register (PTM)

Read: Anytime. Write: Anytime. If the associated data direction bit (DDRMx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRMx) is set to 0 (input), a read returns the value of the pin.

2.3.8.2 Port M Input Register (PTIM)

Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. Module Base + 0x0010 76543210 R0 0 PTM5 PTM4 PTM3 PTM2 PTM1 W CAN0/CAN1: TXCAN1 RXCAN1 TXCAN0 RXCAN0 Chip Select: CS1 Reset 0 0 000000 = Reserved or Unimplemented Figure 2-34. Port M I/O Register (PTM) Module Base + 0x0011 76543210 R 0 0 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 0 W Reset 0 0 u uuuu0 = Reserved or Unimplemented u = Unaffected by reset Figure 2-35. Port M Input Register (PTIM)

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2.3.8.3 Port M Data Direction Register (DDRM)

Read: Anytime. Write: Anytime. This register configures port pins PM[5:1] as either input or output. When a CAN module is enabled, the corresponding transmitter (TXCANx) pin becomes an output, the corresponding receiver (RXCANx) pin becomes an input, and the associated Data Direction Register bits have no effect. If a CAN module is disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.

2.3.8.4 Port M Reduced Drive Register (RDRM)

Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect. Module Base + 0x0012 76543210 R0 0 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 W Reset 0 0 0 00000 = Reserved or Unimplemented Figure 2-36. Port M Data Direction Register (DDRM) Table 2-26. DDRM Field Descriptions Field Description 5:1 DDRM[5:1] Data Direction Port M 0 Associated pin is configured as input. 1 Associated pin is configured as output. Module Base + 0x0013 76543210 R0 0 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 W Reset 0 0 0 00000 = Reserved or Unimplemented Figure 2-37. Port M Reduced Drive Register (RDRM)

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2.3.8.5 Port M Pull Device Enable Register (PERM)

Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input or wired-or output pins. If a pin is configured as push-pull output, the corresponding Pull Device Enable Register bit has no effect.

2.3.8.6 Port M Polarity Select Register (PPSM)

Read: Anytime. Write: Anytime. Table 2-27. RDRM Field Descriptions Field Description 5:1 RDRM[5:1] Reduced Drive Port M

0 Full drive strength at output

1 Associated pin drives at about 1/3 of the full drive strength. Module Base + 0x0014 76543210 R0 0 PERM5 PERM4 PERM3 PERM2 PERM1 W Reset 0 0 0 00000 = Reserved or Unimplemented Figure 2-38. Port M Pull Device Enable Register (PERM) Table 2-28. PERM Field Descriptions Field Description 5:1 PERM[5:1] Pull Device Enable Port M 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Module Base + 0x0015 76543210 R0 0 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 W Reset 0 0 0 00000 = Reserved or Unimplemented Figure 2-39. Port M Polarity Select Register (PPSM)

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The Port M Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port M Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. If a CAN module is enabled, a pull-up device can be activated on the receiver pin, and on the transmitter pin if the corresponding wired-OR mode bit is set. Pull-down devices can not be activated on CAN pins.

2.3.8.7 Port M Wired-OR Mode Register (WOMM)

Read: Anytime. Write: Anytime. This register selects whether a port M output is configured as push-pull or wired-or. When a Wired-OR Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured as an input. These bits apply also to the CAN transmitter and allow a multipoint connection of several serial modules. Table 2-29. PPSM Field Descriptions Field Description 5:1 PPSM[5:1] Pull Select Port M 0 A pull-up device is connected to the associated port M pin. 1 A pull-down device is connected to the associated port M pin. Module Base + 0x0016 76543210 R0 0 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 W Reset 0 0 0 00000 = Reserved or Unimplemented Figure 2-40. Port M Wired-OR Mode Register (WOMM) Table 2-30. WOMM Field Descriptions Field Description 5:1 WOMM[5:1] Wired-OR Mode Port M 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs.

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2.3.8.8 Port M Slew Rate Register (SRRM)

Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PM[5:1]. Module Base + 0x003B 76543210 R0 0 SRRM5 SRRM4 SRRM3 SRRM2 SRRM1 W Reset 0 0 0 00000 = Reserved or Unimplemented Figure 2-41. Port M Slew Rate Register (SRRM) Table 2-31. SRRM Field Descriptions Field Description 5:1 SRRM[5:1] Slew Rate Port M 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.

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2.3.9 Port P

Port P is associated with the chip selects 0 and 2, the Pulse Width Modulator (PWM), the serial communication interface (SCI1) and the Inter-IC bus (IIC0 and IIC1) modules. Each pin is assigned to these modules according to the following priority: CS0/CS2 > PWM > SCI1/IIC1/IIC0 > general-purpose I/O. When a PWM channel is enabled, the corresponding pin becomes a PWM output with the exception of PP[5] which can be PWM input or output. Refer to the PWM block description chapter for information on enabling and disabling the PWM channels. When the IIC1 module is enabled and MODRR1 is clear, PP[7:6] pins become SCL1 and SDA1 respectively as long as the corresponding PWM channels are disabled. When the IIC0 module is enabled and MODRR0 is clear, PP[5:4] pins become SCL0 and SDA0 respectively as long as the corresponding PWM channels are disabled. Refer to the IIC block description chapter for information on enabling and disabling the IIC bus. When the SCI1 receiver and transmitter are enabled and MODRR2 is clear, the PP[2] and PP[0] pins become RXD1 and TXD1 respectively as long as the corresponding PWM channels are disabled. Refer to the SCI block description chapter for information on enabling and disabling the SCI receiver and transmitter. During reset, port P pins are configured as high-impedance inputs.

2.3.9.1 Port P I/O Register (PTP)

Read: Anytime. Write: Anytime. If the associated data direction bit (DDRPx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRPx) is set to 0 (input), a read returns the value of the pin. The PWM function takes precedence over the general-purpose I/O function if the associated PWM channel is enabled. The PWM channels 6-0 are outputs if the respective channels are enabled. PWM channel 7 can be an output, or an input if the shutdown feature is enabled. Module Base + 0x0018 76543210 R PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 W SCI1/ IIC1/IIC0: SCL1 SDA1 SCL0 SDA0 RXD1 TXD1 PWM: PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Chip Select: CS2 CS0 Reset 0 0 0 00000 Figure 2-42. Port P I/O Register (PTP)

Chapter 2 Port Integration Module (S12XHZPIMV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 97 The IIC function takes precedence over the general-purpose I/O function if the IIC bus is enabled and the corresponding PWM channels remain disabled. The SDA and SCL pins are bidirectional with outputs configured as open-drain. If enabled, the SCI1 transmitter takes precedence over the general-purpose I/O function, and the corresponding TXD1 pin is configured as an output. If enabled, the SCI1 receiver takes precedence over the general-purpose I/O function, and the corresponding RXD1 pin is configured as an input.

2.3.9.2 Port P Input Register (PTIP)

Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins.

2.3.9.3 Port P Data Direction Register (DDRP)

Read: Anytime. Write: Anytime. This register configures port pins PP[7:0] as either input or output. If a PWM channel is enabled, the corresponding pin is forced to be an output and the associated Data Direction Register bit has no effect. Channel 5 can also force the corresponding pin to be an input if the shutdown feature is enabled. When an IIC bus is enabled, the corresponding pins become the SCL and SDA bidirectional pins respectively as long as the corresponding PWM channels are disabled. The associated Data Direction Register bits have no effect. Module Base + 0x0019 76543210 R PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 W Reset u u u uuuuu = Reserved or Unimplemented u = Unaffected by reset Figure 2-43. Port P I/O Register (PTP) Module Base + 0x001A 76543210 R DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 W Reset 0 0 0 00000 Figure 2-44. Port P Data Direction Register (DDRP)

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When the SCI1 transmitter is enabled, the PP[0] pin becomes the TXD1 output pin and the associated Data Direction Register bit has no effect. When the SCI1 receiver is enabled, the PP[2] pin becomes the RXD1 input pin and the associated Data Direction Register bit has no effect. If the PWM, IIC0, IIC1 and SCI1 functions are disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.

2.3.9.4 Port P Reduced Drive Register (RDRP)

Read:Anytime. Write:Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect. Table 2-32. DDRP Field Descriptions Field Description 7:0 DDRP[7:0] Data Direction Port P 0 Associated pin is configured as input. 1 Associated pin is configured as output. Module Base + 0x001B 76543210 R RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 W Reset 0 0 0 00000 Figure 2-45. Port P Reduced Drive Register (RDRP) Table 2-33. RDRP Field Descriptions Field Description 7:0 RDRP[7:0] Reduced Drive Port P 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.

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2.3.9.5 Port P Pull Device Enable Register (PERP)

Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input or wired-or (open drain) output pins. If a pin is configured as push-pull output, the corresponding Pull Device Enable Register bit has no effect.

2.3.9.6 Port P Polarity Select Register (PPSP)

Read: Anytime. Write: Anytime. The Port P Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port P Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. If an IIC module is enabled, a pull-up device can be activated on either the SCL or SDA pins. Pull-down devices can not be activated on IIC pins. Module Base + 0x001C 76543210 R PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 W Reset 0 0 0 00000 Figure 2-46. Port P Pull Device Enable Register (PERP) Table 2-34. PERP Field Descriptions Field Description 7:0 PERP[7:0] Pull Device Enable Port P 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Module Base + 0x001D 76543210 R PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 W Reset 0 0 0 00000 Figure 2-47. Port P Polarity Select Register (PPSP) Table 2-35. PPSP Field Descriptions Field Description 7:0 PPSP[7:0] Polarity Select Port P 0 A pull-up device is connected to the associated port P pin. 1 A pull-down device is connected to the associated port P pin.

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2.3.9.7 Port P Wired-OR Mode Register (WOMP)

Read: Anytime. Write: Anytime. This register selects whether a port P output is configured as push-pull or wired-or. When a Wired-OR Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured as an input. If IIC is enabled and the corresponding PWM channels are disabled, the pins are configured as wired-or and the corresponding Wired-OR Mode Register bits have no effect. Module Base + 0x001E 76543210 R WOMP7 WOMP6 WOMP5 WOMP4 WOMP2 WOMPO W Reset 0 0 0 00000 = Reserved or Unimplemented Figure 2-48. Port P Wired-OR Mode Register (WOMP) Table 2-36. WOMP Field Descriptions Field Description 7:4 WOMP[7:4] Wired-OR Mode Port P 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. WOMP2 Wired-OR Mode Port P 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. WOMP0 Wired-OR Mode Port P 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs.

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2.3.9.8 Port P Slew Rate Register (SRRP)

Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PP[7:0]. Module Base + 0x003B 76543210 R SRRP7 SRRP6 SRRP5 SRRP4 SRRP3 SRRP2 SRRP1 SRRP0 W Reset 0 0 0 00000 Figure 2-49. Port P Slew Rate Register (SRRP) Table 2-37. SRRP Field Descriptions Field Description 7:0 SRRP[7:0] Slew Rate Port P 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.

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2.3.10 Port S

Port S is associated with the chip select 3, the serial peripheral interface (SPI) and the serial communication interface (SCI0). Each pin is assigned to these modules according to the following priority: CS3 > SPI/SCI1/SCI0 > general-purpose I/O. When the SPI is enabled, the PS[7:4] pins become SS, SCK, MOSI, and MISO respectively. Refer to the SPI block description chapter for information on enabling and disabling the SPI. When the SCI0 receiver and transmitter are enabled, the PS[1:0] pins become TXD0 and RXD0 respectively. When the SCI1 receiver and transmitter are enabled and MODRR2 is set, the PS[3:2] pins become TXD1 and RXD1 respectively. Refer to the SCI block description chapter for information on enabling and disabling the SCI receiver and transmitter. During reset, port S pins are configured as high-impedance inputs.

2.3.10.1 Port S I/O Register (PTS)

Read: Anytime. Write: Anytime. If the associated data direction bit (DDRSx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRSx) is set to 0 (input), a read returns the value of the pin. The SPI function takes precedence over the general-purpose I/O function if the SPI is enabled. If enabled, the SCI0(1) transmitter takes precedence over the general-purpose I/O function, and the corresponding TXD0(1) pin is configured as an output. If enabled, the SCI0(1) receiver takes precedence over the general-purpose I/O function, and the corresponding RXD0(1) pin is configured as an input. Module Base + 0x0008 76543210 R PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 W SPI/ SCI1/SCI0: SS SCK MOSI MISO TXD1 RXD1 TXD0 RXD0 Chip Select: CS3 Reset 0 0 0 00000 = Reserved or Unimplemented Figure 2-50. Port S I/O Register (PTS)

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2.3.10.2 Port S Input Register (PTIS)

Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins.

2.3.10.3 Port S Data Direction Register (DDRS)

Read: Anytime. Write: Anytime. This register configures port pins PS[7:0] as either input or output. When the SPI is enabled, the PS[7:4] pins become the SPI bidirectional pins. The associated Data Direction Register bits have no effect. When the SCI1 transmitter is enabled, the PS[3] pin becomes the TXD1 output pin and the associated Data Direction Register bit has no effect. When the SCI1 receiver is enabled, the PS[2] pin becomes the RXD1 input pin and the associated Data Direction Register bit has no effect. When the SCI0 transmitter is enabled, the PS[1] pin becomes the TXD0 output pin and the associated Data Direction Register bit has no effect. When the SCI0 receiver is enabled, the PS[0] pin becomes the RXD0 input pin and the associated Data Direction Register bit has no effect. If the SPI, SCI1 and SCI0 functions are disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. Module Base + 0x0009 76543210 R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 W Reset u u u uuuuu = Reserved or Unimplemented u = Unaffected by reset Figure 2-51. Port S Input Register (PTIS) Module Base + 0x000A 76543210 R DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 W Reset 0 0 0 00000 Figure 2-52. Port S Data Direction Register (DDRS) Table 2-38. DDRS Field Descriptions Field Description 7:0 DDRS[7:0] Data Direction Port S 0 Associated pin is configured as input. 1 Associated pin is configured as output.

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2.3.10.4 Port S Reduced Drive Register (RDRS)

Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.

2.3.10.5 Port S Pull Device Enable Register (PERS)

Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input or wired-or (open drain) output pins. If a pin is configured as push-pull output, the corresponding Pull Device Enable Register bit has no effect. Module Base + 0x000B 76543210 R RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 W Reset 0 0 0 00000 Figure 2-53. Port S Reduced Drive Register (RDRS) Table 2-39. RDRS Field Descriptions Field Description 7:0 RDRS[7:0] Reduced Drive Port S 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. Module Base + 0x000C 76543210 R PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 W Reset 0 0 0 00000 Figure 2-54. Port S Pull Device Enable Register (PERS) Table 2-40. PERS Field Descriptions Field Description 7:0 PERS[7:0] Pull Device Enable Port S 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled.

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2.3.10.6 Port S Polarity Select Register (PPSS)

Read: Anytime. Write: Anytime. The Port S Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port S Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.

2.3.10.7 Port S Wired-OR Mode Register (WOMS)

Read: Anytime. Write: Anytime. This register selects whether a port S output is configured as push-pull or wired-or. When a Wired-OR Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured as an input. Module Base + 0x000D 76543210 R PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 W Reset 0 0 0 00000 Figure 2-55. Port S Polarity Select Register (PPSS) Table 2-41. PPSS Field Descriptions Field Description 7:0 PPSS[7:0] Pull Select Port S 0 A pull-up device is connected to the associated port S pin. 1 A pull-down device is connected to the associated port S pin. Module Base + 0x000E 76543210 R WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 W Reset 0 0 0 00000 Figure 2-56. Port S Wired-OR Mode Register (WOMS) Table 2-42. WOMS Field Descriptions Field Description 7:0 WOMS[7:0] Wired-OR Mode Port S 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs.

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2.3.10.8 Port S Slew Rate Register (SRRS)

Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PS[7:0]. Module Base + 0x003B 76543210 R SRRS7 SRRS6 SRRS5 SRRS4 SRRS3 SRRS2 SRRS1 SRRS0 W Reset 0 0 0 00000 Figure 2-57. Port S Slew Rate Register (SRRS) Table 2-43. SRRS Field Descriptions Field Description 7:0 SRRS[7:0] Slew Rate Port S 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.

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2.3.11 Port T

Port T is associated with the 8-channel enhanced capture timer (ECT), the Inter-IC (IIC0 and IIC1) modules and the liquid crystal display (LCD) driver. Each pin is assigned to these modules according to the following priority: LCD Driver > IIC1/IIC0 > ECT > general-purpose I/O. When the IIC1 module is enabled and MODRR1 is set, PT[7:6] pins become SCL1 and SDA1 pins respectively. When the IIC0 module is enabled and MODRR0 is set, PT[5:4] pins become SCL0 and SDA0 respectively. Refer to the IIC block description chapter for information on enabling and disabling the IIC bus. If the corresponding LCD frontplane drivers are enabled (and LCD module is enabled), the FP[27:24] outputs of the LCD module are available on port T pins PT[3:0]. If the corresponding LCD frontplane drivers are disabled (or LCD module is disabled) and the ECT is enabled, the timer channels configured for output compare are available on port T pins PT[3:0]. Refer to the LCD block description chapter for information on enabling and disabling the LCD and its frontplane drivers.Refer to the ECT block description chapter for information on enabling and disabling the ECT module. During reset, port T pins are configured as inputs with pull down.

2.3.11.1 Port T I/O Register (PTT)

Read: Anytime. Write: Anytime. If the associated data direction bit (DDRTx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRTx) is set to 0 (input) and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTTx) reads “1”. If the associated data direction bit (DDRTx) is set to 0 (input) and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin. Module Base + 0x0000 76543210 R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W ECT: OC7 OC6 OC5 OC4 OC3 OC2 OC1 OC0 IIC1/IIC0: SCL1 SDA1 SCL0 SDA0 LCD: 1111 Reset 0 0 0 00000 Figure 2-58. Port T I/O Register (PTT)

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2.3.11.2 Port T Input Register (PTIT)

Read: Anytime. Write: Never, writes to this register have no effect. If the LCD frontplane driver of an associated I/O pin is enabled (and LCD module is enabled), a read returns a 1. If the LCD frontplane driver of the associated I/O pin is disabled (or LCD module is disabled), a read returns the status of the associated pin.

2.3.11.3 Port T Data Direction Register (DDRT)

Read: Anytime. Write: Anytime. This register configures port pins PT[7:0] as either input or output. If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. If the ECT module is enabled, each port pin configured for output compare is forced to be an output and the associated Data Direction Register bit has no effect. If the associated timer output compare is disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. If the ECT module is enabled, each port pin configured as an input capture has the corresponding Data Direction Register bit controlling the I/O direction of the associated pin. Module Base + 0x0001 76543210 R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 W Reset u u u uuuuu = Reserved or Unimplemented u = Unaffected by reset Figure 2-59. Port T Input Register (PTIT) Module Base + 0x0002 76543210 R DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 W Reset 0 0 0 00000 Figure 2-60. Port T Data Direction Register (DDRT)

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2.3.11.4 Port T Reduced Drive Register (RDRT)

Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect. Table 2-44. DDRT Field Descriptions Field Description 7:0 DDRT[7:0] Data Direction Port T 0 Associated pin is configured as input. 1 Associated pin is configured as output. Module Base + 0x0003 76543210 R RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 W Reset 0 0 0 00000 Figure 2-61. Port T Reduced Drive Register (RDRT) Table 2-45. RDRT Field Descriptions Field Description 7:0 RDRT[7:0] Reduced Drive Port T 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.

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2.3.11.5 Port T Pull Device Enable Register (PERT)

Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect. For port pins PT[7:4], a pull-up device can be activated on wired-or (open drain) output pins. If the pin is configured as push-pull output, the corresponding Pull Device Enable Register bit has no effect.

2.3.11.6 Port T Polarity Select Register (PPST)

Read: Anytime. Write: Anytime. The Port T Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port T Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. If an IIC module is enabled, a pull-up device can be activated on either the SCL or SDA pins. Pull-down devices can not be activated on IIC pins. Module Base + 0x0004 76543210 R PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 W Reset 0 0 0 01111 Figure 2-62. Port T Pull Device Enable Register (PERT) Table 2-46. PERT Field Descriptions Field Description 7:0 PERT[7:0] Pull Device Enable Port T 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Module Base + 0x0005 76543210 R PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W Reset 0 0 0 01111 Figure 2-63. Port T Polarity Select Register (PPST)

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2.3.11.7 Port T Wired-OR Mode Register (WOMT)

Read: Anytime. Write: Anytime. This register selects whether a port T output is configured as push-pull or wired-or. When a Wired-OR Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured as an input. If IIC is enabled, the pins are configured as wired-or and the corresponding Wired-OR Mode Register bits have no effect. This register also configures the re-routing of IIC0, IIC1 and SCI1 on alternative ports. Table 2-47. PPST Field Descriptions Field Description 7:0 PPST[7:0] Pull Select Port T 0 A pull-up device is connected to the associated port T pin. 1 A pull-down device is connected to the associated port T pin. Module Base + 0x003B 76543210 R WOMT7 WOMT6 WOMT5 WOMT4 MODRR2 MODRR1 MODRR0 W Reset 0 0 0 00000 = Reserved or Unimplemented Figure 2-64. Port T Wired-OR Mode Register (WOMT) Table 2-48. WOMT Field Descriptions Field Description 7:4 WOMT[7:4] Wired-OR Mode Port T 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. MODRR2 SCI1 Routing Bit — See Table 2-49.. MODRR1 IIC1 Routing Bit — See Table 2-50.. MODRR0 IIC0 Routing Bit — See Table 2-51.. Table 2-49. SCI1 Routing MODRR[2] TXD1 RXD1

0 PP0 PP2

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2.3.11.8 Port T Slew Rate Register (SRRT)

Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PT[7:0].

1 PS3 PS2

Table 2-50. IIC1 Routing MODRR[1] SDA1 SCL1

0 PP6 PP7

1 PT6 PT7

Table 2-51. IIC0 Routing MODRR[0] SDA0 SCL0

0 PP4 PP5

1 PT4 PT5

R SRRT7 SRRT6 SRRT5 SRRT4 SRRT3 SRRT2 SRRT1 SRRT0 W Reset 0 0 0 00000 Figure 2-65. Port T Slew Rate Register (SRRT) Table 2-52. SRRT Field Descriptions Field Description 7:0 SRRT[7:0] Slew Rate Port T 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer. Table 2-49. SCI1 Routing MODRR[2] TXD1 RXD1

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2.3.12 Port U

Port U is associated with the stepper stall detect (SSD1 and SSD0) and motor controller (MC1 and MC0) modules. Each pin is assigned to these modules according to the following priority: SSD1/SSD0 > MC1/MC0 > general-purpose I/O. If SSD1 module is enabled, the PU[7:4] pins are controlled by the SSD1 module. If SSD1 module is disabled, the PU[7:4] pins are controlled by the motor control PWM channels 3 and 2 (MC1). If SSD0 module is enabled, the PU[3:0] pins are controlled by the SSD0 module. If SSD0 module is disabled, the PU[3:0] pins are controlled by the motor control PWM channels 1 and 0 (MC0). Refer to the SSD and MC block description chapters for information on enabling and disabling the SSD module and the motor control PWM channels respectively. During reset, port U pins are configured as high-impedance inputs.

2.3.12.1 Port U I/O Register (PTU)

Read: Anytime. Write: Anytime. If the associated data direction bit (DDRUx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRUx) is set to 0 (input) and the slew rate is enabled, the associated I/O register bit (PTUx) reads “1”. If the associated data direction bit (DDRUx) is set to 0 (input) and the slew rate is disabled, a read returns the value of the pin. Module Base + 0x0038 76543210 R PTU7 PTU6 PTU5 PTU4 PTU3 PTU2 PTU1 PTU0 W MC: M1C1P M1C1M M1COP M1COM M0C1P M0C1M M0C0P M0C0M SSD1/ SSD0: M1SINP M1SINM M1COSP M1COSM M0SINP M0SINM M1COSP M0COSM Reset 0 0 0 00000 Figure 2-66. Port U I/O Register (PTU)

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2.3.12.2 Port U Input Register (PTIU)

Read: Anytime. Write: Never, writes to this register have no effect. If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a “1”. If the associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the associated pin.

2.3.12.3 Port U Data Direction Register (DDRU)

Read: Anytime. Write: Anytime. This register configures port pins PU[7:0] as either input or output. When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the corresponding Data Direction Register bits revert to control the I/O direction of the associated pins. Module Base + 0x0039 76543210 R PTIU7 PTIU6 PTIU5 PTIU4 PTIU3 PTIU2 PTIU1 PTIU0 W Reset u u u uuuuu = Reserved or Unimplemented u = Unaffected by reset Figure 2-67. Port U Input Register (PTIU) Module Base + 0x003A 76543210 R DDRU7 DDRU6 DDRU5 DDRU4 DDRU3 DDRU2 DDRU1 DDRU0 W Reset 0 0 0 00000 Figure 2-68. Port U Data Direction Register (DDRU) Table 2-53. DDRU Field Descriptions Field Description 7:0 DDRU[7:0] Data Direction Port U 0 Associated pin is configured as input. 1 Associated pin is configured as output.

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2.3.12.4 Port U Slew Rate Register (SRRU)

Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PU[7:0].

2.3.12.5 Port U Pull Device Enable Register (PERU)

Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect. Module Base + 0x003B 76543210 R SRRU7 SRRU6 SRRU5 SRRU4 SRRU3 SRRU2 SRRU1 SRRU0 W Reset 0 0 0 00000 Figure 2-69. Port U Slew Rate Register (SRRU) Table 2-54. SRRU Field Descriptions Field Description 7:0 SRRU[7:0] Slew Rate Port U 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer. Module Base + 0x003C 76543210 R PERU7 PERU6 PERU5 PERU4 PERU3 PERU2 PERU1 PERU0 W Reset 0 0 0 00000 Figure 2-70. Port U Pull Device Enable Register (PERU) Table 2-55. PERU Field Descriptions Field Description 7:0 PERU[7:0] Pull Device Enable Port U 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled.

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2.3.12.6 Port U Polarity Select Register (PPSU)

Read: Anytime. Write: Anytime. The Port U Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port U Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. Module Base + 0x003D 76543210 R PPSU7 PPSU6 PPSU5 PPSU4 PPSU3 PPSU2 PPSU1 PPSU0 W Reset 0 0 0 00000 Figure 2-71. Port U Polarity Select Register (PPSU) Table 2-56. PPSU Field Descriptions Field Description 7:0 PPSU[7:0] Pull Select Port U 0 A pull-up device is connected to the associated port U pin. 1 A pull-down device is connected to the associated port U pin.

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2.3.13 Port V

Port V is associated with the stepper stall detect (SSD3 and SSD2) and motor controller (MC3 and MC2) modules. Each pin is assigned to these modules according to the following priority: SSD3/SSD2 > MC3/MC2 > general-purpose I/O. If SSD3 module is enabled, the PV[7:4] pins are controlled by the SSD3 module. If SSD3 module is disabled, the PV[7:4] pins are controlled by the motor control PWM channels 7 and 6 (MC3). If SSD2 module is enabled, the PV[3:0] pins are controlled by the SSD2 module. If SSD2 module is disabled, the PV[3:0] pins are controlled by the motor control PWM channels 5 and 4 (MC2). Refer to the SSD and MC block description chapters for information on enabling and disabling the SSD module and the motor control PWM channels respectively. During reset, port V pins are configured as high-impedance inputs.

2.3.13.1 Port V I/O Register (PTV)

Read: Anytime. Write: anytime. If the associated data direction bit (DDRVx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRVx) is set to 0 (input) and the slew rate is enabled, the associated I/O register bit (PTVx) reads “1”. If the associated data direction bit (DDRVx) is set to 0 (input) and the slew rate is disabled, a read returns the value of the pin. Module Base + 0x0040 76543210 R PTV7 PTV6 PTV5 PTV4 PTV3 PTV2 PTV1 PTV0 W MC: M3C1P M3C1M M3C0P M3C0M M2C1P M2C1M M2C0P M2C0M SSD3/ SSD2 M3SINP M3SINM M3COSP M3COSM M2SINP M2SINM M2COSP M2COSM Reset 0 0 0 00000 Figure 2-72. Port V I/O Register (PTV)

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2.3.13.2 Port V Input Register (PTIV)

Read: Anytime. Write: Never, writes to this register have no effect. If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a “1”. If the associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the associated pin.

2.3.13.3 Port V Data Direction Register (DDRV)

Read: Anytime. Write: Anytime. This register configures port pins PV[7:0] as either input or output. When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the corresponding Data Direction Register bits revert to control the I/O direction of the associated pins. Module Base + 0x0041 76543210 R PTIV7 PTIV6 PTIV5 PTIV4 PTIV3 PTIV2 PTIV1 PTIV0 W Reset u u u uuuuu = Reserved or Unimplemented u = Unaffected by reset Figure 2-73. Port V Input Register (PTIV) Module Base + 0x0042 76543210 R DDRV7 DDRV6 DDRV5 DDRV4 DDRV3 DDRV2 DDRV1 DDRV0 W Reset 0 0 0 00000 Figure 2-74. Port V Data Direction Register (DDRV) Table 2-57. DDRV Field Descriptions Field Description 7:0 DDRV[7:0] Data Direction Port V 0 Associated pin is configured as input. 1 Associated pin is configured as output.

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2.3.13.4 Port V Slew Rate Register (SRRV)

Read: anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PV[7:0].

2.3.13.5 Port V Pull Device Enable Register (PERV)

Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect. Module Base + 0x0043 76543210 R SRRV7 SRRV6 SRRV5 SRRV4 SRRV3 SRRV2 SRRV1 SRRV0 W Reset 0 0 0 00000 Figure 2-75. Port V Slew Rate Register (SRRV) Table 2-58. SRRV Field Descriptions Field Description 7:0 SRRV[7:0] Slew Rate Port V 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer. Module Base + 0x0044 76543210 R PERV7 PERV6 PERV5 PERV4 PERV3 PERV2 PERV1 PERV0 W Reset 0 0 0 00000 Figure 2-76. Port V Pull Device Enable Register (PERV) Table 2-59. PERV Field Descriptions Field Description 7:0 PERV[7:0] Pull Device Enable Port V 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled.

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2.3.13.6 Port V Polarity Select Register (PPSV)

Read: Anytime. Write: Anytime. The Port V Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port V Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. Module Base + 0x0045 76543210 R PPSV7 PPSV6 PPSV5 PPSV4 PPSV3 PPSV2 PPSV1 PPSV0 W Reset 0 0 0 00000 Figure 2-77. Port V Polarity Select Register (PPSV) Table 2-60. PPSV Field Descriptions Field Description 7:0 PPSV[7:0] Pull Select Port V 0 A pull-up device is connected to the associated port V pin. 1 A pull-down device is connected to the associated port V pin.

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2.3.14 Port W

Port W is associated with the stepper stall detect (SSD5 and SSD4) and motor controller (MC5 and MC4) modules. Each pin is assigned to these modules according to the following priority: SSD5/SSD4 > MC5/MC4 > general-purpose I/O. If SSD5 module is enabled, the PW[7:4] pins are controlled by the SSD5 module. If SSD5 module is disabled, the PW[7:4] pins are controlled by the motor control PWM channels 11 and 10 (MC5). If SSD4 module is enabled, the PW[3:0] pins are controlled by the SSD4 module. If SSD4 module is disabled, the PW[3:0] pins are controlled by the motor control PWM channels 9 and 8 (MC4). Refer to the SSD and MC block description chapters for information on enabling and disabling the SSD module and the motor control PWM channels respectively. During reset, port W pins are configured as high-impedance inputs.

2.3.14.1 Port W I/O Register (PTW)

Read: Anytime. Write: anytime. If the associated data direction bit (DDRWx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRWx) is set to 0 (input) and the slew rate is enabled, the associated I/O register bit (PTWx) reads “1”. If the associated data direction bit (DDRWx) is set to 0 (input) and the slew rate is disabled, a read returns the value of the pin. Module Base + 0x0040 76543210 R PTW7 PTW6 PTW5 PTW4 PTW3 PTW2 PTW1 PTW0 W MC: M5C1P M3C1M M5C0P M5C0M M4C1P M4C1M M4C0P M4C0M SSD5/ SSD4 M5SINP M3SINM M5COSP M5COSM M4SINP M4SINM M4COSP M4COSM Reset 0 0 0 00000 Figure 2-78. Port W I/O Register (PTW)

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2.3.14.2 Port W Input Register (PTIW)

Read: Anytime. Write: Never, writes to this register have no effect. If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a “1”. If the associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the associated pin.

2.3.14.3 Port W Data Direction Register (DDRW)

Read: Anytime. Write: Anytime. This register configures port pins PW[7:0] as either input or output. When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the corresponding Data Direction Register bits revert to control the I/O direction of the associated pins. Module Base + 0x0041 76543210 R PTIW7 PTIW6 PTIW5 PTIW4 PTIW3 PTIW2 PTIW1 PTIW0 W Reset u u u uuuuu = Reserved or Unimplemented u = Unaffected by reset Figure 2-79. Port W Input Register (PTIW) Module Base + 0x0042 76543210 R DDRW7 DDRW6 DDRW5 DDRW4 DDRW3 DDRW2 DDRW1 DDRW0 W Reset 0 0 0 00000 Figure 2-80. Port W Data Direction Register (DDRW) Table 2-61. DDRW Field Descriptions Field Description 7:0 DDRW[7:0] Data Direction Port W 0 Associated pin is configured as input. 1 Associated pin is configured as output.

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2.3.14.4 Port W Slew Rate Register (SRRW)

Read: anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PW[7:0].

2.3.14.5 Port W Pull Device Enable Register (PERW)

Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect. Module Base + 0x0043 76543210 R SRRW7 SRRW6 SRRW5 SRRW4 SRRW3 SRRW2 SRRW1 SRRW0 W Reset 0 0 0 00000 Figure 2-81. Port W Slew Rate Register (SRRW) Table 2-62. SRRW Field Descriptions Field Description 7:0 SRRW[7:0] Slew Rate Port W 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer. Module Base + 0x0044 76543210 R PERW7 PERW6 PERW5 PERW4 PERW3 PERW2 PERW1 PERW0 W Reset 0 0 0 00000 Figure 2-82. Port W Pull Device Enable Register (PERW) Table 2-63. PERW Field Descriptions Field Description 7:0 PERW[7:0] Pull Device Enable Port W 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled.

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2.3.14.6 Port W Polarity Select Register (PPSW)

Read: Anytime. Write: Anytime. The Port W Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port W Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. Module Base + 0x0045 76543210 R PPSW7 PPSW6 PPSW5 PPSW4 PPSW3 PPSW2 PPSW1 PPSW0 W Reset 0 0 0 00000 Figure 2-83. Port W Polarity Select Register (PPSW) Table 2-64. PPSW Field Descriptions Field Description 7:0 PPSW[7:0] Pull Select Port W 0 A pull-up device is connected to the associated port W pin. 1 A pull-down device is connected to the associated port W pin.

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2.4 Functional Description

Each pin except PE0, PE1, and BKGD can act as general-purpose I/O. In addition the pin can act as an output from a peripheral module or an input to a peripheral module. A set of configuration registers is common to all ports. All registers can be written at any time, however a specific configuration might not become active. Example: Selecting a pull-up resistor. This resistor does not become active while the port is used as a push-pull output.

2.4.1 I/O Register

The I/O Register holds the value driven out to the pin if the port is used as a general-purpose I/O. Writing to the I/O Register only has an effect on the pin if the port is used as general-purpose output. When reading the I/O Register, the value of each pin is returned if the corresponding Data Direction Register bit is set to 0 (pin configured as input). If the data direction register bits is set to 1, the content of the I/O Register bit is returned. This is independent of any other configuration (Figure 2-84). Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on the I/O Register when changing the data direction register.

2.4.2 Input Register

The Input Register is a read-only register and generally returns the value of the pin (Figure 2-84).It can be used to detect overload or short circuit conditions. Table 2-65. Register Availability per Port1

1 Each cell represents one register with individual configuration bits

A yes yes — yes yes — — yes — — AD yes yes yes yes yes yes — — yes yes L yes yes yes yes yes yes — yes — — M yes yes yes yes yes yes yes yes — — P yes yes yes yes yes yes yes yes — — S yes yes yes yes yes yes yes yes — — T yes yes yes yes yes yes yes yes — — U yes yes yes — yes yes — yes — — V yes yes yes — yes yes — yes — — W yes yes yes — yes yes — yes — —

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Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on the Input Register when changing the Data Direction Register.

2.4.3 Data Direction Register

The Data Direction Register defines whether the pin is used as an input or an output. . A Data Direction Register bit set to 0 configures the pin as an input. A Data Direction Register bit set to 1 configures the pin as an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-84). Figure 2-84. Illustration of I/O Pin Functionality Figure 2-85 shows the state of digital inputs and outputs when an analog module drives the port. When the analog module is enabled all associated digital output ports are disabled and all associated digital input ports read “1”t. Figure 2-85. Digital Ports and Analog Module PTx DDRx output enable module enable PAD PTIx data outDigital Module Analog Module PAD Digital Input Digital Output Analog Module Enable Output PIM Boundary

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2.4.4 Reduced Drive Register

If the port is used as an output the Reduced Drive Register allows the configuration of the drive strength.

2.4.5 Pull Device Enable Register

The Pull Device Enable Register turns on a pull-up or pull-down device. The pull device becomes active only if the pin is used as an input or as a wired-or output.

2.4.6 Polarity Select Register

The Polarity Select Register selects either a pull-up or pull-down device if enabled. The pull device becomes active only if the pin is used as an input or as a wired-or output.

2.4.7 Pin Configuration Summary

The following table summarizes the effect of various configuration in the Data Direction (DDR), Input/Output (I/O), reduced drive (RDR), Pull Enable (PE), Pull Select (PS) and Interrupt Enable (IE) register bits. The PS configuration bit is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device if PE is set to “1”. Table 2-66. Pin Configuration Summary DDR IO RDR PE PS IE 1 1 Applicable only on Port AD. Function2 2 Digital outputs are disabled and digital input logic is forced to “1” when an analog module associated with the port is enabled. Pull Device Interrupt

0 X X 0 X 0 Input Disabled Disabled

0 X X 1 0 0 Input Pull Up Disabled

0 X X 1 1 0 Input Pull Down Disabled

0 X X 0 0 1 Input Disabled Falling Edge

0 X X 0 1 1 Input Disabled Rising Edge

0 X X 1 0 1 Input Pull Up Falling Edge

0 X X 1 1 1 Input Pull Down Rising Edge

1 0 0 X X 0 Output to 0, Full Drive Disabled Disabled 1 1 0 X X 0 Output to 1, Full Drive Disabled Disabled 1 0 1 X X 0 Output to 0, Reduced Drive Disabled Disabled 1 1 1 X X 0 Output to 1, Reduced Drive Disabled Disabled 1 0 0 X 0 1 Output to 0, Full Drive Disabled Falling Edge 1 1 0 X 1 1 Output to 1, Full Drive Disabled Rising Edge 1 0 1 X 0 1 Output to 0, Reduced Drive Disabled Falling Edge 1 1 1 X 1 1 Output to 1, Reduced Drive Disabled Rising Edge

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2.5 Resets

The reset values of all registers are given in the register description in Section 2.3, “Memory Map and Register Definition”. All ports start up as general-purpose inputs on reset.

2.5.1 Reset Initialization

All registers including the data registers get set/reset asynchronously. Table 2-67 summarizes the port properties after reset initialization. P Table 2-67. Port Reset State Summary Port Reset States Data Direction Pull Mode Reduced Drive Slew Rate Wired-OR Mode Interrupt A Input Pull Down Disabled Disabled N/A N/A B Input Pull Down Disabled Disabled N/A N/A C Input Hi-z Disabled Disabled N/A N/A D Input Hi-z Disabled Disabled N/A N/A E Input Pull Down 1 PE[1:0] pins have pull-ups instead of pull-downs. Disabled Disabled N/A N/A K Input Pull Down Disabled Disabled N/A N/A AD Input Hi-z Disabled N/A N/A Disabled L Input Pull Down Disabled Disabled N/A N/A M Input Hi-z Disabled Disabled Disabled N/A P Input Hi-z Disabled Disabled Disabled N/A S Input Hi-z Disabled Disabled Disabled N/A T[7:4] Input Hi-z Disabled Disabled Disabled N/A T[3:0] Input Pull Down Disabled Disabled Disabled N/A U Input Hi-z Disabled Disabled N/A N/A V Input Hi-z Disabled Disabled N/A N/A W Input Hi-z Disabled Disabled N/A N/A

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2.6 Interrupts

2.6.1 General

Port AD generates an edge sensitive interrupt if enabled. It offers eight I/O pins with edge triggered interrupt capability in wired-or fashion. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per pin basis. All eight bits/pins share the same interrupt vector. Interrupts can be used with the pins configured as inputs (with the corresponding ATDDIEN1 bit set to 1)or outputs. An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in stop or wait mode. A digital filter on each pin prevents pulses (Figure 2-87) shorter than a specified time from generating an interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-86 and Table 2-68). Figure 2-86. Interrupt Glitch Filter on Port AD (PPS = 0) Table 2-68. Pulse Detection Criteria Pulse Mode STOP STOP 1

1 These values include the spread of the oscillator frequency over temperature,

voltage and process. Unit Unit Ignored t pulse <= 3 Bus Clock t pulse <= 3.2 µs Uncertain 3 < t pulse < 4 Bus Clock 3.2 < t pulse < 10 µs Valid t pulse >= 4 Bus Clock t pulse >= 10 µs Glitch, filtered out, no interrupt flag set Valid pulse, interrupt flag set tifmin tifmax

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Figure 2-87. Pulse Illustration A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock is generated by a single RC oscillator in the port integration module. To maximize current saving the RC oscillator runs only if the following condition is true on any pin:Sample count <= 4 and port interrupt enabled (PIE=1) and port interrupt flag not set (PIF=0).

2.6.2 Interrupt Sources

Vector addresses and their relative interrupt priority are determined at the MCU level.

2.6.3 Operation in Stop Mode

All clocks are stopped in STOP mode. The port integration module has asynchronous paths on port AD to generate wake-up interrupts from stop mode. For other sources of external interrupts refer to the respective block description chapters. Table 2-69. Port Integration Module Interrupt Sources Interrupt Source Interrupt Flag Local Enable Global (CCR) Mask Port AD PIFAD[7:0] PIEAD[7:0] I Bit tpulse

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3.1 Introduction

This document describes the FTX512K4 module that includes a 512 Kbyte Flash (nonvolatile) memory. The Flash memory may be read as either bytes, aligned words or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. The Flash memory is ideal for program and data storage for single-supply applications allowing for field reprogramming without requiring external voltage sources for program or erase. Program and erase functions are controlled by a command driven interface. The Flash module supports both block erase and sector erase. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase the Flash memory is generated internally. It is not possible to read from a Flash block while it is being erased or programmed. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed.

3.1.1 Glossary

Command Write Sequence — A three-step MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. Multiple-Input Signature Register (MISR) — A Multiple-Input Signature Register is an output response analyzer implemented using a linear feedback shift-register (LFSR). A 16-bit MISR is used to compress data and generate a signature that is particular to the data read from a Flash block.

3.1.2 Features

• 512 Kbytes of Flash memory comprised of four 128 Kbyte blocks with each block divided into 128 sectors of 1024 bytes
• Automated program and erase algorithm
• Interrupts on Flash command completion, command buffer empty
• Fast sector erase and word program operation
• 2-stage command pipeline for faster multi-word program times
• Sector erase abort feature for critical interrupt response
• Flexible protection scheme to prevent accidental program or erase
• Single power supply for all Flash operations including program and erase

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• Security feature to prevent unauthorized access to the Flash memory
• Code integrity check using built-in data compression

3.1.3 Modes of Operation

Program, erase, erase verify, and data compress operations (please refer toSection 3.4.1, “Flash Command Operations” for details).

3.1.4 Block Diagram

A block diagram of the Flash module is shown in Figure 3-1.

Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 133 Figure 3-1. FTX512K4 Block Diagram

3.2 External Signal Description

The Flash module contains no signals that connect off-chip. FTX512K4 Flash Block 0 64K * 16 Bits Flash Block 1 64K * 16 Bits Flash Block 2 64K * 16 Bits 64K * 16 Bits Flash Block 3 sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 Oscillator Clock Divider Clock Command Interrupt Request FCLK Protection Security Command Pipeline cmd2 addr2 data2_0 cmd1 addr1 data1_0 Registers data2_1 data1_1 data2_2 data1_2 data2_3 data1_3 Flash Interface

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3.3 Memory Map and Register Definition

This section describes the memory map and registers for the Flash module.

3.3.1 Module Memory Map

The Flash memory map is shown in Figure 3-2. The HCS12X architecture places the Flash memory addresses between global addresses 0x78_0000 and 0x7F_FFFF. The FPROT register, described in Section 3.3.2.5, “Flash Protection Register (FPROT)”, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0x7F_8000 in the Flash memory (called the lower region), one growing downward from global address 0x7F_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. The lower address region can be used for EEPROM emulation in an MCU without an EEPROM module since it can be left unprotected while the remaining addresses are protected from program or erase. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 3-1. Table 3-1. Flash Configuration Field Global Address Size (Bytes) Description 0x7F_FF00 – 0x7F_FF07 8 Backdoor Comparison Key Refer to Section 3.6.1, “Unsecuring the MCU using Backdoor Key Access” 0x7F_FF08 – 0x7F_FF0C 5 Reserved 0x7F_FF0D 1 Flash Protection byte Refer to Section 3.3.2.5, “Flash Protection Register (FPROT)” 0x7F_FF0E 1 Flash Nonvolatile byte Refer to Section 3.3.2.8, “Flash Control Register (FCTL)” 0x7F_FF0F 1 Flash Security byte Refer to Section 3.3.2.2, “Flash Security Register (FSEC)”

Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 135 Figure 3-2. Flash Memory Map Flash Registers Flash Configuration Field 0x7F_C000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_8000 0x7F_9000 0x7F_8400 0x7F_8800 0x7F_A000 FLASH END = 0x7F_FFFF 0x7F_F800 0x7F_F000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes Flash Protected/Unprotected Region

8 Kbytes (up to 29 Kbytes)

16 bytes (0x7F_FF00 - 0x7F_FF0F) Flash Protected/Unprotected Region

480 Kbytes

FLASH START = 0x78_0000 MODULE BASE + 0x0000 MODULE BASE + 0x000F

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3.3.2 Register Descriptions

The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given inFigure 3-3. Detailed descriptions of each register bit are provided. Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 FCLKDIV R FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W 0x0001 FSEC R KEYEN RNV5 RNV4 RNV3 RNV2 SEC W 0x0002 FTSTMOD MRDS 00000 W 0x0003 FCNFG R CBEIE CCIE KEYACC 00000 W 0x0004 FPROT R FPOPEN RNV6 FPHDIS FPHS FPLDIS FPLS W 0x0005 FSTAT R CBEIF CCIF PVIOL ACCERR

0 BLANK 0 0

W 0x0006 FCMD CMDB W 0x0007 FCTL R 0 NV6 NV5 NV4 NV3 NV2 NV1 NV0 W 0x0008 FADDRHI R FADDRHI W 0x0009 FADDRLO R FADDRLO W 0x000A FDATAHI R FDATAHI W 0x000B FDATALO R FDATALO W Figure 3-3. FTX512K4 Register Summary

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3.3.2.1 Flash Clock Divider Register (FCLKDIV)

The FCLKDIV register is used to control timed events in program and erase algorithms. All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable. 0x000C RESERVED1 R 00000000 W 0x000D RESERVED2 R 00000000 W 0x000E RESERVED3 R 00000000 W 0x000F RESERVED4 R 00000000 W Module Base + 0x0000 76543210 R FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W Reset 00000000 = Unimplemented or Reserved Figure 3-4. Flash Clock Divider Register (FCLKDIV) Table 3-2. FCLKDIV Field Descriptions Field Description FDIVLD Clock Divider Loaded. 0 Register has not been written. 1 Register has been written to since the last reset. PRDIV8 Enable Prescalar by 8 0 The oscillator clock is directly fed into the clock divider . 1 The oscillator clock is divided by 8 before feeding into the clock divider. 5:0 FDIV[5:0] Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a FCLKDIV Register” for more information. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Figure 3-3. FTX512K4 Register Summary (continued)

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3.3.2.2 Flash Security Register (FSEC)

The FSEC register holds all bits associated with the security of the MCU and Flash module. All bits in the FSEC register are readable but are not writable. The FSEC register is loaded from the Flash Configuration Field at address 0x7F_FF0F during the reset sequence, indicated by F in Figure 3-5. The security function in the Flash module is described in Section 3.6, “Flash Module Security”. Module Base + 0x0001 76543210 R KEYEN RNV5 RNV4 RNV3 RNV2 SEC W Reset F F FFFFFF = Unimplemented or Reserved Figure 3-5. Flash Security Register (FSEC) Table 3-3. FSEC Field Descriptions Field Description 7:6 KEYEN[1:0] Backdoor Key Security Enable Bits— The KEYEN[1:0] bits define the enabling of backdoor key access to the Flash module as shown in Table 3-4. 5:2 RNV[5:2] Reserved Nonvolatile Bits — The RNV[5:2] bits should remain in the erased state for future enhancements. 1:0 SEC[1:0] Flash Security Bits— The SEC[1:0] bits define the security state of the MCU as shown inTable 3-5. If the Flash module is unsecured using backdoor key access, the SEC[1:0] bits are forced to 1:0. Table 3-4. Flash KEYEN States KEYEN[1:0] Status of Backdoor Key Access

00 DISABLED

1 Preferred KEYEN state to disable Backdoor Key Access. DISABLED

10 ENABLED

11 DISABLED

Table 3-5. Flash Security States SEC[1:0] Status of Security

00 SECURED

1 Preferred SEC state to set MCU to secured state. SECURED

10 UNSECURED

11 SECURED

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3.3.2.3 Flash Test Mode Register (FTSTMOD)

The FTSTMOD register is used to control Flash test features. MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode. The WRALL bit is writable only in special mode to simplify mass erase and erase verify operations. When writing to the FTSTMOD register in special mode, all unimplemented/reserved bits must be written to 0. Module Base + 0x0002 76543210 MRDS 00000 W Reset 00000000 = Unimplemented or Reserved Figure 3-6. Flash Test Mode Register (FTSTMOD —Normal Mode) Module Base + 0x0002 76543210 MRDS WRALL 0000 W Reset 00000000 = Unimplemented or Reserved Figure 3-7. Flash Test Mode Register (FTSTMOD — Special Mode) Table 3-6. FTSTMOD Field Descriptions Field Description 6:5 MRDS[1:0] Margin Read Setting — The MRDS[1:0] bits are used to set the sense-amp margin level for reads of the Flash array as shown in Table 3-7. WRALL Write to all Register Banks — If the WRALL bit is set, all banked FDATA registers sharing the same register address will be written simultaneously during a register write. 0 Write only to the FDATA register bank selected using BKSEL. 1 Write to all FDATA register banks. Table 3-7. FTSTMOD Margin Read Settings MRDS[1:0] Margin Read Setting

00 Normal

01 Program Margin 1

1 Flash array reads will be sensitive to program margin.

10 Erase Margin 2

2 Flash array reads will be sensitive to erase margin.

11 Normal

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3.3.2.4 Flash Configuration Register (FCNFG)

The FCNFG register enables the Flash interrupts and gates the security backdoor writes. CBEIE, CCIE and KEY ACC bits are readable and writable while all remaining bits read 0 and are not writable in normal mode. KEY ACC is only writable if KEYEN (seeSection 3.3.2.2, “Flash Security Register (FSEC)” is set to the enabled state. BKSEL is readable and writable in special mode to simplify mass erase and erase verify operations. When writing to the FCNFG register in special mode, all unimplemented/ reserved bits must be written to 0. Module Base + 0x0003 76543210 R CBEIE CCIE KEYACC 00000 W Reset 00000000 = Unimplemented or Reserved Figure 3-8. Flash Configuration Register (FCNFG — Normal Mode) Module Base + 0x0003 76543210 R CBEIE CCIE KEYACC 000 BKSEL W Reset 00000000 = Unimplemented or Reserved Figure 3-9. Flash Configuration Register (FCNFG — Special Mode) Table 3-8. FCNFG Field Descriptions Field Description CBEIE Command Buffer Empty Interrupt Enable— The CBEIE bit enables an interrupt in case of an empty command buffer in the Flash module. 0 Command buffer empty interrupt disabled. 1 An interrupt will be requested whenever the CBEIF flag (seeSection 3.3.2.6, “Flash Status Register (FSTAT)”) is set. CCIE Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been completed in the Flash module. 0 Command complete interrupt disabled. 1 An interrupt will be requested whenever the CCIF flag (see Section 3.3.2.6, “Flash Status Register (FSTAT)”) is set. KEYACC Enable Security Key Writing 0 Flash writes are interpreted as the start of a command write sequence. 1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid data. 1:0 BKSEL[1:0] Block Select — The BKSEL[1:0] bits indicates which register bank is active according to Table 3-9.

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3.3.2.5 Flash Protection Register (FPROT)

The FPROT register defines which Flash sectors are protected against program or erase operations. All bits in the FPROT register are readable and writable with restrictions (see Section 3.3.2.5.1, “Flash Protection Restrictions”) except for RNV[6] which is only readable. During the reset sequence, the FPROT register is loaded from the Flash Configuration Field at global address 0x7F_FF0D. To change the Flash protection that will be loaded during the reset sequence, the upper sector of the Flash memory must be unprotected, then the Flash Protect/Security byte located as described in Table 3-1 must be reprogrammed. Trying to alter data in any protected area in the Flash memory will result in a protection violation error and the PVIOL flag will be set in the FSTAT register. The mass erase of a Flash block is not possible if any of the Flash sectors contained in the Flash block are protected. Table 3-9. Flash Register Bank Selects BKSEL[1:0] Selected Block

00 Flash Block 0

01 Flash Block 1

10 Flash Block 2

11 Flash Block 3

R FPOPEN RNV6 FPHDIS FPHS FPLDIS FPLS W Reset F F FFFFFF = Unimplemented or Reserved Figure 3-10. Flash Protection Register (FPROT) Table 3-10. FPROT Field Descriptions Field Description FPOPEN Flash Protection Open — The FPOPEN bit determines the protection function for program or erase as shown in Table 3-11.

0 The FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding

FPHS[1:0] and FPLS[1:0] bits. For an MCU without an EEPROM module, the FPOPEN clear state allows the main part of the Flash block to be protected while a small address range can remain unprotected for EEPROM emulation.

1 The FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding

FPHS[1:0] and FPLS[1:0] bits. RNV6 Reserved Nonvolatile Bit — The RNV[6] bit should remain in the erased state for future enhancements.

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Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the Flash memory ending with global address 0x7F_FFFF. 0 Protection/Unprotection enabled. 1 Protection/Unprotection disabled. 4:3 FPHS[1:0] Flash Protection Higher Address Size— The FPHS[1:0] bits determine the size of the protected/unprotected area as shown inTable 3-12. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set. FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the Flash memory beginning with global address 0x7F_8000. 0 Protection/Unprotection enabled. 1 Protection/Unprotection disabled. 1:0 FPLS[1:0] Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected area as shown in Table 3-13. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. Table 3-11. Flash Protection Function FPOPEN FPHDIS FPLDIS Function 1 1 For range sizes, refer to Table 3-12 and Table 3-13. 1 1 1 No Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full Flash memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges Table 3-12. Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x7F_F800–0x7F_FFFF 2 Kbytes 01 0x7F_F000–0x7F_FFFF 4 Kbytes 10 0x7F_E000–0x7F_FFFF 8 Kbytes 11 0x7F_C000–0x7F_FFFF 16 Kbytes Table 3-13. Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0x7F_8000–0x7F_83FF 1 Kbytes 01 0x7F_8000–0x7F_87FF 2 Kbytes 10 0x7F_8000–0x7F_8FFF 4 Kbytes 11 0x7F_8000–0x7F_9FFF 8 Kbytes Table 3-10. FPROT Field Descriptions (continued) Field Description

Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 143 All possible Flash protection scenarios are shown in Figure 3-11. Although the protection scheme is loaded from the Flash array at global address 0x7F_FF0D during the reset sequence, it can be changed by the user. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if re-programming is not required.

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Figure 3-11. Flash Protection Scenarios 7 6 5 4 3 2 1 0 FPHDIS=1 FPLDIS=1 FPHDIS=1 FPLDIS=0 FPHDIS=0 FPLDIS=1 FPHDIS=0 FPLDIS=0 Scenario Scenario Unprotected region Protected region with size Protected region Protected region with size defined by FPLS defined by FPHSnot defined by FPLS, FPHS 0x7F_8000 0x7F_FFFF 0x7F_8000 0x7F_FFFF 0x78_0000 0x78_0000 FPHS[1:0] FPLS[1:0] FPOPEN=1 FPHS[1:0] FPLS[1:0] FPOPEN=0

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3.3.2.5.1 Flash Protection Restrictions

The general guideline is that Flash protection can only be added and not removed.Table 3-14 specifies all valid transitions between Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS descriptions for additional restrictions.

3.3.2.6 Flash Status Register (FSTAT)

The FSTAT register defines the operational status of the module. Table 3-14. Flash Protection Scenario Transitions From Protection Scenario To Protection Scenario1 1 Allowed transitions marked with X. 01234567

0 XXXX

5 XXXX

6 XX XX

7 XXXXXXXX

R CBEIF CCIF PVIOL ACCERR W Reset 11000000 = Unimplemented or Reserved Figure 3-12. Flash Status Register (FSTAT — Normal Mode) Module Base + 0x0005 76543210 R CBEIF CCIF PVIOL ACCERR

0 BLANK

W Reset 11000000 = Unimplemented or Reserved Figure 3-13. Flash Status Register (FSTAT — Special Mode)

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CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode. FAIL must be clear in special mode when starting a command write sequence. Table 3-15. FSTAT Field Descriptions Field Description CBEIF Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data and command buffers are empty so that a new command write sequence can be started. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the Flash address space, but before CBEIF is cleared, will abort a command write sequence and cause the ACCERR flag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is cleared by writing a 1 to CBEIF. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request (see Figure 3-32). 0 Command buffers are full. 1 Command buffers are ready to accept a new command. CCIF Command Complete Interrupt Flag— The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is cleared and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect on CCIF. The CCIF flag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 3-32). 0 Command in progress. 1 All commands are completed. PVIOL Protection Violation Flag —The PVIOL flag indicates an attempt was made to program or erase an address in a protected area of the Flash memory during a command write sequence. Writing a 0 to the PVIOL flag has no effect on PVIOL. The PVIOL flag is cleared by writing a 1 to PVIOL. While PVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected. 1 Protection violation has occurred. ACCERR Access Error Flag — The ACCERR flag indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (seeSection 3.4.1.2, “Command Write Sequence”), issuing an illegal Flash command (see Table 3-17), launching the sector erase abort command terminating a sector erase operation early (see Section 3.4.2.6, “Sector Erase Abort Command”) or the execution of a CPU STOP instruction while a command is executing (CCIF = 0). Writing a 0 to the ACCERR flag has no effect on ACCERR. The ACCERR flag is cleared by writing a 1 to ACCERR.While ACCERR is set, it is not possible to launch a command or start a command write sequence. If ACCERR is set by an erase verify operation or a data compress operation, any buffered command will not launch. 0 No access error detected. 1 Access error has occurred. BLANK Flag Indicating the Erase Verify Operation Status — When the CCIF flag is set after completion of an erase verify command, the BLANK flag indicates the result of the erase verify operation. The BLANK flag is cleared by the Flash module when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect on BLANK. 0 Flash block verified as not erased. 1 Flash block verified as erased. FAIL Flag Indicating a Failed Flash Operation — The FAIL flag will set if the erase verify operation fails (selected Flash block verified as not erased). Writing a 0 to the FAIL flag has no effect on FAIL. The FAIL flag is cleared by writing a 1 to FAIL. 0 Flash operation completed without error. 1 Flash operation failed.

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3.3.2.7 Flash Command Register (FCMD)

The FCMD register is the Flash command register. All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable.

3.3.2.8 Flash Control Register (FCTL)

The FCTL register is the Flash control register. All bits in the FCTL register are readable but are not writable. Module Base + 0x0006 76543210 CMDB W Reset 11000000 = Unimplemented or Reserved Figure 3-14. Flash Command Register (FCMD) Table 3-16. FCMD Field Descriptions Field Description 6:0 CMDB[6:0] Flash Command — Valid Flash commands are shown in Table 3-17. Writing any command other than those listed in Table 3-17 sets the ACCERR flag in the FSTAT register. Table 3-17. Valid Flash Command List CMDB[6:0] NVM Command 0x05 Erase Verify 0x06 Data Compress 0x20 Word Program 0x40 Sector Erase 0x41 Mass Erase 0x47 Sector Erase Abort Module Base + 0x0007 76543210 R 0 NV6 NV5 NV4 NV3 NV2 NV1 NV0 W Reset 0 F FFFFFF = Unimplemented or Reserved Figure 3-15. Flash Control Register (FCTL)

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The FCTL NV bits are loaded from the Flash nonvolatile byte located at global address 0x7F_FF0E during the reset sequence, indicated by F in Figure 3-15.

3.3.2.9 Flash Address Registers (FADDR)

The FADDRHI and FADDRLO registers are the Flash address registers. All FADDRHI and FADDRLO bits are readable but are not writable. After an array write as part of a command write sequence, the FADDR registers will contain the mapped MCU address written.

3.3.2.10 Flash Data Registers (FDATA)

The FDATAHI and FDATALO registers are the Flash data registers. Table 3-18. FCTL Field Descriptions Field Description 6:0 NV[6:0] Nonvolatile Bits — The NV[6:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper use of the NV bits. Module Base + 0x0008 76543210 R FADDRHI W Reset 00000000 = Unimplemented or Reserved Figure 3-16. Flash Address High Register (FADDRHI) Module Base + 0x0009 76543210 R FADDRLO W Reset 00000000 = Unimplemented or Reserved Figure 3-17. Flash Address Low Register (FADDRLO) Module Base + 0x000A 76543210 R FDATAHI W Reset 00000000 = Unimplemented or Reserved Figure 3-18. Flash Data High Register (FDATAHI)

Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 149 All FDATAHI and FDATALO bits are readable but are not writable. At the completion of a data compress operation, the resulting 16-bit signature is stored in the FDATA registers. The data compression signature is readable in the FDATA registers until a new command write sequence is started.

3.3.2.11 RESERVED1

This register is reserved for factory testing and is not accessible. All bits read 0 and are not writable.

3.3.2.12 RESERVED2

This register is reserved for factory testing and is not accessible. All bits read 0 and are not writable.

3.3.2.13 RESERVED3

This register is reserved for factory testing and is not accessible. Module Base + 0x000B 76543210 R FDATALO W Reset 00000000 = Unimplemented or Reserved Figure 3-19. Flash Data Low Register (FDATALO) Module Base + 0x000C 76543210 R 00000000 W Reset 00000000 = Unimplemented or Reserved Figure 3-20. RESERVED1 Module Base + 0x000D 76543210 R 00000000 W Reset 00000000 = Unimplemented or Reserved Figure 3-21. RESERVED2

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All bits read 0 and are not writable.

3.3.2.14 RESERVED4

This register is reserved for factory testing and is not accessible. All bits read 0 and are not writable.

3.4 Functional Description

3.4.1 Flash Command Operations

Write operations are used to execute program, erase, erase verify, erase abort, and data compress algorithms described in this section. The program and erase algorithms are controlled by a state machine whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command register, as well as the associated address and data registers, operate as a buffer and a register (2-stage FIFO) so that a second command along with the necessary data and address can be stored to the buffer while the first command is still in progress. This pipelined operation allows a time optimization when programming more than one word on a specific row in the Flash block as the high voltage generation can be kept active in between two programming commands. The pipelined operation also allows a simplification of command launching. Buffer empty as well as command completion are signalled by flags in the Flash status register with corresponding interrupts generated, if enabled. The next sections describe: 1. How to write the FCLKDIV register 2. Command write sequences to program, erase, erase verify, erase abort, and data compress operations on the Flash memory Module Base + 0x000E 76543210 R 00000000 W Reset 00000000 = Unimplemented or Reserved Figure 3-22. RESERVED3 Module Base + 0x000F 76543210 R 00000000 W Reset 00000000 = Unimplemented or Reserved Figure 3-23. RESERVED4

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3.4.1.1 Writing the FCLKDIV Register

Prior to issuing any Flash command after a reset, the user is required to write the FCLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account. If we define:

• FCLK as the clock of the Flash timing control block
• Tbus as the period of the bus clock
• INT(x) as taking the integer part of x (e.g. INT(4.323) = 4) then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 3-24. For example, if the oscillator clock frequency is 950kHz and the bus clock frequency is 10MHz, FCLKDIV bits FDIV[5:0] should be set to 0x04 (000100) and bit PRDIV8 set to 0. The resulting FCLK frequency is then 190kHz. As a result, the Flash program and erase algorithm timings are increased over the optimum target by: If the oscillator clock frequency is 16MHz and the bus clock frequency is 40MHz, FCLKDIV bits FDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1. The resulting FCLK frequency is then 182kHz. In this case, the Flash program and erase algorithm timings are increased over the optimum target by: CAUTION Program and erase command execution time will increase proportionally with the period of FCLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the Flash memory with FCLK < 150 kHz should be avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can destroy the Flash memory due to overstress. Setting FCLKDIV to a value such that (1/FCLK+Tbus) < 5µs can result in incomplete programming or erasure of the Flash memory cells. If the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR flag in the FSTAT register will set.

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Figure 3-24. Determination Procedure for PRDIV8 and FDIV Bits PRDIV8=1 yes no PRDIV8=0 (reset) 12.8MHz? FCLK=(PRDCLK)/(1+FDIV[5:0]) PRDCLK=oscillator_clockPRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) no FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 yes START Tbus < 1µs? an integer? FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.15MHz? END yes no FDIV[5:0] > 4? ALL COMMANDS IMPOSSIBLE yes no ALL COMMANDS IMPOSSIBLE no TRY TO DECREASE Tbus yes oscillator_clock

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3.4.1.2 Command Write Sequence

The Flash command controller is used to supervise the command write sequence to execute program, erase, erase verify, erase abort, and data compress algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear (see Section 3.3.2.6, “Flash Status Register (FSTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the Flash module not permitted between the steps. However, Flash register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. Write to a valid address in the Flash memory. Addresses in multiple Flash blocks can be written to as long as the location is at the same relative address in each available Flash block. Multiple addresses must be written in Flash block order starting with the lower Flash block. 2. Write a valid command to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command. The address written in step 1 will be stored in the FADDR registers and the data will be stored in the FDATA registers. If the CBEIF flag in the FSTAT register is clear when the first Flash array write occurs, the contents of the address and data buffers will be overwritten and the CBEIF flag will be set. When the CBEIF flag is cleared, the CCIF flag is cleared on the same bus cycle by the Flash command controller indicating that the command was successfully launched. For all command write sequences except data compress and sector erase abort, the CBEIF flag will set four bus cycles after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. For data compress and sector erase abort operations, the CBEIF flag will remain clear until the operation completes. Except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. The sector erase abort command is launched when the CBEIF flag is cleared as part of a sector erase abort command write sequence. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the FSTAT register. The CCIF flag will set upon completion of all active and buffered commands.

3.4.2 Flash Commands

Table 3-19 summarizes the valid Flash commands along with the effects of the commands on the Flash block. Table 3-19. Flash Command Description FCMDB NVM Command Function on Flash Memory 0x05 Erase Verify Verify all memory bytes in the Flash block are erased. If the Flash block is erased, the BLANK flag in the FSTAT register will set upon command completion.

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A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 0x06 Data Compress Compress data from a selected portion of the Flash block. The resulting signature is stored in the FDATA register. 0x20 Program Program a word (two bytes) in the Flash block. 0x40 Sector Erase Erase all memory bytes in a sector of the Flash block. 0x41 Mass Erase Erase all memory bytes in the Flash block. A mass erase of the full Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. 0x47 Sector Erase Abort Abort the sector erase operation. The sector erase operation will terminate according to a set procedure. The Flash sector should not be considered erased if the ACCERR flag is set upon command completion. Table 3-19. Flash Command Description FCMDB NVM Command Function on Flash Memory

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3.4.2.1 Erase Verify Command

The erase verify operation will verify that a Flash block is erased. An example flow to execute the erase verify operation is shown inFigure 3-25. The erase verify command write sequence is as follows: 1. Write an aligned word to a valid address in the Flash array memory to start the command write sequence for the erase verify command. The address and data written will be ignored. Multiple Flash blocks can be simultaneously erase verified by writing to the same relative address in each Flash block. 2. Write the erase verify command, 0x05, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered. The number of bus cycles required to execute the erase verify operation is equal to the number of addresses in a Flash block plus 14 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Upon completion of the erase verify operation, the BLANK flag in the FSTAT register will be set if all addresses in the selected Flash blocks are verified to be erased. If any address in a selected Flash block is not erased, the erase verify operation will terminate and the BLANK flag in the FSTAT register will remain clear. The MRDS bits in the FTSTMOD register will determine the sense-amp margin setting during the erase verify operation.

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Figure 3-25. Example Erase Verify Command Flow Write: Flash Block Address Write: FCMD register Erase Verify Command 0x05 Write: FSTAT register Clear CBEIF 0x80 Clear ACCERR/PVIOL 0x30 Write: FSTAT registeryes no Access Error and Protection Violation no and Dummy Data Bit Polling for Command Completion Check Read: FSTAT register yes Read: FSTAT register no START yes Check CBEIF Set? Next no yes Address, Data, Command Buffer Empty Check Flash Block? CCIF Set? ACCERR/ PVIOL Set? noErase Verify Status yes EXIT Flash Block Not ErasedEXIT Flash Block Erased BLANK Set? Decrement Global Address Write: FCLKDIV register Read: FCLKDIV register yes noClock Register Written Check FDIVLD Set? NOTE: FCLKDIV needs to be set once after each reset. Simultaneous Multiple Flash Block Decision by 128K

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3.4.2.2 Data Compress Command

The data compress operation will check Flash code integrity by compressing data from a selected portion of the Flash memory into a signature analyzer. An example flow to execute the data compress operation is shown in Figure 3-26. The data compress command write sequence is as follows: 1. Write an aligned word to a valid address in the Flash array memory to start the command write sequence for the data compress command. The address written determines the starting address for the data compress operation and the data written determines the number of consecutive words to compress with an upper limit of 16,384. Multiple Flash blocks can be simultaneously compressed by writing to the same relative address in each Flash block. If more than one Flash block is written to in this step, the first data written will determine the number of consecutive words to compress in each selected Flash block. 2. Write the data compress command, 0x06, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the data compress command. After launching the data compress command, the CCIF flag in the FSTAT register will set after the data compress operation has completed. The number of bus cycles required to execute the data compress operation is equal to two times the number of consecutive words to compress plus the number of Flash blocks simultaneously compressed plus 18 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Once the CCIF flag is set, the signature generated by the data compress operation is available in the FDATA registers. The signature in the FDATA registers can be compared to the expected signature to determine the integrity of the selected data stored in the selected Flash memory. If the last address of a Flash block is reached during the data compress operation, data compression will continue with the starting address of the same Flash block. The MRDS bits in the FTSTMOD register will determine the sense-amp margin setting during the data compress operation. NOTE Since the FDATA registers (or data buffer) are written to as part of the data compress operation, a command write sequence is not allowed to be buffered behind a data compress command write sequence. The CBEIF flag will not set after launching the data compress command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a data compress operation active, the ACCERR flag in the FSTAT register will be set. A new command write sequence should only be started after reading the signature stored in the FDATA registers. In order to take corrective action, it is recommended that the data compress command be executed on a Flash sector or subset of a Flash sector. If the data compress operation on a Flash sector returns an invalid signature, the Flash sector should be erased using the sector erase command and then reprogrammed using the program command. The data compress command can be used to verify that a sector or sequential set of sectors are erased.

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Figure 3-26. Example Data Compress Command Flow Write: Flash Address to start Write: FCMD register Data Compress Command 0x06 Write: FSTAT register Clear CBEIF 0x80 Clear ACCERR/PVIOL 0x30 Write: FSTAT registeryes no Access Error and Protection Violation no compression and number of word Bit Polling for Command Completion Check Read: FSTAT register yes Read: FSTAT register no START yes Check CBEIF Set? Next no yes Address, Data, Command Buffer Empty Check Flash Block? CCIF Set? ACCERR/ PVIOL Set? EXIT Erase and Reprogram by 128K Decrement Global Address Write: FCLKDIV register Read: FCLKDIV register yes noClock Register Written Check FDIVLD Set? NOTE: FCLKDIV needs to be set once after each reset. Simultaneous Multiple Flash Block Decision Flash Sector(s) Compressed Data Compress Signature Read: FDATA registers no yes Signature Valid? addresses to compress (max 16,384) NOTE: address used to select Flash block; data ignored.

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3.4.2.2.1 Data Compress Operation

The Flash module contains a 16-bit multiple-input signature register (MISR) for each Flash block to generate a 16-bit signature based on selected Flash array data. If multiple Flash blocks are selected for simultaneous compression, then the signature from each Flash block is further compressed to generate a single 16-bit signature. The final 16-bit signature, found in the FDATA registers after the data compress operation has completed, is based on the following logic equation which is executed on every data compression cycle during the operation: MISR[15:0] = {MISR[14:0], ^MISR[15,4,2,1]} ^ DATA[15:0] Eqn. 3-1 where MISR is the content of the internal signature register associated with each Flash block and DATA is the data to be compressed as shown in Figure 3-27. Figure 3-27. 16-Bit MISR Diagram During the data compress operation, the following steps are executed: 1. MISR for each Flash block is reset to 0xFFFF. 2. Initialized DATA equal to 0xFFFF is compressed into the MISR for each selected Flash block which results in the MISR containing 0x0001. 3. DATA equal to the selected Flash array data range is read and compressed into the MISR for each selected Flash block with addresses incrementing. 4. DATA equal to the selected Flash array data range is read and compressed into the MISR for each selected Flash block with addresses decrementing. 5. If Flash block 0 is selected for compression, DATA equal to the contents of the MISR for Flash block 0 is compressed into the MISR for Flash block 0. If data in Flash block 0 was not selected for compression, the MISR for Flash block 0 contains 0xFFFF. 6. If Flash block 1 is selected for compression, DATA equal to the contents of the MISR for Flash block 1 is compressed into the MISR for Flash block 0. 7. If Flash block 2 is selected for compression, DATA equal to the contents of the MISR for Flash block 2 is compressed into the MISR for Flash block 0. 8. If Flash block 3 is selected for compression, DATA equal to the contents of the MISR for Flash block 3 is compressed into the MISR for Flash block 0. 9. If Flash block 4 is selected for compression, DATA equal to the contents of the MISR for Flash block 4 is compressed into the MISR for Flash block 0. DQ = Exclusive-OR DATA[0] DQ DATA[1] DQ DATA[2] DQ DATA[3] DQ DATA[4] DQ DATA[5] DQ DATA[15] M15 ... + + MISR[15:0] = Q[15:0]

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1. If Flash block 5 is selected for compression, DATA equal to the contents of the MISR for Flash block 5 is compressed into the MISR for Flash block 0. 11. If Flash block 6 is selected for compression, DATA equal to the contents of the MISR for Flash block 6 is compressed into the MISR for Flash block 0. 12. If Flash block 7 is selected for compression, DATA equal to the contents of the MISR for Flash block 7 is compressed into the MISR for Flash block 0. 13. The contents of the MISR for Flash block 0 are written to the FDATA registers.

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3.4.2.3 Program Command

The program operation will program a previously erased word in the Flash memory using an embedded algorithm. An example flow to execute the program operation is shown inFigure 3-28. The program command write sequence is as follows: 1. Write an aligned word to a valid address in the Flash array memory to start the command write sequence for the program command. The data written will be programmed to the address written. Multiple Flash blocks can be simultaneously programmed by writing to the same relative address in each Flash block. 2. Write the program command, 0x20, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command. If a word to be programmed is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the FSTAT register will set after the program operation has completed unless a new command write sequence has been buffered. By executing a new program command write sequence on sequential words after the CBEIF flag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF flag to set after each program operation.

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Figure 3-28. Example Program Command Flow Write: Flash Address Write: FCMD register Program Command 0x20 Write: FSTAT register Clear CBEIF 0x80 Clear ACCERR/PVIOL 0x30 Write: FSTAT registeryes no Access Error and Protection Violation no and program Data Bit Polling for Buffer Empty Check Read: FSTAT register yes Read: FSTAT register no START yes Check CBEIF Set? Next no yes Address, Data, Command Buffer Empty Check Flash Block? CBEIF Set? ACCERR/ PVIOL Set? EXIT by 128K Decrement Global Address Write: FCLKDIV register Read: FCLKDIV register yes noClock Register Written Check FDIVLD Set? NOTE: FCLKDIV needs to be set once after each reset. Simultaneous Multiple Flash Block Decision no yesSequential Programming Decision Next Word? noBit Polling for Command Completion Check Read: FSTAT register yes CCIF Set?

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3.4.2.4 Sector Erase Command

The sector erase operation will erase all addresses in a 1 Kbyte sector of Flash memory using an embedded algorithm. An example flow to execute the sector erase operation is shown inFigure 3-29. The sector erase command write sequence is as follows: 1. Write an aligned word to a valid address in the Flash array memory to start the command write sequence for the sector erase command. The Flash address written determines the sector to be erased while global address bits [9:0] and the data written are ignored. Multiple Flash sectors can be simultaneously erased by writing to the same relative address in each Flash block. 2. Write the sector erase command, 0x40, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command. If a Flash sector to be erased is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered.

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Figure 3-29. Example Sector Erase Command Flow Write: Flash Sector Address Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Clear ACCERR/PVIOL 0x30 Write: FSTAT registeryes no Access Error and Protection Violation and Dummy Data Read: FSTAT register Read: FSTAT register no START yes Check CBEIF Set? Next no yes Address, Data, Command Buffer Empty Check Flash Block? ACCERR/ PVIOL Set? EXIT by 128K Decrement Global Address Write: FCLKDIV register Read: FCLKDIV register yes noClock Register Written Check FDIVLD Set? NOTE: FCLKDIV needs to be set once after each reset. Simultaneous Multiple Flash Block Decision noBit Polling for Command Completion Check yes CCIF Set?

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3.4.2.5 Mass Erase Command

The mass erase operation will erase all addresses in a Flash block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 3-30. The mass erase command write sequence is as follows: 1. Write an aligned word to any valid address in a Flash block to start the command write sequence for the mass erase command. The data written will be ignored while the address written determines which Flash block is erased. Multiple Flash blocks can be simultaneously mass erased by writing to the same relative address in each Flash block. 2. Write the mass erase command, 0x41, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command. If a Flash block to be erased contains any protected area, the PVIOL flag in the FSTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered.

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Figure 3-30. Example Mass Erase Command Flow Write: Flash Block Address Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Clear ACCERR/PVIOL 0x30 Write: FSTAT registeryes no Access Error and Protection Violation and Dummy Data Read: FSTAT register Read: FSTAT register no START yes Check CBEIF Set? Next no yes Address, Data, Command Buffer Empty Check Flash Block? ACCERR/ PVIOL Set? EXIT by 128K Decrement Global Address Write: FCLKDIV register Read: FCLKDIV register yes noClock Register Written Check FDIVLD Set? NOTE: FCLKDIV needs to be set once after each reset. Simultaneous Multiple Flash Block Decision noBit Polling for Command Completion Check yes CCIF Set?

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3.4.2.6 Sector Erase Abort Command

The sector erase abort operation will terminate the active sector erase operation so that other sectors in a Flash block are available for read and program operations without waiting for the sector erase operation to complete. An example flow to execute the sector erase abort operation is shown inFigure 3-31. The sector erase abort command write sequence is as follows: 1. Write an aligned word to any valid address in the Flash array memory to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2. Write the sector erase abort command, 0x47, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase abort command. If the sector erase abort command is launched resulting in the early termination of an active sector erase operation, the ACCERR flag will set once the operation completes as indicated by the CCIF flag being set. The ACCERR flag sets to inform the user that the Flash sector may not be fully erased and a new sector erase command must be launched before programming any location in that specific sector. If the sector erase abort command is launched but the active sector erase operation completes normally, the ACCERR flag will not set upon completion of the operation as indicated by the CCIF flag being set. Therefore, if the ACCERR flag is not set after the sector erase abort command has completed, a Flash sector being erased when the abort command was launched will be fully erased. The maximum number of cycles required to abort a sector erase operation is equal to four FCLK periods (seeSection 3.4.1.1, “Writing the FCLKDIV Register”) plus five bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. If sectors in multiple Flash blocks are being simultaneously erased, the sector erase abort operation will be applied to all active Flash blocks without writing to each Flash block in the sector erase abort command write sequence. NOTE Since the ACCERR bit in the FSTAT register may be set at the completion of the sector erase abort operation, a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence. The CBEIF flag will not set after launching the sector erase abort command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a sector erase abort operation active, the ACCERR flag in the FSTAT register will be set. A new command write sequence may be started after clearing the ACCERR flag, if set. NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle.

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Figure 3-31. Example Sector Erase Abort Command Flow Write: Dummy Flash Address Write: FCMD register Sector Erase Abort Cmd 0x47 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register and Dummy Data Bit Polling for Command Completion Check yes CCIF Set? Execute Sector Erase Command Flow noBit Polling for Command Completion Check Read: FSTAT register yes CCIF Set? no yes Abort Needed? Erase Clear ACCERR 0x10 Write: FSTAT registeryes no Access Error Check ACCERR Set? Sector Erase Completed Sector Erase Aborted no EXIT EXIT Sector Erase Completed EXIT

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3.4.3 Illegal Flash Operations

The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to a Flash address before initializing the FCLKDIV register. 2. Writing a byte or misaligned word to a valid Flash address. 3. Starting a command write sequence while a data compress operation is active. 4. Starting a command write sequence while a sector erase abort operation is active. 5. Writing a Flash address in step 1 of a command write sequence that is not the same relative address as the first one written in the same command write sequence. 6. Writing to any Flash register other than FCMD after writing to a Flash address. 7. Writing a second command to the FCMD register in the same command write sequence. 8. Writing an invalid command to the FCMD register. 9. When security is enabled, writing a command other than mass erase to the FCMD register when the write originates from a non-secure memory location or from the Background Debug Mode. 10. Writing to a Flash address after writing to the FCMD register. 11. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD register. 12. Writing a 0 to the CBEIF flag in the FSTAT register to abort a command write sequence. The ACCERR flag will not be set if any Flash register is read during a valid command write sequence. The ACCERR flag will also be set if any of the following events occur: 1. Launching the sector erase abort command while a sector erase operation is active which results in the early termination of the sector erase operation (see Section 3.4.2.6, “Sector Erase Abort Command”). 2. The MCU enters stop mode and a program or erase operation is in progress. The operation is aborted immediately and any pending command is purged (see Section 3.5.2, “Stop Mode”). If the Flash memory is read during execution of an algorithm (CCIF = 0), the read operation will return invalid data and the ACCERR flag will not be set. If the ACCERR flag is set in the FSTAT register, the user must clear the ACCERR flag before starting another command write sequence (see Section 3.3.2.6, “Flash Status Register (FSTAT)”). The PVIOL flag will be set after the command is written to the FCMD register during a command write sequence if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. Writing the program command if an address written in the command write sequence was in a protected area of the Flash memory 2. Writing the sector erase command if an address written in the command write sequence was in a protected area of the Flash memory 3. Writing the mass erase command to a Flash block while any Flash protection is enabled in the block

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If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 3.3.2.6, “Flash Status Register (FSTAT)”).

3.5 Operating Modes

3.5.1 Wait Mode

If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 3.8, “Interrupts”).

3.5.2 Stop Mode

If a command is active (CCIF = 0) when the MCU enters stop mode, the operation will be aborted and, if the operation is program or erase, the Flash array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the Flash memory will immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set and any buffered command will not be launched. The ACCERR flag must be cleared before starting a command write sequence (see Section 3.4.1.2, “Command Write Sequence”). NOTE As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program or erase operations.

3.5.3 Background Debug Mode

In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all Flash commands listed in Table 3-19 can be executed. If the MCU is secured and is in special single chip mode, only mass erase can be executed.

3.6 Flash Module Security

The Flash module provides the necessary security information to the MCU. After each reset, the Flash module determines the security state of the MCU as defined in Section 3.3.2.2, “Flash Security Register (FSEC)”. The contents of the Flash security byte at 0x7F_FF0F in the Flash Configuration Field must be changed directly by programming 0x7F_FF0F when the MCU is unsecured and the higher address sector is unprotected. If the Flash security byte is left in a secured state, any reset will cause the MCU to initialize to a secure operating mode.

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3.6.1 Unsecuring the MCU using Backdoor Key Access

The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If the KEYEN[1:0] bits are in the enabled state (seeSection 3.3.2.2, “Flash Security Register (FSEC)”) and the KEY ACC bit is set, a write to a backdoor key address in the Flash memory triggers a comparison between the written data and the backdoor key data stored in the Flash memory. If all four words of data are written to the correct addresses in the correct order and the data matches the backdoor keys stored in the Flash memory, the MCU will be unsecured. The data must be written to the backdoor keys sequentially starting with 0x7F_FF00–1 and ending with 0x7F_FF06–7. 0x0000 and 0xFFFF are not permitted as backdoor keys. While the KEY ACC bit is set, reads of the Flash memory will return invalid data. The user code stored in the Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 3.3.2.2, “Flash Security Register (FSEC)”), the MCU can be unsecured by the backdoor key access sequence described below: 1. Set the KEY ACC bit in the Flash Configuration Register (FCNFG). 2. Write the correct four 16-bit words to Flash addresses 0xFF00–0xFF07 sequentially starting with 0x7F_FF00. 3. Clear the KEY ACC bit. Depending on the user code used to write the backdoor keys, a wait cycle (NOP) may be required before clearing the KEY ACC bit. 4. If all four 16-bit words match the backdoor keys stored in Flash addresses 0x7F_FF00–0x7F_FF07, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 1:0. The backdoor key access sequence is monitored by an internal security state machine. An illegal operation during the backdoor key access sequence will cause the security state machine to lock, leaving the MCU in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted. The following operations during the backdoor key access sequence will lock the security state machine: 1. If any of the four 16-bit words does not match the backdoor keys programmed in the Flash array. 2. If the four 16-bit words are written in the wrong sequence. 3. If more than four 16-bit words are written. 4. If any of the four 16-bit words written are 0x0000 or 0xFFFF. 5. If the KEY ACC bit does not remain set while the four 16-bit words are written. 6. If any two of the four 16-bit words are written on successive MCU clock cycles. After the backdoor keys have been correctly matched, the MCU will be unsecured. Once the MCU is unsecured, the Flash security byte can be programmed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x7F_FF00–0x7F_FF07 in the Flash Configuration Field. The security as defined in the Flash security byte (0x7F_FF0F) is not changed by using the backdoor key access sequence to unsecure. The backdoor keys stored in addresses 0x7F_FF00–0x7F_FF07 are

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unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the Flash module is determined by the Flash security byte (0x7F_FF0F). The backdoor key access sequence has no effect on the program and erase protections defined in the Flash protection register. It is not possible to unsecure the MCU in special single chip mode by using the backdoor key access sequence in background debug mode (BDM).

3.6.2 Unsecuring the MCU in Special Single Chip Mode using BDM

The MCU can be unsecured in special single chip mode by erasing the Flash module by the following method:

• Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the Flash module, and execute a mass erase command write sequence to erase the Flash memory. After the CCIF flag sets to indicate that the mass operation has completed, reset the MCU into special single chip mode. The BDM secure ROM will verify that the Flash memory is erased and will assert the UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security state and the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state by the following method:
• Send BDM commands to execute a word program sequence to program the Flash security byte to the unsecured state and reset the MCU.

3.7 Resets

3.7.1 Flash Reset Sequence

On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash memory according to Table 3-1:

• FPROT — Flash Protection Register (see Section 3.3.2.5).
• FCTL - Flash Control Register (see Section 3.3.2.8).
• FSEC — Flash Security Register (see Section 3.3.2.2).

3.7.2 Reset While Flash Command Active

If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed.

3.8 Interrupts

The Flash module can generate an interrupt when all Flash command operations have completed, when the Flash address, data and command buffers are empty.

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3.8.1 Description of Flash Interrupt Operation

The logic used for generating interrupts is shown in Figure 3-32. The Flash module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the Flash command interrupt request. Figure 3-32. Flash Interrupt Implementation For a detailed description of the register bits, refer to Section 3.3.2.4, “Flash Configuration Register (FCNFG)” and Section 3.3.2.6, “Flash Status Register (FSTAT)”. Table 3-20. Flash Interrupt Sources Interrupt Source Interrupt Flag Local Enable Global (CCR) Mask Flash Address, Data and Command Buffers empty CBEIF (FSTAT register) CBEIE (FCNFG register) I Bit All Flash commands completed CCIF (FSTAT register) CCIE (FCNFG register) I Bit Flash Command Interrupt Request CBEIE CBEIF CCIE CCIF

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MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 175 Chapter 4

4.1 Introduction

This document describes the EETX4K module which includes a 4 Kbyte EEPROM (nonvolatile) memory. The EEPROM memory may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. The EEPROM memory is ideal for data storage for single-supply applications allowing for field reprogramming without requiring external voltage sources for program or erase. Program and erase functions are controlled by a command driven interface. The EEPROM module supports both block erase (all memory bytes) and sector erase (4 memory bytes). An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase the EEPROM memory is generated internally. It is not possible to read from the EEPROM block while it is being erased or programmed. CAUTION An EEPROM word (2 bytes) must be in the erased state before being programmed. Cumulative programming of bits within a word is not allowed.

4.1.1 Glossary

Command Write Sequence — A three-step MCU instruction sequence to execute built-in algorithms (including program and erase) on the EEPROM memory.

4.1.2 Features

• 4 Kbytes of EEPROM memory divided into 1024 sectors of 4 bytes
• Automated program and erase algorithm
• Interrupts on EEPROM command completion and command buffer empty
• Fast sector erase and word program operation
• 2-stage command pipeline
• Sector erase abort feature for critical interrupt response
• Flexible protection scheme to prevent accidental program or erase
• Single power supply for all EEPROM operations including program and erase

4.1.3 Modes of Operation

Program, erase and erase verify operations (please refer to Section 4.4.1, “EEPROM Command Operations” for details).

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4.1.4 Block Diagram

A block diagram of the EEPROM module is shown in Figure 4-1. Figure 4-1. EETX4K Block Diagram

4.2 External Signal Description

The EEPROM module contains no signals that connect off-chip.

4.3 Memory Map and Register Definition

This section describes the memory map and registers for the EEPROM module.

4.3.1 Module Memory Map

The EEPROM memory map is shown in Figure 4-2. The HCS12X architecture places the EEPROM memory addresses between global addresses 0x13_F000 and 0x13_FFFF. The EPROT register, described in Section 4.3.2.5, “EEPROM Protection Register (EPROT)”, can be set to protect the upper region in the EEPROM memory from accidental program or erase. The EEPROM addresses covered by this protectable EETX4K EEPROM 2K * 16 Bits sector 0 sector 1 sector 1023 Oscillator Clock Divider Clock Command Interrupt Request EECLK Protection Command Pipeline cmd2 addr2 data2 cmd1 addr1 data1 Registers EEPROM Interface

Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 177 region are shown in the EEPROM memory map. The default protection setting is stored in the EEPROM configuration field as described in Table 4-1. Table 4-1. EEPROM Configuration Field Global Address Size (bytes) Description 0x13_FFFC 1 Reserved 0x13_FFFD 1 EEPROM Protection byte Refer to Section 4.3.2.5, “EEPROM Protection Register (EPROT)” 0x13_FFFE – 0x13_FFFF 2 Reserved

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Figure 4-2. EEPROM Memory Map EEPROM Registers MODULE BASE+ 0x0000 EEPROM Configuration Field MODULE BASE + 0x000B EEPROM START = 0x13_F000 EEPROM END = 0x13_FFFF 0x13_FFC0 0x13_FF80 EEPROM Memory Protected Region 64, 128, 192, 256, 320, 384, 448, 512 bytes EEPROM Memory 3584 bytes (up to 4032 bytes) 12 bytes 4 bytes (0x13_FFFC – 0x13_FFFF) 0x13_FF40 0x13_FF00 0x13_FEC0 0x13_FE80 0x13_FE40 0x13_FE00

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4.3.2 Register Descriptions

The EEPROM module also contains a set of 12 control and status registers located between EEPROM module base + 0x0000 and 0x000B. A summary of the EEPROM module registers is given inFigure 4-3. Detailed descriptions of each register bit are provided. Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 ECLKDIV R EDIVLD PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 W 0x0001 RESERVED1 R 00000000 W 0x0002 RESERVED2 R 00000000 W 0x0003 ECNFG R CBEIE CCIE 000000 W 0x0004 EPROT R EPOPEN RNV6 RNV5 RNV4 EPDIS EPS2 EPS1 EPS0 W 0x0005 ESTAT R CBEIF CCIF PVIOL ACCERR W 0x0006 ECMD CMDB W 0x0007 RESERVED3 R 00000000 W 0x0008 EADDRHI R 00000 EABHI W 0x0009 EADDRLO R EABLO W 0x000A EDATAHI R EDHI W 0x000B EDATALO R EDLO W = Unimplemented or Reserved Figure 4-3. EETX4K Register Summary

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4.3.2.1 EEPROM Clock Divider Register (ECLKDIV)

The ECLKDIV register is used to control timed events in program and erase algorithms. All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.

4.3.2.2 RESERVED1

This register is reserved for factory testing and is not accessible. All bits read 0 and are not writable.

4.3.2.3 RESERVED2

This register is reserved for factory testing and is not accessible. Module Base + 0x0000 76543210 R EDIVLD PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 W Reset 00000000 = Unimplemented or Reserved Figure 4-4. EEPROM Clock Divider Register (ECLKDIV) Table 4-2. ECLKDIV Field Descriptions Field Description EDIVLD Clock Divider Loaded 0 Register has not been written. 1 Register has been written to since the last reset. PRDIV8 Enable Prescalar by 8 0 The oscillator clock is directly fed into the ECLKDIV divider. 1 Enables a Prescalar by 8, to divide the oscillator clock before feeding into the clock divider. 5:0 EDIV[5:0] Clock Divider Bits— The combination of PRDIV8 and EDIV[5:0] effectively divides the EEPROM module input oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Please refer to Section 4.4.1.1, “Writing the ECLKDIV Register” for more information. Module Base + 0x0001 76543210 R 00000000 W Reset 00000000 = Unimplemented or Reserved Figure 4-5. RESERVED1

Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 181 All bits read 0 and are not writable.

4.3.2.4 EEPROM Configuration Register (ECNFG)

The ECNFG register enables the EEPROM interrupts. CBEIE and CCIE bits are readable and writable while all remaining bits read 0 and are not writable. Module Base + 0x0002 76543210 R 00000000 W Reset 00000000 = Unimplemented or Reserved Figure 4-6. RESERVED2 Module Base + 0x0003 76543210 R CBEIE CCIE 000000 W Reset 00000000 = Unimplemented or Reserved Figure 4-7. EEPROM Configuration Register (ECNFG) Table 4-3. ECNFG Field Descriptions Field Description CBEIE Command Buffer Empty Interrupt Enable— The CBEIE bit enables an interrupt in case of an empty command buffer in the EEPROM module. 0 Command Buffer Empty interrupt disabled. 1 An interrupt will be requested whenever the CBEIF flag (see Section 4.3.2.6, “EEPROM Status Register (ESTAT)”) is set. CCIE Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been completed in the EEPROM module. 0 Command Complete interrupt disabled. 1 An interrupt will be requested whenever the CCIF flag (see Section 4.3.2.6, “EEPROM Status Register (ESTAT)”) is set.

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4.3.2.5 EEPROM Protection Register (EPROT)

The EPROT register defines which EEPROM sectors are protected against program or erase operations. During the reset sequence, the EPROT register is loaded from the EEPROM Protection byte at address offset 0x0FFD (see Table 4-1).All bits in the EPROT register are readable and writable except for RNV[6:4] which are only readable. The EPOPEN and EPDIS bits can only be written to the protected state. The EPS bits can be written anytime until bit EPDIS is cleared. If the EPOPEN bit is cleared, the state of the EPDIS and EPS bits is irrelevant. To change the EEPROM protection that will be loaded during the reset sequence, the EEPROM memory must be unprotected, then the EEPROM Protection byte must be reprogrammed. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the PVIOL flag will be set in the ESTAT register. The mass erase of an EEPROM block is possible only when protection is fully disabled by setting the EPOPEN and EPDIS bits. Module Base + 0x0004 76543210 R EPOPEN RNV6 RNV5 RNV4 EPDIS EPS2 EPS1 EPS0 W Reset F F FFFFFF = Unimplemented or Reserved Figure 4-8. EEPROM Protection Register (EPROT) Table 4-4. EPROT Field Descriptions Field Description EPOPEN Opens the EEPROM for Program or Erase 0 The entire EEPROM memory is protected from program and erase. 1 The EEPROM sectors not protected are enabled for program or erase. 6:4 RNV[6:4] Reserved Nonvolatile Bits— The RNV[6:4] bits should remain in the erased state “1” for future enhancements. EPDIS EEPROM Protection Address Range Disable— The EPDIS bit determines whether there is a protected area in a specific region of the EEPROM memory ending with address offset 0x0FFF. 0 Protection enabled. 1 Protection disabled. 2:0 EPS[2:0] EEPROM Protection Address Size — The EPS[2:0] bits determine the size of the protected area as shown inTable 4-5. The EPS bits can only be written to while the EPDIS bit is set.

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4.3.2.6 EEPROM Status Register (ESTAT)

The ESTAT register defines the operational status of the module. CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode. Table 4-5. EEPROM Protection Address Range EPS[2:0] Address Offset Range Protected Size 000 0x0FC0 – 0x0FFF 64 bytes 001 0x0F80 – 0x0FFF 128 bytes 010 0x0F40 – 0x0FFF 192 bytes 011 0x0F00 – 0x0FFF 256 bytes 100 0x0EC0 – 0x0FFF 320 bytes 101 0x0E80 – 0x0FFF 384 bytes 110 0x0E40 – 0x0FFF 448 bytes 111 0x0E00 – 0x0FFF 512 bytes Module Base + 0x0005 76543210 R CBEIF CCIF PVIOL ACCERR W Reset 11000000 = Unimplemented or Reserved Figure 4-9. EEPROM Status Register (ESTAT — Normal Mode) Module Base + 0x0005 76543210 R CBEIF CCIF PVIOL ACCERR W Reset 11000000 = Unimplemented or Reserved Figure 4-10. EEPROM Status Register (ESTAT — Special Mode)

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Table 4-6. ESTAT Field Descriptions Field Description CBEIF Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data, and command buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the EEPROM address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is used together with the CBEIE bit in the ECNFG register to generate an interrupt request (see Figure 4-24). 0 Buffers are full. 1 Buffers are ready to accept a new command. CCIF Command Complete Interrupt Flag— The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect on CCIF. The CCIF flag is used together with the CCIE bit in the ECNFG register to generate an interrupt request (see Figure 4-24). 0 Command in progress. 1 All commands are completed. PVIOL Protection Violation Flag — The PVIOL flag indicates an attempt was made to program or erase an address in a protected area of the EEPROM memory during a command write sequence. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No failure. 1 A protection violation has occurred. ACCERR Access Error Flag — The ACCERR flag indicates an illegal access has occurred to the EEPROM memory caused by either a violation of the command write sequence (seeSection 4.4.1.2, “Command Write Sequence”), issuing an illegal EEPROM command (seeTable 4-8), launching the sector erase abort command terminating a sector erase operation early (see Section 4.4.2.5, “Sector Erase Abort Command”) or the execution of a CPU STOP instruction while a command is executing (CCIF = 0). The ACCERR flag is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR flag has no effect on ACCERR. While ACCERR is set, it is not possible to launch a command or start a command write sequence. If ACCERR is set by an erase verify operation, any buffered command will not launch. 0 No access error detected. 1 Access error has occurred. BLANK Flag Indicating the Erase Verify Operation Status — When the CCIF flag is set after completion of an erase verify command, the BLANK flag indicates the result of the erase verify operation. The BLANK flag is cleared by the EEPROM module when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect on BLANK. 0 EEPROM block verified as not erased. 1 EEPROM block verified as erased. FAIL Flag Indicating a Failed EEPROM Operation — The FAIL flag will set if the erase verify operation fails (EEPROM block verified as not erased). The FAIL flag is cleared by writing a 1 to FAIL. Writing a 0 to the FAIL flag has no effect on FAIL. 0 EEPROM operation completed without error. 1 EEPROM operation failed.

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4.3.2.7 EEPROM Command Register (ECMD)

The ECMD register is the EEPROM command register. All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable.

4.3.2.8 RESERVED3

This register is reserved for factory testing and is not accessible. Module Base + 0x0006 76543210 CMDB W Reset 00000000 = Unimplemented or Reserved Figure 4-11. EEPROM Command Register (ECMD) Table 4-7. ECMD Field Descriptions Field Description 6:0 CMDB[6:0] EEPROM Command Bits — Valid EEPROM commands are shown in Table 4-8. Writing any command other than those listed in Table 4-8 sets the ACCERR flag in the ESTAT register. Table 4-8. Valid EEPROM Command List CMDB[6:0] Command 0x05 Erase Verify 0x20 Word Program 0x40 Sector Erase 0x41 Mass Erase 0x47 Sector Erase Abort 0x60 Sector Modify Module Base + 0x0007 76543210 R 00000000 W Reset 00000000 = Unimplemented or Reserved Figure 4-12. RESERVED3

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All bits read 0 and are not writable. EEPROM Address Registers (EADDR) The EADDRHI and EADDRLO registers are the EEPROM address registers. All EABHI and EABLO bits read 0 and are not writable in normal modes. All EABHI and EABLO bits are readable and writable in special modes. The MCU address bit AB0 is not stored in the EADDR registers since the EEPROM block is not byte addressable.

4.3.2.9 EEPROM Data Registers (EDATA)

The EDATAHI and EDATALO registers are the EEPROM data registers. Module Base + 0x0008 76543210 R 00000 EABHI W Reset 00000000 = Unimplemented or Reserved Figure 4-13. EEPROM Address High Register (EADDRHI) Module Base + 0x0009 76543210 R EABLO W Reset 00000000 = Unimplemented or Reserved Figure 4-14. EEPROM Address Low Register (EADDRLO) Module Base + 0x000A 76543210 R EDHI W Reset 00000000 = Unimplemented or Reserved Figure 4-15. EEPROM Data High Register (EDATAHI)

Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 187 All EDHI and EDLO bits read 0 and are not writable in normal modes. All EDHI and EDLO bits are readable and writable in special modes.

4.4 Functional Description

4.4.1 EEPROM Command Operations

Write operations are used to execute program, erase, erase verify, sector erase abort, and sector modify algorithms described in this section. The program, erase, and sector modify algorithms are controlled by a state machine whose timebase, EECLK, is derived from the oscillator clock via a programmable divider. The command register as well as the associated address and data registers operate as a buffer and a register (2-stage FIFO) so that a second command along with the necessary data and address can be stored to the buffer while the first command is still in progress. Buffer empty as well as command completion are signalled by flags in the EEPROM status register with interrupts generated, if enabled. The next sections describe: 1. How to write the ECLKDIV register 2. Command write sequences to program, erase, erase verify, sector erase abort, and sector modify operations on the EEPROM memory 3. Valid EEPROM commands 4. Effects resulting from illegal EEPROM command write sequences or aborting EEPROM operations

4.4.1.1 Writing the ECLKDIV Register

Prior to issuing any EEPROM command after a reset, the user is required to write the ECLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase timings are also a function of the bus clock, the ECLKDIV determination must take this information into account. If we define:

• ECLK as the clock of the EEPROM timing control block
• Tbus as the period of the bus clock
• INT(x) as taking the integer part of x (e.g., INT(4.323)=4) Module Base + 0x000B 76543210 R EDLO W Reset 00000000 = Unimplemented or Reserved Figure 4-16. EEPROM Data Low Register (EDATALO)

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then ECLKDIV register bits PRDIV8 and EDIV[5:0] are to be set as described in Figure 4-17. For example, if the oscillator clock frequency is 950 kHz and the bus clock frequency is 10 MHz, ECLKDIV bits EDIV[5:0] should be set to 0x04 (000100) and bit PRDIV8 set to 0. The resulting EECLK frequency is then 190 kHz. As a result, the EEPROM program and erase algorithm timings are increased over the optimum target by: If the oscillator clock frequency is 16 MHz and the bus clock frequency is 40 MHz, ECLKDIV bits EDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1. The resulting EECLK frequency is then 182 kHz. In this case, the EEPROM program and erase algorithm timings are increased over the optimum target by: CAUTION Program and erase command execution time will increase proportionally with the period of EECLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the EEPROM memory cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the EEPROM memory with EECLK < 150 kHz should be avoided. Setting ECLKDIV to a value such that EECLK < 150 kHz can destroy the EEPROM memory due to overstress. Setting ECLKDIV to a value such that (1/EECLK+Tbus) < 5 µs can result in incomplete programming or erasure of the EEPROM memory cells. If the ECLKDIV register is written, the EDIVLD bit is set automatically. If the EDIVLD bit is 0, the ECLKDIV register has not been written since the last reset. If the ECLKDIV register has not been written to, the EEPROM command loaded during a command write sequence will not execute and the ACCERR flag in the ESTAT register will set.

Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 189 Figure 4-17. Determination Procedure for PRDIV8 and EDIV Bits PRDIV8 = 1 yes no PRDIV8 = 0 (reset) >12.8 MHz? EECLK = (PRDCLK)/(1+EDIV[5:0]) PRDCLK = oscillator_clockPRDCLK = oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) no EDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])–1 yes START Tbus < 1µs? an integer? EDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) 1/EECLK[MHz] + Tbus[ms] > 5 AND EECLK > 0.15 MHz END yes no EDIV[5:0] > 4? ALL COMMANDS IMPOSSIBLE yes no ALL COMMANDS IMPOSSIBLE no TRY TO DECREASE Tbus yes oscillator_clock

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4.4.1.2 Command Write Sequence

The EEPROM command controller is used to supervise the command write sequence to execute program, erase, erase verify, sector erase abort, and sector modify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the ESTAT register must be clear (see Section 4.3.2.6, “EEPROM Status Register (ESTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the EEPROM module not permitted between the steps. However, EEPROM register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. Write to one address in the EEPROM memory. 2. Write a valid command to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the command. The address written in step 1 will be stored in the EADDR registers and the data will be stored in the EDATA registers. If the CBEIF flag in the ESTAT register is clear when the first EEPROM array write occurs, the contents of the address and data buffers will be overwritten and the CBEIF flag will be set. When the CBEIF flag is cleared, the CCIF flag is cleared on the same bus cycle by the EEPROM command controller indicating that the command was successfully launched. For all command write sequences except sector erase abort, the CBEIF flag will set four bus cycles after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. For sector erase abort operations, the CBEIF flag will remain clear until the operation completes. Except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. The sector erase abort command is launched when the CBEIF flag is cleared as part of a sector erase abort command write sequence. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the ESTAT register. The CCIF flag will set upon completion of all active and buffered commands.

4.4.2 EEPROM Commands

Table 4-9 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. Table 4-9. EEPROM Command Description ECMDB Command Function on EEPROM Memory 0x05 Erase Verify Verify all memory bytes in the EEPROM block are erased. If the EEPROM block is erased, the BLANK flag in the ESTAT register will set upon command completion. 0x20 Program Program a word (two bytes) in the EEPROM block. 0x40 Sector Erase Erase all four memory bytes in a sector of the EEPROM block.

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4.4.2.1 Erase Verify Command

The erase verify operation will verify that the EEPROM memory is erased. An example flow to execute the erase verify operation is shown inFigure 4-18. The erase verify command write sequence is as follows: 1. Write to an EEPROM address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the ESTAT register will set after the operation has completed unless a new command write sequence has been buffered. The number of bus cycles required to execute the erase verify operation is equal to the number of words in the EEPROM memory plus 14 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Upon completion of the erase verify operation, the BLANK flag in the ESTAT register will be set if all addresses in the EEPROM memory are verified to be erased. If any address in the EEPROM memory is not erased, the erase verify operation will terminate and the BLANK flag in the ESTAT register will remain clear.

Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 193 Figure 4-18. Example Erase Verify Command Flow Write: EEPROM Address Write: ECMD register Erase Verify Command 0x05 Write: ESTAT register Clear CBEIF 0x80 Clear ACCERR/PVIOL 0x30 Write: ESTAT registeryes no Access Error and Protection Violation no and Dummy Data Bit Polling for Command Completion Check Read: ESTAT register yes NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Read: ESTAT register no START yes Check CBEIF Set? Address, Data, Command Buffer Empty Check CCIF Set? ACCERR/ PVIOL Set? noErase Verify Status yes EXIT EEPROM Memory Not ErasedEXIT EEPROM Memory Erased BLANK Set? Write: ECLKDIV register Read: ECLKDIV register yes noClock Register Written Check EDIVLD Set? NOTE: ECLKDIV needs to be set once after each reset.

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4.4.2.2 Program Command

The program operation will program a previously erased word in the EEPROM memory using an embedded algorithm. An example flow to execute the program operation is shown inFigure 4-19. The program command write sequence is as follows: 1. Write to an EEPROM block address to start the command write sequence for the program command. The data written will be programmed to the address written. 2. Write the program command, 0x20, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the program command. If a word to be programmed is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the ESTAT register will set after the program operation has completed unless a new command write sequence has been buffered.

Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 195 Figure 4-19. Example Program Command Flow Write: EEPROM Address Write: ECMD register Program Command 0x20 Write: ESTAT register Clear CBEIF 0x80 Clear ACCERR/PVIOL 0x30 Write: ESTAT registeryes no Access Error and Protection Violation no and program Data Bit Polling for Buffer Empty Check Read: ESTAT register yes NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Read: ESTAT register no START yes Check CBEIF Set? Address, Data, Command Buffer Empty Check CBEIF Set? ACCERR/ PVIOL Set? EXIT Write: ECLKDIV register Read: ECLKDIV register yes noClock Register Written Check EDIVLD Set? NOTE: ECLKDIV needs to be set once after each reset. no yesSequential Programming Decision Next Word? noBit Polling for Command Completion Check Read: ESTAT register yes CCIF Set?

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4.4.2.3 Sector Erase Command

The sector erase operation will erase both words in a sector of EEPROM memory using an embedded algorithm. An example flow to execute the sector erase operation is shown inFigure 4-20. The sector erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector erase command. The EEPROM address written determines the sector to be erased while global address bits [1:0] and the data written are ignored. 2. Write the sector erase command, 0x40, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase command. If an EEPROM sector to be erased is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the ESTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered.

Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 197 Figure 4-20. Example Sector Erase Command Flow Write: EEPROM Sector Address Write: ECMD register Sector Erase Command 0x40 Write: ESTAT register Clear CBEIF 0x80 Clear ACCERR/PVIOL 0x30 Write: ESTAT registeryes no Access Error and Protection Violation and Dummy Data Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Read: ESTAT register no START yes Check CBEIF Set? Address, Data, Command Buffer Empty Check ACCERR/ PVIOL Set? EXIT Write: ECLKDIV register Read: ECLKDIV register yes noClock Register Written Check EDIVLD Set? NOTE: ECLKDIV needs to be set once after each reset. noBit Polling for Command Completion Check yes CCIF Set?

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4.4.2.4 Mass Erase Command

The mass erase operation will erase all addresses in an EEPROM block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 4-21. The mass erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the mass erase command. If the EEPROM memory to be erased contains any protected area, the PVIOL flag in the ESTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the ESTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered.

Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 199 Figure 4-21. Example Mass Erase Command Flow Write: EEPROM Address Write: ECMD register Mass Erase Command 0x41 Write: ESTAT register Clear CBEIF 0x80 Clear ACCERR/PVIOL 0x30 Write: ESTAT registeryes no Access Error and Protection Violation and Dummy Data Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Read: ESTAT register no START yes Check CBEIF Set? Address, Data, Command Buffer Empty Check ACCERR/ PVIOL Set? EXIT Write: ECLKDIV register Read: ECLKDIV register yes noClock Register Written Check EDIVLD Set? NOTE: ECLKDIV needs to be set once after each reset. noBit Polling for Command Completion Check yes CCIF Set?

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4.4.2.5 Sector Erase Abort Command

The sector erase abort operation will terminate the active sector erase or sector modify operation so that other sectors in an EEPROM block are available for read and program operations without waiting for the sector erase or sector modify operation to complete. An example flow to execute the sector erase abort operation is shown inFigure 4-22. The sector erase abort command write sequence is as follows: 1. Write to any EEPROM memory address to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2. Write the sector erase abort command, 0x47, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase abort command. If the sector erase abort command is launched resulting in the early termination of an active sector erase or sector modify operation, the ACCERR flag will set once the operation completes as indicated by the CCIF flag being set. The ACCERR flag sets to inform the user that the EEPROM sector may not be fully erased and a new sector erase or sector modify command must be launched before programming any location in that specific sector. If the sector erase abort command is launched but the active sector erase or sector modify operation completes normally, the ACCERR flag will not set upon completion of the operation as indicated by the CCIF flag being set. If the sector erase abort command is launched after the sector modify operation has completed the sector erase step, the program step will be allowed to complete. The maximum number of cycles required to abort a sector erase or sector modify operation is equal to four EECLK periods (see Section 4.4.1.1, “Writing the ECLKDIV Register”) plus five bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. NOTE Since the ACCERR bit in the ESTAT register may be set at the completion of the sector erase abort operation, a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence. The CBEIF flag will not set after launching the sector erase abort command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a sector erase abort operation active, the ACCERR flag in the ESTAT register will be set. A new command write sequence may be started after clearing the ACCERR flag, if set. NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle.

Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 201 Figure 4-22. Example Sector Erase Abort Command Flow Write: Dummy EEPROM Address Write: ECMD register Sector Erase Abort Cmd 0x47 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register and Dummy Data Bit Polling for Command Completion Check yes NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. CCIF Set? Execute Sector Erase/Modify Command Flow noBit Polling for Command Completion Check Read: ESTAT register yes CCIF Set? no yes Abort Needed? Erase Clear ACCERR 0x10 Write: ESTAT registeryes no Access Error Check ACCERR Set? Sector Erase or Modify Sector Erase or Modify no EXIT EXIT Sector Erase Completed EXIT Completed Aborted

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4.4.2.6 Sector Modify Command

The sector modify operation will erase both words in a sector of EEPROM memory followed by a reprogram of the addressed word using an embedded algorithm. An example flow to execute the sector modify operation is shown in Figure 4-23. The sector modify command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector modify command. The EEPROM address written determines the sector to be erased and word to be reprogrammed while byte address bit 0 is ignored. 2. Write the sector modify command, 0x60, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase command. If an EEPROM sector to be modified is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the sector modify command will not launch. Once the sector modify command has successfully launched, the CCIF flag in the ESTAT register will set after the sector modify operation has completed unless a new command write sequence has been buffered.

Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 203 Figure 4-23. Example Sector Modify Command Flow Write: EEPROM Word Address Write: ECMD register Sector Modify Command 0x60 Write: ESTAT register Clear CBEIF 0x80 Clear ACCERR/PVIOL 0x30 Write: ESTAT registeryes no Access Error and Protection Violation and program Data Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Read: ESTAT register no START yes Check CBEIF Set? Address, Data, Command Buffer Empty Check ACCERR/ PVIOL Set? EXIT Write: ECLKDIV register Read: ECLKDIV register yes noClock Register Written Check EDIVLD Set? NOTE: ECLKDIV needs to be set once after each reset. noBit Polling for Command Completion Check yes CCIF Set?

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4.4.3 Illegal EEPROM Operations

The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to an EEPROM address before initializing the ECLKDIV register. 2. Writing a byte or misaligned word to a valid EEPROM address. 3. Starting a command write sequence while a sector erase abort operation is active. 4. Writing to any EEPROM register other than ECMD after writing to an EEPROM address. 5. Writing a second command to the ECMD register in the same command write sequence. 6. Writing an invalid command to the ECMD register. 7. Writing to an EEPROM address after writing to the ECMD register. 8. Writing to any EEPROM register other than ESTAT (to clear CBEIF) after writing to the ECMD register. 9. Writing a 0 to the CBEIF flag in the ESTAT register to abort a command write sequence. The ACCERR flag will not be set if any EEPROM register is read during a valid command write sequence. The ACCERR flag will also be set if any of the following events occur: 1. Launching the sector erase abort command while a sector erase or sector modify operation is active which results in the early termination of the sector erase or sector modify operation (see Section 4.4.2.5, “Sector Erase Abort Command”). 2. The MCU enters stop mode and a command operation is in progress. The operation is aborted immediately and any pending command is purged (see Section 4.5.2, “Stop Mode”). If the EEPROM memory is read during execution of an algorithm (CCIF = 0), the read operation will return invalid data and the ACCERR flag will not be set. If the ACCERR flag is set in the ESTAT register, the user must clear the ACCERR flag before starting another command write sequence (see Section 4.3.2.6, “EEPROM Status Register (ESTAT)”). The PVIOL flag will be set after the command is written to the ECMD register during a command write sequence if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. Writing the program command if the address written in the command write sequence was in a protected area of the EEPROM memory. 2. Writing the sector erase command if the address written in the command write sequence was in a protected area of the EEPROM memory. 3. Writing the mass erase command to the EEPROM memory while any EEPROM protection is enabled. 4. Writing the sector modify command if the address written in the command write sequence was in a protected area of the EEPROM memory. If the PVIOL flag is set in the ESTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 4.3.2.6, “EEPROM Status Register (ESTAT)”).

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4.5 Operating Modes

4.5.1 Wait Mode

If a command is active (CCIF = 0) when the MCU enters the wait mode, the active command and any buffered command will be completed. The EEPROM module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 4.8, “Interrupts”).

4.5.2 Stop Mode

If a command is active (CCIF = 0) when the MCU enters the stop mode, the operation will be aborted and, if the operation is program, sector erase, mass erase, or sector modify, the EEPROM array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the EEPROM memory will immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set and any buffered command will not be launched. The ACCERR flag must be cleared before starting a command write sequence (seeSection 4.4.1.2, “Command Write Sequence”). NOTE As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program, sector erase, mass erase, or sector modify operations.

4.5.3 Background Debug Mode

In background debug mode (BDM), the EPROT register is writable. If the MCU is unsecured, then all EEPROM commands listed in Table 4-9 can be executed. If the MCU is secured and is in special single chip mode, the only command available to execute is mass erase.

4.6 EEPROM Module Security

The EEPROM module does not provide any security information to the MCU. After each reset, the security state of the MCU is a function of information provided by the Flash module (see the specific FTX Block Guide).

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4.6.1 Unsecuring the MCU in Special Single Chip Mode using BDM

Before the MCU can be unsecured in special single chip mode, the EEPROM memory must be erased using the following method :

• Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the EEPROM module, and execute a mass erase command write sequence to erase the EEPROM memory. After the CCIF flag sets to indicate that the EEPROM mass operation has completed and assuming that the Flash memory has also been erased, reset the MCU into special single chip mode. The BDM secure ROM will verify that the Flash and EEPROM memory are erased and will assert the UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security state and the MCU will be unsecured. Once the MCU is unsecured, BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state.

4.7 Resets

4.7.1 EEPROM Reset Sequence

On each reset, the EEPROM module executes a reset sequence to hold CPU activity while loading the EPROT register from the EEPROM memory according toTable 4-1.

4.7.2 Reset While EEPROM Command Active

If a reset occurs while any EEPROM command is in progress, that command will be immediately aborted. The state of a word being programmed or the sector / block being erased is not guaranteed.

4.8 Interrupts

The EEPROM module can generate an interrupt when all EEPROM command operations have completed, when the EEPROM address, data, and command buffers are empty. NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. Table 4-10. EEPROM Interrupt Sources Interrupt Source Interrupt Flag Local Enable Global (CCR) Mask EEPROM address, data, and command buffers empty CBEIF (ESTAT register) CBEIE (ECNFG register) I Bit All EEPROM commands completed CCIF (ESTAT register) CCIE (ECNFG register) I Bit

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4.8.1 Description of EEPROM Interrupt Operation

The logic used for generating interrupts is shown in Figure 4-24. The EEPROM module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the EEPROM command interrupt request. Figure 4-24. EEPROM Interrupt Implementation For a detailed description of the register bits, refer to Section 4.3.2.4, “EEPROM Configuration Register (ECNFG)” and Section 4.3.2.6, “EEPROM Status Register (ESTAT)” . EEPROM Command Interrupt Request CBEIE CBEIF CCIE CCIF

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MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 209 Chapter 5 XGATE (S12XGATEV2)

5.1 Introduction

The XGATE module is a peripheral co-processor that allows autonomous data transfers between the MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the transferred data and perform complex communication protocols. The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s interrupt load. Figure 5-1 gives an overview on the XGATE architecture. This document describes the functionality of the XGATE module, including:

• XGATE registers ( Section 5.3, “Memory Map and Register Definition” )
• XGATE RISC core ( Section 5.4.1, “XGATE RISC Core”)
• Hardware semaphores ( Section 5.4.4, “Semaphores”)
• Interrupt handling ( Section 5.5, “Interrupts”)
• Debug features ( Section 5.6, “Debug Mode”)
• Security ( Section 5.7, “Security”)
• Instruction set ( Section 5.8, “Instruction Set”)

5.1.1 Glossary of Terms

Number Date Author Description of Changes 02.22 14 Dec

2005 Updated code example

02.23 19 Mar

2007 Internal updates

V03.24 13 Feb 2009 - Minor corrections (5.3.1.4/5-220)

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A service request from a peripheral module which is directed to the XGATE by the S12X_INT module (see Figure 5-1). XGATE Channel The resources in the XGATE module (i.e. Channel ID number, Priority level, Service Request Vector, Interrupt Flag) which are associated with a particular XGATE Request. XGATE Channel ID A 7-bit identifier associated with an XGATE channel. In S12X designs valid Channel IDs range from $78 to $09. XGATE Channel Interrupt An S12X_CPU interrupt that is triggered by a code sequence running on the XGATE module. XGATE Software Channel Special XGATE channel that is not associated with any peripheral service request. A Software Channel is triggered by its Software Trigger Bit which is implemented in the XGATE module. XGATE Semaphore A set of hardware flip-flops that can be exclusively set by either the S12X_CPU or the XGATE. (see 5.4.4/5-231) XGATE Thread A code sequence which is executed by the XGATE’s RISC core after receiving an XGATE request. XGATE Debug Mode A special mode in which the XGATE’s RISC core is halted for debug purposes. This mode enables the XGATE’s debug features (see5.6/5-233). XGATE Software Error The XGATE is able to detect a number of error conditions caused by erratic software (see 5.4.5/5-232). These error conditions will cause the XGATE to seize program execution and flag an Interrupt to the S12X_CPU. Word A 16 bit entity. Byte An 8 bit entity.

5.1.2 Features

The XGATE module includes these features:

• Data movement between various targets (i.e Flash, RAM, and peripheral modules)
• Data manipulation through built in RISC core
• Provides up to 112 XGATE channels

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 211 — 104 hardware triggered channels — 8 software triggered channels

• Hardware semaphores which are shared between the S12X_CPU and the XGATE module
• Able to trigger S12X_CPU interrupts upon completion of an XGATE transfer
• Software error detection to catch erratic application code

5.1.3 Modes of Operation

There are four run modes on S12X devices.

• Run mode, wait mode, stop mode The XGATE is able to operate in all of these three system modes. Clock activity will be automatically stopped when the XGATE module is idle.
• Freeze mode (BDM active) In freeze mode all clocks of the XGATE module may be stopped, depending on the module configuration (see Section 5.3.1.1, “XGATE Control Register (XGMCTL)”).

5.1.4 Block Diagram

Figure Figure 5-1 shows a block diagram of the XGATE. Figure 5-1. XGATE Block Diagram INTERRUPTS XGATE REQUESTS RISC Core S12X_MMC XGATE Peripherals Semaphores Interrupt Flags Software Triggers Peripheral Interrupts S12X_DBG Data/Code Software Triggers XGATE S12X_INT

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5.2 External Signal Description

The XGATE module has no external pins.

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5.3 Memory Map and Register Definition

This section provides a detailed description of address space and registers used by the XGATE module. The memory map for the XGATE module is given below inFigure 5-2.The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reserved registers read zero. Write accesses to the reserved registers have no effect.

5.3.1 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Register Name 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 0x0000 XGMCTL R 00000000 XGE XGFRZ XGDBG XGSS XG FACT XG SWEIF XGIE W XGEM XG FRZM XG DBGM XGSSM XG FACTM XG SWEIFM XGIEM 0x0002 XGMCHID R 0 XGCHID[6:0] W 0x0003 Reserved R W 0x0004 Reserved R W 0x0005 Reserved R W 0x0006 XGVBR R XGVBR[15:1] W = Unimplemented or Reserved Figure 5-2. XGATE Register Summary (Sheet 1 of 3)

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127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 0x0008 XGIF R 0000000 XGIF_78 XGF_77 XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70 W 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 0x000A XGIF R XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68 XGF_67 XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60 W 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 0x000C XGIF R XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58 XGF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50 W 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 0x000E XGIF R XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40 W Register Name 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 0x0010 XGIF R XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30 W 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 0x0012 XGIF R XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20 W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x0014 XGIF R XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10 W 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 0x0016 XGIF R XGIF_0F XGIF_0E XGIF_0D XGIF_0C XGIF_0B XGIF_0A XGIF_09 0 0 0 0 0 0 0 0 0 W = Unimplemented or Reserved Figure 5-2. XGATE Register Summary (Sheet 2 of 3)

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5.3.1.1 XGATE Control Register (XGMCTL)

All module level switches and flags are located in the module control register Figure 5-3. Read: Anytime Write: Anytime Module Base +0x00000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 00000000 XGE XGFRZ XGDBG XGSS XGFACT 0 XG SWEIF XGIEW XGEM XG FRZM XG DBGM XG SSM XG FACTM XG SWEIFM XGIEM Reset 0 0 0 0 000000000000 = Unimplemented or Reserved Figure 5-3. XGATE Control Register (XGMCTL) Table 5-1. XGMCTL Field Descriptions (Sheet 1 of 3) Field Description XGEM XGE Mask — This bit controls the write access to the XGE bit. The XGE bit can only be set or cleared if a "1" is written to the XGEM bit in the same register access. Read: This bit will always read "0". Write:

0 Disable write access to the XGE in the same bus cycle

1 Enable write access to the XGE in the same bus cycle

XGFRZ Mask — This bit controls the write access to the XGFRZ bit. The XGFRZ bit can only be set or cleared if a "1" is written to the XGFRZM bit in the same register access. Read: This bit will always read "0". Write:

0 Disable write access to the XGFRZ in the same bus cycle

1 Enable write access to the XGFRZ in the same bus cycle

XGDBG Mask — This bit controls the write access to the XGDBG bit. The XGDBG bit can only be set or cleared if a "1" is written to the XGDBGM bit in the same register access. Read: This bit will always read "0". Write:

0 Disable write access to the XGDBG in the same bus cycle

1 Enable write access to the XGDBG in the same bus cycle

XGSS Mask — This bit controls the write access to the XGSS bit. The XGSS bit can only be set or cleared if a "1" is written to the XGSSM bit in the same register access. Read: This bit will always read "0". Write:

0 Disable write access to the XGSS in the same bus cycle

1 Enable write access to the XGSS in the same bus cycle

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 217 XGFACTM XGFACT Mask — This bit controls the write access to the XGFACT bit. The XGFACT bit can only be set or cleared if a "1" is written to the XGFACTM bit in the same register access. Read: This bit will always read "0". Write:

0 Disable write access to the XGFACT in the same bus cycle

1 Enable write access to the XGFACT in the same bus cycle

XGSWEIF Mask — This bit controls the write access to the XGSWEIF bit. The XGSWEIF bit can only be cleared if a "1" is written to the XGSWEIFM bit in the same register access. Read: This bit will always read "0". Write:

0 Disable write access to the XGSWEIF in the same bus cycle

1 Enable write access to the XGSWEIF in the same bus cycle

XGIE Mask — This bit controls the write access to the XGIE bit. The XGIE bit can only be set or cleared if a "1" is written to the XGIEM bit in the same register access. Read: This bit will always read "0". Write:

0 Disable write access to the XGIE in the same bus cycle

1 Enable write access to the XGIE in the same bus cycle

XGATE Module Enable — This bit enables the XGATE module. If the XGATE module is disabled, pending XGATE requests will be ignored. The thread that is executed by the RISC core while the XGE bit is cleared will continue to run. Read:

0 XGATE module is disabled

1 XGATE module is enabled

Write:

0 Disable XGATE module

1 Enable XGATE module

Halt XGATE in Freeze Mode — The XGFRZ bit controls the XGATE operation in Freeze Mode (BDM active). Read:

0 RISC core operates normally in Freeze (BDM active)

1 RISC core stops in Freeze Mode (BDM active)

Write:

0 Don’t stop RISC core in Freeze Mode (BDM active)

1 Stop RISC core in Freeze Mode (BDM active)

XGATE Debug Mode— This bit indicates that the XGATE is in Debug Mode (see Section 5.6, “Debug Mode”). Debug Mode can be entered by Software Breakpoints (BRK instruction), Tagged or Forced Breakpoints (see S12X_DBG Section), or by writing a "1" to this bit. Read:

0 RISC core is not in Debug Mode

1 RISC core is in Debug Mode

Write:

0 Leave Debug Mode

1 Enter Debug Mode

Note: Freeze Mode and Software Error Interrupts have no effect on the XGDBG bit. Table 5-1. XGMCTL Field Descriptions (Sheet 2 of 3) Field Description

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XGATE Single Step— This bit forces the execution of a single instruction if the XGATE is in DEBUG Mode and no software error has occurred (XGSWEIF cleared). Read:

0 No single step in progress

1 Single step in progress

0 No effect

1 Execute a single RISC instruction

Note: Invoking a Single Step will cause the XGATE to temporarily leave Debug Mode until the instruction has been executed. XGFACT Fake XGATE Activity— This bit forces the XGATE to flag activity to the MCU even when it is idle. When it is set the MCU will never enter system stop mode which assures that peripheral modules will be clocked during XGATE idle periods Read: 0 XGATE will only flag activity if it is not idle or in debug mode. 1 XGATE will always signal activity to the MCU. Write: 0 Only flag activity if not idle or in debug mode. 1 Always signal XGATE activity. XGSWEIF XGATE Software Error Interrupt Flag— This bit signals a pending Software Error Interrupt. It is set if the RISC core detects an error condition (see Section 5.4.5, “Software Error Detection”). The RISC core is stopped while this bit is set. Clearing this bit will terminate the current thread and cause the XGATE to become idle. Read:

0 Software Error Interrupt is not pending

1 Software Error Interrupt is pending if XGIE is set

Write:

1 Clears the XGSWEIF bit

XGATE Interrupt Enable — This bit acts as a global interrupt enable for the XGATE module Read:

0 All XGATE interrupts disabled

1 All XGATE interrupts enabled

Write:

0 Disable all XGATE interrupts

1 Enable all XGATE interrupts

Table 5-1. XGMCTL Field Descriptions (Sheet 3 of 3) Field Description

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5.3.1.2 XGATE Channel ID Register (XGCHID)

The XGATE channel ID register (Figure 5-4) shows the identifier of the XGATE channel that is currently active. This register will read “$00” if the XGATE module is idle. In debug mode this register can be used to start and terminate threads (see Section 5.6.1, “Debug Features”). Read: Anytime Write: In Debug Mode

5.3.1.3 XGATE Vector Base Address Register (XGVBR)

The vector base address register (Figure 5-5 and Figure 5-6) determines the location of the XGATE vector block. Read: Anytime Write: Only if the module is disabled (XGE = 0) and idle (XGCHID = $00)) Module Base +0x0002 76543210 R 0 XGCHID[6:0] W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 5-4. XGATE Channel ID Register (XGCHID) Table 5-2. XGCHID Field Descriptions Field Description 6–0 XGCHID[6:0] Request Identifier — ID of the currently active channel Module Base +0x0006 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGVBR[15:1] 0 W Reset 0 0 0 0 000000000000 = Unimplemented or Reserved Figure 5-5. XGATE Vector Base Address Register (XGVBR) Table 5-3. XGVBR Field Descriptions Field Description 15–1 XBVBR[15:1] Vector Base Address — The XGVBR register holds the start address of the vector block in the XGATE memory map.

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5.3.1.4 XGATE Channel Interrupt Flag Vector (XGIF)

The interrupt flag vector (Figure 5-6) provides access to the interrupt flags bits of each channel. Each flag may be cleared by writing a "1" to its bit location. Read: Anytime Module Base +0x0008 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 R 0000000 XGIF_78 XGF_77 XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70 W Reset 0 0 0 0 000000000000 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 R XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68 XGF_67 XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60 W Reset 0 0 0 0 000000000000 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 R XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58 XGF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50 W Reset 0 0 0 0 000000000000 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 R XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40 W Reset 0 0 0 0 000000000000 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 R XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30 W Reset 0 0 0 0 000000000000 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 R XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20 W Reset 0 0 0 0 000000000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10 W Reset 0 0 0 0 000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGIF_0F XGIF_0E XGIF_0D XGIF_0C XGIF_0B XGIF_0A XGIF_09 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 000000000000 = Unimplemented or Reserved Figure 5-6. XGATE Channel Interrupt Flag Vector (XGIF)

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 221 Write: Anytime NOTE Suggested Mnemonics for accessing the interrupt flag vector on a word basis are: XGIF_7F_70 (XGIF[127:112]), XGIF_6F_60 (XGIF[111:96]), XGIF_5F_50 (XGIF[95:80]), XGIF_4F_40 (XGIF[79:64]), XGIF_3F_30 (XGIF[63:48]), XGIF_2F_20 (XGIF[47:32]), XGIF_1F_10 (XGIF[31:16]), XGIF_0F_00 (XGIF[15:0]) Table 5-4. XGIV Field Descriptions Field Description 120–9 XGIF_78 XGIF_09 Channel Interrupt Flags — These bits signal pending channel interrupts. They can only be set by the RISC core. Each flag can be cleared by writing a "1" to its bit location. Unimplemented interrupt flags will always read "0". Refer to Section “Interrupts” of theSoC Guide for a list of implemented Interrupts. Read:

0 Channel interrupt is not pending

1 Channel interrupt is pending if XGIE is set

Write:

1 Clears the interrupt flag

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5.3.1.5 XGATE Software Trigger Register (XGSWT)

The eight software triggers of the XGATE module can be set and cleared through the XGATE software trigger register (Figure 5-7). The upper byte of this register, the software trigger mask, controls the write access to the lower byte, the software trigger bits. These bits can be set or cleared if a "1" is written to the associated mask in the same bus cycle. Read: Anytime Write: Anytime NOTE The XGATE channel IDs that are associated with the eight software triggers are determined on chip integration level. (see Section “Interrupts” of theSoc Guide) XGATE software triggers work like any peripheral interrupt. They can be used as XGATE requests as well as S12X_CPU interrupts. The target of the software trigger must be selected in the S12X_INT module. Module Base +0x00018 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 00000000 XGSWT[7:0]W XGSWTM[7:0] Reset 0 0 0 0 000000000000 Figure 5-7. XGATE Software Trigger Register (XGSWT) Table 5-5. XGSWT Field Descriptions Field Description 15–8 XGSWTM[7:0] Software Trigger Mask— These bits control the write access to the XGSWT bits. Each XGSWT bit can only be written if a "1" is written to the corresponding XGSWTM bit in the same access. Read: These bits will always read "0". Write:

0 Disable write access to the XGSWT in the same bus cycle

1 Enable write access to the corresponding XGSWT bit in the same bus cycle

7–0 XGSWT[7:0] Software Trigger Bits — These bits act as interrupt flags that are able to trigger XGATE software channels. They can only be set and cleared by software. Read:

0 No software trigger pending

1 Software trigger pending if the XGIE bit is set

Write:

0 Clear Software Trigger

1 Set Software Trigger

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5.3.1.6 XGATE Semaphore Register (XGSEM)

The XGATE provides a set of eight hardware semaphores that can be shared between the S12X_CPU and the XGATE RISC core. Each semaphore can either be unlocked, locked by the S12X_CPU or locked by the RISC core. The RISC core is able to lock and unlock a semaphore through its SSEM and CSEM instructions. The S12X_CPU has access to the semaphores through the XGATE semaphore register (Figure 5-8). Refer to section Section 5.4.4, “Semaphores” for details. Read: Anytime Write: Anytime (see Section 5.4.4, “Semaphores”) Module Base +0x0001A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 00000000 XGSEM[7:0]W XGSEMM[7:0] Reset 0 0 0 0 000000000000 Figure 5-8. XGATE Semaphore Register (XGSEM) Table 5-6. XGSEM Field Descriptions Field Description 15–8 XGSEMM[7:0] Semaphore Mask — These bits control the write access to the XGSEM bits. Read: These bits will always read "0". Write:

0 Disable write access to the XGSEM in the same bus cycle

1 Enable write access to the XGSEM in the same bus cycle

7–0 XGSEM[7:0] Semaphore Bits — These bits indicate whether a semaphore is locked by the S12X_CPU. A semaphore can be attempted to be set by writing a "1" to the XGSEM bit and to the corresponding XGSEMM bit in the same write access. Only unlocked semaphores can be set. A semaphore can be cleared by writing a "0" to the XGSEM bit and a "1" to the corresponding XGSEMM bit in the same write access. Read:

0 Semaphore is unlocked or locked by the RISC core

1 Semaphore is locked by the S12X_CPU

Write:

0 Clear semaphore if it was locked by the S12X_CPU

1 Attempt to lock semaphore by the S12X_CPU

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5.3.1.7 XGATE Condition Code Register (XGCCR)

The XGCCR register (Figure 5-9) provides access to the RISC core’s condition code register. Read: In debug mode if unsecured Write: In debug mode if unsecured Module Base +0x001D 76543210 R 0000 XGN XGZ XGV XGC W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 5-9. XGATE Condition Code Register (XGCCR) Table 5-7. XGCCR Field Descriptions Field Description XGN Sign Flag — The RISC core’s Sign flag XGZ Zero Flag — The RISC core’s Zero flag XGV Overflow Flag — The RISC core’s Overflow flag XGC Carry Flag — The RISC core’s Carry flag

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5.3.1.8 XGATE Program Counter Register (XGPC)

The XGPC register (Figure 5-10) provides access to the RISC core’s program counter. Read: In debug mode if unsecured Write: In debug mode if unsecured

5.3.1.9 XGATE Register 1 (XGR1)

The XGR1 register (Figure 5-12) provides access to the RISC core’s register 1. Read: In debug mode if unsecured Write: In debug mode if unsecured Module Base +0x0001E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGPCW Reset 0 0 0 0 000000000000 Figure 5-10. XGATE Program Counter Register (XGPC) Figure 5-11. Table 5-8. XGPC Field Descriptions Field Description 15–0 XGPC[15:0] Program Counter — The RISC core’s program counter Module Base +0x00022 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGR1W Reset 0 0 0 0 000000000000 Figure 5-12. XGATE Register 1 (XGR1) Table 5-9. XGR1 Field Descriptions Field Description 15–0 XGR1[15:0] XGATE Register 1 — The RISC core’s register 1

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5.3.1.10 XGATE Register 2 (XGR2)

The XGR2 register (Figure 5-13) provides access to the RISC core’s register 2. Read: In debug mode if unsecured Write: In debug mode if unsecured

5.3.1.11 XGATE Register 3 (XGR3)

The XGR3 register (Figure 5-14) provides access to the RISC core’s register 3. Read: In debug mode if unsecured Write: In debug mode if unsecured Module Base +0x00024 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGR2W Reset 0 0 0 0 000000000000 Figure 5-13. XGATE Register 2 (XGR2) Table 5-10. XGR2 Field Descriptions Field Description 15–0 XGR2[15:0] XGATE Register 2 — The RISC core’s register 2 Module Base +0x00026 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGR3W Reset 0 0 0 0 000000000000 Figure 5-14. XGATE Register 3 (XGR3) Table 5-11. XGR3 Field Descriptions Field Description 15–0 XGR3[15:0] XGATE Register 3 — The RISC core’s register 3

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5.3.1.12 XGATE Register 4 (XGR4)

The XGR4 register (Figure 5-15) provides access to the RISC core’s register 4. Read: In debug mode if unsecured Write: In debug mode if unsecured

5.3.1.13 XGATE Register 5 (XGR5)

The XGR5 register (Figure 5-16) provides access to the RISC core’s register 5. Read: In debug mode if unsecured Write: In debug mode if unsecured Module Base +0x00028 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGR4W Reset 0 0 0 0 000000000000 Figure 5-15. XGATE Register 4 (XGR4) Table 5-12. XGR4 Field Descriptions Field Description 15–0 XGR4[15:0] XGATE Register 4 — The RISC core’s register 4 Module Base +0x0002A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGR5W Reset 0 0 0 0 000000000000 Figure 5-16. XGATE Register 5 (XGR5) Table 5-13. XGR5 Field Descriptions Field Description 15–0 XGR5[15:0] XGATE Register 5 — The RISC core’s register 5

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5.3.1.14 XGATE Register 6 (XGR6)

The XGR6 register (Figure 5-17) provides access to the RISC core’s register 6. Read: In debug mode if unsecured Write: In debug mode if unsecured

5.3.1.15 XGATE Register 7 (XGR7)

The XGR7 register (Figure 5-18) provides access to the RISC core’s register 7. Read: In debug mode if unsecured Write: In debug mode if unsecured Module Base +0x0002C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGR6W Reset 0 0 0 0 000000000000 Figure 5-17. XGATE Register 6 (XGR6) Table 5-14. XGR6 Field Descriptions Field Description 15–0 XGR6[15:0] XGATE Register 6 — The RISC core’s register 6 Module Base +0x0002E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGR7W Reset 0 0 0 0 000000000000 Figure 5-18. XGATE Register 7 (XGR7) Table 5-15. XGR7 Field Descriptions Field Description 15–0 XGR7[15:0] XGATE Register 7 — The RISC core’s register 7

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5.4 Functional Description

The core of the XGATE module is a RISC processor which is able to access the MCU’s internal memories and peripherals (see Figure 5-1). The RISC processor always remains in an idle state until it is triggered by an XGATE request. Then it executes a code sequence that is associated with the request and optionally triggers an interrupt to the S12X_CPU upon completion. Code sequences are not interruptible. A new XGATE request can only be serviced when the previous sequence is finished and the RISC core becomes idle. The XGATE module also provides a set of hardware semaphores which are necessary to ensure data consistency whenever RAM locations or peripherals are shared with the S12X_CPU. The following sections describe the components of the XGATE module in further detail.

5.4.1 XGATE RISC Core

The RISC core is a 16 bit processor with an instruction set that is well suited for data transfers, bit manipulations, and simple arithmetic operations (see Section 5.8, “Instruction Set”). It is able to access the MCU’s internal memories and peripherals without blocking these resources from the S12X_CPU1. Whenever the S12X_CPU and the RISC core access the same resource, the RISC core will be stalled until the resource becomes available again1. The XGATE offers a high access rate to the MCU’s internal RAM. Depending on the bus load, the RISC core can perform up to two RAM accesses per S12X_CPU bus cycle. Bus accesses to peripheral registers or flash are slower. A transfer rate of one bus access per S12X_CPU cycle can not be exceeded. The XGATE module is intended to execute short interrupt service routines that are triggered by peripheral modules or by software.

5.4.2 Programmer’s Model

Figure 5-19. Programmer’s Model 1. With the exception of PRR registers (see Section “S12X_MMC”). R0 = 0 VC Register Block Program Counter Condition Code Register 1 0 (Variable Pointer) PC15 0 NZ 3 2

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The programmer’s model of the XGATE RISC core is shown inFigure 5-19. The processor offers a set of seven general purpose registers (R1 - R7), which serve as accumulators and index registers. An additional eighth register (R0) is tied to the value “$0000”. Register R1 has an additional functionality. It is preloaded with the initial variable pointer of the channel’s service request vector (seeFigure 5-20). The initial content of the remaining general purpose registers is undefined. The 16 bit program counter allows the addressing of a 64 kbyte address space. The condition code register contains four bits: the sign bit (S), the zero flag (Z), the overflow flag (V), and the carry bit (C). The initial content of the condition code register is undefined.

5.4.3 Memory Map

The XGATE’s RISC core is able to access an address space of 64K bytes. The allocation of memory blocks within this address space is determined on chip level. Refer to the S12X_MMC Section for a detailed information. The XGATE vector block assigns a start address and a variable pointer to each XGATE channel. Its position in the XGATE memory map can be adjusted through the XGVBR register (seeSection 5.3.1.3, “XGATE Vector Base Address Register (XGVBR)”). Figure 5-20 shows the layout of the vector block. Each vector consists of two 16 bit words. The first contains the start address of the service routine. This value will be loaded into the program counter before a service routine is executed. The second word is a pointer to the service routine’s variable space. This value will be loaded into register R1 before a service routine is executed. Figure 5-20. XGATE Vector Block +$0000 unused +$0024 +$0028 +$002C +$0030 +$01E0 Code Variables Code Variables XGVBR Channel $0A Initial Program Counter Channel $0A Initial Variable Pointer Channel $09 Initial Program Counter Channel $09 Initial Variable Pointer Channel $0B Initial Program Counter Channel $0B Initial Variable Pointer Channel $0C Initial Program Counter Channel $0C Initial Variable Pointer Channel $78 Initial Program Counter Channel $78 Initial Variable Pointer

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5.4.4 Semaphores

The XGATE module offers a set of eight hardware semaphores. These semaphores provide a mechanism to protect system resources that are shared between two concurrent threads of program execution; one thread running on the S12X_CPU and one running on the XGATE RISC core. Each semaphore can only be in one of the three states: “Unlocked”, “Locked by S12X_CPU”, and “Locked by XGATE”. The S12X_CPU can check and change a semaphore’s state through the XGATE semaphore register (XGSEM, see Section 5.3.1.6, “XGATE Semaphore Register (XGSEM)”). The RISC core does this through its SSEM and CSEM instructions. Figure 5-21 illustrates the valid state transitions. Figure 5-21. Semaphore State Transitions UNLOCKED LOCKED BY S12X_CPU LOCKED BY XGATE CSEM Instruction %0 ⇒ XGSEM CSEM Instruction SSEM Instruction %1 ⇒ XGSEM SSEM Instruction %0 ⇒ XGSEM %1 ⇒ XGSEM CSEM Instruction ⇒ XGSEM%1 ⇒ XGSEM SSEM Instruction or ⇒ XGSEM and SSEM Instr.

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Figure 5-22 gives an example of the typical usage of the XGATE hardware semaphores. Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is running on the RISC core. They both have a critical section of code that accesses the same system resource. To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence must be embedded in a semaphore lock/release sequence as shown.Figure 5-22. Algorithm for Locking and Releasing Semaphores

5.4.5 Software Error Detection

The XGATE module will immediately terminate program execution after detecting an error condition caused by erratic application code. There are three error conditions:

• Execution of an illegal opcode
• Illegal vector or opcode fetches
• Illegal load or store accesses All opcodes which are not listed in sectionSection 5.8, “Instruction Set” are illegal opcodes. Illegal vector and opcode fetches as well as illegal load and store accesses are defined on chip level. Refer to the S12X_MMC Section for a detailed information. SSEM XGSEM ≡ %1? XGSEM ⇒ %0 BCC? %1 ⇒ XGSEMx CSEM critical code sequence critical code sequence S12X_CPU XGATE

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5.5 Interrupts

5.5.1 Incoming Interrupt Requests

XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which specific interrupt requests these are and which channel ID they are assigned to is documented in Section “Interrupts” of the SoC Guide.

5.5.2 Outgoing Interrupt Requests

There are three types of interrupt requests which can be triggered by the XGATE module: 5. Channel interrupts For each XGATE channel there is an associated interrupt flag in the XGATE interrupt flag vector (XGIF, see Section 5.3.1.4, “XGATE Channel Interrupt Flag Vector (XGIF)”). These flags can be set through the "SIF" instruction by the RISC core. They are typically used to flag an interrupt to the S12X_CPU when the XGATE has completed one of its tasks. 6. Software triggers Software triggers are interrupt flags, which can be set and cleared by software (seeSection 5.3.1.5, “XGATE Software Trigger Register (XGSWT)”). They are typically used to trigger XGATE tasks by the S12X_CPU software. However these interrupts can also be routed to the S12X_CPU (see S12X_INT Section) and triggered by the XGATE software. 7. Software error interrupt The software error interrupt signals to the S12X_CPU the detection of an error condition in the XGATE application code (see Section 5.4.5, “Software Error Detection”). All XGATE interrupts can be disabled by the XGIE bit in the XGATE module control register (XGMCTL, see Section 5.3.1.1, “XGATE Control Register (XGMCTL)”).

5.6 Debug Mode

The XGATE debug mode is a feature to allow debugging of application code.

5.6.1 Debug Features

In debug mode the RISC core will be halted and the following debug features will be enabled:

• Read and Write accesses to RISC core registers (XGCCR, XGPC, XGR1–XGR7) 1 All RISC core registers can be modified. Leaving debug mode will cause the RISC core to continue program execution with the modified register values. 1. Only possible if MCU is unsecured

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• Single Stepping Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core registers will be updated accordingly.
• Write accesses to the XGCHID register Three operations can be performed by writing to the XGCHID register: – Change of channel ID If a non-zero value is written to the XGCHID while a thread is active (XGCHID≠ $00), then the current channel ID will be changed without any influence on the program counter or the other RISC core registers. – Start of a thread If a non-zero value is written to the XGCHID while the XGATE is idle (XGCHID = $00), then the thread that is associated with the new channel ID will be executed upon leaving debug mode. – Termination of a thread If zero is written to the XGCHID while a thread is active (XGCHID≠ $00), then the current thread will be terminated and the XGATE will become idle.

5.6.2 Entering Debug Mode

Debug mode can be entered in four ways: 1. Setting XGDBG to "1" Writing a "1" to XGDBG and XGDBGM in the same write access causes the XGATE to enter debug mode upon completion of the current instruction. NOTE After writing to the XGDBG bit the XGATE will not immediately enter debug mode. Depending on the instruction that is executed at this time there may be a delay of several clock cycles. The XGDBG will read "0" until debug mode is entered. 2. Software breakpoints XGATE programs which are stored in the internal RAM allow the use of software breakpoints. A software breakpoint is set by replacing an instruction of the program code with the "BRK" instruction. As soon as the program execution reaches the "BRK" instruction, the XGATE enters debug mode. Additionally a software breakpoint request is sent to the S12X_DBG module (see section 4.9 of the S12X_DBG Section). Upon entering debug mode, the program counter will point to the "BRK" instruction. The other RISC core registers will hold the result of the previous instruction. To resume program execution, the "BRK" instruction must be replaced by the original instruction before leaving debug mode.

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 235 3. Tagged Breakpoints The S12X_DBG module is able to place tags on fetched opcodes. The XGATE is able to enter debug mode right before a tagged opcode is executed (see section 4.9 of theS12X_DBG Section). Upon entering debug mode, the program counter will point to the tagged instruction. The other RISC core registers will hold the result of the previous instruction. 4. Forced Breakpoints Forced breakpoints are triggered by the S12X_DBG module (see section 4.9 of the S12X_DBG Section). When a forced breakpoint occurs, the XGATE will enter debug mode upon completion of the current instruction.

5.6.3 Leaving Debug Mode

Debug mode can only be left by setting the XGDBG bit to "0". If a thread is active (XGCHID has not been cleared in debug mode), program execution will resume at the value of XGPC.

5.7 Security

In order to protect XGATE application code on secured S12X devices, a few restrictions in the debug features have been made. These are:

• Registers XGCCR, XGPC, and XGR1–XGR7 will read zero on a secured device
• Registers XGCCR, XGPC, and XGR1–XGR7 can not be written on a secured device
• Single stepping is not possible on a secured device

5.8 Instruction Set

5.8.1 Addressing Modes

For the ease of implementation the architecture is a strict Load/Store RISC machine, which means all operations must have one of the eight general purpose registers R0 … R7 as their source as well their destination. All word accesses must work with a word aligned address, that is A[0] = 0!

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5.8.1.1 Naming Conventions

RD Destination register, allowed range is R0–R7 RD.L Low byte of the destination register, bits [7:0] RD.H High byte of the destination register, bits [15:8] RS, RS1, RS2 Source register, allowed range is R0–R7 RS.L, RS1.L, RS2.L Low byte of the source register, bits [7:0] RS.H, RS1.H, RS2.H High byte of the source register, bits[15:8] RB Base register for indexed addressing modes, allowed range is R0–R7 RI Offset register for indexed addressing modes with register offset, allowed range is R0–R7 RI+ Offset register for indexed addressing modes with register offset and post-increment, Allowed range is R0–R7 (R0+ is equivalent to R0) –RI Offset register for indexed addressing modes with register offset and pre-decrement, Allowed range is R0–R7 (–R0 is equivalent to R0) NOTE Even though register R1 is intended to be used as a pointer to the variable segment, it may be used as a general purpose data register as well. Selecting R0 as destination register will discard the result of the instruction. Only the condition code register will be updated

5.8.1.2 Inherent Addressing Mode (INH)

Instructions that use this addressing mode either have no operands or all operands are in internal XGATE registers:. Examples BRK RTS

5.8.1.3 Immediate 3-Bit Wide (IMM3)

Operands for immediate mode instructions are included in the instruction stream and are fetched into the instruction queue along with the rest of the 16 bit instruction. The ’#’ symbol is used to indicate an immediate addressing mode operand. This address mode is used for semaphore instructions. Examples: CSEM #1 ; Unlock semaphore 1 SSEM #3 ; Lock Semaphore 3

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5.8.1.4 Immediate 4 Bit Wide (IMM4)

The 4 bit wide immediate addressing mode is supported by all shift instructions. RD = RD ∗ imm4 Examples: LSL R4,#1 ; R4 = R4 << 1; shift register R4 by 1 bit to the left LSR R4,#3 ; R4 = R4 >> 3; shift register R4 by 3 bits to the right

5.8.1.5 Immediate 8 Bit Wide (IMM8)

The 8 bit wide immediate addressing mode is supported by four major commands (ADD, SUB, LD, CMP). RD = RD ∗ imm8 Examples: ADDL R1,#1 ; adds an 8 bit value to register R1 SUBL R2,#2 ; subtracts an 8 bit value from register R2 LDH R3,#3 ; loads an 8 bit immediate into the high byte of Register R3 CMPL R4,#4 ; compares the low byte of register R4 with an immediate value

5.8.1.6 Immediate 16 Bit Wide (IMM16)

The 16 bit wide immediate addressing mode is a construct to simplify assembler code. Instructions which offer this mode are translated into two opcodes using the eight bit wide immediate addressing mode. RD = RD ∗ imm16 Examples: LDW R4,#$1234 ; translated to LDL R4,#$34; LDH R4,#$12 ADD R4,#$5678 ; translated to ADDL R4,#$78; ADDH R4,#$56

5.8.1.7 Monadic Addressing (MON)

In this addressing mode only one operand is explicitly given. This operand can either be the source (f(RD)), the target (RD = f()), or both source and target of the operation (RD = f(RD)). Examples: JAL R1 ; PC = R1, R1 = PC+2 SIF R2 ; Trigger IRQ associated with the channel number in R2.L

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5.8.1.8 Dyadic Addressing (DYA)

In this mode the result of an operation between two registers is stored in one of the registers used as operands. RD = RD ∗ RS is the general register to register format, with register RD being the first operand and RS the second. RD and RS can be any of the 8 general purpose registers R0 … R7. If R0 is used as the destination register, only the condition code flags are updated. This addressing mode is used only for shift operations with a variable shift value Examples: LSL R4,R5 ; R4 = R4 << R5 LSR R4,R5 ; R4 = R4 >> R5

5.8.1.9 Triadic Addressing (TRI)

In this mode the result of an operation between two or three registers is stored into a third one. RD = RS1 ∗ RS2 is the general format used in the order RD, RS1, RS1. RD, RS1, RS2 can be any of the 8 general purpose registers R0 … R7. If R0 is used as the destination register RD, only the condition code flags are updated. This addressing mode is used for all arithmetic and logical operations. Examples: ADC R5,R6,R7 ; R5 = R6 + R7 + Carry SUB R5,R6,R7 ; R5 = R6 - R7

5.8.1.10 Relative Addressing 9-Bit Wide (REL9)

A 9-bit signed word address offset is included in the instruction word. This addressing mode is used for conditional branch instructions. Examples: BCC REL9 ; PC = PC + 2 + (REL9 << 1) BEQ REL9 ; PC = PC + 2 + (REL9 << 1)

5.8.1.11 Relative Addressing 10-Bit Wide (REL10)

An 11-bit signed word address offset is included in the instruction word. This addressing mode is used for the unconditional branch instruction. Examples: BRA REL10 ; PC = PC + 2 + (REL10 << 1)

5.8.1.12 Index Register plus Immediate Offset (IDO5)

(RS, #offset5) provides an unsigned offset from the base register. Examples: LDB R4,(R1,#offset) ; loads a byte from R1+offset into R4 STW R4,(R1,#offset) ; stores R4 as a word to R1+offset

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5.8.1.13 Index Register plus Register Offset (IDR)

For load and store instructions (RS, RI) provides a variable offset in a register. Examples: LDB R4,(R1,R2) ; loads a byte from R1+R2 into R4 STW R4,(R1,R2) ; stores R4 as a word to R1+R2

5.8.1.14 Index Register plus Register Offset with Post-increment (IDR+)

[RS, RI+] provides a variable offset in a register, which is incremented after accessing the memory. In case of a byte access the index register will be incremented by one. In case of a word access it will be incremented by two. Examples: LDB R4,(R1,R2+) ; loads a byte from R1+R2 into R4, R2+=1 STW R4,(R1,R2+) ; stores R4 as a word to R1+R2, R2+=2

5.8.1.15 Index Register plus Register Offset with Pre-decrement (–IDR)

[RS, -RI] provides a variable offset in a register, which is decremented before accessing the memory. In case of a byte access the index register will be decremented by one. In case of a word access it will be decremented by two. Examples: LDB R4,(R1,-R2) ; R2 -=1, loads a byte from R1+R2 into R4 STW R4,(R1,-R2) ; R2 -=2, stores R4 as a word to R1+R2

5.8.2 Instruction Summary and Usage

5.8.2.1 Load & Store Instructions

Any register can be loaded either with an immediate or from the address space using indexed addressing modes. LDL RD,#IMM8 ; loads an immediate 8 bit value to the lower byte of RD LDW RD,(RB,RI) ; loads data using RB+RI as effective address LDB RD,(RB, RI+) ; loads data using RB+RI as effective address ; followed by an increment of RI depending on ; the size of the operation The same set of modes is available for the store instructions STB RS,(RB, RI) ; stores data using RB+RI as effective address STW RS,(RB, RI+) ; stores data using RB+RI as effective address ; followed by an increment of RI depending on ; the size of the operation.

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5.8.2.2 Logic and Arithmetic Instructions

All logic and arithmetic instructions support the 8 bit immediate addressing mode (IMM8: RD = RD ∗ #IMM8) and the triadic addressing mode (TRI: RD = RS1 ∗ RS2). All arithmetic is considered as signed, sign, overflow, zero and carry flag will be updated. The carry will not be affected for logical operations. ADDL R2,#1 ; increment R2 ANDH R4,#$FE ; R4.H = R4.H & $FE, clear lower bit of higher byte ADD R3,R4,R5 ; R3 = R4 + R5 SUB R3,R4,R5 ; R3 = R4 - R5 AND R3,R4,R5 ; R3 = R4 & R5 logical AND on the whole word OR R3,R4,R5 ; R3 = R4 | R5

5.8.2.3 Register – Register Transfers

This group comprises transfers from and to some special registers TFR R3,CCR ; transfers the condition code register to the low byte of ; register R3 Branch Instructions The branch offset is +255 words or -256 words counted from the beginning of the next instruction. Since instructions have a fixed 16 bit width, the branch offsets are word aligned by shifting the offset value by 2. BEQ label ; if Z flag = 1 branch to label An unconditional branch allows a +511 words or -512 words branch distance. BRA label

5.8.2.4 Shift Instructions

Shift operations allow the use of a 4 bit wide immediate value to identify a shift width within a 16 bit word. For shift operations a value of 0 does not shift at all, while a value of 15 shifts the register RD by 15 bits. In a second form the shift value is contained in the bits 3:0 of the register RS. Examples: LSL R4,#1 ; R4 = R4 << 1; shift register R4 by 1 bit to the left LSR R4,#3 ; R4 = R4 >> 3; shift register R4 by 3 bits to the right ASR R4,R2 ; R4 = R4 >> R2;arithmetic shift register R4 right by the amount ; of bits contained in R2[3:0].

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5.8.2.5 Bit Field Operations

This addressing mode is used to identify the position and size of a bit field for insertion or extraction. The width and offset are coded in the lower byte of the source register 2, RS2. The content of the upper byte is ignored. An offset of 0 denotes the right most position and a width of 0 denotes 1 bit. These instructions are very useful to extract, insert, clear, set or toggle portions of a 16 bit word. Figure 5-23. Bit Field Addressing BFEXT R3,R4,R5 ; R5: W4 bits offset O4, will be extracted from R4 into R3

5.8.2.6 Special Instructions for DMA Usage

The XGATE offers a number of additional instructions for flag manipulation, program flow control and debugging: 1. SIF: Set a channel interrupt flag 2. SSEM: Test and set a hardware semaphore 3. CSEM: Clear a hardware semaphore 4. BRK: Software breakpoint 5. NOP: No Operation 6. RTS: Terminate the current thread W4 O4 15 0 25 W4=3, O4=2 15 03 Bit Field Extract Bit Field Insert RS2 RS1 RD

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5.8.3 Cycle Notation

Table 5-16show the XGATE access detail notation. Each code letter equals one XGATE cycle. Each letter implies additional wait cycles if memories or peripherals are not accessible. Memories or peripherals are not accessible if they are blocked by the S12X_CPU. In addition to this Peripherals are only accessible every other XGATE cycle. Uppercase letters denote 16 bit operations. Lowercase letters denote 8 bit operations. The XGATE is able to perform two bus or wait cycles per S12X_CPU cycle.

5.8.4 Thread Execution

When the RISC core is triggered by an interrupt request (see Figure 5-1) it first executes a vector fetch sequence which performs three bus accesses: 1. A V-cycle to fetch the initial content of the program counter. 2. A V-cycle to fetch the initial content of the data segment pointer (R1). 3. A P-cycle to load the initial opcode. Afterwards a sequence of instructions (thread) is executed which is terminated by an "RTS" instruction. If further interrupt requests are pending after a thread has been terminated, a new vector fetch will be performed. Otherwise the RISC core will idle until a new interrupt request is received. A thread can not be interrupted by an interrupt request.

5.8.5 Instruction Glossary

This section describes the XGATE instruction set in alphabetical order. Table 5-16. Access Detail Notation V— Vector fetch: always an aligned word read, lasts for at least one RISC core cycle P— Program word fetch: always an aligned word read, lasts for at least one RISC core cycle r— 8 bit data read: lasts for at least one RISC core cycle R— 16 bit data read: lasts for at least one RISC core cycle w— 8 bit data write: lasts for at least one RISC core cycle W— 16 bit data write: lasts for at least one RISC core cycle A— Alignment cycle: no read or write, lasts for zero or one RISC core cycles f— Free cycle: no read or write, lasts for one RISC core cycles Special Cases PP/P— Branch: PP if branch taken, P if not

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 243 Operation RS1 + RS2 + C ⇒ RD Adds the content of register RS1, the content of register RS2 and the value of the Carry bit using binary addition and stores the result in the destination register RD. The Zero Flag is also carried forward from the previous operation allowing 32 and more bit additions. Example: ADC R6,R2,R2 ADC R7,R3,R3 ; R7:R6 = R5:R4 + R3:R2 BCC ; conditional branch on 32 bit addition CCR Effects Code and CPU Cycles ADC Add with Carry ADC NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000 and Z was set before this operation; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new C: Set if there is a carry from bit 15 of the result; cleared otherwise. RD[15]new | RS2[15] & RD[15]new Source Form Address Mode Machine Code Cycles ADC RD, RS1, RS2 TRI 0 0 0 1 1 RD RS1 RS2 1 1 P

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RS1 + RS2 ⇒ RD RD + IMM16 ⇒ RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #[15:8]) Performs a 16 bit addition and stores the result in the destination register RD. CCR Effects Code and CPU Cycles ADD Add without Carry ADD NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new Refer to ADDH instruction for #IMM16 operations. C: Set if there is a carry from bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new Refer to ADDH instruction for #IMM16 operations. Source Form Address Mode Machine Code Cycles ADD RD, RS1, RS2 TRI 0 0 0 1 1 RD RS1 RS2 1 0 P ADD RD, #IMM16 IMM8 1 1 1 0 0 RD IMM16[7:0] P IMM8 1 1 1 0 1 RD IMM16[15:8] P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 245 Operation RD + IMM8:$00 ⇒ RD Adds the content of high byte of register RD and a signed immediate 8 bit constant using binary addition and stores the result in the high byte of the destination register RD. This instruction can be used after an ADDL for a 16 bit immediate addition. Example: ADDL R2,#LOWBYTE ADDH R2,#HIGHBYTE ; R2 = R2 + 16 bit immediate CCR Effects Code and CPU Cycles ADDH Add Immediate 8 bit Constant (High Byte) ADDH NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old & IMM8[7] & RD[15]new | RD[15]old & IMM8[7] & RD[15]new C: Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15] old & IMM8[7] | RD[15]old & RD[15]new | IMM8[7] & RD[15]new Source Form Address Mode Machine Code Cycles ADDH RD, #IMM8 IMM8 1 1 1 0 1 RD IMM8 P

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RD + $00:IMM8 ⇒ RD Adds the content of register RD and an unsigned immediate 8 bit constant using binary addition and stores the result in the destination register RD. This instruction must be used first for a 16 bit immediate addition in conjunction with the ADDH instruction. CCR Effects Code and CPU Cycles ADDL Add Immediate 8 bit Constant (Low Byte) ADDL NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise. RD[15]old & RD[15]new C: Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15]old & RD[15]new Source Form Address Mode Machine Code Cycles ADDL RD, #IMM8 IMM8 1 1 1 0 0 RD IMM8 P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 247 Operation RS1 & RS2 ⇒ RD RD & IMM16 ⇒ RD (translates to ANDL RD, #IMM16[7:0]; ANDH RD, #IMM16[15:8]) Performs a bit wise logical AND of two 16 bit values and stores the result in the destination register RD. Remark: There is no complement to the BITH and BITL functions. This can be imitated by using R0 as a destination register. AND R0, RS1, RS2 performs a bit wise test without storing a result. CCR Effects Code and CPU Cycles AND Logical AND AND NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. Refer to ANDH instruction for #IMM16 operations. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles AND RD, RS1, RS2 TRI 0 0 0 1 0 RD RS1 RS2 0 0 P AND RD, #IMM16 IMM8 1 0 0 0 0 RD IMM16[7:0] P IMM8 1 0 0 0 1 RD IMM16[15:8] P

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RD.H & IMM8 ⇒ RD.H Performs a bit wise logical AND between the high byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects Code and CPU Cycles ANDH Logical AND Immediate 8 bit Constant (High Byte) ANDH NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the 8 bit result is $00; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles ANDH RD, #IMM8 IMM8 1 0 0 0 1 RD IMM8 P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 249 Operation RD.L & IMM8 ⇒ RD.L Performs a bit wise logical AND between the low byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects Code and CPU Cycles ANDL Logical AND Immediate 8 bit Constant (Low Byte) ANDL NZVC ∆∆ 0— N: Set if bit 7 of the result is set; cleared otherwise. Z: Set if the 8 bit result is $00; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles ANDL RD, #IMM8 IMM8 1 0 0 0 0 RD IMM8 P

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n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the sign bit (RD[15]). The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0. In dyadic address mode,n is determined by the content of RS.n is considered to be 16 if the content of RS is greater than 15. CCR Effects Code and CPU Cycles ASR Arithmetic Shift Right ASR NZVC ∆∆ 0 ∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old ^ RD[15]new C: Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected. Source Form Address Mode Machine Code Cycles ASR RD, #IMM4 IMM4 0 0 0 0 1 RD IMM4 1 0 0 1 P ASR RD, RS DYA 0 0 0 0 1 RD RS 1 0 0 0 1 P b15 RD C n

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 251 Operation If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Carry flag and branches if C = 0. CCR Effects Code and CPU Cycles BCC Branch if Carry Cleared (Same as BHS) BCC NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BCC REL9 REL9 0 0 1 0 0 0 0 REL9 PP/P

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If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Carry flag and branches if C = 1. CCR Effects Code and CPU Cycles BCS Branch if Carry Set (Same as BLO) BCS NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BCS REL9 REL9 0 0 1 0 0 0 1 REL9 PP/P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 253 Operation If Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Zero flag and branches if Z = 1. CCR Effects Code and CPU Cycles BEQ Branch if Equal BEQ NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BEQ REL9 REL9 0 0 1 0 0 1 1 REL9 PP/P

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RS1[(o+w):o] ⇒ RD[w:0]; 0 ⇒ RD[15:(w+1)] w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position o and writes them right aligned into register RD. The remaining bits in RD will be cleared. If (o+w) > 15 only bits [15:o] get extracted. CCR Effects Code and CPU Cycles BFEXT Bit Field Extract BFEXT NZVC 0 ∆ 0 ∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles BFEXT RD, RS1, RS2 TRI 0 1 1 0 0 RD RS1 RS2 1 1 P W4 O4 15 0 25 W4=3, O4=2 15 03 Bit Field Extract RS2 RS1 RD0 15 0 374

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 255 Operation FirstOne (RS) ⇒ RD; Searches the first “1” in register RS (from MSB to LSB) and writes the bit position into the destination register RD. The upper bits of RD are cleared. In case the content of RS is equal to $0000, RD will be cleared and the carry flag will be set. This is used to distinguish a “1” in position 0 versus no “1” in the whole RS register at all. CCR Effects Code and CPU Cycles BFFO Bit Field Find First One BFFO NZVC 0 ∆ 0 ∆ N: 0; cleared. Z: Set if the result is $0000; cleared otherwise. V: 0; cleared. C: Set if RS = $00001; cleared otherwise.

1 Before executing the instruction

BFFO RD, RS DYA 0 0 0 0 1 RD RS 1 0 0 0 0 P

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RS1[w:0] ⇒ RD[(w+o):o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0 and writes them into register RD starting at position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to clear bits. CCR Effects Code and CPU Cycles BFINS Bit Field Insert BFINS NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles BFINS RD, RS1, RS2 TRI 0 1 1 0 1 RD RS1 RS2 1 1 P W4 O4 15 0 25 W4=3, O4=2 15 03 Bit Field Insert RS2 RD RS1 15 0 374

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 257 Operation !RS1[w:0] ⇒ RD[w+o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, inverts them and writes into register RD starting at position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to set bits. CCR Effects Code and CPU Cycles BFINSI Bit Field Insert and Invert BFINSI NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles BFINSI RD, RS1, RS2 TRI 0 1 1 1 0 RD RS1 RS2 1 1 P W4 O4 15 0 25 W4=3, O4=2 15 03 Inverted Bit Field Insert RS2 RD RS1 15 0 374

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!(RS1[w:0] ^ RD[w+o:o]) ⇒ RD[w+o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes the bits back io RD. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to toggle bits. CCR Effects Code and CPU Cycles BFINSX Bit Field Insert and XNOR BFINSX NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles BFINSX RD, RS1, RS2 TRI 0 1 1 1 1 RD RS1 RS2 1 1 P W4 O4 15 0 25 W4=3, O4=2 15 03 Bit Field Insert XNOR RS2 RD RS1 15 0 374

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 259 Operation If N ^ V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 ≥ RS2: SUB R0,RS1,RS2 BGE REL9 CCR Effects Code and CPU Cycles BGE Branch if Greater than or Equal to Zero BGE NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BGE REL9 REL9 0 0 1 1 0 1 0 REL9 PP/P

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If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 > RS2: SUB R0,RS1,RS2 BGE REL9 CCR Effects Code and CPU Cycles BGT Branch if Greater than Zero BGT NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BGT REL9 REL9 0 0 1 1 1 0 0 REL9 PP/P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 261 Operation If C | Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 > RS2: SUB R0,RS1,RS2 BHI REL9 CCR Effects Code and CPU Cycles BHI Branch if Higher BHI NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BHI REL9 REL9 0 0 1 1 0 0 0 REL9 PP/P

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If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 ≥ RS2: SUB R0,RS1,RS2 BHS REL9 CCR Effects Code and CPU Cycles BHS Branch if Higher or Same (Same as BCC) BHS NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BHS REL9 REL9 0 0 1 0 0 0 0 REL9 PP/P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 263 Operation RD.H & IMM8 ⇒ NONE Performs a bit wise logical AND between the high byte of register RD and an immediate 8 bit constant. Only the condition code flags get updated, but no result is written back CCR Effects Code and CPU Cycles BITH Bit Test Immediate 8 bit Constant (High Byte) BITH NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the 8 bit result is $00; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles BITH RD, #IMM8 IMM8 1 0 0 1 1 RD IMM8 P

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RD.L & IMM8 ⇒ NONE Performs a bit wise logical AND between the low byte of register RD and an immediate 8 bit constant. Only the condition code flags get updated, but no result is written back. CCR Effects Code and CPU Cycles BITL Bit Test Immediate 8 bit Constant (Low Byte) BITL NZVC ∆∆ 0— N: Set if bit 7 of the result is set; cleared otherwise. Z: Set if the 8 bit result is $00; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles BITL RD, #IMM8 IMM8 1 0 0 1 0 RD IMM8 P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 265 Operation If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 ≤ RS2: SUB R0,RS1,RS2 BLE REL9 CCR Effects Code and CPU Cycles BLE Branch if Less or Equal to Zero BLE NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BLE REL9 REL9 0 0 1 1 1 0 1 REL9 PP/P

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If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 < RS2: SUB R0,RS1,RS2 BLO REL9 CCR Effects Code and CPU Cycles BLO Branch if Carry Set (Same as BCS) BLO NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BLO REL9 REL9 0 0 1 0 0 0 1 REL9 PP/P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 267 Operation If C | Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 ≤ RS2: SUB R0,RS1,RS2 BLS REL9 CCR Effects Code and CPU Cycles BLS Branch if Lower or Same BLS NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BLS REL9 REL9 0 0 1 1 0 0 1 REL9 PP/P

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If N ^ V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 < RS2: SUB R0,RS1,RS2 BLT REL9 CCR Effects Code and CPU Cycles BLT Branch if Lower than Zero BLT NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BLT REL9 REL9 0 0 1 1 0 1 1 REL9 PP/P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 269 Operation If N = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Sign flag and branches if N = 1. CCR Effects Code and CPU Cycles BMI Branch if Minus BMI NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BMI REL9 REL9 0 0 1 0 1 0 1 REL9 PP/P

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If Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Zero flag and branches if Z = 0. CCR Effects Code and CPU Cycles BNE Branch if Not Equal BNE NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BNE REL9 REL9 0 0 1 0 0 1 0 REL9 PP/P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 271 Operation If N = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Sign flag and branches if N = 0. CCR Effects Code and CPU Cycles BPL Branch if Plus BPL NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BPL REL9 REL9 0 0 1 0 1 0 0 REL9 PP/P

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———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BRA REL10 REL10 0 0 1 1 1 1 REL10 PP

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 273 Operation Put XGATE into Debug Mode (seeSection 5.6.2, “Entering Debug Mode”)and signals a Software breakpoint to the S12X_DBG module (see section 4.9 of the S12X_DBG Section). NOTE It is not possible to single step over a BRK instruction. This instruction does not advance the program counter. CCR Effects Code and CPU Cycles BRK Break BRK NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles B R K I N H 0000000000000000 P A f f

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If V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Overflow flag and branches if V = 0. CCR Effects Code and CPU Cycles BVC Branch if Overflow Cleared BVC NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BVC REL9 REL9 0 0 1 0 1 1 0 REL9 PP/P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 275 Operation If V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Overflow flag and branches if V = 1. CCR Effects Code and CPU Cycles BVS Branch if Overflow Set BVS NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles BVS REL9 REL9 0 0 1 0 1 1 1 REL9 PP/P

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RS1 – RS2 ⇒ NONE (translates to SUB R0, RS1, RS2) RD – IMM16 ⇒ NONE (translates to CMPL RD, #IMM16[7:0]; CPCH RD, #IMM16[15:8]) Subtracts two 16 bit values and discards the result. CCR Effects Code and CPU Cycles CMP Compare CMP NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS1[15] & RS2[15] & result[15] | RS1[15] & RS2[15] & result[15] RD[15] & IMM16[15] & result[15] | RD[15] & IMM16[15] & result[15] C: Set if there is a carry from the bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & result[15] | RS2[15] & result[15] RD[15] & IMM16[15] | RD[15] & result[15] | IMM16[15] & result[15] Source Form Address Mode Machine Code Cycles CMP RS1, RS2 TRI 0 0 0 1 1 0 0 0 RS1 RS2 0 0 P CMP RS, #IMM16 IMM8 1 1 0 1 0 RS IMM16[7:0] P IMM8 1 1 0 1 1 RS IMM16[15:8] P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 277 Operation RS.L – IMM8 ⇒ NONE, only condition code flags get updated Subtracts the 8 bit constant IMM8 contained in the instruction code from the low byte of the source register RS.L using binary subtraction and updates the condition code register accordingly. Remark: There is no equivalent operation using triadic addressing. Comparing the values of two registers can be performed by using the subtract instruction with R0 as destination register. CCR Effects Code and CPU Cycles CMPL Compare Immediate 8 bit Constant (Low Byte) CMPL NZVC ∆∆∆∆ N: Set if bit 7 of the result is set; cleared otherwise. Z: Set if the 8 bit result is $00; cleared otherwise. V: Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise. RS[7] & IMM8[7] & result[7] | RS[7] & IMM8[7] & result[7] C: Set if there is a carry from the Bit 7 to Bit 8 of the result; cleared otherwise. RS[7] & IMM8[7] | RS[7] & result[7] | IMM8[7] & result[7] Source Form Address Mode Machine Code Cycles CMPL RS, #IMM8 IMM8 1 1 0 1 0 RS IMM8 P

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~RS ⇒ RD (translates to XNOR RD, R0, RS) ~RD ⇒ RD (translates to XNOR RD, R0, RD) Performs a one’s complement on a general purpose register. CCR Effects Code and CPU Cycles COM One’s Complement COM NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles COM RD, RS TRI 0 0 0 1 0 RD 0 0 0 RS 1 1 P COM RD TRI 0 0 0 1 0 RD 0 0 0 RD 1 1 P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 279 Operation RS2 – RS1 - C ⇒ NONE (translates to SBC R0, RS1, RS2) Subtracts the carry bit and the content of register RS2 from the content of register RS1 using binary subtraction and discards the result. CCR Effects Code and CPU Cycles CPC Compare with Carry CPC NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS1[15] & RS2[15] & result[15] | RS1[15] & RS2[15] & result[15] C: Set if there is a carry from the bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & result[15] | RS2[15] & result[15] Source Form Address Mode Machine Code Cycles CPC RS1, RS2 TRI 0 0 0 1 1 0 0 0 RS1 RS2 0 1 P

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RS.H - IMM8 - C ⇒ NONE, only condition code flags get updated Subtracts the carry bit and the 8 bit constant IMM8 contained in the instruction code from the high byte of the source register RD using binary subtraction and updates the condition code register accordingly. The carry bit and Zero bits are taken into account to allow a 16 bit compare in the form of CMPL R2,#LOWBYTE CPCH R2,#HIGHBYTE BCC ; branch condition Remark: There is no equivalent operation using triadic addressing. Comparing the values of two registers can be performed by using the subtract instruction with R0 as destination register. CCR Effects Code and CPU Cycles CPCH Compare Immediate 8 bit Constant with Carry (High Byte) CPCH NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $00 and Z was set before this operation; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS[15] & IMM8[7] & result[15] | RS[15] & IMM8[7] & result[15] C: Set if there is a carry from the bit 15 of the result; cleared otherwise. RS[15] & IMM8[7] | RS[15] & result[15] | IMM8[7] & result[15] Source Form Address Mode Machine Code Cycles CPCH RD, #IMM8 IMM8 1 1 0 1 1 RS IMM8 P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 281 Operation Unlocks a semaphore that was locked by the RISC core. In monadic address mode, bits RS[2:0] select the semaphore to be cleared. CCR Effects Code and CPU Cycles CSEM Clear Semaphore CSEM NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles CSEM #IMM3 IMM3 00000 IMM3 1 1110000 P A CSEM RS MON 00000 R S 11110001 P A

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n = RS or IMM4 Shifts the bits in register RDn positions to the left. The lowern bits of the register RD become filled with the carry flag. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0. In dyadic address mode,n is determined by the content of RS.n is considered to be 16 if the content of RS is greater than 15. CCR Effects Code and CPU Cycles CSL Logical Shift Left with Carry CSL NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old ^ RD[15]new C: Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected. Source Form Address Mode Machine Code Cycles CSL RD, #IMM4 IMM4 0 0 0 0 1 RD IMM4 1 0 1 0 P CSL RD, RS DYA 0 0 0 0 1 RD RS 1 0 0 1 0 P CRD C C C n bits C n

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 283 Operation n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the carry flag. The carry flag will be updated to the bit contained in RD[n-1] before the shift forn >0 . n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0. In dyadic address mode,n is determined by the content of RS.n is considered to be 16 if the content of RS is greater than 15. CCR Effects Code and CPU Cycles CSR Logical Shift Right with Carry CSR NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old ^ RD[15]new C: Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected. Source Form Address Mode Machine Code Cycles CSR RD, #IMM4 IMM4 0 0 0 0 1 RD IMM4 1 0 1 1 P CSR RD, RS DYA 0 0 0 0 1 RD RS 1 0 0 1 1 P C C RDCC n bits C n

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PC + $0002 ⇒ RD; RD ⇒ PC Jumps to the address stored in RD and saves the return address in RD. CCR Effects Code and CPU Cycles JAL Jump and Link JAL NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles J A L R D M O N 00000 R D 11110110 P P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 285 Operation M[RB, #OFFS5 ⇒ RD.L; $00 ⇒ RD.H M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H; RI+1 ⇒ RI;1 RI-1 ⇒ RI; M[RS, RI] ⇒ RD.L; $00 ⇒ RD.H Loads a byte from memory into the low byte of register RD. The high byte is cleared. CCR Effects Code and CPU Cycles LDB Load Byte from Memory (Low Byte) LDB 1.If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not be incremented after the data move: M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles LDB RD, (RB, #OFFS5) IDO5 0 1 0 0 0 RD RB OFFS5 Pr LDB RD, (RS, RI) IDR 0 1 1 0 0 RD RB RI 0 0 Pr LDB RD, (RS, RI+) IDR+ 0 1 1 0 0 RD RB RI 0 1 Pr LDB RD, (RS, -RI) -IDR 0 1 1 0 0 RD RB RI 1 0 Pr

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IMM8 ⇒ RD.H; Loads an eight bit immediate constant into the high byte of register RD. The low byte is not affected. CCR Effects Code and CPU Cycles LDH Load Immediate 8 bit Constant (High Byte) LDH NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles LDH RD, #IMM8 IMM8 1 1 1 1 1 RD IMM8 P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 287 Operation IMM8 ⇒ RD.L; $00 ⇒ RD.H Loads an eight bit immediate constant into the low byte of register RD. The high byte is cleared. CCR Effects Code and CPU Cycles LDL Load Immediate 8 bit Constant (Low Byte) LDL NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles LDL RD, #IMM8 IMM8 1 1 1 1 0 RD IMM8 P

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M[RB, #OFFS5] ⇒ RD M[RB, RI] ⇒ RD M[RB, RI] ⇒ RD; RI+2 ⇒ RI1 RI-2 ⇒ RI; M[RS, RI] ⇒ RD IMM16 ⇒ RD (translates to LDL RD, #IMM16[7:0]; LDH RD, #IMM16[15:8]) Loads a 16 bit value into the register RD. CCR Effects Code and CPU Cycles LDW Load Word from Memory LDW 1. If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not be incremented after the data move: M[RB, RI] ⇒ RD NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles LDW RD, (RB, #OFFS5) IDO5 0 1 0 0 1 RD RB OFFS5 PR LDW RD, (RB, RI) IDR 0 1 1 0 1 RD RB RI 0 0 PR LDW RD, (RB, RI+) IDR+ 0 1 1 0 1 RD RB RI 0 1 PR LDW RD, (RB, -RI) -IDR 0 1 1 0 1 RD RB RI 1 0 PR LDW RD, #IMM16 IMM8 1 1 1 1 0 RD IMM16[7:0] P IMM8 1 1 1 1 1 RD IMM16[15:8] P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 289 Operation n = RS or IMM4 Shifts the bits in register RDn positions to the left. The lowern bits of the register RD become filled with zeros. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0. In dyadic address mode,n is determined by the content of RS.n is considered to be 16 if the content of RS is greater than 15. CCR Effects Code and CPU Cycles LSL Logical Shift Left LSL NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old ^ RD[15]new C: Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected. Source Form Address Mode Machine Code Cycles LSL RD, #IMM4 IMM4 0 0 0 0 1 RD IMM4 1 1 0 0 P LSL RD, RS DYA 0 0 0 0 1 RD RS 1 0 1 0 0 P 0RD 0 0 0 n bits C n

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n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with zeros. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0. In dyadic address mode,n is determined by the content of RS.n is considered to be 16 if the content of RS is greater than 15. CCR Effects Code and CPU Cycles LSR Logical Shift Right LSR NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old ^ RD[15]new C: Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected. Source Form Address Mode Machine Code Cycles LSR RD, #IMM4 IMM4 0 0 0 0 1 RD IMM4 1 1 0 1 P LSR RD, RS DYA 0 0 0 0 1 RD RS 1 0 1 0 1 P

0 RD000

C n

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 291 Operation RS ⇒ RD (translates to OR RD, R0, RS) Copies the content of RS to RD. CCR Effects Code and CPU Cycles MOV Move Register Content MOV NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles MOV RD, RS TRI 0 0 0 1 0 RD 0 0 0 RS 1 0 P

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–RS ⇒ RD (translates to SUB RD, R0, RS) –RD ⇒ RD (translates to SUB RD, R0, RD) Performs a two’s complement on a general purpose register. CCR Effects Code and CPU Cycles NEG Two’s Complement NEG NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS[15] & RD[15]new C: Set if there is a carry from the bit 15 of the result; cleared otherwise RS[15] | RD[15] new Source Form Address Mode Machine Code Cycles NEG RD, RS TRI 0 0 0 1 1 RD 0 0 0 RS 0 0 P NEG RD TRI 0 0 0 1 1 RD 0 0 0 RD 0 0 P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 293 Operation No Operation for one cycle. CCR Effects Code and CPU Cycles NOP No Operation NOP NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles N O P I N H 0000000100000000 P

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RS1 | RS2 ⇒ RD RD | IMM16⇒ RD (translates to ORL RD, #IMM16[7:0]; ORH RD, #IMM16[15:8] Performs a bit wise logical OR between two 16 bit values and stores the result in the destination register RD. CCR Effects Code and CPU Cycles OR Logical OR OR NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. Refer to ORH instruction for #IMM16 operations. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles OR RD, RS1, RS2 TRI 0 0 0 1 0 RD RS1 RS2 1 0 P OR RD, #IMM16 IMM8 1 0 1 0 0 RD IMM16[7:0] P IMM8 1 0 1 0 1 RD IMM16[15:8] P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 295 Operation RD.H | IMM8 ⇒ RD.H Performs a bit wise logical OR between the high byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects Code and CPU Cycles ORH Logical OR Immediate 8 bit Constant (High Byte) ORH NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the 8 bit result is $00; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles ORH RD, #IMM8 IMM8 1 0 1 0 1 RD IMM8 P

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RD.L | IMM8 ⇒ RD.L Performs a bit wise logical OR between the low byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects Code and CPU Cycles ORL Logical OR Immediate 8 bit Constant (Low Byte) ORL NZVC ∆∆ 0— N: Set if bit 7 of the result is set; cleared otherwise. Z: Set if the 8 bit result is $00; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles ORL RD, #IMM8 IMM8 1 0 1 0 0 RD IMM8 P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 297 Operation Calculates the number of ones in the register RD. The Carry flag will be set if the number is odd, otherwise it will be cleared. CCR Effects Code and CPU Cycles PAR Calculate Parity PAR NZVC 0 ∆ 0 ∆ N: 0; cleared. Z: Set if RD is $0000; cleared otherwise. V: 0; cleared. C: Set if there the number of ones in the register RD is odd; cleared otherwise. Source Form Address Mode Machine Code Cycles PAR, RD MON 0 0 0 0 0 RD 1 1 1 1 0 1 0 1 P

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n = RS or IMM4 Rotates the bits in register RDn positions to the left. The lowern bits of the register RD are filled with the upper n bits. Two source forms are available. In the first form, the parameter n is contained in the instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits of the source register RS[3:0]. All other bits in RS are ignored. Ifn is zero, no shift will take place and the register RD will be unaffected; however, the condition code flags will be updated. CCR Effects Code and CPU Cycles ROL Rotate Left ROL NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles ROL RD, #IMM4 IMM4 0 0 0 0 1 RD IMM4 1 1 1 0 P ROL RD, RS DYA 0 0 0 0 1 RD RS 1 0 1 1 0 P RD n bits

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 299 Operation n = RS or IMM4 Rotates the bits in register RD n positions to the right. The upper n bits of the register RD are filled with the lower n bits. Two source forms are available. In the first form, the parameter n is contained in the instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits of the source register RS[3:0]. All other bits in RS are ignored. Ifn is zero no shift will take place and the register RD will be unaffected; however, the condition code flags will be updated. CCR Effects Code and CPU Cycles ROR Rotate Right ROR NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles ROR RD, #IMM4 IMM4 0 0 0 0 1 RD IMM4 1 1 1 1 P ROR RD, RS DYA 0 0 0 0 1 RD RS 1 0 1 1 1 P RD n bits

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Terminates the current thread of program execution and remains idle until a new thread is started by the hardware scheduler. CCR Effects Code and CPU Cycles RTS Return to Scheduler RTS NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles R T S I N H 0000001000000000 P A

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 301 Operation RS1 - RS2 - C ⇒ RD Subtracts the content of register RS2 and the value of the Carry bit from the content of register RS1 using binary subtraction and stores the result in the destination register RD. Also the zero flag is carried forward from the previous operation allowing 32 and more bit subtractions. Example: SUB R6,R4,R2 SBC R7,R5,R3 ; R7:R6 = R5:R4 - R3:R2 BCC ; conditional branch on 32 bit subtraction CCR Effects Code and CPU Cycles SBC Subtract with Carry SBC NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000 and Z was set before this operation; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new C: Set if there is a carry from bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new Source Form Address Mode Machine Code Cycles SBC RD, RS1, RS2 TRI 0 0 0 1 1 RD RS1 RS2 0 1 P

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The result in RD is the 16 bit sign extended representation of the original two’s complement number in the low byte of RD.L. CCR Effects Code and CPU Cycles SEX Sign Extend Byte to Word SEX NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles SEX RD MON 0 0 0 0 0 RD 1 1 1 1 0 1 0 0 P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 303 Operation Sets the Interrupt Flag of an XGATE Channel. This instruction supports two source forms. If inherent address mode is used, then the interrupt flag of the current channel (XGCHID) will be set. If the monadic address form is used, the interrupt flag associated with the channel id number contained in RS[6:0] is set. The content of RS[15:7] is ignored. CCR Effects Code and CPU Cycles SIF Set Interrupt Flag SIF NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles S I F I N H 0000001100000000 P A SIF RS MON 0 0 0 0 0 RS 1 1 1 1 0 1 1 1 PA

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Attempts to set a semaphore. The state of the semaphore will be stored in the Carry-Flag: 1 = Semaphore is locked by the RISC core 0 = Semaphore is locked by the S12X_CPU In monadic address mode, bits RS[2:0] select the semaphore to be set. CCR Effects Code and CPU Cycles SSEM Set Semaphore SSEM NZVC ——— ∆ N: Not affected. Z: Not affected. V: Not affected. C: Set if semaphore is locked by the RISC core; cleared otherwise. Source Form Address Mode Machine Code Cycles SSEM #IMM3 IMM3 0 0 0 0 0 IMM3 1 1 1 1 0 0 1 0 PA SSEM RS MON 0 0 0 0 0 RS 1 1 1 1 0 0 1 1 PA

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 305 Operation RS.L ⇒ M[RB, #OFFS5] RS.L ⇒ M[RB, RI] RS.L ⇒ M[RB, RI]; RI+1 ⇒ RI; RI–1 ⇒ RI; RS.L ⇒ M[RB, RI]1 Stores the low byte of register RD to memory. CCR Effects Code and CPU Cycles STB Store Byte to Memory (Low Byte) STB 1. If the same general purpose register is used as index (RI) and source register (RS), the unmodified content of the source register is written to the memory: RS.L ⇒ M[RB, RS-1]; RS-1 ⇒ RS NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles STB RS, (RB, #OFFS5), IDO5 0 1 0 1 0 RS RB OFFS5 Pw STB RS, (RB, RI) IDR 0 1 1 1 0 RS RB RI 0 0 Pw STB RS, (RB, RI+) IDR+ 0 1 1 1 0 RS RB RI 0 1 Pw STB RS, (RB, -RI) -IDR 0 1 1 1 0 RS RB RI 1 0 Pw

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RS ⇒ M[RB, #OFFS5] RS ⇒ M[RB, RI] RS ⇒ M[RB, RI]; RI+2 ⇒ RI; RI–2 ⇒ RI; RS ⇒ M[RB, RI]1 Stores the content of register RS to memory. CCR Effects Code and CPU Cycles STW Store Word to Memory STW 1. If the same general purpose register is used as index (RI) and source register (RS), the unmodified content of the source register is written to the memory: RS ⇒ M[RB, RS–2]; RS–2 ⇒ RS NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles STW RS, (RB, #OFFS5) IDO5 0 1 0 1 1 RS RB OFFS5 PW STW RS, (RB, RI) IDR 0 1 1 1 1 RS RB RI 0 0 PW STW RS, (RB, RI+) IDR+ 0 1 1 1 1 RS RB RI 0 1 PW STW RS, (RB, -RI) -IDR 0 1 1 1 1 RS RB RI 1 0 PW

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 307 Operation RS1 – RS2 ⇒ RD RD − IMM16 ⇒ RD (translates to SUBL RD, #IMM16[7:0]; SUBH RD, #IMM16{15:8]) Subtracts two 16 bit values and stores the result in the destination register RD. CCR Effects Code and CPU Cycles SUB Subtract without Carry SUB NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new Refer to SUBH instruction for #IMM16 operations. C: Set if there is a carry from the bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new Refer to SUBH instruction for #IMM16 operations. Source Form Address Mode Machine Code Cycles SUB RD, RS1, RS2 TRI 0 0 0 1 1 RD RS1 RS2 0 0 P SUB RD, #IMM16 IMM8 1 1 0 0 0 RD IMM16[7:0] P IMM8 1 1 0 0 1 RD IMM16[15:8] P

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RD – IMM8:$00 ⇒ RD Subtracts a signed immediate 8 bit constant from the content of high byte of register RD and using binary subtraction and stores the result in the high byte of destination register RD. This instruction can be used after an SUBL for a 16 bit immediate subtraction. Example: SUBL R2,#LOWBYTE SUBH R2,#HIGHBYTE ; R2 = R2 - 16 bit immediate CCR Effects Code and CPU Cycles SUBH Subtract Immediate 8 bit Constant (High Byte) SUBH NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old & IMM8[7] & RD[15]new | RD[15]old & IMM8[7] & RD[15]new C: Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15]old & IMM8[7] | RD[15]old & RD[15]new | IMM8[7] & RD[15]new Source Form Address Mode Machine Code Cycles SUBH RD, #IMM8 IMM8 1 1 0 0 1 RD IMM8 P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 309 Operation RD – $00:IMM8 ⇒ RD Subtracts an immediate 8 bit constant from the content of register RD using binary subtraction and stores the result in the destination register RD. CCR Effects Code and CPU Cycles SUBL Subtract Immediate 8 bit Constant (Low Byte) SUBL NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise. RD[15]old & RD[15]new C: Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15]old & RD[15]new Source Form Address Mode Machine Code Cycles SUBL RD, #IMM8 IMM8 1 1 0 0 0 RD IMM8 P

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TFR RD,CCR: CCR ⇒ RD[3:0]; 0 ⇒ RD[15:4] TFR CCR,RD: RD[3:0] ⇒ CCR TFR RD,PC: PC+4 ⇒ RD Transfers the content of one RISC core register to another. The TFR RD,PC instruction can be used to implement relative subroutine calls. Example: TFR R7,PC ;Return address (RETADDR) is stored in R7 BRA SUBR ;Relative branch to subroutine (SUBR) RETADDR ... SUBR ... JAL R7 ;Jump to return address (RETADDR) CCR Effects Code and CPU Cycles TFR Transfer from and to Special Registers TFR Source Form Address Mode Machine Code Cycles TFR RD,CCR CCR ⇒ R D M O N 00000 R D 11111000 P TFR CCR,RS RS ⇒ C C R M O N 00000 R S 11111001 P TFR RD,PCPC+4 ⇒ R D M O N 00000 R D 11111010 P TFR RD,CCR, TFR RD,PC: TFR CCR,RS: NZVC ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. NZVC ∆∆∆∆ N: RS[3]. Z: RS[2]. V: RS[1]. C: RS[0].

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 311 Operation RS – 0 ⇒ NONE (translates to SUB R0, RS, R0) Subtracts zero from the content of register RS using binary subtraction and discards the result. CCR Effects Code and CPU Cycles TST Test Register TST NZVC ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS[15] & result[15] C: Set if there is a carry from the bit 15 of the result; cleared otherwise. RS1[15] & result[15] Source Form Address Mode Machine Code Cycles TST RS TRI 0 0 0 1 1 0 0 0 RS1 0 0 0 0 0 P

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~(RS1 ^ RS2) ⇒ RD ~(RD ^ IMM16)⇒ RD (translates to XNOR RD, #IMM16{15:8]; XNOR RD, #IMM16[7:0]) Performs a bit wise logical exclusive NOR between two 16 bit values and stores the result in the destination register RD. Remark: Using R0 as a source registers will calculate the one’s complement of the other source register. Using R0 as both source operands will fill RD with $FFFF. CCR Effects Code and CPU Cycles XNOR Logical Exclusive NOR XNOR NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. Refer to XNORH instruction for #IMM16 operations. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles XNOR RD, RS1, RS2 TRI 0 0 0 1 0 RD RS1 RS2 1 1 P XNOR RD, #IMM16 IMM8 1 0 1 1 0 RD IMM16[7:0] P IMM8 1 0 1 1 1 RD IMM16[15:8] P

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 313 Operation ~(RD.H ^ IMM8) ⇒ RD.H Performs a bit wise logical exclusive NOR between the high byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects Code and CPU Cycles XNORH Logical Exclusive NOR Immediate 8 bit Constant (High Byte) XNORH NZVC ∆∆ 0— N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the 8 bit result is $00; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles XNORH RD, #IMM8 IMM8 1 0 1 1 1 RD IMM8 P

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~(RD.L ^ IMM8) ⇒ RD.L Performs a bit wise logical exclusive NOR between the low byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects Code and CPU Cycles XNORL Logical Exclusive NOR Immediate 8 bit Constant (Low Byte) XNORL NZVC ∆∆ 0— N: Set if bit 7 of the result is set; cleared otherwise. Z: Set if the 8 bit result is $00; cleared otherwise. V: 0; cleared. C: Not affected. Source Form Address Mode Machine Code Cycles XNORL RD, #IMM8 IMM8 1 0 1 1 0 RD IMM8 P

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5.8.6 Instruction Coding

Table 5-17 summarizes all XGATE instructions in the order of their machine coding. Table 5-17. Instruction Set Summary (Sheet 1 of 3) Functionality 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Return to Scheduler and Others BRK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOP 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 RTS 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 SIF 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Semaphore Instructions CSEM IMM3 0 0 0 0 0 IMM3 11110000 CSEM RS 0 0 0 0 0 R S 11110001 SSEM IMM3 0 0 0 0 0 IMM3 11110010 SSEM RS 0 0 0 0 0 R S 11110011 Single Register Instructions SEX RD 0 0 0 0 0 R D 11110100 PAR RD 0 0 0 0 0 R D 11110101 JAL RD 0 0 0 0 0 R D 11110110 SIF RS 0 0 0 0 0 R S 11110111 Special Move instructions TFR RD,CCR 0 0 0 0 0 R D 11111000 TFR CCR,RS 0 0 0 0 0 R S 11111001 TFR RD,PC 0 0 0 0 0 R D 11111010 Shift instructions Dyadic BFFO RD, RS 0 0 0 0 1 RD RS 1 0 0 0 0 ASR RD, RS 0 0 0 0 1 RD RS 1 0 0 0 1 CSL RD, RS 0 0 0 0 1 RD RS 1 0 0 1 0 CSR RD, RS 0 0 0 0 1 RD RS 1 0 0 1 1 LSL RD, RS 0 0 0 0 1 RD RS 1 0 1 0 0 LSR RD, RS 0 0 0 0 1 RD RS 1 0 1 0 1 ROL RD, RS 0 0 0 0 1 RD RS 1 0 1 1 0 ROR RD, RS 0 0 0 0 1 RD RS 1 0 1 1 1 Shift instructions immediate ASR RD, #IMM4 0 0 0 0 1 RD IMM4 1 0 0 1 CSL RD, #IMM4 0 0 0 0 1 RD IMM4 1 0 1 0 CSR RD, #IMM4 0 0 0 0 1 RD IMM4 1 0 1 1 LSL RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 0 0 LSR RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 0 1 ROL RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 1 0 ROR RD, #IMM4 0 0 0 0 1 RD IMM4 1 1 1 1

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AND RD, RS1, RS2 00010 R D R S 1 R S 2 00 OR RD, RS1, RS2 00010 R D R S 1 R S 2 10 XNOR RD, RS1, RS2 00010 R D R S 1 R S 2 11 Arithmetic Triadic For compare use SUB R0,Rs1,Rs2 SUB RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 0 0 SBC RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 0 1 ADD RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 1 0 ADC RD, RS1, RS2 0 0 0 1 1 RD RS1 RS2 1 1 Branches BCC REL9 0 0 1 0 0 0 0 REL9 BCS REL9 0 0 1 0 0 0 1 REL9 BNE REL9 0 0 1 0 0 1 0 REL9 BEQ REL9 0 0 1 0 0 1 1 REL9 BPL REL9 0 0 1 0 1 0 0 REL9 BMI REL9 0 0 1 0 1 0 1 REL9 BVC REL9 0 0 1 0 1 1 0 REL9 BVS REL9 0 0 1 0 1 1 1 REL9 BHI REL9 0 0 1 1 0 0 0 REL9 BLS REL9 0 0 1 1 0 0 1 REL9 BGE REL9 0 0 1 1 0 1 0 REL9 BLT REL9 0 0 1 1 0 1 1 REL9 BGT REL9 0 0 1 1 1 0 0 REL9 BLE REL9 0 0 1 1 1 0 1 REL9 BRA REL10 0 0 1 1 1 1 REL10 Load and Store Instructions LDB RD, (RB, #OFFS5) 0 1 0 0 0 RD RB OFFS5 LDW RD, (RB, #OFFS5) 0 1 0 0 1 RD RB OFFS5 STB RS, (RB, #OFFS5) 0 1 0 1 0 RS RB OFFS5 STW RS, (RB, #OFFS5) 0 1 0 1 1 RS RB OFFS5 LDB RD, (RB, RI) 0 1 1 0 0 RD RB RI 0 0 LDW RD, (RB, RI) 0 1 1 0 1 RD RB RI 0 0 STB RS, (RB, RI) 0 1 1 1 0 RS RB RI 0 0 STW RS, (RB, RI) 0 1 1 1 1 RS RB RI 0 0 LDB RD, (RB, RI+) 0 1 1 0 0 RD RB RI 0 1 LDW RD, (RB, RI+) 0 1 1 0 1 RD RB RI 0 1 STB RS, (RB, RI+) 0 1 1 1 0 RS RB RI 0 1 STW RS, (RB, RI+) 0 1 1 1 1 RS RB RI 0 1 LDB RD, (RB, –RI) 0 1 1 0 0 RD RB RI 1 0 LDW RD, (RB, –RI) 0 1 1 0 1 RD RB RI 1 0 STB RS, (RB, –RI) 0 1 1 1 0 RS RB RI 1 0 STW RS, (RB, –RI) 0 1 1 1 1 RS RB RI 1 0 Bit Field Instructions BFEXT RD, RS1, RS2 0 1 1 0 0 RD RS1 RS2 1 1 BFINS RD, RS1, RS2 0 1 1 0 1 RD RS1 RS2 1 1 BFINSI RD, RS1, RS2 0 1 1 1 0 RD RS1 RS2 1 1 BFINSX RD, RS1, RS2 0 1 1 1 1 RD RS1 RS2 1 1 Logic Immediate Instructions ANDL RD, #IMM8 1 0 0 0 0 RD IMM8 Table 5-17. Instruction Set Summary (Sheet 2 of 3) Functionality 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 317 ANDH RD, #IMM8 1 0 0 0 1 RD IMM8 BITL RD, #IMM8 1 0 0 1 0 RD IMM8 BITH RD, #IMM8 1 0 0 1 1 RD IMM8 ORL RD, #IMM8 1 0 1 0 0 RD IMM8 ORH RD, #IMM8 1 0 1 0 1 RD IMM8 XNORL RD, #IMM8 1 0 1 1 0 RD IMM8 XNORH RD, #IMM8 1 0 1 1 1 RD IMM8 Arithmetic Immediate Instructions SUBL RD, #IMM8 1 1 0 0 0 RD IMM8 SUBH RD, #IMM8 1 1 0 0 1 RD IMM8 CMPL RS, #IMM8 1 1 0 1 0 RS IMM8 CPCH RS, #IMM8 1 1 0 1 1 RS IMM8 ADDL RD, #IMM8 1 1 1 0 0 RD IMM8 ADDH RD, #IMM8 1 1 1 0 1 RD IMM8 LDL RD, #IMM8 1 1 1 1 0 RD IMM8 LDH RD, #IMM8 1 1 1 1 1 RD IMM8 Table 5-17. Instruction Set Summary (Sheet 3 of 3) Functionality 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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5.9 Initialization and Application Information

5.9.1 Initialization

The recommended initialization of the XGATE is as follows: 1. Clear the XGE bit to suppress any incoming service requests. 2. Make sure that no thread is running on the XGATE. This can be done in several ways: a) Poll the XGCHID register until it reads $00. Also poll XGDBG and XGSWEIF to make sure that the XGATE has not been stopped. b) Enter Debug Mode by setting the XGDBG bit. Clear the XGCHID register. Clear the XGDBG bit. The recommended method is a). 3. Set the XGVBR register to the lowest address of the XGATE vector space. 4. Clear all Channel ID flags. 5. Copy XGATE vectors and code into the RAM. 6. Initialize the S12X_INT module. 7. Enable the XGATE by setting the XGE bit. The following code example implements the XGATE initialization sequence. 5.9.2 Code Example (Transmit "Hello World!" on SCI) CPU S12X ;# SYMBOLS # SCI_REGS EQU $00C8 ;SCI register space SCIBDH EQU SCI_REGS+$00 ;SCI Baud Rate Register SCIBDL EQU SCI_REGS+$00 ;SCI Baud Rate Register SCICR2 EQU SCI_REGS+$03 ;SCI Control Register 2 SCISR1 EQU SCI_REGS+$04 ;SCI Status Register 1 SCIDRL EQU SCI_REGS+$07 ;SCI Control Register 2 TIE EQU $80 ;TIE bit mask TE EQU $08 ;TE bit mask RE EQU $04 ;RE bit mask SCI_VEC EQU $D6 ;SCI vector number INT_REGS EQU $0120 ;S12X_INT register space INT_CFADDR EQU INT_REGS+$07 ;Interrupt Configuration Address Register INT_CFDATA EQU INT_REGS+$08 ;Interrupt Configuration Data Registers RQST EQU $80 ;RQST bit mask XGATE_REGS EQU $0380 ;XGATE register space XGMCTL EQU XGATE_REGS+$00 ;XGATE Module Control Register XGMCTL_CLEAR EQU $FA02 ;Clear all XGMCTL bits XGMCTL_ENABLE EQU $8282 ;Enable XGATE XGCHID EQU XGATE_REGS+$02 ;XGATE Channel ID Register XGVBR EQU XGATE_REGS+$06 ;XGATE ISP Select Register XGIF EQU XGATE_REGS+$08 ;XGATE Interrupt Flag Vector

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 319 XGSWT EQU XGATE_REGS+$18 ;XGATE Software Trigger Register XGSEM EQU XGATE_REGS+$1A ;XGATE Semaphore Register RPAGE EQU $0016 RAM_SIZE EQU 32*$400 ;32k RAM RAM_START EQU $1000 RAM_START_XG EQU $10000-RAM_SIZE RAM_START_GLOB EQU $100000-RAM_SIZE XGATE_VECTORS EQU RAM_START XGATE_VECTORS_XG EQU RAM_START_XG XGATE_DATA EQU RAM_START+(4*128) XGATE_DATA_XG EQU RAM_START_XG+(4*128) XGATE_CODE EQU XGATE_DATA+(XGATE_CODE_FLASH-XGATE_DATA_FLASH) XGATE_CODE_XG EQU XGATE_DATA_XG+(XGATE_CODE_FLASH-XGATE_DATA_FLASH) BUS_FREQ_HZ EQU 40000000 ;# S12XE VECTOR TABLE # ORG $FF10 ;non-maskable interrupts DW DUMMY_ISR DUMMY_ISR DUMMY_ISR DUMMY_ISR ORG $FFF4 ;non-maskable interrupts DW DUMMY_ISR DUMMY_ISR DUMMY_ISR ;# DISABLE COP # ORG $FF0E DW $FFFE ORG $C000 START_OF_CODE ;# INITIALIZE S12XE CORE # SEI MOVB #(RAM_START_GLOB>>12), RPAGE;set RAM page ;# INITIALIZE SCI # INIT_SCI MOVW #(BUS_FREQ_HZ/(16*9600)), SCIBDH;set baud rate MOVB #(TIE|TE), SCICR2;enable tx buffer empty interrupt ;# INITIALIZE S12X_INT # INIT_INT MOVB #(SCI_VEC&$F0), INT_CFADDR ;switch SCI interrupts to XGATE MOVB #RQST|$01, INT_CFDATA+((SCI_VEC&$0F)>>1)

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;# INITIALIZE XGATE # INIT_XGATE MOVW #XGMCTL_CLEAR , XGMCTL;clear all XGMCTL bits INIT_XGATE_BUSY_LOOP TST XGCHID ;wait until current thread is finished BNE INIT_XGATE_BUSY_LOOP LDX #XGIF ;clear all channel interrupt flags LDD #$FFFF STD 2,X+ STD 2,X+ STD 2,X+ STD 2,X+ STD 2,X+ STD 2,X+ STD 2,X+ STD 2,X+ MOVW #XGATE_VECTORS_XG, XGVBR;set vector base register MOVW #$FF00, XGSWT ;clear all software triggers ;# INITIALIZE XGATE VECTOR TABLE # LDAA #128 ;build XGATE vector table LDY #XGATE_VECTORS INIT_XGATE_VECTAB_LOOP MOVW #XGATE_DUMMY_ISR_XG, 4,Y+ DBNE A, INIT_XGATE_VECTAB_LOOP MOVW #XGATE_CODE_XG, RAM_START+(2*SCI_VEC) MOVW #XGATE_DATA_XG, RAM_START+(2*SCI_VEC)+2 ;# COPY XGATE CODE # COPY_XGATE_CODE LDX #XGATE_DATA_FLASH COPY_XGATE_CODE_LOOP MOVW 2,X+, 2,Y+ MOVW 2,X+, 2,Y+ MOVW 2,X+, 2,Y+ MOVW 2,X+, 2,Y+ CPX #XGATE_CODE_FLASH_END BLS COPY_XGATE_CODE_LOOP ;# START XGATE # START_XGATE MOVW #XGMCTL_ENABLE, XGMCTL;enable XGATE BRA * ;# DUMMY INTERRUPT SERVICE ROUTINE # DUMMY_ISR RTI CPU XGATE

Chapter 5 XGATE (S12XGATEV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 321 ;# XGATE DATA # ALIGN1 XGATE_DATA_FLASH EQU * XGATE_DATA_SCI EQU *-XGATE_DATA_FLASH DW SCI_REGS ;pointer to SCI register space XGATE_DATA_IDX EQU *-XGATE_DATA_FLASH DB XGATE_DATA_MSG ;string pointer XGATE_DATA_MSG EQU *-XGATE_DATA_FLASH FCC "Hello World! ;ASCII string DB $0D ;CR ;# XGATE CODE # ALIGN1 XGATE_CODE_FLASH LDW R2,(R1,#XGATE_DATA_SCI);SCI -> R2 LDB R3,(R1,#XGATE_DATA_IDX);msg -> R3 LDB R4,(R1,R3+) ;curr. char -> R4 STB R3,(R1,#XGATE_DATA_IDX);R3 -> idx LDB R0,(R2,#(SCISR1-SCI_REGS));initiate SCI transmit STB R4,(R2,#(SCIDRL-SCI_REGS));initiate SCI transmit CMPL R4,#$0D BEQ XGATE_CODE_DONE RTS XGATE_CODE_DONE LDL R4,#$00 ;disable SCI interrupts STB R4,(R2,#(SCICR2-SCI_REGS)) LDL R3,#XGATE_DATA_MSG;reset R3 STB R3,(R1,#XGATE_DATA_IDX) XGATE_CODE_FLASH_END RTS XGATE_DUMMY_ISR_XG EQU (XGATE_CODE_FLASH_END-XGATE_CODE_FLASH)+XGATE_CODE_XG

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MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 323 Chapter 6 Security (S12X9SECV2)

6.1 Introduction

This specification describes the function of the security mechanism in the S12XD chip family (9SEC). NOTE No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH and/or EEPROM difficult for unauthorized users.

6.1.1 Features

The user must be reminded that part of the security must lie with the application code. An extreme example would be application code that dumps the contents of the internal memory. This would defeat the purpose of security. At the same time, the user may also wish to put a backdoor in the application program. An example of this is the user downloads a security key through the SCI, which allows access to a programming routine that updates parameters stored in another section of the Flash memory. The security features of the S12X chip family (in secure mode) are:

• Protect the content of non-volatile memories (Flash, EEPROM)
• Execution of NVM commands is restricted
• Disable access to internal memory via background debug module (BDM)
• Disable access to internal Flash/EEPROM in expanded modes
• Disable debugging features for the CPU and XGATE

6.1.2 Modes of Operation

Table 6-2 gives an overview over availability of security relevant features in unsecure and secure modes. Table 6-1. Revision History Revision Number Revision Date Sections Affected Description of Changes 02.00 27 Aug 2004 reviewed and updated for S12XD architecture 02.01 21 Feb 2007 added S12XE, S12XF and S12XS architectures 02.02 19 Apr 2007 corrected statement about Backdoor key access via BDM on XE, XF , XS

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6.1.3 Securing the Microcontroller

Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the security bits located in the options/security byte in the Flash memory array. These non-volatile bits will keep the device secured through reset and power-down. The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this byte are copied into the Flash security register (FSEC) during a reset sequence. The meaning of the bits KEYEN[1:0] is shown in Table 6-3. Please refer to Section 6.1.5.1, “Unsecuring the MCU Using the Backdoor Key Access” for more information. Table 6-2. Feature Availability in Unsecure and Secure Modes on S12XD Unsecure Mode Secure Mode NS SS NX ES EX ST NS SS NX ES EX ST Flash Array Access ✔✔ ✔ (1) 1. Availability of Flash arrays in the memory map depends on ROMCTL/EROMCTL pins and/or the state of the ROMON/EROMON bits in the MMCCTL1 register. Please refer to the S12X_MMC block guide for detailed information. NVM Commands ✔(2) 2. Restricted NVM command set only. Please refer to the NVM wrapper block guides for detailed information. 3. BDM hardware commands restricted to peripheral registers only. ———— Internal status visible multiplexed on external bus Internal accesses visible on external bus 76543210 0xFF0F KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0 Figure 6-1. Flash Options/Security Byte

Chapter 6 Security (S12X9SECV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 325 The meaning of the security bits SEC[1:0] is shown inTable 6-4. For security reasons, the state of device security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’. NOTE Please refer to the Flash block guide for actual security configuration (in section “Flash Module Security”).

6.1.4 Operation of the Secured Microcontroller

By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented. However, it must be understood that the security of the EEPROM and Flash memory contents also depends on the design of the application program. For example, if the application has the capability of downloading code through a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the EEPROM and Flash memory contents even when the microcontroller is in the secure state. In this example, the security of the application could be enhanced by requiring a challenge/response authentication before any code can be downloaded. Secured operation has the following effects on the microcontroller:

6.1.4.1 Normal Single Chip Mode (NS)

• Background debug module (BDM) operation is completely disabled.
• Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details.
• Tracing code execution using the DBG module is disabled.
• Debugging XGATE code (breakpoints, single-stepping) is disabled. Table 6-3. Backdoor Key Access Enable Bits KEYEN[1:0] Backdoor Key Access Enabled 00 0 (disabled) 01 0 (disabled) 10 1 (enabled) 11 0 (disabled) Table 6-4. Security Bits SEC[1:0] Security State 00 1 (secured) 01 1 (secured) 10 0 (unsecured) 11 1 (secured)

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6.1.4.2 Special Single Chip Mode (SS)

• BDM firmware commands are disabled.
• BDM hardware commands are restricted to the register space.
• Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details.
• Tracing code execution using the DBG module is disabled.
• Debugging XGATE code (breakpoints, single-stepping) is disabled. Special single chip mode means BDM is active after reset. The availability of BDM firmware commands depends on the security state of the device. The BDM secure firmware first performs a blank check of both the Flash memory and the EEPROM. If the blank check succeeds, security will be temporarily turned off and the state of the security bits in the appropriate Flash memory location can be changed If the blank check fails, security will remain active, only the BDM hardware commands will be enabled, and the accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used to erase the EEPROM and Flash memory without giving access to their contents. After erasing both Flash memory and EEPROM, another reset into special single chip mode will cause the blank check to succeed and the options/security byte can be programmed to “unsecured” state via BDM. While the BDM is executing the blank check, the BDM interface is completely blocked, which means that all BDM commands are temporarily blocked.

6.1.4.3 Expanded Modes (NX, ES, EX, and ST)

• BDM operation is completely disabled.
• Internal Flash memory and EEPROM are disabled.
• Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details.
• Tracing code execution using the DBG module is disabled.
• Debugging XGATE code (breakpoints, single-stepping) is disabled

6.1.5 Unsecuring the Microcontroller

Unsecuring the microcontroller can be done by three different methods: 1. Backdoor key access 2. Reprogramming the security bits 3. Complete memory erase (special modes)

6.1.5.1 Unsecuring the MCU Using the Backdoor Key Access

In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method. This method requires that:

• The backdoor key at 0xFF00–0xFF07 (= global addresses 0x7F_FF00–0x7F_FF07) has been programmed to a valid value.

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• The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’.
• In single chip mode, the application program programmed into the microcontroller must be designed to have the capability to write to the backdoor key locations. The backdoor key values themselves would not normally be stored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g. through a serial port). It is not possible to download the backdoor keys using background debug mode. The backdoor key access method allows debugging of a secured microcontroller without having to erase the Flash. This is particularly useful for failure analysis. NOTE No word of the backdoor key is allowed to have the value 0x0000 or 0xFFFF.

6.1.5.2 Backdoor Key Access Sequence

These are the necessary steps for a successful backdoor key access sequence: 1. Set the KEY ACC bit in the Flash configuration register FCNFG. 2. Write the first 16-bit word of the backdoor key to 0xFF00 (0x7F_FF00). 3. Write the second 16-bit word of the backdoor key to 0xFF02 (0x7F_FF02). 4. Write the third 16-bit word of the backdoor key to 0xFF04 (0x7F_FF04). 5. Write the fourth 16-bit word of the backdoor key to 0xFF06 (0x7F_FF06). 6. Clear the KEY ACC bit in the Flash Configuration register FCNFG. NOTE Flash cannot be read while KEY ACC is set. Therefore the code for the backdoor key access sequence must execute from RAM. If all four 16-bit words match the Flash contents at 0xFF00–0xFF07 (0x7F_FF00–0x7F_FF07), the microcontroller will be unsecured and the security bits SEC[1:0] in the Flash Security register FSEC will be forced to the unsecured state (‘10’). The contents of the Flash options/security byte are not changed by this procedure, and so the microcontroller will revert to the secure state after the next reset unless further action is taken as detailed below. If any of the four 16-bit words does not match the Flash contents at 0xFF00–0xFF07 (0x7F_FF00–0x7F_FF07), the microcontroller will remain secured.

6.1.6 Reprogramming the Security Bits

In normal single chip mode (NS), security can also be disabled by erasing and reprogramming the security bits within Flash options/security byte to the unsecured value. Because the erase operation will erase the entire sector from 0xFE00–0xFFFF (0x7F_FE00–0x7F_FFFF), the backdoor key and the interrupt vectors will also be erased; this method is not recommended for normal single chip mode. The application software can only erase and program the Flash options/security byte if the Flash sector containing the Flash

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options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of preventing this method. The microcontroller will enter the unsecured state after the next reset following the programming of the security bits to the unsecured value. This method requires that:

• The application software previously programmed into the microcontroller has been designed to have the capability to erase and program the Flash options/security byte, or security is first disabled using the backdoor key method, allowing BDM to be used to issue commands to erase and program the Flash options/security byte.
• The Flash sector containing the Flash options/security byte is not protected.

6.1.7 Complete Memory Erase (Special Modes)

The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory contents. When a secure microcontroller is reset into special single chip mode (SS), the BDM firmware verifies whether the EEPROM and Flash memory are erased. If any EEPROM or Flash memory address is not erased, only BDM hardware commands are enabled. BDM hardware commands can then be used to write to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks. When next reset into special single chip mode, the BDM firmware will again verify whether all EEPROM and Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash security register will indicate the unsecure state following the next reset.

Chapter 6 Security (S12X9SECV2) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 329 Special single chip erase and unsecure sequence: 1. Reset into special single chip mode. 2. Write an appropriate value to the ECLKDIV register for correct timing. 3. Write 0xFF to the EPROT register to disable protection. 4. Write 0x30 to the ESTAT register to clear the PVIOL and ACCERR bits. 5. Write 0x0000 to the EDATA register (0x011A–0x011B). 6. Write 0x0000 to the EADDR register (0x0118–0x0119). 7. Write 0x41 (mass erase) to the ECMD register. 8. Write 0x80 to the ESTAT register to clear CBEIF. 9. Write an appropriate value to the FCLKDIV register for correct timing. 10. Write 0x00 to the FCNFG register to select Flash block 0. 11. Write 0x10 to the FTSTMOD register (0x0102) to set the WRALL bit, so the following writes affect all Flash blocks. 12. Write 0xFF to the FPROT register to disable protection. 13. Write 0x30 to the FSTAT register to clear the PVIOL and ACCERR bits. 14. Write 0x0000 to the FDATA register (0x010A–0x010B). 15. Write 0x0000 to the FADDR register (0x0108–0x0109). 16. Write 0x41 (mass erase) to the FCMD register. 17. Write 0x80 to the FSTAT register to clear CBEIF. 18. Wait until all CCIF flags are set. 19. Reset back into special single chip mode. 20. Write an appropriate value to the FCLKDIV register for correct timing. 21. Write 0x00 to the FCNFG register to select Flash block 0. 22. Write 0xFF to the FPROT register to disable protection. 23. Write 0xFFBE to Flash address 0xFF0E. 24. Write 0x20 (program) to the FCMD register. 25. Write 0x80 to the FSTAT register to clear CBEIF. 26. Wait until the CCIF flag in FSTAT is are set. 27. Reset into any mode.

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MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 331 Chapter 7 Clocks and Reset Generator (S12CRGV6)

7.1 Introduction

This specification describes the function of the clocks and reset generator (CRG).

7.1.1 Features

The main features of this block are:

• Phase locked loop (PLL) frequency multiplier — Reference divider — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — Interrupt request on entry or exit from locked condition — Self clock mode in absence of reference clock
• System clock generator — Clock quality check — User selectable fast wake-up from Stop in self-clock mode for power saving and immediate program execution — Clock switch for either oscillator or PLL based system clocks
• Computer operating properly (COP) watchdog timer with time-out clear window
• System reset generation from the following possible sources: — Power on reset — Low voltage reset — Illegal address reset — COP reset — Loss of clock reset — External pin reset
• Real-time interrupt (RTI)

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7.1.2 Modes of Operation

This subsection lists and briefly describes all operating modes supported by the CRG.

• Run mode All functional parts of the CRG are running during normal run mode. If RTI or COP functionality is required, the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be set to a nonzero value.
• Wait mode In this mode, the PLL can be disabled automatically depending on the PLLSEL bit in the CLKSEL register.
• Stop mode Depending on the setting of the PSTP bit, stop mode can be differentiated between full stop mode (PSTP = 0) and pseudo stop mode (PSTP = 1). — Full stop mode The oscillator is disabled and thus all system and core clocks are stopped. The COP and the RTI remain frozen. — Pseudo stop mode The oscillator continues to run and most of the system and core clocks are stopped. If the respective enable bits are set, the COP and RTI will continue to run, or else they remain frozen.
• Self clock mode Self clock mode will be entered if the clock monitor enable bit (CME) and the self clock mode enable bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of clock. As soon as self clock mode is entered, the CRG starts to perform a clock quality check. Self clock mode remains active until the clock quality check indicates that the required quality of the incoming clock signal is met (frequency and amplitude). Self clock mode should be used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions.

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7.1.3 Block Diagram

Figure 7-1 shows a block diagram of the CRG. Figure 7-1. CRG Block Diagram CRG Registers Clock and Reset COP RESET RTI PLL XFC VDDPLL VSSPLL OscillatorEXTAL XTAL Control Bus Clock System Reset Oscillator Clock PLLCLK OSCCLK Core Clock CM fail Clock Quality Checker Reset Generator XCLKS Power on Reset Low Voltage Reset COP Timeout Real Time Interrupt PLL Lock Interrupt Self Clock Mode Interrupt Voltage Regulator S12X_MMC Illegal Address Reset Clock Monitor

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7.2 External Signal Description

This section lists and describes the signals that connect off chip.

7.2.1 V DDPLL and VSSPLL — Operating and Ground Voltage Pins

These pins provide operating voltage (VDDPLL) and ground (VSSPLL) for the PLL circuitry. This allows the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required, VDDPLL and VSSPLL must be connected to properly.

7.2.2 XFC — External Loop Filter Pin

A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter that eliminates the VCO input ripple. The value of the external filter network and the reference frequency determines the speed of the corrections and the stability of the PLL. Refer to the device specification for calculation of PLL Loop Filter (XFC) components. If PLL usage is not required, the XFC pin must be tied to V DDPLL. Figure 7-2. PLL Loop Filter Connections

7.2.3 RESET — Reset Pin

RESET is an active low bidirectional reset pin. As an input. it initializes the MCU asynchronously to a known start-up state. As an open-drain output, it indicates that a system reset (internal to the MCU) has been triggered.

7.3 Memory Map and Register Definition

This section provides a detailed description of all registers accessible in the CRG. MCU XFC RS CS VDDPLL CP

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7.3.1 Module Memory Map

Table 7-1 gives an overview on all CRG registers. NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. Table 7-1. CRG Memory Map Address Offset Use Access 0x_00 CRG Synthesizer Register (SYNR) R/W 0x_01 CRG Reference Divider Register (REFDV) R/W 0x_02 CRG Test Flags Register (CTFLG)1 1 CTFLG is intended for factory test purposes only. R/W 0x_03 CRG Flags Register (CRGFLG) R/W 0x_04 CRG Interrupt Enable Register (CRGINT) R/W 0x_05 CRG Clock Select Register (CLKSEL) R/W 0x_06 CRG PLL Control Register (PLLCTL) R/W 0x_07 CRG RTI Control Register (RTICTL) R/W 0x_08 CRG COP Control Register (COPCTL) R/W 0x_09 CRG Force and Bypass Test Register (FORBYP)2 2 FORBYP is intended for factory test purposes only. R/W 0x_0A CRG Test Control Register (CTCTL)3 3 CTCTL is intended for factory test purposes only. R/W 0x_0B CRG COP Arm/Timer Reset (ARMCOP) R/W

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7.3.2 Register Descriptions

This section describes in address order all the CRG registers and their individual bits. Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x_00 SYNR R0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 W 0x_01 REFDV R0 0 REFDV5 REFDV4 REFDV3 REFDV2 REFDV1 REFDV0 W 0x_02 CTFLG R 00000000 W 0x_03 CRGFLG R RTIF PORF LVRF LOCKIF LOCK TRACK SCMIF SCM W 0x_04 CRGINT R RTIE ILAF LOCKIE SCMIE W 0x_05 CLKSEL R PLLSEL PSTP PLLWAI RTIWAI COPWAI W 0x_06 PLLCTL R CME PLLON AUTO ACQ FSTWKP PRE PCE SCME W 0x_07 RTICTL R RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 W 0x_08 COPCTL R WCOP RSBCK 000 CR2 CR1 CR0 W WRTMASK 0x_09 FORBYP R 00000000 W 0x_0A CTCTL R 10000000 W 0x_0B ARMCOP R 00000000 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 = Unimplemented or Reserved Figure 7-3. S12CRGV6 Register Summary

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7.3.2.1 CRG Synthesizer Register (SYNR)

The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency by 2 x (SYNR + 1). PLLCLK will not be below the minimum VCO frequency (f SCM). NOTE If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2 Bus Clock must not exceed the maximum operating system frequency. Read: Anytime Write: Anytime except if PLLSEL = 1 NOTE Write to this register initializes the lock detector bit and the track detector bit.

7.3.2.2 CRG Reference Divider Register (REFDV)

The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference divider divides OSCCLK frequency by REFDV + 1. Read: Anytime Write: Anytime except when PLLSEL = 1 Module Base +0x_00 76543210 R0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 7-4. CRG Synthesizer Register (SYNR) Module Base +0x_01 76543210 R0 0 REFDV5 REFDV4 REFDV3 REFDV2 REFDV1 REFDV0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 7-5. CRG Reference Divider Register (REFDV) PLLCLK 2xOSCCLKx SYNR 1+()

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Write to this register initializes the lock detector bit and the track detector bit.

7.3.2.3 Reserved Register (CTFLG)

This register is reserved for factory testing of the CRG module and is not available in normal modes. Read: Always reads 0x_00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this register when in special mode can alter the CRG fucntionality.

7.3.2.4 CRG Flags Register (CRGFLG)

This register provides CRG status bits and flags. Read: Anytime Write: Refer to each bit for individual write conditions Module Base +0x_02 76543210 R 00000000 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 7-6. Reserved Register (CTFLG) Module Base +0x_03 76543210 R RTIF PORF LVRF LOCKIF LOCK TRACK SCMIF SCM W Reset 0 12 00000 1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset. 2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset. = Unimplemented or Reserved Figure 7-7. CRG Flags Register (CRGFLG)

Chapter 7 Clocks and Reset Generator (S12CRGV6) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 339 Table 7-2. CRGFLG Field Descriptions Field Description RTIF Real Time Interrupt Flag— RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred. PORF Power on Reset Flag— PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Power on reset has not occurred. 1 Power on reset has occurred. LVRF Low Voltage Reset Flag— If low voltage reset feature is not available (see device specification) LVRF always reads 0. LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Low voltage reset has not occurred. 1 Low voltage reset has occurred. LOCKIF PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE = 1), LOCKIF causes an interrupt request. 0 No change in LOCK bit. 1 LOCK bit has changed. LOCK Lock Status Bit — LOCK reflects the current state of PLL lock condition. This bit is cleared in self clock mode. Writes have no effect. 0 PLL VCO is not within the desired tolerance of the target frequency. 1 PLL VCO is within the desired tolerance of the target frequency. TRACK Track Status Bit — TRACK reflects the current state of PLL track condition. This bit is cleared in self clock mode. Writes have no effect. 0 Acquisition mode status. 1Tracking mode status. SCMIF Self Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE = 1), SCMIF causes an interrupt request. 0 No change in SCM bit. 1 SCM bit has changed. SCM Self Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect. 0 MCU is operating normally with OSCCLK available. 1 MCU is operating in self clock mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK running at its minimum frequency f SCM.

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7.3.2.5 CRG Interrupt Enable Register (CRGINT)

This register enables CRG interrupt requests. Read: Anytime Write: Anytime Module Base +0x_04 76543210 R RTIE ILAF LOCKIE SCMIE W Reset 0 1 000000 1. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset. = Unimplemented or Reserved Figure 7-8. CRG Interrupt Enable Register (CRGINT) Table 7-3. CRGINT Field Descriptions Field Description RTIE Real Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. ILAF Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to S12XMMC Block Guide for details. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Illegal address reset has not occurred. 1 Illegal address reset has occurred. LOCKIE Lock Interrupt Enable Bit 0 LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. SCMIE Self Clock Mode Interrupt Enable Bit 0 SCM interrupt requests are disabled. 1 Interrupt will be requested whenever SCMIF is set.

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7.3.2.6 CRG Clock Select Register (CLKSEL)

This register controls CRG clock selection. Refer to Figure 7-17 for more details on the effect of each bit. Read: Anytime Write: Refer to each bit for individual write conditions Module Base +0x_05 76543210 R PLLSEL PSTP PLLWAI RTIWAI COPWAI W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 7-9. CRG Clock Select Register (CLKSEL) Table 7-4. CLKSEL Field Descriptions Field Description PLLSEL PLL Select Bit — Write anytime. Writing a1 when LOCK = 0 and AUTO = 1, or TRACK = 0 and AUTO = 0 has no effect This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU enters self clock mode, Stop mode or wait mode with PLLWAI bit set. It is recommended to read back the PLLSEL bit to make sure PLLCLK has really been selected as SYSCLK, as LOCK status bit could theoretically change at the very moment writing the PLLSEL bit.

0 System clocks are derived from OSCCLK (f

BUS = fOSC / 2). 1 System clocks are derived from PLLCLK (f BUS = fPLL / 2). PSTP Pseudo Stop Bit Write: Anytime This bit controls the functionality of the oscillator during stop mode. 0 Oscillator is disabled in stop mode. 1 Oscillator continues to run in stop mode (pseudo stop). Note: Pseudo stop mode allows for faster STOP recovery and reduces the mechanical stress and aging of the resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption. PLLWAI PLL Stops in Wait Mode Bit Write: Anytime If PLLWAI is set, the CRG will clear the PLLSEL bit before entering wait mode. The PLLON bit remains set during wait mode, but the PLL is powered down. Upon exiting wait mode, the PLLSEL bit has to be set manually if PLL clock is required. While the PLLWAI bit is set, the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected target frequency after exiting wait mode. 0 PLL keeps running in wait mode. 1 PLL stops in wait mode. RTIWAI RTI Stops in Wait Mode Bit Write: Anytime 0 RTI keeps running in wait mode. 1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode. COPWAI COP Stops in Wait Mode Bit Normal modes: Write once Special modes: Write anytime 0 COP keeps running in wait mode. 1 COP stops and initializes the COP counter whenever the part goes into wait mode.

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7.3.2.7 CRG PLL Control Register (PLLCTL)

This register controls the PLL functionality. Read: Anytime Write: Refer to each bit for individual write conditions Module Base +0x_06 76543210 R CME PLLON AUTO ACQ FSTWKP PRE PCE SCME W Reset 1 1 1 10001 Figure 7-10. CRG PLL Control Register (PLLCTL) Table 7-5. PLLCTL Field Descriptions Field Description CME Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1. 0 Clock monitor is disabled. 1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self clock mode. Note: Operating with CME = 0 will not detect any loss of clock. In case of poor clock quality, this could cause unpredictable operation of the MCU! Note: In stop mode (PSTP = 0) the clock monitor is disabled independently of the CME bit setting and any loss of external clock will not be detected. Also after wake-up from stop mode (PSTP = 0) with fast wake-up enabled (FSTWKP = 1) the clock monitor is disabled independently of the CME bit setting and any loss of external clock will not be detected. PLLON Phase Lock Loop On Bit— PLLON turns on the PLL circuitry. In self clock mode, the PLL is turned on, but the PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1. 0 PLL is turned off. 1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically. AUTO Automatic Bandwidth Control Bit — AUTO selects either the high bandwidth (acquisition) mode or the low bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write anytime except when PLLWAI = 1, because PLLWAI sets the AUTO bit to 1. 0 Automatic mode control is disabled and the PLL is under software control, using ACQ bit. 1 Automatic mode control is enabled and ACQ bit has no effect. ACQ Acquisition Bit Write anytime. If AUTO=1 this bit has no effect. 0 Low bandwidth filter is selected. 1 High bandwidth filter is selected. FSTWKP Fast Wake-up from Full Stop Bit — FSTWKP enables fast wake-up from full stop mode. Write anytime. If self-clock mode is disabled (SCME = 0) this bit has no effect. 0 Fast wake-up from full stop mode is disabled. 1 Fast wake-up from full stop mode is enabled. When waking up from full stop mode the system will immediately resume operation i self-clock mode (see mode with oscillator and clock monitor disabled until FSTWKP bit is cleared. The clearing of FSTWKP will start the oscillator, the clock monitor and the clock quality check. If the clock quality check is successful, the CRG will switch all system clocks to OSCCLK. The SCMIF flag will be set. See application examples in Figure 7-23 and Figure 7-24.

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7.3.2.8 CRG RTI Control Register (RTICTL)

This register selects the timeout period for the real time interrupt. Read: Anytime Write: Anytime NOTE A write to this register initializes the RTI counter. PRE RTI Enable during Pseudo Stop Bit — PRE enables the RTI during pseudo stop mode. Write anytime. 0 RTI stops running during pseudo stop mode. 1 RTI continues running during pseudo stop mode. Note: If the PRE bit is cleared the RTI dividers will go static while pseudo stop mode is active. The RTI dividers will not initialize like in wait mode with RTIWAI bit set. PCE COP Enable during Pseudo Stop Bit — PCE enables the COP during pseudo stop mode. Write anytime.

0 COP stops running during pseudo stop mode

1 COP continues running during pseudo stop mode

Note: If the PCE bit is cleared, the COP dividers will go static while pseudo stop mode is active. The COP dividers will not initialize like in wait mode with COPWAI bit set. SCME Self Clock Mode Enable Bit Normal modes: Write once Special modes: Write anytime SCME can not be cleared while operating in self clock mode (SCM = 1). 0 Detection of crystal clock failure causes clock monitor reset (see Section 7.5.2, “Clock Monitor Reset”). 1 Detection of crystal clock failure forces the MCU in self clock mode (see Section 7.4.2.2, “Self Clock Mode”). Module Base +0x_07 76543210 R RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 W Reset 0 0 0 00000 Figure 7-11. CRG RTI Control Register (RTICTL) Table 7-6. RTICTL Field Descriptions Field Description RTDEC Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values. 0 Binary based divider value. See Table 7-7 1 Decimal based divider value. See Table 7-8 6–4 RTR[6:4] Real Time Interrupt Prescale Rate Select Bits— These bits select the prescale rate for the RTI. SeeTable 7-7 and Table 7-8. 3–0 RTR[3:0] Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to provide additional granularity.Table 7-7and Table 7-8show all possible divide values selectable by the RTICTL register. The source clock for the RTI is OSCCLK. Table 7-5. PLLCTL Field Descriptions (continued) Field Description

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Table 7-7. RTI Frequency Divide Rates for RTDEC = 0 RTR[3:0] RTR[6:4] = 000 (OFF) 001 (210) 010 (211) 011 (212) 100 (213) 101 (214) 110 (215) 111 (216) 0000 (÷1) OFF* 210 211 212 213 214 215 216 0001 (÷2) OFF 2x2 10 2x211 2x212 2x213 2x214 2x215 2x216 0010 (÷3) OFF 3x2 10 3x211 3x212 3x213 3x214 3x215 3x216 0011 (÷4) OFF 4x2 10 4x211 4x212 4x213 4x214 4x215 4x216 0100 (÷5) OFF 5x2 10 5x211 5x212 5x213 5x214 5x215 5x216 0101 (÷6) OFF 6x2 10 6x211 6x212 6x213 6x214 6x215 6x216 0110 (÷7) OFF 7x2 10 7x211 7x212 7x213 7x214 7x215 7x216 0111 (÷8) OFF 8x2 10 8x211 8x212 8x213 8x214 8x215 8x216 1000 (÷9) OFF 9x2 10 9x211 9x212 9x213 9x214 9x215 9x216 1001 (÷10) OFF 10x2 10 10x211 10x212 10x213 10x214 10x215 10x216 1010 (÷11) OFF 11x2 10 11x211 11x212 11x213 11x214 11x215 11x216 1011 (÷12) OFF 12x2 10 12x211 12x212 12x213 12x214 12x215 12x216 1100 (÷13) OFF 13x2 10 13x211 13x212 13x213 13x214 13x215 13x216 1101 (÷14) OFF 14x2 10 14x211 14x212 14x213 14x214 14x215 14x216 1110 (÷15) OFF 15x2 10 15x211 15x212 15x213 15x214 15x215 15x216 1111 (÷16) OFF 16x2 10 16x211 16x212 16x213 16x214 16x215 16x216 * Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.

Chapter 7 Clocks and Reset Generator (S12CRGV6) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 345 Table 7-8. RTI Frequency Divide Rates for RTDEC = 1 RTR[3:0] RTR[6:4] = 000 (1x103) 001 (2x103) 010 (5x103) 011 (10x103) 100 (20x103) 101 (50x103) 110 (100x103) 111 (200x103) 0000 (÷1) 1x103 2x103 5x103 10x103 20x103 50x103 100x103 200x103 0001 (÷2) 2x103 4x103 10x103 20x103 40x103 100x103 200x103 400x103 0010 (÷3) 3x103 6x103 15x103 30x103 60x103 150x103 300x103 600x103 0011 (÷4) 4x103 8x103 20x103 40x103 80x103 200x103 400x103 800x103 0100 (÷5) 5x103 10x103 25x103 50x103 100x103 250x103 500x103 1x106 0101 (÷6) 6x103 12x103 30x103 60x103 120x103 300x103 600x103 1.2x106 0110 (÷7) 7x103 14x103 35x103 70x103 140x103 350x103 700x103 1.4x106 0111 (÷8) 8x103 16x103 40x103 80x103 160x103 400x103 800x103 1.6x106 1000 (÷9) 9x103 18x103 45x103 90x103 180x103 450x103 900x103 1.8x106 1001 (÷10) 10 x103 20x103 50x103 100x103 200x103 500x103 1x106 2x106 1010 (÷11) 11 x103 22x103 55x103 110x103 220x103 550x103 1.1x106 2.2x106 1011 (÷12) 12x103 24x103 60x103 120x103 240x103 600x103 1.2x106 2.4x106 1100 (÷13) 13x103 26x103 65x103 130x103 260x103 650x103 1.3x106 2.6x106 1101 (÷14) 14x103 28x103 70x103 140x103 280x103 700x103 1.4x106 2.8x106 1110 (÷15) 15x103 30x103 75x103 150x103 300x103 750x103 1.5x106 3x106 1111 (÷16) 16x103 32x103 80x103 160x103 320x103 800x103 1.6x106 3.2x106

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7.3.2.9 CRG COP Control Register (COPCTL)

This register controls the COP (computer operating properly) watchdog. Read: Anytime Write: 1. RSBCK: Anytime in special modes; write to “1” but not to “0” in all other modes 2. WCOP, CR2, CR1, CR0: — Anytime in special modes — Write once in all other modes Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition. Writing WCOP to “0” has no effect, but counts for the “write once” condition. The COP time-out period is restarted if one these two conditions is true: 1. Writing a nonzero value to CR[2:0] (anytime in special modes, once in all other modes) with WRTMASK = 0. or 2. Changing RSBCK bit from “0” to “1”. Module Base +0x_08 76543210 R WCOP RSBCK 000 CR2 CR1 CR0 W WRTMASK Reset1 0000 1. Refer to Device User Guide (Section: CRG) for reset values of WCOP , CR2, CR1, and CR0. = Unimplemented or Reserved Figure 7-12. CRG COP Control Register (COPCTL) Table 7-9. COPCTL Field Descriptions Field Description WCOP Window COP Mode Bit— When set, a write to the ARMCOP register must occur in the last 25% of the selected period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during this window, 0x_55 can be written as often as desired. Once 0x_AA is written after the 0x_55, the time-out logic restarts and the user must wait until the next window before writing to ARMCOP.Table 7-10shows the duration of this window for the seven available COP rates.

0 Normal COP operation

1 Window COP operation

COP and RTI Stop in Active BDM Mode Bit 0 Allows the COP and RTI to keep running in active BDM mode. 1 Stops the COP and RTI counters whenever the part is in active BDM mode.

Chapter 7 Clocks and Reset Generator (S12CRGV6) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 347 WRTMASK Write Mask for WCOP and CR[2:0] Bit— This write-only bit serves as a mask for the WCOP and CR[2:0] bits while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of WCOP and CR[2:0].

0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL

1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL. (Does not count for “write once”.) 2–0 CR[1:0] COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 7-10). The COP time-out period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out causes a system reset. This can be avoided by periodically (before time-out) reinitializing the COP counter via the ARMCOP register. While all of the following three conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at highest time-out period ( 2 24 cycles) in normal COP mode (Window COP mode disabled): 1) COP is enabled (CR[2:0] is not 000) 2) BDM mode active 3) RSBCK = 0 4) Operation in emulation or special modes Table 7-10. COP Watchdog Rates1

1 OSCCLK cycles are referenced from the previous COP time-out reset

(writing 0x_55/0x_AA to the ARMCOP register) CR2 CR1 CR0 OSCCLK Cycles to Time-out 0 0 0 COP disabled 001 2 010 2 16 011 2 18 100 2 20 101 2 22 110 2 23 111 2 24 Table 7-9. COPCTL Field Descriptions (continued) Field Description

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7.3.2.10 Reserved Register (FORBYP)

This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special modes can alter the CRG’s functionality. Read: Always read 0x_00 except in special modes Write: Only in special modes

7.3.2.11 Reserved Register (CTCTL)

This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special test modes can alter the CRG’s functionality. Read: always read 0x_80 except in special modes Write: only in special modes Module Base +0x_09 76543210 R 00000000 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 7-13. Reserved Register (FORBYP) Module Base +0x_0A 76543210 R 10000000 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 7-14. Reserved Register (CTCTL)

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7.3.2.12 CRG COP Timer Arm/Reset Register (ARMCOP)

This register is used to restart the COP time-out period. Read: Always reads 0x_00 Write: Anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect. When the COP is enabled by setting CR[2:0] nonzero, the following applies: Writing any value other than 0x_55 or 0x_AA causes a COP reset. To restart the COP time-out period you must write 0x_55 followed by a write of 0x_AA. Other instructions may be executed between these writes but the sequence (0x_55, 0x_AA) must be completed prior to COP end of time-out period to avoid a COP reset. Sequences of 0x_55 writes or sequences of 0x_AA writes are allowed. When the WCOP bit is set, 0x_55 and 0x_AA writes must be done in the last 25% of the selected time-out period; writing any value in the first 75% of the selected period will cause a COP reset. Module Base +0x_0B 76543210 R 00000000 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 0 0 0 00000 Figure 7-15. ARMCOP Register Diagram

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7.4 Functional Description

7.4.1 Functional Blocks

7.4.1.1 Phase Locked Loop (PLL)

The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,... 126,128 based on the SYNR register. CAUTION Although it is possible to set the two dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the MCU. If (PLLSEL = 1), Bus Clock = PLLCLK / 2 The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on the difference between the output frequency and the target frequency. The PLL can change between acquisition and tracking modes either automatically or manually. The VCO has a minimum operating frequency, which corresponds to the self clock mode frequency f SCM. Figure 7-16. PLL Functional Diagram PLLCLK 2 OSCCLK SYNR 1+[] REDUCED CONSUMPTION OSCILLATOR EXTAL XTAL OSCCLK PLLCLK REFERENCE PROGRAMMABLE DIVIDER PDET PHASE DETECTOR REFDV <5:0> LOOP PROGRAMMABLE DIVIDER SYN <5:0> CPUMP VCO LOCK LOOP FILTER XFC PIN UP DOWN LOCK DETECTOR REFERENCE FEEDBACK VDDPLL VDDPLL/VSSPLL CRYSTAL MONITOR VDDPLL/VSSPLL VDD/VSS supplied by:

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7.4.1.1.1 PLL Operation

The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is divided in a range of 1 to 64 (REFDV + 1) to output the REFERENCE clock. The VCO output clock, (PLLCLK) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2 x (SYNR + 1)] to output the FEEDBACK clock. Figure 7-16. The phase detector then compares the FEEDBACK clock, with the REFERENCE clock. Correction pulses are generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external filter capacitor connected to XFC pin, based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, as described in the next subsection. The values of the external filter network and the reference frequency determine the speed of the corrections and the stability of the PLL. The minimum VCO frequency is reached with the XFC pin forced to V DDPLL. This is the self clock mode frequency.

7.4.1.1.2 Acquisition and Tracking Modes

The lock detector compares the frequencies of the FEEDBACK clock, and the REFERENCE clock. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison. The PLL filter can be manually or automatically configured into one of two possible operating modes:

• Acquisition mode In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start-up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the TRACK status bit is cleared in the CRGFLG register.
• Tracking mode In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct and the TRACK bit is set in the CRGFLG register. The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the PLL clock (PLLCLK) is safe to use as the source for the system and core clocks. If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during PLL start-up, usually) or at periodic intervals. In either case, only when the LOCK bit is set, is the PLLCLK clock safe to use as the source for the system and core clocks. If the PLL is selected as the source for the system and core clocks and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application.

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The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO = 1):

• The TRACK bit is a read-only indicator of the mode of the filter.
• The TRACK bit is set when the VCO frequency is within a certain tolerance,∆trk, and is clear when the VCO frequency is out of a certain tolerance, ∆unt.
• The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆ Lock, and is cleared when the VCO frequency is out of a certain tolerance, ∆unl.
• Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. The PLL can also operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below the maximum system frequency (f sys) and require fast start-up. The following conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit should be asserted to configure the filter in acquisition mode.
• After turning on the PLL by setting the PLLON bit software must wait a given time (t acq) before entering tracking mode (ACQ = 0).
• After entering tracking mode software must wait a given time (t al) before selecting the PLLCLK as the source for system and core clocks (PLLSEL = 1).

7.4.1.2 System Clocks Generator

Figure 7-17. System Clocks Generator OSCILLATOR PHASE LOCK LOOP EXTAL XTAL SYSCLK RTIOSCCLK PLLCLK CLOCK PHASE GENERATOR BUS CLOCK CLOCK MONITOR PLLSEL or SCM CORE CLOCK COP OSCILLATOR = CLOCK GATE GA TING CONDITION WAIT(RTIWAI), STOP(PSTP,PRE), RTI ENABLE WAIT(COPWAI), STOP(PSTP,PCE), COP ENABLE STOP SCM CLOCK STOP

Chapter 7 Clocks and Reset Generator (S12CRGV6) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 353 The clock generator creates the clocks used in the MCU (seeFigure 7-17). The gating condition placed on top of the individual clock gates indicates the dependencies of different modes (STOP, W AIT) and the setting of the respective configuration bits. The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The memory blocks use the bus clock. If the MCU enters self clock mode (see Section 7.4.2.2, “Self Clock Mode”) oscillator clock source is switched to PLLCLK running at its minimum frequency f SCM. The bus clock is used to generate the clock visible at the ECLK pin. The core clock signal is the clock for the CPU. The core clock is twice the bus clock as shown in Figure 7-18. But note that a CPU cycle corresponds to one bus clock. PLL clock mode is selected with PLLSEL bit in the CLKSEL registerr. When selected, the PLL output clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU activity ceases. Figure 7-18. Core Clock and Bus Clock Relationship

7.4.1.3 Clock Monitor (CM)

If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event. The CRG then asserts self clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by the CME control bit.

7.4.1.4 Clock Quality Checker

The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker provides a more accurate check in addition to the clock monitor. A clock quality check is triggered by any of the following events:

• Power on reset ( POR)
• Low voltage reset ( LVR)
• Wake-up from full stop mode ( exit full stop)
• Clock monitor fail indication ( CM fail) A time window of 50,000 VCO clock cycles 1 is called check window. 1. VCO clock cycles are generated by the PLL when running at minimum frequency fSCM. CORE CLOCK BUS CLOCK / ECLK

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A number greater equal than 4096 rising OSCCLK edges within acheck windowis called osc ok. Note that osc ok immediately terminates the current check window. See Figure 7-19 as an example. Figure 7-19. Check Window Example The sequence for clock quality check is shown in Figure 7-20. Figure 7-20. Sequence for Clock Quality Check 12 49999 50000 VCO Clock check window 12345 4095 4096 OSCCLK osc ok check window osc ok SCM active? Switch to OSCCLK Exit SCM Clock OK num = 50 num > 0 num=num–1 yes no yes SCME=1 no Enter SCM SCM active? yes Clock Monitor Reset no yes no num = 0 yes no POR exit full stop CM fail LVR yes no FSTWKP = 0 no num = 0 Enter SCM yes SCME = 1 & FSTWKP = 1

Chapter 7 Clocks and Reset Generator (S12CRGV6) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 355 NOTE Remember that in parallel to additional actions caused by self clock mode or clock monitor reset1 handling the clock quality checker continues to check the OSCCLK signal. The clock quality checker enables the PLL and the voltage regulator (VREG) anytime a clock check has to be performed. An ongoing clock quality check could also cause a running PLL (f SCM) and an active VREG during pseudo stop mode or wait mode.

7.4.1.5 Computer Operating Properly Watchdog (COP)

The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping the COP from timing out. If the COP times out it is an indication that the software is no longer being executed in the intended sequence; thus a system reset is initiated (see Section 7.4.1.5, “Computer Operating Properly Watchdog (COP)”). The COP runs with a gated OSCCLK. Three control bits in the COPCTL register allow selection of seven COP time-out periods. When COP is enabled, the program must write 0x_55 and 0x_AA (in this order) to the ARMCOP register during the selected time-out period. Once this is done, the COP time-out period is restarted. If the program fails to do this and the COP times out, the part will reset. Also, if any value other than 0x_55 or 0x_AA is written, the part is immediately reset. Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period. A premature write will immediately reset the part. If PCE bit is set, the COP will continue to run in pseudo stop mode.

7.4.1.6 Real Time Interrupt (RTI)

The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting RTIE = 1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated OSCCLK. At the end of the RTI time-out period the RTIF flag is set to 1 and a new RTI time-out period starts immediately. A write to the RTICTL register restarts the RTI time-out period. If the PRE bit is set, the RTI will continue to run in pseudo stop mode.

7.4.2 Operating Modes

7.4.2.1 Normal Mode

The CRG block behaves as described within this specification in all normal modes. 1. A Clock Monitor Reset will always set the SCME bit to logical 1.

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7.4.2.2 Self Clock Mode

The VCO has a minimum operating frequency, fSCM. If the external clock frequency is not available due to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO running at minimum operating frequency; this mode of operation is called self clock mode. This requires CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self clock mode, the PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically select OSCCLK to be the system clock and return to normal mode. Section 7.4.1.4, “Clock Quality Checker” for more information on entering and leaving self clock mode. NOTE In order to detect a potential clock loss the CME bit should be always enabled (CME = 1)! If CME bit is disabled and the MCU is configured to run on PLL clock (PLLCLK), a loss of external clock (OSCCLK) will not be detected and will cause the system clock to drift towards the VCO’s minimum frequency f SCM. As soon as the external clock is available again the system clock ramps up to its PLL target frequency. If the MCU is running on external clock any loss of clock will cause the system to go static.

7.4.3 Low Power Options

This section summarizes the low power options available in the CRG.

7.4.3.1 Run Mode

The RTI can be stopped by setting the associated rate select bits to 0. The COP can be stopped by setting the associated rate select bits to 0.

7.4.3.2 Wait Mode

The W AI instruction puts the MCU in a low power consumption stand-by mode depending on setting of the individual bits in the CLKSEL register. All individual wait mode configuration bits can be superposed. This provides enhanced granularity in reducing the level of power consumption during wait mode. Table 7-11 lists the individual configuration bits and the parts of the MCU that are affected in wait mode After executing the W AI instruction the core requests the CRG to switch MCU into wait mode. The CRG then checks whether the PLLW AI bit is asserted (Figure 7-21). Depending on the configuration, the CRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit and disables the PLL. As soon as all clocks are switched off wait mode is active. Table 7-11. MCU Configuration During Wait Mode PLLWAI RTIWAI COPWAI PLL Stopped — — RTI — Stopped — COP — — Stopped

Chapter 7 Clocks and Reset Generator (S12CRGV6) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 357 Figure 7-21. Wait Mode Entry/Exit Sequence Enter Wait Mode PLLWAI=1 Exit Wait w. CMRESET Exit Wait w. ext.RESET Exit Wait Mode Enter SCM Exit Wait Mode CPU Req’s Wait Mode. Clear PLLSEL, Disable PLL CME=1 INT CM Fail SCME=1 SCMIE=1 Continue w. Normal OP No No No No No Yes Yes Yes Yes Yes No Yes Wait Mode left due to external reset Generate SCM Interrupt (Wakeup from Wait) SCM=1 Enter SCM No Yes

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There are four different scenarios for the CRG to restart the MCU from wait mode:

• External reset
• Clock monitor reset
• COP reset
• Any interrupt If the MCU gets an external reset or COP reset during wait mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal or COP reset vector. Wait mode is left and the MCU is in run mode again. If the clock monitor is enabled (CME = 1) the MCU is able to leave wait mode when loss of oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE = 1). After generating the interrupt the CRG enters self-clock mode and starts the clock quality checker (Section 7.4.1.4, “Clock Quality Checker”). Then the MCU continues with normal operation.If the SCM interrupt is blocked by SCMIE = 0, the SCMIF flag will be asserted and clock quality checks will be performed but the MCU will not wake-up from wait-mode. If any other interrupt source (e.g., RTI) triggers exit from wait mode, the MCU immediately continues with normal operation. If the PLL has been powered-down during wait mode, the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving wait mode. The software must manually set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. If wait mode is entered from self-clock mode the CRG will continue to check the clock quality until clock check is successful. The PLL and voltage regulator (VREG) will remain enabled. Table 7-12 summarizes the outcome of a clock loss while in wait mode.

7.4.3.3 System Stop Mode

All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE, and PSTP bit. The oscillator is disabled in STOP mode unless the PSTP bit is set. All counters and dividers remain frozen but do not initialize. If the PRE or PCE bits are set, the RTI or COP continues to run in pseudo stop mode. In addition to disabling system and core clocks the CRG requests other functional units of the MCU (e.g., voltage-regulator) to enter their individual power saving modes (if available). This is the main difference between pseudo stop mode and wait mode. If the PLLSEL bit is still set when entering stop mode, the CRG will switch the system and core clocks to OSCCLK by clearing the PLLSEL bit. Then the CRG disables the PLL, disables the core clock and finally disables the remaining system clocks. As soon as all clocks are switched off, stop mode is active. If pseudo stop mode (PSTP = 1) is entered from self-clock mode, the CRG will continue to check the clock quality until clock check is successful. The PLL and the voltage regulator (VREG) will remain enabled. If full stop mode (PSTP = 0) is entered from self-clock mode, an ongoing clock quality check will be stopped. A complete timeout window check will be started when stop mode is left again. Wake-up from stop mode also depends on the setting of the PSTP bit.

Chapter 7 Clocks and Reset Generator (S12CRGV6) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 359 Table 7-12. Outcome of Clock Loss in Wait Mode CME SCME SCMIE CRG Actions 0X X Clock failure --> No action, clock loss not detected.

10 X Clock failure -->

CRG performs Clock Monitor Reset immediately 11 0 Clock failure --> Scenario 1: OSCCLK recovers prior to exiting wait mode. – MCU remains in wait mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag. Some time later OSCCLK recovers. – CM no longer indicates a failure, – 4096 OSCCLK cycles later clock quality check indicates clock o.k., – SCM deactivated, – PLL disabled depending on PLLWAI, – VREG remains enabled (never gets disabled in wait mode). – MCU remains in wait mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit wait mode using OSCCLK as system clock (SYSCLK), – Continue normal operation. or an External Reset is applied. – Exit wait mode using OSCCLK as system clock, – Start reset sequence. Scenario 2: OSCCLK does not recover prior to exiting wait mode. – MCU remains in wait mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag, – Keep performing clock quality checks (could continue infinitely) while in wait mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit wait mode in SCM using PLL clock (f SCM) as system clock, – Continue to perform additional clock quality checks until OSCCLK is o.k. again. or an External RESET is applied. – Exit wait mode in SCM using PLL clock (fSCM) as system clock, – Start reset sequence, – Continue to perform additional clock quality checks until OSCCLK is o.k.again. 11 1 Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – SCMIF set. SCMIF generates self clock mode wakeup interrupt. – Exit wait mode in SCM using PLL clock (f SCM) as system clock, – Continue to perform a additional clock quality checks until OSCCLK is o.k. again.

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Figure 7-22. Stop Mode Entry/Exit Sequence Exit Stop w. CMRESET Exit Stop Mode Enter SCM Exit Stop Mode Core req’s Stop Mode. Clear PLLSEL, Disable PLL CME=1 INT CM fail SCME=1 SCMIE=1 Continue w. normal OP No No no No Yes Yes Yes Yes Yes Generate SCM Interrupt (Wakeup from Stop) Enter Stop Mode Exit Stop w. ext.RESET Stop Mode left due to external reset Clock OK SCME=1 Enter SCM Yes No Yes Exit Stop w. CMRESET No NoNo PSTP=1 INT YesNo Yes Exit Stop Mode Exit Stop Mode SCM=1 Enter SCM No Yes Yes No SCME=1 & FSTWKP=1 Exit Stop Mode Enter SCM SCMIF not set!

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7.4.3.3.1 Wake-up from Pseudo Stop Mode (PSTP=1)

Wake-up from pseudo stop mode is the same as wake-up from wait mode. There are also four different scenarios for the CRG to restart the MCU from pseudo stop mode:

• External reset
• Clock monitor fail
• COP reset
• Wake-up interrupt If the MCU gets an external reset or COP reset during pseudo stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal or COP reset vector. pseudo stop mode is left and the MCU is in run mode again. If the clock monitor is enabled (CME = 1), the MCU is able to leave pseudo stop mode when loss of oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE = 1). After generating the interrupt the CRG enters self-clock mode and starts the clock quality checker (Section 7.4.1.4, “Clock Quality Checker”). Then the MCU continues with normal operation. If the SCM interrupt is blocked by SCMIE=0, the SCMIF flag will be asserted but the CRG will not wake-up from pseudo stop mode. If any other interrupt source (e.g., RTI) triggers exit from pseudo stop mode, the MCU immediately continues with normal operation. Because the PLL has been powered-down during stop mode, the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 7-13 summarizes the outcome of a clock loss while in pseudo stop mode.

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Table 7-13. Outcome of Clock Loss in Pseudo Stop Mode CME SCME SCMIE CRG Actions 0X X Clock failure --> No action, clock loss not detected. CRG performs Clock Monitor Reset immediately 110 Clock Monitor failure --> Scenario 1: OSCCLK recovers prior to exiting pseudo stop mode. – MCU remains in pseudo stop mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag. Some time later OSCCLK recovers. – CM no longer indicates a failure, – 4096 OSCCLK cycles later clock quality check indicates clock o.k., – SCM deactivated, – PLL disabled, – VREG disabled. – MCU remains in pseudo stop mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit pseudo stop mode using OSCCLK as system clock (SYSCLK), – Continue normal operation. or an External Reset is applied. – Exit pseudo stop mode using OSCCLK as system clock, – Start reset sequence. Scenario 2: OSCCLK does not recover prior to exiting pseudo stop mode. – MCU remains in pseudo stop mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag, – Keep performing clock quality checks (could continue infinitely) while in pseudo stop mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit pseudo stop mode in SCM using PLL clock (f SCM) as system clock – Continue to perform additional clock quality checks until OSCCLK is o.k. again. or an External RESET is applied. – Exit pseudo stop mode in SCM using PLL clock (fSCM) as system clock – Start reset sequence, – Continue to perform additional clock quality checks until OSCCLK is o.k.again. 111 Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – SCMIF set. SCMIF generates self clock mode wakeup interrupt. – Exit pseudo stop mode in SCM using PLL clock (f SCM) as system clock, – Continue to perform a additional clock quality checks until OSCCLK is o.k. again.

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7.4.3.3.2 Wake-up from Full Stop (PSTP = 0)

The MCU requires an external interrupt or an external reset in order to wake-up from stop-mode. If the MCU gets an external reset during full stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and will perform a maximum of 50 clock check_windows (see Section 7.4.1.4, “Clock Quality Checker”). After completing the clock quality check the CRG starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Full stop-mode is left and the MCU is in run mode again. If the MCU is woken-up by an interrupt and the fast wake-up feature is disabled (FSTWKP = 0 or SCME = 0), the CRG will also perform a maximum of 50 clock check_windows (see Section 7.4.1.4, “Clock Quality Checker”). If the clock quality check is successful, the CRG will release all system and core clocks and will continue with normal operation. If all clock checks within the Timeout-Window are failing, the CRG will switch to self-clock mode or generate a clock monitor reset (CMRESET) depending on the setting of the SCME bit. If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and SCME = 1), the system will immediately resume operation in self-clock mode (seeSection 7.4.1.4, “Clock Quality Checker”). The SCMIF flag will not be set. The system will remain in self-clock mode with oscillator disabled until FSTWKP bit is cleared. The clearing of FSTWKP will start the oscillator and the clock quality check. If the clock quality check is successful, the CRG will switch all system clocks to oscillator clock. The SCMIF flag will be set. See application examples in Figure 7-23 and Figure 7-24. Because the PLL has been powered-down during stop-mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop-mode. The software must manually set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. NOTE In full stop mode or self-clock mode caused by the fast wake-up feature, the clock monitor and the oscillator are disabled.

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Figure 7-23. Fast Wake-up from Full Stop Mode: Example 1 Figure 7-24. Fast Wake-up from Full Stop Mode: Example 2 Oscillator Clock PLL Clock Core Clock Instruction STOP IRQ ServiceFSTWKP=1 Interrupt IRQ Service Interrupt Interrupt STOP STOP IRQ Service Oscillator Disabled Power Saving Self-Clock Mode SCME=1 CPU resumes program execution immediately Oscillator Clock PLL Clock Core Clock Instruction Clock Quality Check STOP IRQ ServiceFSTWKP=1 IRQ Interrupt FSTWKP=0 SCMIE=1 Freq. Uncritical Instructions Freq. Critical Instr. Possible OSC StartupOscillator Disabled CPU resumes program execution immediately SCM Interrupt Self-Clock Mode SCME=1

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7.5 Resets

This section describes how to reset the CRG, and how the CRG itself controls the reset of the MCU. It explains all special reset requirements. Since the reset generator for the MCU is part of the CRG, this section also describes all automatic actions that occur during or as a result of individual reset conditions. The reset values of registers and signals are provided in Section 7.3, “Memory Map and Register Definition” . All reset sources are listed in Table 7-14. Refer to MCU specification for related vector addresses and priorities.

7.5.1 Description of Reset Operation

The reset sequence is initiated by any of the following events:

• Low level is detected at the RESET pin (external reset)
• Power on is detected
• Low voltage is detected
• Illegal Address Reset is detected (see S12XMMC Block Guide for details)
• COP watchdog times out
• Clock monitor failure is detected and self-clock mode was disabled (SCME=0) Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles (see Figure 7-25). Since entry into reset is asynchronous, it does not require a running SYSCLK. However, the internal reset circuit of the CRG cannot sequence out of current reset condition without a running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional SYSCLK cycles depending on the internal synchronization latency. After 128 + n SYSCLK cycles the RESET pin is released. The reset generator of the CRG waits for additional 64 SYSCLK cycles and then samples the RESET pin to determine the originating source. Table 7-15 shows which vector will be fetched. Table 7-14. Reset Summary Reset Source Local Enable Power on Reset None Low Voltage Reset None External Reset None Illegal Address Reset None Clock Monitor Reset PLLCTL (CME = 1, SCME = 0) COP Watchdog Reset COPCTL (CR[2:0] nonzero)

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External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic 1 within 64 SYSCLK cycles after the low drive is released. The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too. Figure 7-25. RESET Timing Table 7-15. Reset Vector Selection Sampled RESET Pin (64 cycles after release) Clock Monitor Reset Pending COP Reset Pending Vector Fetch 1 0 0 POR / LVR / Illegal Address Reset / External Reset 1 1 X Clock Monitor Reset 1 0 1 COP Reset

0 X X POR / LVR / Illegal Address Reset / External Reset

) ( ) ( SYSCLK 128 + n cycles 64 cycles With n being min 3 / max 6 cycles depending on internal synchronization delay CRG drives RESET pin low Possibly SYSCLK not running Possibly RESET driven low externally RESET RESET pin released

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7.5.2 Clock Monitor Reset

The CRG generates a clock monitor reset in case all of the following conditions are true:

• Clock monitor is enabled (CME = 1)
• Loss of clock is detected
• Self-clock mode is disabled (SCME = 0). The reset event asynchronously forces the configuration registers to their default settings (seeSection 7.3, “Memory Map and Register Definition”). In detail the CME and the SCME are reset to logical ‘1’ (which doesn’t change the state of the CME bit, because it has already been set). As a consequence the CRG immediately enters self clock mode and starts its internal reset sequence. In parallel the clock quality check starts. As soon as clock quality check indicates a valid oscillator clock the CRG switches to OSCCLK and leaves self clock mode. Since the clock quality checker is running in parallel to the reset generator, the CRG may leave self clock mode while still completing the internal reset sequence. When the reset sequence is finished, the CRG checks the internally latched state of the clock monitor fail circuit. If a clock monitor fail is indicated, processing begins by fetching the clock monitor reset vector.

7.5.3 Computer Operating Properly Watchdog (COP) Reset

When COP is enabled, the CRG expects sequential write of 0x_55 and 0x_AA (in this order) to the ARMCOP register during the selected time-out period. Once this is done, the COP time-out period restarts. If the program fails to do this the CRG will generate a reset. Also, if any value other than 0x_55 or 0x_AA is written, the CRG immediately generates a reset. In case windowed COP operation is enabled writes (0x_55 or 0x_AA) to the ARMCOP register must occur in the last 25% of the selected time-out period. A premature write the CRG will immediately generate a reset. As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching the COP vector.

7.5.4 Power On Reset, Low Voltage Reset

The on-chip voltage regulator detects when VDD to the MCU has reached a certain level and asserts power on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the CRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid oscillator clock signal, the reset sequence starts using the oscillator clock. If after 50 check windows the clock quality check indicated a non-valid oscillator clock, the reset sequence starts using self-clock mode. Figure 7-26 and Figure 7-27 show the power-up sequence for cases when the RESET pin is tied to VDD and when the RESET pin is held low.

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Figure 7-26. RESET Pin Tied to VDD (by a pull-up resistor) Figure 7-27. RESET Pin Held Low Externally

7.6 Interrupts

The interrupts/reset vectors requested by the CRG are listed inTable 7-16. Refer to MCU specification for related vector addresses and priorities.

7.6.1 Real Time Interrupt

The CRG generates a real time interrupt when the selected interrupt time period elapses. RTI interrupts are locally disabled by setting the RTIE bit to 0. The real time interrupt flag (RTIF) is set to1 when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit. The RTI continues to run during pseudo stop mode if the PRE bit is set to 1. This feature can be used for periodic wakeup from pseudo stop if the RTI interrupt is enabled. Table 7-16. CRG Interrupt Vectors Interrupt Source CCR Mask Local Enable Real time interrupt I bit CRGINT (RTIE) LOCK interrupt I bit CRGINT (LOCKIE) SCM interrupt I bit CRGINT (SCMIE) RESET Internal POR

128 SYSCLK

64 SYSCLKInternal RESET

(no Self-Clock Mode) ) ( ) ( ) ( Clock Quality Check RESET Internal POR Internal RESET

64 SYSCLK

(no Self Clock Mode) ) ( ) ( ) (

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7.6.2 PLL Lock Interrupt

The CRG generates a PLL Lock interrupt when the LOCK condition of the PLL has changed, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to 0. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.

7.6.3 Self Clock Mode Interrupt

The CRG generates a self clock mode interrupt when the SCM condition of the system has changed, either entered or exited self clock mode. SCM conditions can only change if the self clock mode enable bit (SCME) is set to 1. SCM conditions are caused by a failing clock quality check after power on reset (POR) or low voltage reset (LVR) or recovery from full stop mode (PSTP = 0) or clock monitor failure. For details on the clock quality check refer to Section 7.4.1.4, “Clock Quality Checker”. If the clock monitor is enabled (CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1). SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt flag (SCMIF) is set to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.

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MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 371 Chapter 8 Pierce Oscillator (S12XOSCLCPV1)

8.1 Introduction

The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source. The module will be operated from the VDDPLL supply rail (2.5 V nominal) and require the minimum number of external components. It is designed for optimal start-up margin with typical crystal oscillators.

8.1.1 Features

The XOSC will contain circuitry to dynamically control current gain in the output amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.

• High noise immunity due to input hysteresis
• Low RF emissions with peak-to-peak swing limited dynamically
• Transconductance (gm) sized for optimum start-up margin for typical oscillators
• Dynamic gain control eliminates the need for external current limiting resistor
• Integrated resistor eliminates the need for external bias resistor
• Low power consumption: — Operates from 2.5 V (nominal) supply — Amplitude control limits power
• Clock monitor

8.1.2 Modes of Operation

Two modes of operation exist: 1. Loop controlled Pierce oscillator 2. External square wave mode featuring also full swing Pierce without internal feedback resistor

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8.1.3 Block Diagram

Figure 8-1 shows a block diagram of the XOSC. Figure 8-1. XOSC Block Diagram

8.2 External Signal Description

This section lists and describes the signals that connect off chip

8.2.1 V DDPLL and VSSPLL — Operating and Ground Voltage Pins

Theses pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the XOSC circuitry. This allows the supply voltage to the XOSC to be independently bypassed.

8.2.2 EXTAL and XTAL — Input and Output Pins

These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal system clock is derived from the EXTAL XTAL Gain Control VDDPLL = 2.5 V Rf OSCCLK Monitor_Failure Clock Monitor Peak Detector

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8.2.3 XCLKS — Input Signal

The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. Refer to the Device Overview chapter for polarity and sampling conditions of the XCLKS pin. Table 8-1 lists the state coding of the sampled XCLKS signal.

8.3 Memory Map and Register Definition

The CRG contains the registers and associated bits for controlling and monitoring the oscillator module.

8.4 Functional Description

The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal level which is determined by the amount of hysteresis being used and the maximum oscillation range. The oscillator block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is intended to be connected to either a crystal or an external clock source. The selection of loop controlled Pierce oscillator or full swing Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. The XTAL pin is an output signal that provides crystal circuit feedback. A buffered EXTAL signal becomes the internal clock. To improve noise immunity, the oscillator is powered by the V DDPLL and VSSPLL power supply pins.

8.4.1 Gain Control

A closed loop control system will be utilized whereby the amplifier is modulated to keep the output waveform sinusoidal and to limit the oscillation amplitude. The output peak to peak voltage will be kept above twice the maximum hysteresis level of the input buffer. Electrical specification details are provided in the Electrical Characteristics appendix.

8.4.2 Clock Monitor

The clock monitor circuit is based on an internal RC time delay so that it can operate without any MCU clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates failure which asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function is enabled/disabled by the CME control bit, described in the CRG block description chapter. Table 8-1. Clock Selection Based on XCLKS XCLKS Description

1 Full swing Pierce oscillator/external clock selected

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8.4.3 Wait Mode Operation

During wait mode, XOSC is not impacted.

8.4.4 Stop Mode Operation

XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled. During pseudo-stop mode, XOSC is not impacted.

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MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 377 Chapter 9 Analog-to-Digital Converter (ATD10B16CV4) Block Description

9.1 Introduction

The ATD10B16C is a 16-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to the Electrical Specifications chapter for ATD accuracy.

9.1.1 Features

• 8-/10-bit resolution
• 7 µs, 10-bit single conversion time
• Sample buffer amplifier
• Programmable sample time
• Left/right justified, signed/unsigned result data
• External trigger control
• Conversion completion interrupt generation
• Analog input multiplexer for 16 analog input channels
• Analog/digital input pin multiplexing
• 1 to 16 conversion sequence lengths
• Continuous conversion mode
• Multiple channel scans
• Configurable external trigger functionality on any AD channel or any of four additional trigger inputs. The four additional trigger inputs can be chip external or internal. Refer to device specification for availability and connectivity
• Configurable location for channel wrap around (when converting multiple channels in a sequence)

9.1.2 Modes of Operation

There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels.

9.1.3 Block Diagram

Refer to Figure 9-1 for a block diagram of the ATD0B16C block.

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Figure 9-1. ATD10B16C Block Diagram VSSA AN8 ATD10B16C Analog MUX Mode and Successive Approximation Register (SAR) Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 and DAC Sample & Hold VDDA VRL VRH Sequence Complete Interrupt Comparator Clock Prescaler Bus Clock ATD clock ATD 8 ATD 9 ATD 10 ATD 11 ATD 12 ATD 13 ATD 14 ATD 15 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ETRIG0 (see Device Overview chapter for availability ETRIG1 ETRIG2 ETRIG3 and connectivity) Timing Control ATDDIENATDCTL1 PORTAD Trigger Mux

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9.2 External Signal Description

This section lists all inputs to the ATD10B16C block.

9.2.1 AN x (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input

This pin serves as the analog input channel x. It can also be configured as general-purpose digital input and/or external trigger for the ATD conversion.

9.2.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 — External Trigger Pins

These inputs can be configured to serve as an external trigger for the ATD conversion. Refer to the Device Overview chapter for availability and connectivity of these inputs.

9.2.3 V RH,V RL — High Reference Voltage Pin, Low Reference Voltage Pin

VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.

9.2.4 V DDA, VSSA — Analog Circuitry Power Supply Pins

These pins are the power supplies for the analog circuitry of the ATD10B16CV4 block.

9.3 Memory Map and Register Definition

This section provides a detailed description of all registers accessible in the ATD10B16C.

9.3.1 Module Memory Map

Table 9-1 gives an overview of all ATD10B16C registers

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Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. Table 9-1. ATD10B16CV4 Memory Map Address Offset Use Access 0x0000 ATD Control Register 0 (ATDCTL0) R/W 0x0001 ATD Control Register 1 (ATDCTL1) R/W 0x0002 ATD Control Register 2 (ATDCTL2) R/W 0x0003 ATD Control Register 3 (ATDCTL3) R/W 0x0004 ATD Control Register 4 (ATDCTL4) R/W 0x0005 ATD Control Register 5 (ATDCTL5) R/W 0x0006 ATD Status Register 0 (ATDSTAT0) R/W 0x0007 Unimplemented 0x0008 ATD Test Register 0 (ATDTEST0) (1) 1. ATDTEST0 is intended for factory test purposes only. R 0x0009 ATD Test Register 1 (ATDTEST1) R/W 0x000A ATD Status Register 2 (ATDSTAT2) R 0x000B ATD Status Register 1 (ATDSTAT1) R 0x000C ATD Input Enable Register 0 (ATDDIEN0) R/W 0x000D ATD Input Enable Register 1 (ATDDIEN1) R/W 0x000E Port Data Register 0 (PORTAD0) R 0x000F Port Data Register 1 (PORTAD1) R 0x0010, 0x0011 ATD Result Register 0 (ATDDR0H, ATDDR0L) R/W 0x0012, 0x0013 ATD Result Register 1 (ATDDR1H, ATDDR1L) R/W 0x0014, 0x0015 ATD Result Register 2 (ATDDR2H, ATDDR2L) R/W 0x0016, 0x0017 ATD Result Register 3 (ATDDR3H, ATDDR3L) R/W 0x0018, 0x0019 ATD Result Register 4 (ATDDR4H, ATDDR4L) R/W 0x001A, 0x001B ATD Result Register 5 (ATDDR5H, ATDDR5L) R/W 0x001C, 0x001D ATD Result Register 6 (ATDDR6H, ATDDR6L) R/W 0x001E, 0x001F ATD Result Register 7 (ATDDR7H, ATDDR7L) R/W 0x0020, 0x0021 ATD Result Register 8 (ATDDR8H, ATDDR8L) R/W 0x0022, 0x0023 ATD Result Register 9 (ATDDR9H, ATDDR9L) R/W 0x0024, 0x0025 ATD Result Register 10 (ATDDR10H, ATDDR10L) R/W 0x0026, 0x0027 ATD Result Register 11 (ATDDR11H, ATDDR11L) R/W 0x0028, 0x0029 ATD Result Register 12 (ATDDR12H, ATDDR12L) R/W 0x002A, 0x002B ATD Result Register 13 (ATDDR13H, ATDDR13L) R/W 0x002C, 0x002D ATD Result Register 14 (ATDDR14H, ATDDR14L) R/W 0x002E, 0x002F ATD Result Register 15 (ATDDR15H, ATDDR15L) R/W

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9.3.2 Register Descriptions

This section describes in address order all the ATD10B16C registers and their individual bits. Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 ATDCTL0 R 0000 WRAP3 WRAP2 WRAP1 WRAP0 W 0x0001 ATDCTL1 R ETRIGSEL 000 ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 W 0x0002 ATDCTL2 R ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE ASCIF W 0x0003 ATDCTL3 S8C S4C S2C S1C FIFO FRZ1 FRZ0 W 0x0004 ATDCTL4 R SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 W 0x0005 ATDCTL5 R DJM DSGN SCAN MULT CD CC CB CA W 0x0006 ATDSTAT0 R SCF ETORF FIFOR CC3 CC2 CC1 CC0 W 0x0007 Unimplemented R W 0x0008 ATDTEST0 R Unimplemented W 0x0009 ATDTEST1 R Unimplemented SC W 0x000A ATDSTAT2 R CCF15 CCF14 CCF13 CCF12 CCF11 CCF10 CCF9 CCF8 W 0x000B ATDSTAT1 R CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 W 0x000C ATDDIEN0 R IEN15 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 IEN8 W = Unimplemented or Reserved u = Unaffected Figure 9-2. ATD Register Summary

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9.3.2.1 ATD Control Register 0 (ATDCTL0)

Writes to this register will abort current conversion sequence but will not start a new sequence. Read: Anytime Write: Anytime 0x000D ATDDIEN1 R IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 W 0x000E PORTAD0 R PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9 PTAD8 W 0x000F PORTAD1 R PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 W R BIT 9 MSB BIT 7 MSB BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 0x0010–0x002F ATDDRxH– ATDDRxL W R BIT 1 u BIT 0 u W Module Base + 0x0000 76543210 R 0000 WRAP3 WRAP2 WRAP1 WRAP0 W Reset 0 0 0 01111 = Unimplemented or Reserved Figure 9-3. ATD Control Register 0 (ATDCTL0) Table 9-2. ATDCTL0 Field Descriptions Field Description 3:0 WRAP[3:0] Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi- channel conversions. The coding is summarized in Table 9-3. Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved u = Unaffected Figure 9-2. ATD Register Summary (continued)

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9.3.2.2 ATD Control Register 1 (ATDCTL1)

Writes to this register will abort current conversion sequence but will not start a new sequence. Read: Anytime Write: Anytime Table 9-3. Multi-Channel Wrap Around Coding WRAP3 WRAP2 WRAP1 WRAP0 Multiple Channel Conversions (MULT = 1) Wrap Around to AN0 after Converting 0 0 0 0 Reserved

0001 A N 1

0010 A N 2

0011 A N 3

0100 A N 4

0101 A N 5

0110 A N 6

0111 A N 7

1000 A N 8

1001 A N 9

R ETRIGSEL 000 ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 W Reset 0 0 0 01111 = Unimplemented or Reserved Figure 9-4. ATD Control Register 1 (ATDCTL1) Table 9-4. ATDCTL1 Field Descriptions Field Description ETRIGSEL External Trigger Source Select — This bit selects the external trigger source to be either one of the AD channels or one of the ETRIG[3:0] inputs. See device specification for availability and connectivity of ETRIG[3:0] inputs. If ETRIG[3:0] input option is not available, writing a 1 to ETRISEL only sets the bit but has no effect, that means one of the AD channels (selected by ETRIGCH[3:0]) remains the source for external trigger. The coding is summarized in Table 9-5. 3:0 ETRIGCH[3:0] External Trigger Channel Select— These bits select one of the AD channels or one of the ETRIG[3:0] inputs as source for the external trigger. The coding is summarized in Table 9-5.

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9.3.2.3 ATD Control Register 2 (ATDCTL2)

This register controls power down, interrupt and external trigger. Writes to this register will abort current conversion sequence but will not start a new sequence. Table 9-5. External Trigger Channel Select Coding ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External Trigger Source 0 0 0 0 0 AN0 0 0 0 0 1 AN1 0 0 0 1 0 AN2 0 0 0 1 1 AN3 0 0 1 0 0 AN4 0 0 1 0 1 AN5 0 0 1 1 0 AN6 0 0 1 1 1 AN7 0 1 0 0 0 AN8 0 1 0 0 1 AN9 0 1 0 1 0 AN10 0 1 0 1 1 AN11 0 1 1 0 0 AN12 0 1 1 0 1 AN13 0 1 1 1 0 AN14 0 1 1 1 1 AN15 1 0 0 0 0 ETRIG0 (1) 1. Only if ETRIG[3:0] input option is available (see device specification), else ETRISEL is ignored, that means external trigger source remains on one of the AD channels selected by ETRIGCH[3:0] 1 0 0 0 1 ETRIG1 1 1 0 0 1 0 ETRIG2 1 1 0 0 1 1 ETRIG3 1 1 0 1 X X Reserved 1 1 X X X Reserved

Chapter 9 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 385 Read: Anytime Write: Anytime Module Base + 0x0002 76543210 R ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE ASCIF W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 9-5. ATD Control Register 2 (ATDCTL2) Table 9-6. ATDCTL2 Field Descriptions Field Description ADPU ATD Power Down— This bit provides on/off control over the ATD10B16C block allowing reduced MCU power consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after ADPU bit is enabled.

0 Power down ATD

1 Normal ATD functionality

0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to clear the associate CCF flag). 1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will cause the associate CCF flag to clear automatically. AWAI ATD Power Down in Wait Mode — When entering Wait Mode this bit provides on/off control over the ATD10B16C block allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after exit from Wait mode.

0 ATD continues to run in Wait mode

1 Halt conversion and power down ATD during Wait mode

After exiting Wait mode with an interrupt conversion will resume. But due to the recovery time the result of this conversion should be ignored. ETRIGLE External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See Table 9-7 for details. ETRIGP External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 9-7 for details. ETRIGE External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the ETRIG[3:0] inputs as described inTable 9-5. If external trigger source is one of the AD channels, the digital input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with external events.

0 Disable external trigger

1 Enable external trigger

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ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Interrupt will be requested whenever ASCIF = 1 is set. ASCIF ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see

0 No ATD interrupt occurred

1 ATD sequence complete interrupt pending

Table 9-7. External Trigger Configurations ETRIGLE ETRIGP External Trigger Sensitivity 0 0 Falling Edge 0 1 Ring Edge 1 0 Low Level 1 1 High Level Table 9-6. ATDCTL2 Field Descriptions (continued) Field Description

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9.3.2.4 ATD Control Register 3 (ATDCTL3)

This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze Mode. Writes to this register will abort current conversion sequence but will not start a new sequence. Read: Anytime Write: Anytime Module Base + 0x0003 76543210 S8C S4C S2C S1C FIFO FRZ1 FRZ0 W Reset 0 0 1 00000 = Unimplemented or Reserved Figure 9-6. ATD Control Register 3 (ATDCTL3) Table 9-8. ATDCTL3 Field Descriptions Field Description S8C Conversion Sequence Length— This bit controls the number of conversions per sequence. Table 9-9shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. S4C Conversion Sequence Length— This bit controls the number of conversions per sequence. Table 9-9shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. S2C Conversion Sequence Length— This bit controls the number of conversions per sequence. Table 9-9shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. S1C Conversion Sequence Length— This bit controls the number of conversions per sequence. Table 9-9shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family.

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Result Register FIFO Mode —If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on. If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register file. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register file, the current conversion result will be placed. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. So the first result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register (ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion (ETRIG=1). Finally, which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode may or may not be useful in a particular application to track valid data. 0 Conversion results are placed in the corresponding result register up to the selected sequence length. 1 Conversion results are placed in consecutive result registers (wrap around at end). 1:0 FRZ[1:0] Background Debug Freeze Enable— When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 9-10. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. Table 9-9. Conversion Sequence Length Coding S8C S4C S2C S1C Number of Conversions per Sequence 0000 1 6 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 1 0 1011 1 1 1100 1 2 1101 1 3 1110 1 4 1111 1 5 Table 9-8. ATDCTL3 Field Descriptions (continued) Field Description

Chapter 9 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 389 Table 9-10. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode 0 0 Continue conversion 0 1 Reserved 1 0 Finish current conversion, then freeze 1 1 Freeze Immediately

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9.3.2.5 ATD Control Register 4 (ATDCTL4)

This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e., 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence. Read: Anytime Write: Anytime Module Base + 0x0004 76543210 R SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 W Reset 0 0 0 00101 Figure 9-7. ATD Control Register 4 (ATDCTL4) Table 9-11. ATDCTL4 Field Descriptions Field Description SRES8 A/D Resolution Select — This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The A/D converter has an accuracy of 10 bits. However, if low resolution is required, the conversion can be speeded up by selecting 8-bit resolution. 0 10 bit resolution 1 8 bit resolution 6:5 SMP[1:0] Sample Time Select—These two bits select the length of the second phase of the sample time in units of ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0). The sample time consists of two phases. The first phase is two ATD conversion clock cycles long and transfers the sample quickly (via the buffer amplifier) onto the A/D machine’s storage node. The second phase attaches the external analog signal directly to the storage node for final charging and high accuracy. Table 9-12 lists the lengths available for the second sample phase. 4:0 PRS[4:0] ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock frequency is calculated as follows: Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12. Table 9-13illustrates the divide-by operation and the appropriate range of the bus clock. Table 9-12. Sample Time Select SMP1 SMP0 Length of 2nd Phase of Sample Time 0 0 2 A/D conversion clock periods 0 1 4 A/D conversion clock periods 1 0 8 A/D conversion clock periods 1 1 16 A/D conversion clock periods ATDclock BusClock[]

Chapter 9 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 391 Table 9-13. Clock Prescaler Values Prescale Value Total Divisor Value Max. Bus Clock(1) 1. Maximum ATD conversion clock frequency is 2 MHz. The maximum allowed bus clock frequency is shown in this column. Min. Bus Clock(2) 2. Minimum ATD conversion clock frequency is 500 kHz. The minimum allowed bus clock frequency is shown in this column. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Divide by 2 Divide by 4 Divide by 6 Divide by 8 Divide by 10 Divide by 12 Divide by 14 Divide by 16 Divide by 18 Divide by 20 Divide by 22 Divide by 24 Divide by 26 Divide by 28 Divide by 30 Divide by 32 Divide by 34 Divide by 36 Divide by 38 Divide by 40 Divide by 42 Divide by 44 Divide by 46 Divide by 48 Divide by 50 Divide by 52 Divide by 54 Divide by 56 Divide by 58 Divide by 60 Divide by 62 Divide by 64

4 MHz

8 MHz

12 MHz

16 MHz

20 MHz

24 MHz

28 MHz

32 MHz

36 MHz

40 MHz

44 MHz

48 MHz

52 MHz

56 MHz

60 MHz

64 MHz

68 MHz

72 MHz

76 MHz

80 MHz

84 MHz

88 MHz

92 MHz

96 MHz

100 MHz

104 MHz

108 MHz

112 MHz

116 MHz

120 MHz

124 MHz

128 MHz

1 MHz

2 MHz

3 MHz

5 MHz

6 MHz

7 MHz

9 MHz

10 MHz

11 MHz

13 MHz

14 MHz

15 MHz

17 MHz

18 MHz

19 MHz

21 MHz

22 MHz

23 MHz

25 MHz

26 MHz

27 MHz

29 MHz

30 MHz

31 MHz

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9.3.2.6 ATD Control Register 5 (ATDCTL5)

This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. If external trigger is enabled (ETRIGE = 1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event. Start of conversion means the beginning of the sampling phase. Read: Anytime Write: Anytime Module Base + 0x0005 76543210 R DJM DSGN SCAN MULT CD CC CB CA W Reset 0 0 0 00000 Figure 9-8. ATD Control Register 5 (ATDCTL5) Table 9-14. ATDCTL5 Field Descriptions Field Description DJM Result Register Data Justification — This bit controls justification of conversion data in the result registers. See Section 9.3.2.16, “ATD Conversion Result Registers (ATDDRx)” for details. 0 Left justified data in the result registers. 1 Right justified data in the result registers. DSGN Result Register Data Signed or Unsigned Representation— This bit selects between signed and unsigned conversion data representation in the result registers. Signed data is represented as 2’s complement. Signed data is not available in right justification. See <st-bold>9.3.2.16 ATD Conversion Result Registers (ATDDRx) for details. 0 Unsigned data representation in the result registers. 1 Signed data representation in the result registers. Table 9-15 summarizes the result data formats available and how they are set up using the control bits. Table 9-16 illustrates the difference between the signed and unsigned, left justified output codes for an input signal range between 0 and 5.12 Volts. SCAN Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed continuously or only once. If external trigger is enabled (ETRIGE=1) setting this bit has no effect, that means each trigger event starts a single conversion sequence.

0 Single conversion sequence

1 Continuous conversion sequences (scan mode)

Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C, S1C). The first analog channel examined is determined by channel selection code (CC, CB, CA control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code or wrapping around to AN0 (channel 0.

0 Sample only one channel

1 Sample across several channels

Chapter 9 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 393 3:0 C[D:A} Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are sampled and converted to digital codes. Table 9-17 lists the coding used to select the various analog input channels. In the case of single channel conversions (MULT = 0), this selection code specified the channel to be examined. In the case of multiple channel conversions (MULT = 1), this selection code represents the first channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing the channel selection code or wrapping around to AN0 (after converting the channel defined by the Wrap Around Channel Select Bits WRAP[3:0] in ATDCTL0). In case starting with a channel number higher than the one defined by WRAP[3:0] the first wrap around will be AN15 to AN0. Table 9-15. Available Result Data Formats. SRES8 DJM DSGN Result Data Formats Description and Bus Bit Mapping X X 8-bit / left justified / unsigned — bits 15:8 8-bit / left justified / signed — bits 15:8 8-bit / right justified / unsigned — bits 7:0 10-bit / left justified / unsigned — bits 15:6 10-bit / left justified / signed -— bits 15:6 10-bit / right justified / unsigned — bits 9:0 Table 9-16. Left Justified, Signed and Unsigned ATD Output Codes. Input Signal VRL = 0 Volts VRH = 5.12 Volts Signed 8-Bit Codes Unsigned 8-Bit Codes Signed 10-Bit Codes Unsigned 10-Bit Codes

5.120 Volts

5.100 5.080 2.580 2.560 2.540 0.020 0.000 FF FF FF FE 7FC0 7F00 7E00 0100 0000 FF00 8100 8000 FFC0 FF00 FE00 8100 8000 7F00 0100 0000 Table 9-14. ATDCTL5 Field Descriptions (continued) Field Description

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Table 9-17. Analog Input Channel Select Coding CD CC CB CA Analog Input Channel 0 0 0 0 AN0 0 0 0 1 AN1 0 0 1 0 AN2 0 0 1 1 AN3 0 1 0 0 AN4 0 1 0 1 AN5 0 1 1 0 AN6 0 1 1 1 AN7 1 0 0 0 AN8 1 0 0 1 AN9 1 0 1 0 AN10 1 0 1 1 AN11 1 1 0 0 AN12 1 1 0 1 AN13 1 1 1 0 AN14 1 1 1 1 AN15

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9.3.2.7 ATD Status Register 0 (ATDSTAT0)

This read-only register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. Read: Anytime Write: Anytime (No effect on CC[3:0]) Module Base + 0x0006 76543210 R SCF ETORF FIFOR CC3 CC2 CC1 CC0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 9-9. ATD Status Register 0 (ATDSTAT0) Table 9-18. ATDSTAT0 Field Descriptions Field Description SCF Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN = 1), the flag is set after each one is completed. This flag is cleared when one of the following occurs:

• Write “1” to SCF
• Write to ATDCTL5 (a new conversion sequence is started)
• If AFFC = 1 and read of a result register

0 Conversion sequence not completed

1 Conversion sequence has completed

External Trigger Overrun Flag —While in edge trigger mode (ETRIGLE = 0), if additional active edges are detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the following occurs:

• Write “1” to ETORF
• Write to ATDCTL0,1,2,3,4 (a conversion sequence is aborted)
• Write to ATDCTL5 (a new conversion sequence is started)

0 No External trigger over run error has occurred

1 External trigger over run error has occurred

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FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels. However, it is also practical for non-FIFO modes, and indicates that a result register has been over written before it has been read (i.e., the old data has been lost). This flag is cleared when one of the following occurs:

• Write “1” to FIFOR
• Start a new conversion sequence (write to ATDCTL5 or external trigger)

0 No over run has occurred

1 Overrun condition exists (result register has been written while associated CCFx flag remained set)

3:0 CC[3:0} Conversion Counter— These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. For example, CC3 = 0, CC2 = 1, CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. Table 9-18. ATDSTAT0 Field Descriptions (continued) Field Description

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9.3.2.8 Reserved Register 0 (ATDTEST0)

Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this register when in special modes can alter functionality.

9.3.2.9 ATD Test Register 1 (ATDTEST1)

This register contains the SC bit used to enable special channel conversions. Read: Anytime, returns unpredictable values for bit 7 and bit 6 Write: Anytime NOTE Writing to this register when in special modes can alter functionality. Module Base + 0x0008 76543210 R uuuuuuuu W Reset 1 0 0 00000 = Unimplemented or Reserved u = Unaffected Figure 9-10. Reserved Register 0 (ATDTEST0) Module Base + 0x0009 76543210 R uuuuuuu SC W Reset 0 0 0 00000 = Unimplemented or Reserved u = Unaffected Figure 9-11. Reserved Register 1 (ATDTEST1) Table 9-19. ATDTEST1 Field Descriptions Field Description SC Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CC, CB, and CA of ATDCTL5.Table 9-20 lists the coding.

0 Special channel conversions disabled

1 Special channel conversions enabled

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9.3.2.10 ATD Status Register 2 (ATDSTAT2)

This read-only register contains the Conversion Complete Flags CCF15 to CCF8. Read: Anytime Write: Anytime, no effect Table 9-20. Special Channel Select Coding SC CD CC CB CA Analog Input Channel 1 0 0 X X Reserved 101 0 0 V RH 101 0 1 V RL 101 1 0 ( V RH+VRL) / 2 1 0 1 1 1 Reserved 1 1 X X X Reserved Module Base + 0x000A 76543210 R CCF15 CCF14 CCF13 CCF12 CCF11 CCF10 CCF9 CCF8 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 9-12. ATD Status Register 2 (ATDSTAT2) Table 9-21. ATDSTAT2 Field Descriptions Field Description 7:0 CCF[15:8] Conversion Complete Flag Bits — A conversion complete flag is set at the end of each conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and also the result register number). Therefore, CCF8 is set when the ninth conversion in a sequence is complete and the result is available in result register ATDDR8; CCF9 is set when the tenth conversion in a sequence is complete and the result is available in ATDDR9, and so forth. A flag CCFx (x = 15, 14, 13, 12, 11, 10, 9, 8) is cleared when one of the following occurs:

• Write to ATDCTL5 (a new conversion sequence is started)
• If AFFC = 0 and read of ATDSTAT2 followed by read of result register ATDDRx
• If AFFC = 1 and read of result register ATDDRx In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by methods B) or C) will be overwritten by the set.

0 Conversion number x not completed

1 Conversion number x has completed, result ready in ATDDRx

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9.3.2.11 ATD Status Register 1 (ATDSTAT1)

This read-only register contains the Conversion Complete Flags CCF7 to CCF0 Read: Anytime Write: Anytime, no effect Module Base + 0x000B 76543210 R CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 9-13. ATD Status Register 1 (ATDSTAT1) Table 9-22. ATDSTAT1 Field Descriptions Field Description 7:0 CCF[7:0] Conversion Complete Flag Bits — A conversion complete flag is set at the end of each conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and also the result register number). Therefore, CCF0 is set when the first conversion in a sequence is complete and the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is complete and the result is available in ATDDR1, and so forth. A CCF flag is cleared when one of the following occurs:

• Write to ATDCTL5 (a new conversion sequence is started)
• If AFFC = 0 and read of ATDSTAT1 followed by read of result register ATDDRx
• If AFFC = 1 and read of result register ATDDRx In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by methods B) or C) will be overwritten by the set. Conversion number x not completed Conversion number x has completed, result ready in ATDDRx

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9.3.2.12 ATD Input Enable Register 0 (ATDDIEN0)

Read: Anytime Write: anytime

9.3.2.13 ATD Input Enable Register 1 (ATDDIEN1)

Read: Anytime Write: Anytime Module Base + 0x000C 76543210 R IEN15 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 IEN8 W Reset 0 0 0 00000 Figure 9-14. ATD Input Enable Register 0 (ATDDIEN0) Table 9-23. ATDDIEN0 Field Descriptions Field Description 7:0 IEN[15:8] ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input pin (ANx) to PTADx data register.

0 Disable digital input buffer to PTADx

1 Enable digital input buffer to PTADx. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region. Module Base + 0x000D 76543210 R IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 W Reset 0 0 0 00000 Figure 9-15. ATD Input Enable Register 1 (ATDDIEN1) Table 9-24. ATDDIEN1 Field Descriptions Field Description 7:0 IEN[7:0] ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input pin (ANx) to PTADx data register. 1 Enable digital input buffer to PTADx. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region.

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9.3.2.14 Port Data Register 0 (PORTAD0)

The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN[15:8]. Read: Anytime Write: Anytime, no effect The A/D input channels may be used for general-purpose digital input. Module Base + 0x000E 76543210 R PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9 PTAD8 W Reset 1 1 1 11111 Pin Function AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 = Unimplemented or Reserved Figure 9-16. Port Data Register 0 (PORTAD0) Table 9-25. PORTAD0 Field Descriptions Field Description 7:0 PTAD[15:8] A/D Channel x (ANx) Digital Input Bits— If the digital input buffer on the ANx pin is enabled (IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1, ETRIGCH[3-0] = x, ETRIGSEL = 0) read returns the logic level on ANx pin (signal potentials not meeting V IL or VIH specifications will have an indeterminate value)). If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns a “1”. Reset sets all PORTAD0 bits to “1”.

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9.3.2.15 Port Data Register 1 (PORTAD1)

The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN7-0. Read: Anytime Write: Anytime, no effect The A/D input channels may be used for general-purpose digital input. Module Base + 0x000F 76543210 R PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 W Reset 1 1 1 11111 Pin Function AN 7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 = Unimplemented or Reserved Figure 9-17. Port Data Register 1 (PORTAD1) Table 9-26. PORTAD1 Field Descriptions Field Description 7:0 PTAD[7:8] A/D Channel x (ANx) Digital Input Bits — If the digital input buffer on the ANx pin is enabled (IENx=1) or channel x is enabled as external trigger (ETRIGE = 1, ETRIGCH[3-0] = x, ETRIGSEL = 0) read returns the logic level on ANx pin (signal potentials not meeting V IL or VIH specifications will have an indeterminate value)). If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns a “1”. Reset sets all PORTAD1 bits to “1”.

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9.3.2.16 ATD Conversion Result Registers (ATDDRx)

The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the result registers bases on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left justified format. Signed data selected for right justified format is ignored. Read: Anytime Write: Anytime in special mode, unimplemented in normal modes

9.3.2.16.1 Left Justified Result Data

Module Base + 0x0010 = ATDDR0H 0x0012 = ATDDR1H 0x0014 = ATDDR2H 0x0016 = ATDDR3H 0x0018 = ATDDR4H 0x001A = ATDDR5H 0x001C = ATDDR6H 0x001E = ATDDR7H 0x0020 = ATDDR8H 0x0022 = ATDDR9H 0x0024 = ATDDR10H 0x0026 = ATDDR11H 0x0028 = ATDDR12H 0x002A = ATDDR13H 0x002C = ATDDR14H 0x002E = ATDDR15H 76543210 R (10-BIT) R (8-BIT) BIT 9 MSB BIT 7 MSB BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 W Reset 00000000 = Unimplemented or Reserved Figure 9-18. Left Justified, ATD Conversion Result Register x, High Byte (ATDDRxH) Module Base + 0x0011 = ATDDR0L 0x0013 = ATDDR1L 0x0015 = ATDDR2L 0x0017 = ATDDR3L 0x0019 = ATDDR4L 0x001B = ATDDR5L 0x001D = ATDDR6L 0x001F = ATDDR7L 0x0021 = ATDDR8L 0x0023 = ATDDR9L 0x0025 = ATDDR10L 0x0027 = ATDDR11L 0x0029 = ATDDR12L 0x002B = ATDDR13L 0x002D = ATDDR14L 0x002F = ATDDR15L 76543210 R (10-BIT) R (8-BIT) BIT 1 u BIT 0 u W Reset 00000000 = Unimplemented or Reserved u = Unaffected Figure 9-19. Left Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL)

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9.3.2.16.2 Right Justified Result Data

9.4 Functional Description

The ATD10B16C is structured in an analog and a digital sub-block.

9.4.1 Analog Sub-block

The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block.

9.4.1.1 Sample and Hold Machine

The sample and hold (S/H) machine accepts analog signals from the external world and stores them as capacitor charge on a storage node. The sample process uses a two stage approach. During the first stage, the sample amplifier is used to quickly charge the storage node.The second stage connects the input directly to the storage node to complete the sample for high accuracy. Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H 0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H 0x0020 = ATDDR8H, 0x0022 = ATDDR9H, 0x0024 = ATDDR10H, 0x0026 = ATDDR11H 0x0028 = ATDDR12H, 0x002A = ATDDR13H, 0x002C = ATDDR14H, 0x002E = ATDDR15H 76543210 R (10-BIT) R (8-BIT) BIT 9 MSB BIT 8 W Reset 00000000 = Unimplemented or Reserved Figure 9-20. Right Justified, ATD Conversion Result Register x, High Byte (ATDDRxH) Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L 0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L 0x0021 = ATDDR8L, 0x0023 = ATDDR9L, 0x0025 = ATDDR10L, 0x0027 = ATDDR11L 0x0029 = ATDDR12L, 0x002B = ATDDR13L, 0x002D = ATDDR14L, 0x002F = ATDDR15L 76543210 R (10-BIT) R (8-BIT) BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 W Reset 00000000 = Unimplemented or Reserved Figure 9-21. Right Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL)

Chapter 9 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 405 When not sampling, the sample and hold machine disables its own clocks. The analog electronics continue drawing their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. The input analog signals are unipolar and must fall within the potential range of V SSA to VDDA.

9.4.1.2 Analog Input Multiplexer

The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold machine.

9.4.1.3 Sample Buffer Amplifier

The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential.

9.4.1.4 Analog-to-Digital (A/D) Machine

The A/D machine performs analog to digital conversions. The resolution is program selectable at either 8 or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the stored analog sample potential with a series of digitally generated analog potentials. By following a binary search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled potential. When not converting the A/D machine disables its own clocks. The analog electronics continue drawing quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. Only analog input signals within the potential range of V RL to VRH (A/D reference potentials) will result in a non-railed digital output codes.

9.4.2 Digital Sub-Block

This subsection explains some of the digital features in more detail. See register descriptions for all details.

9.4.2.1 External Trigger Input

The external trigger feature allows the user to synchronize ATD conversions to the external environment events rather than relying on software to signal the ATD module when ATD conversions are to take place. The external trigger signal (out of reset ATD channel 15, configurable in ATDCTL1) is programmable to be edge or level sensitive with polarity control. Table 9-27 gives a brief description of the different combinations of control bits and their effect on the external trigger function.

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During a conversion, if additional active edges are detected the overrun error flag ETORF is set. In either level or edge triggered modes, the first conversion begins when the trigger is received. In both cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger circuitry. After ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be triggered externally. If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion sequence, this does not constitute an overrun. Therefore, the flag is not set. If the trigger remains asserted in level mode while a sequence is completing, another sequence will be triggered immediately.

9.4.2.2 General-Purpose Digital Input Port Operation

The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external input data that can be accessed through the digital port registers (PORTAD0 & PORTAD1) (input-only). The analog/digital multiplex operation is performed in the input pads. The input pad is always connected to the analog inputs of the ATD10B16C. The input pad signal is buffered to the digital port registers. This buffer can be turned on or off with the ATDDIEN0 & ATDDIEN1 register. This is important so that the buffer does not draw excess current when analog potentials are presented at its input.

9.4.3 Operation in Low Power Modes

The ATD10B16C can be configured for lower MCU power consumption in three different ways:

• Stop Mode Stop Mode: This halts A/D conversion. Exit from Stop mode will resume A/D conversion, But due to the recovery time the result of this conversion should be ignored. Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power standby mode. This halts any conversion sequence in progress. During recovery from stop mode, there must be a minimum delay for the stop recovery time t SR before initiating a new ATD conversion sequence.
• Wait Mode Wait Mode with AW AI = 1: This halts A/D conversion. Exit from Wait mode will resume A/D conversion, but due to the recovery time the result of this conversion should be ignored. Table 9-27. External Trigger Control Bits ETRIGLE ETRIGP ETRIGE SCAN Description X X 0 0 Ignores external trigger. Performs one conversion sequence and stops. X X 0 1 Ignores external trigger. Performs continuous conversion sequences. 0 0 1 X Falling edge triggered. Performs one conversion sequence per trigger. 0 1 1 X Rising edge triggered. Performs one conversion sequence per trigger. 1 0 1 X Trigger active low. Performs continuous conversions while trigger is active. 1 1 1 X Trigger active high. Performs continuous conversions while trigger is active.

Chapter 9 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 407 Entering wait mode, the ATD conversion either continues or halts for low power depending on the logical value of the AW AIT bit.

• Freeze Mode Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D conversion in progress. In freeze mode, the ATD10B16C will behave according to the logical values of the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. NOTE The reset value for the ADPU bit is zero. Therefore, when this module is reset, it is reset into the power down state.

9.5 Initialization/Application Information

9.5.1 Setting up and starting an A/D conversion

The following describes a typical setup procedure for starting A/D conversions. It is highly recommended to follow this procedure to avoid common mistakes. Each step of the procedure will have a general remark and a typical example

9.5.1.1 Step 1

Power up the ATD and concurrently define other settings in ATDCTL2 Example: Write to ATDCTL2: ADPU=1 -> powers up the ATD, ASCIE=1 enable interrupt on finish of a conversion sequence.

9.5.1.2 Step 2

Wait for the ATD Recovery TimetREC before you proceed with Step 3. Example: Use the CPU in a branch loop to wait for a defined number of bus clocks.

9.5.1.3 Step 3

Configure how many conversions you want to perform in one sequence and define other settings in ATDCTL3. Example: Write S4C=1 to do 4 conversions per sequence.

9.5.1.4 Step 4

Configure resolution, sampling time and ATD clock speed in ATDCTL4. Example: Use default for resolution and sampling time by leaving SRES8, SMP1 and SMP0 clear. For a bus clock of 40MHz write 9 to PR4-0, this gives an ATD clock of 0.5*40MHz/(9+1) = 2MHz which is within the allowed range for f ATDCLK.

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9.5.1.5 Step 5

Configure starting channel, single/multiple channel, continuous or single sequence and result data format in ATDCTL5. Writing ATDCTL5 will start the conversion, so make sure your write ATDCTL5 in the last step. Example: Leave CD, CC,CB,CA clear to start on channel AN0. Write MULT=1 to convert channel AN0 to AN3 in a sequence (4 conversion per sequence selected in ATDCTL3).

9.5.2 Aborting an A/D conversion

9.5.2.1 Step 1

Write to ATDCTL4. This will abort any ongoing conversion sequence. (Do not use write to other ATDCTL registers to abort, as this under certain circumstances might not work correctly.)

9.5.2.2 Step 2

Disable the ATD Interrupt by writing ASCIE=0 in ATDCTL2. It is important to clear the interrupt enable at this point, prior to step 3, as depending on the device clock gating it may not always be possible to clear it or the SCF flag once the module is disabled (ADPU=0).

9.5.2.3 Step 3

Clear the SCF flag by writing a 1 in ATDSTAT0. (Remaining flags will be cleared with the next start of a conversions, but SCF flag should be cleared to avoid SCF interrupt.)

9.5.2.4 Step 4

Power down ATD by writing ADPU=0 in ATDCTL2.

9.6 Resets

At reset the ATD10B16C is in a power down state. The reset state of each individual bit is listed within Section 9.3, “Memory Map and Register Definition,” which details the registers and their bit fields.

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9.7 Interrupts

The interrupt requested by the ATD10B16C is listed inTable 9-28. Refer to MCU specification for related vector address and priority. See Section 9.3.2, “Register Descriptions,” for further details. Table 9-28. ATD Interrupt Vectors Interrupt Source CCR Mask Local Enable Sequence Complete Interrupt I bit ASCIE in ATDCTL2

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MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 411 Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description

10.1 Introduction

The LCD32F4BV1 driver module has 32 frontplane drivers and 4 backplane drivers so that a maximum of 128 LCD segments are controllable. Each segment is controlled by a corresponding bit in the LCD RAM. Four multiplex modes (1/1, 1/2, 1/3, 1/4 duty), and three bias (1/1, 1/2, 1/3) methods are available. The V voltage is the lowest level of the output waveform and V3 becomes the highest level. All frontplane and backplane pins can be multiplexed with other port functions. The LCD32F4BV1 driver system consists of five major sub-modules:

• Timing and Control – consists of registers and control logic for frame clock generation, bias voltage level select, frame duty select, backplane select, and frontplane select/enable to produce the required frame frequency and voltage waveforms.
• LCD RAM – contains the data to be displayed on the LCD. Data can be read from or written to the display RAM at any time.
• Frontplane Drivers – consists of 32 frontplane drivers.
• Backplane Drivers – consists of 4 backplane drivers.
• Voltage Generator – Based on voltage applied to VLCD, it generates the voltage levels for the timing and control logic to produce the frontplane and backplane waveforms.

10.1.1 Features

The LCD32F4BV1 includes these distinctive features:

• Supports five LCD operation modes
• 32 frontplane drivers
• 4 backplane drivers — Each frontplane has an enable bit respectively
• Programmable frame clock generator
• Programmable bias voltage level selector
• On-chip generation of 4 different output voltage levels

10.1.2 Modes of Operation

The LCD32F4BV1 module supports five operation modes with different numbers of backplanes and different biasing levels. During pseudo stop mode and wait mode the LCD operation can be suspended

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under software control. Depending on the state of internal bits, the LCD can operate normally or the LCD clock generation can be turned off and the LCD32F4BV1 module enters a power conservation state. This is a high level description only, detailed descriptions of operating modes are contained in Section 10.4.2, “Operation in Wait Mode”, Section 10.4.3, “Operation in Pseudo Stop Mode”, and Section 10.4.4, “Operation in Stop Mode”.

10.1.3 Block Diagram

Figure 10-1 is a block diagram of the LCD32F4BV1 module. Figure 10-1. LCD32F4BV1 Block Diagram LCD RAM 16 bytes Timing and Control Logic Frontplane Drivers Voltage Generator Backplane Drivers Internal Address/Data/Clocks FP[31:0] VLCD BP[3:0] Prescaler OSCCLK LCD Clock

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10.2 External Signal Description

The LCD32F4BV1 module has a total of 37 external pins.

10.2.1 BP[3:0] — Analog Backplane Pins

This output signal vector represents the analog backplane waveforms of the LCD32F4BV1 module and is connected directly to the corresponding pads.

10.2.2 FP[31:0] — Analog Frontplane Pins

This output signal vector represents the analog frontplane waveforms of the LCD32F4BV1 module and is connected directly to the corresponding pads.

10.2.3 VLCD — LCD Supply Voltage Pin

Positive supply voltage for the LCD waveform generation.

10.3 Memory Map and Register Definition

This section provides a detailed description of all memory and registers.

10.3.1 Module Memory Map

The memory map for the LCD32F4BV1 module is given inTable 10-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the LCD32F4BV1 module and the address offset for each register. Table 10-1. Signal Properties Name Port Function Reset State 4 backplane waveforms BP[3:0] Backplane waveform signals that connect directly to the pads High impedance 32 frontplane waveforms FP[31:0] Frontplane waveform signals that connect directly to the pads High impedance LCD voltage VLCD LCD supply voltage —

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Table 10-2. LCD32F4BV1 Memory Map Address Offset Use Access 0x0000 LCD Control Register 0 (LCDCR0) Read/Write 0x0001 LCD Control Register 1 (LCDCR1) Read/Write 0x0002 LCD Frontplane Enable Register 0 (FPENR0) Read/Write 0x0003 LCD Frontplane Enable Register 1 (FPENR1) Read/Write 0x0004 LCD Frontplane Enable Register 2 (FPENR2) Read/Write 0x0005 LCD Frontplane Enable Register 3 (FPENR3) Read/Write 0x0006 Unimplemented 0x0007 Unimplemented 0x0008 LCDRAM (Location 0) Read/Write 0x0009 LCDRAM (Location 1) Read/Write 0x000A LCDRAM (Location 2) Read/Write 0x000B LCDRAM (Location 3) Read/Write 0x000C LCDRAM (Location 4) Read/Write 0x000D LCDRAM (Location 5) Read/Write 0x000E LCDRAM (Location 6) Read/Write 0x000F LCDRAM (Location 7) Read/Write 0x0010 LCDRAM (Location 8) Read/Write 0x0011 LCDRAM (Location 9) Read/Write 0x0012 LCDRAM (Location 10) Read/Write 0x0013 LCDRAM (Location 11) Read/Write 0x0014 LCDRAM (Location 12) Read/Write 0x0015 LCDRAM (Location 13) Read/Write 0x0016 LCDRAM (Location 14) Read/Write 0x0017 LCDRAM (Location 15) Read/Write

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 415

10.3.2 Register Descriptions

This section consists of register descriptions. Each description includes a standard register diagram. Details of register bit and field function follow the register diagrams, in bit order.

10.3.2.1 LCD Control Register 0 (LCDCR0)

Read: anytime Write: LCDEN anytime. To avoid segment flicker the clock prescaler bits, the bias select bit and the duty select bits must not be changed when the LCD is enabled. Module Base + 0x0000 76543210 R LCDEN LCLK2 LCLK1 LCLK0 BIAS DUTY1 DUTY0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 10-2. LCD Control Register 0 (LCDCR0) Table 10-3. LCDCR0 Field Descriptions Field Description LCDEN LCD32F4BV1 Driver System Enable — The LCDEN bit starts the LCD waveform generator. 0 All frontplane and backplane pins are disabled. In addition, the LCD32F4BV1 system is disabled and all LCD waveform generation clocks are stopped. 1 LCD driver system is enabled. All FP[31:0] pins with FP[31:0]EN set, will output an LCD driver waveform The BP[3:0] pins will output an LCD32F4BV1 driver waveform based on the settings of DUTY0 and DUTY1. 5:3 LCLK[2:0] LCD Clock Prescaler— The LCD clock prescaler bits determine the OSCCLK divider value to produce the LCD clock frequency. For detailed description of the correlation between LCD clock prescaler bits and the divider value please refer to Table 10-7. BIAS BIAS Voltage Level Select — This bit selects the bias voltage levels during various LCD operating modes, as shown in Table 10-8. 1:0 DUTY[1:0] LCD Duty Select — The DUTY1 and DUTY0 bits select the duty (multiplex mode) of the LCD32F4BV1 driver system, as shown in Table 10-8.

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10.3.2.2 LCD Control Register 1 (LCDCR1)

Read: anytime Write: anytime

10.3.2.3 LCD Frontplane Enable Register 0–3 (FPENR0–FPENR3)

W Reset 0 0 0 00000 Unimplemented or Reserved Figure 10-3. LCD Control Register 1 (LCDCR1) Table 10-4. LCDCR1 Field Descriptions Field Description LCDSWAI LCD Stop in Wait Mode — This bit controls the LCD operation while in wait mode. 0 LCD operates normally in wait mode. 1 Stop LCD32F4BV1 driver system when in wait mode. LCDRPSTP LCD Run in Pseudo Stop Mode — This bit controls the LCD operation while in pseudo stop mode. 0 Stop LCD32F4BV1 driver system when in pseudo stop mode. 1 LCD operates normally in pseudo stop mode. Module Base + 0x0002 76543210 R FP7EN FP6EN FP5EN FP4EN FP3EN FP2EN FP1EN FP0EN W Reset 0 0 0 00000 Figure 10-4. LCD Frontplane Enable Register 0 (FPENR0) Module Base + 0x0003 76543210 R FP15EN FP14EN FP13EN FP12EN FP11EN FP10EN FP9EN FP8EN W Reset 0 0 0 00000 Figure 10-5. LCD Frontplane Enable Register 1 (FPENR1)

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 417 These bits enable the frontplane output waveform on the corresponding frontplane pin when LCDEN = 1. Read: anytime Write: anytime

10.3.2.4 LCD RAM (LCDRAM)

The LCD RAM consists of 16 bytes. After reset the LCD RAM contents will be indeterminate (I), as indicated by Figure 10-8. Module Base + 0x0004 76543210 R FP23EN FP22EN FP21EN FP20EN FP19EN FP18EN FP17EN FP16EN W Reset 0 0 0 00000 Figure 10-6. LCD Frontplane Enable Register 2 (FPENR2) Module Base + 0x0005 76543210 R FP31EN FP30EN FP29EN FP28EN FP27EN FP26EN FP25EN FP24EN W Reset 0 0 0 00000 Figure 10-7. LCD Frontplane Enable Register 3 (FPENR3) Table 10-5. FPENR0–FPENR3 Field Descriptions Field Description 31:0 FP[31:0]EN Frontplane Output Enable — The FP[31:0]EN bit enables the frontplane driver outputs. If LCDEN = 0, these bits have no effect on the state of the I/O pins. It is recommended to set FP[31:0]EN bits before LCDEN is set. 0 Frontplane driver output disabled on FP[31:0]. 1 Frontplane driver output enabled on FP[31:0]. 76543210 0x0008 R FP1BP3 FP1BP2 FP1BP1 FP1BP0 FP0BP3 FP0BP2 FP0BP1 FP0BP0 LCDRAM W Reset I I I I I I I I 0x0009 R FP3BP3 FP3BP2 FP3BP1 FP3BP0 FP2BP3 FP2BP2 FP2BP1 FP2BP0 LCDRAM W Reset I I I I I I I I 0x000A R FP5BP3 FP5BP2 FP5BP1 FP5BP0 FP4BP3 FP4BP2 FP4BP1 FP4BP0 LCDRAM W Reset I I I I I I I I I = Value is indeterminate Figure 10-8. LCD RAM (LCDRAM)

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FP7BP3 FP7BP2 FP7BP1 FP7BP0 FP6BP3 FP6BP2 FP6BP1 FP6BP0 LCDRAM W Reset I I I I I I I I 0x000C R FP9BP3 FP9BP2 FP9BP1 FP9BP0 FP8BP3 FP8BP2 FP8BP1 FP8BP0 LCDRAM W Reset I I I I I I I I 0x000D R FP11BP3 FP11BP2 FP11BP1 FP11BP0 FP10BP3 FP10BP2 FP10BP1 FP10BP0 LCDRAM W Reset I I I I I I I I 0x000E R FP13BP3 FP13BP2 FP13BP1 FP13BP0 FP12BP3 FP12BP2 FP12BP1 FP12BP0 LCDRAM W Reset I I I I I I I I 0x000F R FP15BP3 FP15BP2 FP15BP1 FP15BP0 FP14BP3 FP14BP2 FP14BP1 FP14BP0 LCDRAM W Reset I I I I I I I I 0x0010 R FP17BP3 FP17BP2 FP17BP1 FP17BP0 FP16BP3 FP16BP2 FP16BP1 FP16BP0 LCDRAM W Reset I I I I I I I I 0x0011 R FP19BP3 FP19BP2 FP19BP1 FP19BP0 FP18BP3 FP18BP2 FP18BP1 FP18BP0 LCDRAM W Reset I I I I I I I I 0x0012 R FP21BP3 FP21BP2 FP21BP1 FP21BP0 FP20BP3 FP20BP2 FP20BP1 FP20BP0 LCDRAM W Reset I I I I I I I I 0x0013 R FP23BP3 FP23BP2 FP23BP1 FP23BP0 FP22BP3 FP22BP2 FP22BP1 FP22BP0 LCDRAM W Reset I I I I I I I I 0x0014 R FP25BP3 FP25BP2 FP25BP1 FP25BP0 FP24BP3 FP24BP2 FP24BP1 FP24BP0 LCDRAM W Reset I I I I I I I I 0x0015 R FP27BP3 FP27BP2 FP27BP1 FP27BP0 FP26BP3 FP26BP2 FP26BP1 FP26BP0 LCDRAM W Reset I I I I I I I I 0x0016 R FP29BP3 FP29BP2 FP29BP1 FP29BP0 FP28BP3 FP28BP2 FP28BP1 FP28BP0 LCDRAM W Reset I I I I I I I I 0x0017 R FP31BP3 FP31BP2 FP31BP1 FP31BP0 FP30BP3 FP30BP2 FP30BP1 FP30BP0 LCDRAM W Reset I I I I I I I I I = Value is indeterminate Figure 10-8. LCD RAM (LCDRAM) (continued)

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 419 Read: anytime Write: anytime

10.4 Functional Description

This section provides a complete functional description of the LCD32F4BV1 block, detailing the operation of the design from the end user perspective in a number of subsections.

10.4.1 LCD Driver Description

10.4.1.1 Frontplane, Backplane, and LCD System During Reset

During a reset the following conditions exist:

• The LCD32F4BV1 system is configured in the default mode, 1/4 duty and 1/3 bias, that means all backplanes are used.
• All frontplane enable bits, FP[31:0]EN are cleared and the ON/OFF control for the display, the LCDEN bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high impedance state. The MCU pin state during reset is defined by the port integration module (PIM).

10.4.1.2 LCD Clock and Frame Frequency

The frequency of the oscillator clock (OSCCLK) and divider determine the LCD clock frequency. The divider is set by the LCD clock prescaler bits, LCLK[2:0], in the LCD control register 0 (LCDCR0). Table 10-7 shows the LCD clock and frame frequency for some multiplexed mode at OSCCLK = 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, and 0.5 MHz. Table 10-6. LCD RAM Field Descriptions Field Description 31:0 3:0 FP[31:0] BP[3:0] LCD Segment ON— The FP[31:0]BP[3:0] bit displays (turns on) the LCD segment connected between FP[31:0] and BP[3:0].

0 LCD segment OFF

1 LCD segment ON

Table 10-7. LCD Clock and Frame Frequency Oscillator Frequency in MHz LCD Clock Prescaler Divider LCD Clock Frequency [Hz] Frame Frequency [Hz] LCLK2 LCLK1 LCLK0 1/1 Duty 1/2 Duty 1/3 Duty 1/4 Duty OSCCLK = 0.5 0 1024 2048 488 244 488 244 244 122 163 122 OSCCLK = 1.0 0 2048 4096 488 244 488 244 244 122 163 122 OSCCLK = 2.0 0 4096 8192 488 244 488 244 244 122 163 122

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For other combinations of OSCCLK and divider not shown in Table 10-7, the following formula may be used to calculate the LCD frame frequency for each multiplex mode: The possible divider values are shown in Table 10-7.

10.4.1.3 LCD RAM

For a segment on the LCD to be displayed, data must be written to the LCD RAM which is shown in Section 10.3, “Memory Map and Register Definition”. The 128 bits in the LCD RAM correspond to the 128 segments that are driven by the frontplane and backplane drivers. Writing a 1 to a given location will result in the corresponding display segment being driven with a differential RMS voltage necessary to turn the segment ON when the LCDEN bit is set and the corresponding FP[31:0]EN bit is set. Writing a 0 to a given location will result in the corresponding display segment being driven with a differential RMS voltage necessary to turn the segment OFF. The LCD RAM is a dual port RAM that interfaces with the internal address and data buses of the MCU. It is possible to read from LCD RAM locations for scrolling purposes. When LCDEN = 0, the LCD RAM can be used as on-chip RAM. Writing or reading of the LCDEN bit does not change the contents of the LCD RAM. After a reset, the LCD RAM contents will be indeterminate.

10.4.1.4 LCD Driver System Enable and Frontplane Enable Sequencing

If LCDEN = 0 (LCD32F4BV1 driver system disabled) and the frontplane enable bit, FP[31:0]EN, is set, the frontplane driver waveform will not appear on the output until LCDEN is set. If LCDEN = 1 (LCD32F4BV1 driver system enabled), the frontplane driver waveform will appear on the output as soon as the corresponding frontplane enable bit, FP[31:0]EN, in the registers FPENR0–FPENR3 is set.

10.4.1.5 LCD Bias and Modes of Operation

The LCD32F4BV1 driver has five modes of operation:

• 1/1 duty (1 backplane), 1/1 bias (2 voltage levels)
• 1/2 duty (2 backplanes), 1/2 bias (3 voltage levels)
• 1/2 duty (2 backplanes), 1/3 bias (4 voltage levels) OSCCLK = 4.0 0 8192 16384 488 244 488 244 244 122 163 122 OSCCLK = 8.0 1 16384 32768 488 244 488 244 244 122 163 122 OSCCLK = 16.0 1 65536 131072 244 122 244 122 122 Table 10-7. LCD Clock and Frame Frequency Oscillator Frequency in MHz LCD Clock Prescaler Divider LCD Clock Frequency [Hz] Frame Frequency [Hz] LCLK2 LCLK1 LCLK0 1/1 Duty 1/2 Duty 1/3 Duty 1/4 Duty LCD Frame Frequency (Hz) OSCCLK (Hz)

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 421

• 1/3 duty (3 backplanes), 1/3 bias (4 voltage levels)
• 1/4 duty (4 backplanes), 1/3 bias (4 voltage levels) The voltage levels required for the different operating modes are generated internally based on VLCD. Changing VLCD alters the differential RMS voltage across the segments in the ON and OFF states, thereby setting the display contrast. The backplane waveforms are continuous and repetitive every frame. They are fixed within each operating mode and are not affected by the data in the LCD RAM. The frontplane waveforms generated are dependent on the state (ON or OFF) of the LCD segments as defined in the LCD RAM. The LCD32F4BV1 driver hardware uses the data in the LCD RAM to construct the frontplane waveform to create a differential RMS voltage necessary to turn the segment ON or OFF. The LCD duty is decided by the DUTY1 and DUTY0 bits in the LCD control register 0 (LCDCR0). The number of bias voltage levels is determined by the BIAS bit in LCDCR0. Table 10-8 summarizes the multiplex modes (duties) and the bias voltage levels that can be selected for each multiplex mode (duty). The backplane pins have their corresponding backplane waveform output BP[3:0] in high impedance state when in the OFF state as indicated in Table 10-8. In the OFF state the corresponding pins BP[3:0]can be used for other functionality, for example as general purpose I/O ports.

10.4.2 Operation in Wait Mode

The LCD32F4BV1 driver system operation during wait mode is controlled by the LCD stop in wait (LCDSWAI) bit in the LCD control register 1 (LCDCR1). If LCDSWAI is reset, the LCD32F4BV1 driver system continues to operate during wait mode. If LCDSWAI is set, the LCD32F4BV1 driver system is turned off during wait mode. In this case, the LCD waveform generation clocks are stopped and the LCD32F4BV1 drivers pull down to VSSX those frontplane and backplane pins that were enabled before entering wait mode. The contents of the LCD RAM and the LCD registers retain the values they had prior to entering wait mode.

10.4.3 Operation in Pseudo Stop Mode

The LCD32F4BV1 driver system operation during pseudo stop mode is controlled by the LCD run in pseudo stop (LCDRPSTP) bit in the LCD control register 1 (LCDCR1). If LCDRPSTP is reset, the LCD32F4BV1 driver system is turned off during pseudo stop mode. In this case, the LCD waveform generation clocks are stopped and the LCD32F4BV1 drivers pull down to VSSX those frontplane and backplane pins that were enabled before entering pseudo stop mode. If LCDRPSTP is set, the Table 10-8. LCD Duty and Bias Duty LCDCR0 Register Backplanes Bias (BIAS = 0) Bias (BIAS = 1) DUTY1 DUTY0 BP3 BP2 BP1 BP0 1/1 1/2 1/3 1/1 1/2 1/3 OFF OFF OFF BP3 OFF OFF BP2 BP2 OFF BP1 BP1 BP1 BP0 BP0 BP0 BP0 YES NA NA NA NA YES NA NA NA NA YES YES YES NA NA NA NA NA NA NA NA YES YES YES

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06

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LCD32F4BV1 driver system continues to operate during pseudo stop mode. The contents of the LCD RAM and the LCD registers retain the values they had prior to entering pseudo stop mode.

10.4.4 Operation in Stop Mode

All LCD32F4BV1 driver system clocks are stopped, the LCD32F4BV1 driver system pulls down to VSSX those frontplane and backplane pins that were enabled before entering stop mode. Also, during stop mode, the contents of the LCD RAM and the LCD registers retain the values they had prior to entering stop mode. As a result, after exiting from stop mode, the LCD32F4BV1 driver system clocks will run (if LCDEN = 1) and the frontplane and backplane pins retain the functionality they had prior to entering stop mode.

10.4.5 LCD Waveform Examples

Figure 10-9 through Figure 10-13 show the timing examples of the LCD output waveforms for the available modes of operation.

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 423 10.4.5.1 1/1 Duty Multiplexed with 1/1 Bias Mode Duty = 1/1:DUTY1 = 0, DUTY0 = 1 Bias = 1/1:BIAS = 0 or BIAS = 1 V0 = V1 = VSSX, V2 = V3 = VLCD - BP1, BP2, and BP3 are not used, a maximum of 32 segments are displayed. Figure 10-9. 1/1 Duty and 1/1 Bias VLCD VSSX BP0 +VLCD -VLCD BP0-FPx (OFF) +VLCD -VLCD BP0-FPy (ON) VLCD VSSX FPx (xxx0) VLCD VSSX FPy (xxx1)

1 Frame

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06

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10.4.5.2 1/2 Duty Multiplexed with 1/2 Bias Mode Duty = 1/2:DUTY1 = 1, DUTY0 = 0 Bias = 1/2:BIAS = 0 V0 = VSSX, V1 = V2 = VLCD * 1/2, V3 = VLCD - BP2 and BP3 are not used, a maximum of 64 segments are displayed. Figure 10-10. 1/2 Duty and 1/2 Bias VLCD VSSX BP0 +VLCD -VLCD BP0-FPx (OFF) VLCD × 1/2 VLCD VSSX BP1 VLCD VSSX FPx (xx10) VLCD VSSX FPy (xx00) VLCD VSSX FPz (xx11) +VLCD × 1/2 -VLCD × 1/2 +VLCD -VLCD BP1-FPx (ON) +VLCD × 1/2 -VLCD × 1/2 +VLCD -VLCD BP0-FPy (OFF) +VLCD × 1/2 -VLCD × 1/2 +VLCD -VLCD BP0-FPz (ON) +VLCD × 1/2 -VLCD × 1/2 VLCD × 1/2 VLCD × 1/2 VLCD × 1/2 VLCD × 1/2

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 425 10.4.5.3 1/2 Duty Multiplexed with 1/3 Bias Mode Duty = 1/2:DUTY1 = 1, DUTY0 = 0 Bias = 1/3:BIAS = 1 V0 = VSSX, V1 = VLCD * 1/3, V2 = VLCD * 2/3, V3 = VLCD - BP2 and BP3 are not used, a maximum of 64 segments are displayed. Figure 10-11. 1/2 Duty and 1/3 Bias -VLCD × 1/3 +VLCD × 1/3 -VLCD × 1/3 +VLCD × 1/3 -VLCD × 1/3 VLCD × 1/3 VLCD VSSX BP0 -VLCD BP0-FPx (OFF) VLCD × 2/3 +VLCD × 2/3 -VLCD × 2/3 VLCD VSSX BP1 VLCD × 2/3 VLCD VSSX FPx (xx10) VLCD × 2/3 VLCD VSSX FPy (xx00) VLCD × 2/3 VLCD VSSX FPz (xx11) VLCD × 2/3 +VLCD × 1/3 -VLCD × 1/3 +VLCD -VLCD BP1-FPx (ON) +VLCD × 2/3 -VLCD × 2/3 +VLCD × 1/3 +VLCD -VLCD BP0-FPy (OFF) +VLCD × 2/3 -VLCD × 2/3 +VLCD -VLCD BP0-FPz (ON) +VLCD × 2/3 -VLCD × 2/3 VLCD × 1/3 VLCD × 1/3 VLCD × 1/3 VLCD × 1/3 +VLCD

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06

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10.4.5.4 1/3 Duty Multiplexed with 1/3 Bias Mode Duty = 1/3:DUTY1 = 1, DUTY0 = 1 Bias = 1/3:BIAS = 0 or BIAS = 1 V0 = VSSX, V1 = VLCD * 1/3, V2 = VLCD * 2/3, V3 = VLCD - BP3 is not used, a maximum of 96 segments are displayed. Figure 10-12. 1/3 Duty and 1/3 Bias +VLCD × 1/3 -VLCD × 1/3 +VLCD × 1/3 -VLCD × 1/3 VLCD × 1/3 VLCD × 1/3 VLCD × 1/3 VLCD × 1/3 VLCD VSSX BP0 +VLCD -VLCD BP0-FPx (OFF) VLCD × 2/3 +VLCD × 2/3 -VLCD × 2/3 VLCD VSSX BP1 VLCD × 2/3 VLCD VSSX BP2 VLCD × 2/3 +VLCD -VLCD BP1-FPx (ON) +VLCD × 2/3 -VLCD × 2/3 VLCD VSSX FPx (x010) VLCD × 2/3

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 427 10.4.5.5 1/4 Duty Multiplexed with 1/3 Bias Mode Duty = 1/4:DUTY1 = 0, DUTY0 = 0 Bias = 1/3:BIAS = 0 or BIAS = 1 V0 = VSSX, V1 = VLCD * 1/3, V2 = VLCD * 2/3, V3 = VLCD - A maximum of 128 segments are displayed. Figure 10-13. 1/4 Duty and 1/3 Bias +VLCD × 1/3 -VLCD × 1/3 +VLCD × 1/3 -VLCD × 1/3 VLCD × 1/3 VLCD × 1/3 VLCD × 1/3 VLCD × 1/3 VLCD × 1/3 VLCD VSSX BP0 +VLCD -VLCD BP0-FPx (ON) VLCD × 2/3 +VLCD × 2/3 -VLCD × 2/3 VLCD VSSX BP1 VLCD × 2/3 VLCD VSSX BP2 VLCD × 2/3 +VLCD -VLCD BP1-FPx (OFF) +VLCD × 2/3 -VLCD × 2/3 VLCD VSSX FPx (1001) VLCD × 2/3 VLCD VSSX BP3 VLCD × 2/3

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06

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10.5 Resets

The reset values of registers and signals are described in Section 10.3, “Memory Map and Register Definition”. The behavior of the LCD32F4BV1 system during reset is described inSection 10.4.1, “LCD Driver Description”.

10.6 Interrupts

This module does not generate any interrupts.

MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 429 Chapter 11 Motor Controller (MC10B12CV2) Block Description

11.1 Introduction

The block MC10B12C is a PWM motor controller suitable to drive instruments in a cluster configuration or any other loads requiring a PWM signal. The motor controller has twelve PWM channels associated with two pins each (24 pins in total).

11.1.1 Features

The MC_10B12C includes the following features:

• 10/11-bit PWM counter
• 11-bit resolution with selectable PWM dithering function
• 7-bit resolution mode (fast mode): duty cycle can be changed by accessing only 1 byte/output
• Left, right, or center aligned PWM
• Output slew rate control
• This module is suited for, but not limited to, driving small stepper and air core motors used in instrumentation applications. This module can be used for other motor control or PWM applications that match the frequency, resolution, and output drive capabilities of the module.

11.1.2 Modes of Operation

11.1.2.1 Functional Modes

11.1.2.1.1 PWM Resolution

The motor controller can be configured to either 11- or 7-bits resolution mode by clearing or setting the Controller Duty Cycle Registers”.

11.1.2.1.2 Dither Function

Dither function can be selected or deselected by setting or clearing the DITH bit. This bit influences all

Chapter 11 Motor Controller (MC10B12CV2) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06

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11.1.2.2 PWM Channel Configuration Modes

The twelve PWM channels can operate in three functional modes. Those modes are, with some restrictions, selectable for each channel independently.

11.1.2.2.1 Dual Full H-Bridge Mode

This mode is suitable to drive a stepper motor or a 360o air gauge instrument. For details, please refer to are combined, and two PWM channels drive four pins.

11.1.2.2.2 Full H-Bridge Mode

This mode is suitable to drive any load requiring a PWM signal in a H-bridge configuration using two pins.

11.1.2.2.3 Half H-Bridge Mode

This mode is suitable to drive a 90o instrument driven by one pin. For details, please refer to

11.1.2.3 PWM Alignment Modes

Each PWM channel can operate independently in three different alignment modes. For details, please refer

11.1.2.4 Low-Power Modes

The behavior of the motor controller in low-power modes is programmable. For details, please refer to Section 11.4.5, “Operation in Wait Mode” and Section 11.4.6, “Operation in Stop and Pseudo-Stop Modes”.

Chapter 11 Motor Controller (MC10B12CV2) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 431

11.1.3 Block Diagram

Figure 11-1. MC10B12C Block Diagram Period Register 11-Bit Timer/Counter Duty Register 0 Comparator M0C0M M0C0P Duty Register 1 Comparator M0C1M M0C1P Duty Register 2 Comparator M1C0M M1C0P Duty Register 3 Comparator M1C1M M1C1P Duty Register 4 Comparator M2C0M M2C0P Duty Register 5 Comparator M2C1M M2C1P Duty Register 6 Comparator M3C0M M3C0P Duty Register 7 Comparator M3C1M M3C1P Control Registers FAST DITH PWM Channel Pair PWM Channel Duty Register 8 Comparator M4C0M M4C0P Duty Register 9 Comparator M4C1M M4C1P Duty Register 10 Comparator M5C0M M5C0P Duty Register 11 Comparator M5C1M M5C1P

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11.2 External Signal Description

The motor controller is associated with 24 pins. Table 11-1 lists the relationship between the PWM channels and signal pins as well as PWM channel pair (motor number), coils, and nodes they are supposed to drive if all channels are set to dual full H-bridge configuration.

11.2.1 M0C0M/M0C0P/M0C1M/M0C1P — PWM Output Pins for Motor 0

High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 0. PWM output on M0C0M results in a positive current flow through coil 0 when M0C0P is driven to a logic high state. PWM output on M0C1M results in a positive current flow through coil 1 when M0C1P is driven to a logic high state. Table 11-1. PWM Channel and Pin Assignment Pin Name PWM Channel PWM Channel Pair 1 1 A PWM Channel Pair always consists of PWM channel x and PWM channel x+1 (x = 2⋅n). The term “PWM Channel Pair” is equivalent to the term “Motor”. E.g. Channel Pair 0 is equivalent to Motor 0 Coil Node M0C0M 0 0 0 Minus M0C0P Plus M0C1M 1 1 Minus M0C1P Plus M1C0M 2 1 0 Minus M1C0P Plus M1C1M 3 1 Minus M1C1P Plus M2C0M 4 2 0 Minus M2C0P Plus M2C1M 5 1 Minus M2C1P Plus M3C0M 6 3 0 Minus M3C0P Plus M3C1M 7 1 Minus M3C1P Plus M4C0M 8 4 0 Minus M4C0P Plus M4C1M 9 1 Minus M4C1P Plus M5C0M 10 5 0 Minus M5C0P Plus M5C1M 11 1 Minus M5C1P Plus

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11.2.2 M1C0M/M1C0P/M1C1M/M1C1P — PWM Output Pins for Motor 1

High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 1. PWM output on M1C0M results in a positive current flow through coil 0 when M1C0P is driven to a logic high state. PWM output on M1C1M results in a positive current flow through coil 1 when M1C1P is driven to a logic high state.

11.2.3 M2C0M/M2C0P/M2C1M/M2C1P — PWM Output Pins for Motor 2

High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 2. PWM output on M2C0M results in a positive current flow through coil 0 when M2C0P is driven to a logic high state. PWM output on M2C1M results in a positive current flow through coil 1 when M2C1P is driven to a logic high state.

11.2.4 M3C0M/M3C0P/M3C1M/M3C1P — PWM Output Pins for Motor 3

High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 3. PWM output on M3C0M results in a positive current flow through coil 0 when M3C0P is driven to a logic high state. PWM output on M3C1M results in a positive current flow through coil 1 when M3C1P is driven to a logic high state.

11.2.5 M4C0M/M4C0P/M4C1M/M4C1P — PWM Output Pins for Motor 4

High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 4. PWM output on M4C0M results in a positive current flow through coil 0 when M4C0P is driven to a logic high state. PWM output on M4C1M results in a positive current flow through coil 1 when M4C1P is driven to a logic high state.

11.2.6 M5C0M/M5C0P/M5C1M/M5C1P — PWM Output Pins for Motor 5

High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 5. PWM output on M5C0M results in a positive current flow through coil 0 when M5C0P is driven to a logic high state. PWM output on M5C1M results in a positive current flow through coil 1 when M5C1P is driven to a logic high state.

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11.3 Memory Map and Register Definition

This section provides a detailed description of all registers of the 10-bit 12-channel motor controller module.

11.3.1 Module Memory Map

Table 11-2 shows the memory map of the 10-bit 12-channel motor controller module. Table 11-2. MC10B12C - Memory Map Address offset Use Access $00 MCCTL0 RW $01 MCCTL1 RW $02 MCPER (high byte) RW $03 MCPER (low byte) RW $04 Reserved - $05 Reserved - $06 Reserved - $07 Reserved - $08 Reserved - $09 Reserved - $0A Reserved - $0B Reserved - $0C Reserved - $0D Reserved - $0E Reserved - $0F Reserved - $10 MCCC0 RW $11 MCCC1 RW $12 MCCC2 RW $13 MCCC3 RW $14 MCCC4 RW $15 MCCC5 RW $16 MCCC6 RW $17 MCCC7 RW $18 MCCC8 RW $19 MCCC9 RW $1A MCCC10 RW $1B MCCC11 RW $1C Reserved - $1D Reserved - $1E Reserved - $1F Reserved - $20 MCDC0 (high byte) RW $21 MCDC0 (low byte) RW $22 MCDC1 (high byte) RW

Chapter 11 Motor Controller (MC10B12CV2) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 435 $23 MCDC1 (low byte) RW $24 MCDC2 (high byte) RW $25 MCDC2 (low byte) RW $26 MCDC3 (high byte) RW $27 MCDC3 (low byte) RW $28 MCDC4 (high byte) RW $29 MCDC4 (low byte) RW $2A MCDC5 (high byte) RW $2B MCDC5 (low byte) RW $2C MCDC6 (high byte) RW $2D MCDC6 (low byte) RW $2E MCDC7 (high byte) RW $2F MCDC7 (low byte) RW $30 MCDC8 (high byte) RW $31 MCDC8 (low byte) RW $32 MCDC9 (high byte) RW $33 MCDC9 (low byte) RW $34 MCDC10 (high byte) RW $35 MCDC10 (low byte) RW $36 MCDC11 (high byte) RW $37 MCDC11 (low byte) RW $38 Reserved - $39 Reserved - $3A Reserved - $3B Reserved - $3C Reserved - $3D Reserved - $3E Reserved - $3F Reserved - Table 11-2. MC10B12C - Memory Map

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11.3.2 Register Descriptions

11.3.2.1 Motor Controller Control Register 0

This register controls the operating mode of the motor controller module. Offset Module Base + 0x0000 76543210 MCPRE[1:0] MCSWAI FAST DITH MCTOIF W Reset 00000000 = Unimplemented or Reserved Figure 11-3. Motor Controller Control Register 0 (MCCTL0) Table 11-3. MCCTL0 Field Descriptions Field Description 6:5 MCPRE[1:0] Motor Controller Prescaler Select — MCPRE1 and MCPRE0 determine the prescaler value that sets the motor controller timer counter clock frequency (fTC). The clock source for the prescaler is the peripheral bus clock (fBUS) as shown in Figure 11-22. Writes to MCPRE1 or MCPRE0 will not affect the timer counter clock frequency fTC until the start of the next PWM period. Table 11-4 shows the prescaler values that result from the possible combinations of MCPRE1 and MCPRE0 MCSWAI Motor Controller Module Stop in Wait Mode 0 Entering wait mode has no effect on the motor controller module and the associated port pins maintain the functionality they had prior to entering wait mode both during wait mode and after exiting wait mode. 1 Entering wait mode will stop the clock of the module and debias the analog circuitry. The module will release the pins. FAST Motor Controller PWM Resolution Mode 0 PWM operates in 11-bit resolution mode, duty cycle registers of all channels are switched to word mode. 1 PWM operates in 7-bit resolution (fast) mode, duty cycle registers of all channels are switched to byte mode. DITH Motor Control/Driver Dither Feature Enable (refer to Section 11.4.1.3.5, “Dither Bit (DITH)”) 0 Dither feature is disabled. 1 Dither feature is enabled. MCTOIF Motor Controller Timer Counter Overflow Interrupt Flag — This bit is set when a motor controller timer counter overflow occurs. The bit is cleared by writing a 1 to the bit. 0 A motor controller timer counter overflow has not occurred since the last reset or since the bit was cleared. 1 A motor controller timer counter overflow has occurred. Table 11-4. Prescaler Values MCPRE[1:0] f TC 00 f Bus 01 f Bus/2 10 f Bus/4 11 f Bus/8

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11.3.2.2 Motor Controller Control Register 1

This register controls the behavior of the analog section of the motor controller as well as the interrupt enables. Offset Module Base + 0x0001 76543210 R RECIRC 000000 MCTOIE W Reset 00000000 = Unimplemented or Reserved Figure 11-4. Motor Controller Control Register 1 (MCCTL1) Table 11-5. MCCTL1 Field Descriptions Field Description RECIRC Recirculation in (Dual) Full H-Bridge Mode (refer to Section 11.4.1.3.3, “RECIRC Bit”)— RECIRC only affects the outputs in (dual) full H-bridge modes. In half H-bridge mode, the PWM output is always active low. RECIRC = 1 will also invert the effect of the S bits (refer to Section 11.4.1.3.2, “Sign Bit (S)”) in (dual) full H-bridge modes. RECIRC must be changed only while no PWM channel is operating in (dual) full H-bridge mode; otherwise, erroneous output pattern may occur. 0 Recirculation on the high side transistors. Active state for PWM output is logic low, the static channel will output logic high. 1 Recirculation on the low side transistors. Active state for PWM output is logic high, the static channel will output logic low. MCTOIE Motor Controller Timer Counter Overflow Interrupt Enable 0 Interrupt disabled. 1 Interrupt enabled. An interrupt will be generated when the motor controller timer counter overflow interrupt flag (MCTOIF) is set.

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11.3.2.3 Motor Controller Period Register

The period register defines PER, the number of motor controller timer counter clocks a PWM period lasts. The motor controller timer counter is clocked with the frequency fTC. If dither mode is enabled (DITH = 1, PER = 2 * D[10:1]. For example, programming MCPER to 0x0022 (PER = 34 decimal) will result in 34 counts for each complete PWM period. Setting MCPER to 0 will shut off all PWM channels as if MCAM[1:0] is set to 0 in all channel control registers after the next period timer counter overflow. In this case, the motor controller releases all pins. NOTE Programming MCPER to 0x0001 and setting the DITH bit will be managed as if MCPER is programmed to 0x0000. All PWM channels will be shut off after the next period timer counter overflow. Offset Module Base + 0x0002, 0x0003 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R 00000 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 11-5. Motor Controller Period Register (MCPER) with DITH = 0 Offset Module Base + 0x0002, 0x0003 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R 00000 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 11-6. Motor Controller Period Register (MCPER) with DITH = 1

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11.3.2.4 Motor Controller Channel Control Registers

Each PWM channel has one associated control register to control output delay, PWM alignment, and reference for all twelve registers. Offset Module Base + 0x0010 . . . 0x001B 76543210 R MCOM1 MCOM0 MCAM1 MCAM0 CD1 CD0 W Reset 00000000 = Unimplemented or Reserved Table 11-6. MCCC0–MCCC11 Field Descriptions Field Description 7:6 MCOM[1:0] Output Mode — MCOM1, MCOM0 control the PWM channel’s output mode. See Table 11-7. 5:4 MCAM[1:0] PWM Channel Alignment Mode — MCAM1, MCAM0 control the PWM channel’s PWM alignment mode and operation. See Table 11-8. MCAM[1:0] and MCOM[1:0] are double buffered. The values used for the generation of the output waveform will be copied to the working registers either at once (if all PWM channels are disabled or MCPER is set to 0) or if a timer counter overflow occurs. Reads of the register return the most recent written value, which are not necessarily the currently active values. 1:0 CD[1:0] PWM Channel Delay — Each PWM channel can be individually delayed by a programmable number of PWM timer counter clocks. The delay will be n/f TC. See Table 11-9. Table 11-7. Output Mode MCOM[1:0] Output Mode

00 Half H-bridge mode, PWM on MnCxM, MnCxP is released

01 Half H-bridge mode, PWM on MnCxP , MnCxM is released

10 Full H-bridge mode

11 Dual full H-bridge mode

Table 11-8. PWM Alignment Mode MCAM[1:0] PWM Alignment Mode

00 Channel disabled

01 Left aligned

10 Right aligned

11 Center aligned

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The PWM motor controller will release the pins after the next PWM timer counter overflow without accommodating any channel delay if a single channel has been disabled or if the period register has been cleared or all channels have been disabled. Program one or more inactive PWM frames (duty cycle = 0) before writing a configuration that disables a single channel or the entire PWM motor controller.

11.3.2.5 Motor Controller Duty Cycle Registers

Each duty cycle register sets the sign and duty functionality for the respective PWM channel. The contents of the duty cycle registers define DUTY , the number of motor controller timer counter clocks the corresponding output is driven low (RECIRC = 0) or is driven high (RECIRC = 1). Setting all bits to 0 will give a static high output in case of RECIRC = 0; otherwise, a static low output. Values greater than or equal to the contents of the period register will generate a static low output in case of RECIRC = 0, or a static high output if RECIRC = 1. The layout of the duty cycle registers differ dependent upon the state of the FAST bit in the control register 0. Table 11-9. Channel Delay CD[1:0] n [# of PWM Clocks] 00 0 01 1 10 2 11 3 Offset Module Base + 0x0020 . . . 0x0037 Access: User read/write 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R S SSSS D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 11-8. Motor Controller Duty Cycle Register x (MCDCx) with FAST = 0

Chapter 11 Motor Controller (MC10B12CV2) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 441 Whenever FAST = 1, the bits D10, D9, D1, and D0 will be set to 0 if the duty cycle register is written. For example setting MCDCx = 0x0158 with FAST = 0 gives the same output waveform as setting MCDCx = 0x5600 with FAST = 1 (with FAST = 1, the low byte of MCDCx needs not to be written). The state of the FAST bit has impact only during write and read operations. A change of the FAST bit (set or clear) without writing a new value does not impact the internal interpretation of the duty cycle values. To prevent the output from inconsistent signals, the duty cycle registers are double buffered. The motor controller module will use working registers to generate the output signals. The working registers are copied from the bus accessible registers at the following conditions:

• MCPER is set to 0 (all channels are disabled in this case)
• MCAM[1:0] of the respective channel is set to 0 (channel is disabled)
• A PWM timer counter overflow occurs while in half H-bridge or full H-bridge mode
• A PWM channel pair is configured to work in Dual Full H-Bridge mode and a PWM timer counter overflow occurs after the odd 1 duty cycle register of the channel pair has been written. In this way, the output of the PWM will always be either the old PWM waveform or the new PWM waveform, not some variation in between. Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active sign, duty cycle, and dither functionality due to the double buffering scheme. Offset Module Base + 0x0020 . . . 0x0037 Access: User read/write 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R S D 8D 7D 6D 5D 4D 3D 2 00000000 W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 11-9. Motor Controller Duty Cycle Register x (MCDCx) with FAST = 1 Table 11-10. MCDCx Field Descriptions Field Description S SIGN — The SIGN bit is used to define which output will drive the PWM signal in (dual) full-H-bridge modes. The detailed information about the impact of RECIRC and SIGN bit on the PWM output. 1. Odd duty cycle register: MCDCx+1, x = 2⋅n

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11.4 Functional Description

11.4.1 Modes of Operation

11.4.1.1 PWM Output Modes

The motor controller is configurable between three output modes.

• Dual full H-bridge mode can be used to control either a stepper motor or a 360° air core instrument. In this case two PWM channels are combined.
• In full H-bridge mode, each PWM channel is updated independently.
• In half H-bridge mode, one pin of the PWM channel can generate a PWM signal to control a 90 ° air core instrument (or other load requiring a PWM signal) and the other pin is unused. The mode of operation for each PWM channel is determined by the corresponding MCOM[1:0] bits in channel control registers. After a reset occurs, each PWM channel will be disabled, the corresponding pins are released. Each PWM channel consists of two pins. One output pin will generate a PWM signal. The other will operate as logic high or low output depending on the state of the RECIRC bit (refer toSection 11.4.1.3.3, “RECIRC Bit”), while in (dual) full H-bridge mode, or will be released, while in half H-bridge mode. The state of the S bit in the duty cycle register determines the pin where the PWM signal is driven in full H-bridge mode. While in half H-bridge mode, the state of the released pin is determined by other modules associated with this pin. Associated with each PWM channel pair n are two PWM channels, x and x + 1, where x = 2 * n and n (0,1,2... 5) is the PWM channel pair number. Duty cycle register x controls the sign of the PWM signal (which pin drives the PWM signal) and the duty cycle of the PWM signal for motor controller channel x. The pins associated with PWM channel x are MnC0P and MnC0M. Similarly, duty cycle register x + 1 controls the sign of the PWM signal and the duty cycle of the PWM signal for channel x + 1. The pins associated with PWM channel x + 1 are MnC1P and MnC1M. This is summarized in Table 11-11. Table 11-11. Corresponding Registers and Pin Names for each PWM Channel Pair PWM Channel Pair Number PWM Channel Control Register Duty Cycle Register Channel Number Pin Names n MCMCx MCDCx PWM Channel x, x = 2⋅n MnC0M MnC0P MCMCx+1 MCDCx+1 PWM Channel x+1, x = 2⋅n MnC1M MnC1P MCMC0 MCDC0 PWM Channel 0 M0C0M M0C0P MCMC1 MCDC1 PWM Channel 1 M0C1M M0C1P

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11.4.1.1.1 Dual Full H-Bridge Mode (MCOM = 11)

PWM channel pairs x and x + 1 operate in dual full H-bridge mode if both channels have been enabled (MCAM[1:0]=01, 10, or 11) and both of the corresponding output mode bits MCOM[1:0] in both PWM channel control registers are set. A typical configuration in dual full H-bridge mode is shown in Figure 11-10. PWM channel x drives the PWM output signal on either MnC0P or MnC0M. If MnC0P drives the PWM signal, MnC0M will be output either high or low depending on the RECIRC bit. If MnC0M drives the PWM signal, MnC0P will be an output high or low. PWM channel x + 1 drives the PWM output signal on either MnC1P or MnC1M. If MnC1P drives the PWM signal, MnC1M will be an output high or low. If MnC1M drives the PWM signal, MnC1P will be an output high or low. This results in motor recirculation currents on the high side drivers (RECIRC = 0) while the PWM signal is at a logic high level, or motor recirculation currents on the low side drivers (RECIRC = 1) while the PWM signal is at a logic low level. The pin driving the PWM signal is determined by the S (sign) bit in the corresponding duty cycle register and the state of the RECIRC bit. The value of the PWM duty cycle is determined by the value of the D[10:0] or D[8:2] bits respectively in the duty cycle register depending on the state of the FAST bit. MCMC2 MCDC2 PWM Channel 2 M1C0M M1C0P MCMC3 MCDC3 PWM Channel 3 M1C1M M1C1P MCMC4 MCDC4 PWM Channel 4 M2C0M M2C0P MCMC5 MCDC5 PWM Channel 5 M2C1M M2C1P MCMC6 MCDC6 PWM Channel 6 M3C0M M3C0P MCMC7 MCDC7 PWM Channel 7 M3C1M M3C1P MCMC8 MCDC8 PWM Channel 8 M4C0M M4C0P MCMC9 MCDC9 PWM Channel 9 M4C1M M4C1P MCMC10 MCDC10 PWM Channel 10 M5C0M M5C0P MCMC11 MCDC11 PWM Channel 11 M5C1M M5C1P Table 11-11. Corresponding Registers and Pin Names for each PWM Channel Pair PWM Channel Pair Number PWM Channel Control Register Duty Cycle Register Channel Number Pin Names

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Figure 11-10. Typical Dual Full H-Bridge Mode Configuration Whenever FAST = 0 only 16-bit write accesses to the duty cycle registers are allowed, 8-bit write accesses can lead to unpredictable duty cycles. While fast mode is enabled (FAST = 1), 8-bit write accesses to the high byte of the duty cycle registers are allowed, because only the high byte of the duty cycle register is used to determine the duty cycle. The following sequence should be used to update the current magnitude and direction for coil 0 and coil 1 of the motor to achieve consistent PWM output: 1. Write to duty cycle register x 2. Write to duty cycle register x + 1. At the next timer counter overflow, the duty cycle registers will be copied to the working duty cycle registers. Sequential writes to the duty cycle register x will result in the previous data being overwritten.

11.4.1.1.2 Full H-Bridge Mode (MCOM = 10)

In full H-bridge mode, the PWM channels x and x + 1 operate independently. The duty cycle working registers are updated whenever a timer counter overflow occurs.

11.4.1.1.3 Half H-Bridge Mode (MCOM = 00 or 01)

In half H-bridge mode, the PWM channels x and x + 1 operate independently. In this mode, each PWM channel can be configured such that one pin is released and the other pin is a PWM output. Figure 11-11 shows a typical configuration in half H-bridge mode. The two pins associated with each channel are switchable between released mode and PWM output dependent upon the state of the MCOM[1:0] bits in the MCCCx (channel control) register. See register description in Section 11.3.2.4, “Motor Controller Channel Control Registers”. In half H-bridge mode, the state of the S bit has no effect. PWM Channel x PWM Channel x + 1 MnC0P MnC0M MnC1P MnC1M Motor n, Coil 0 Motor n, Coil 1

Chapter 11 Motor Controller (MC10B12CV2) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 445 Figure 11-11. Typical Quad Half H-Bridge Mode Configuration

11.4.1.2 Relationship Between PWM Mode and PWM Channel Enable

The pair of motor controller channels cannot be placed into dual full H-bridge mode unless both motor controller channels have been enabled (MCAM[1:0] not equal to 00) and dual full H-bridge mode is selected for both PWM channels (MCOM[1:0] = 11). If only one channel is set to dual full H-bridge mode, this channel will operate in full H-bridge mode, the other as programmed.

11.4.1.3 Relationship Between Sign, Duty, Dither, RECIRC, Period,

11.4.1.3.1 PWM Alignment Modes

Each PWM channel can be programmed individually to three different alignment modes. The mode is determined by the MCAM[1:0] bits in the corresponding channel control register. Left aligned (MCAM[1:0] = 01): The output will start active (low if RECIRC = 0 or high if RECIRC = 1) and will turn inactive (high if RECIRC = 0 or low if RECIRC = 1) after the number of counts specified by the corresponding duty cycle register. PWM Channel x PWM Channel x + 1 MnC0P MnC0M MnC1P MnC1M Released PWM Output VSSM VDDM VSSM VDDM Released PWM Output

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Right aligned (MCAM[1:0] = 10): The output will start inactive (high if RECIRC = 0 and low if RECIRC = 1) and will turn active after the number of counts specified by the difference of the contents of period register and the corresponding duty cycle register. Center aligned (MCAM[1:0] = 11): Even periods will be output left aligned, odd periods will be output right aligned. PWM operation starts with the even period after the channel has been enabled. PWM operation in center aligned mode might start with the odd period if the channel has not been disabled before changing the alignment mode to center aligned. 0 15 PWM Output

1 Period

100 Counts

DITH = 0, MCAM[1:0] = 01, MCDCx = 15, MCPER = 100, RECIRC = 0 0 85 PWM Output DITH = 0, MCAM[1:0] = 10, MCDCx = 15, MCPER = 100, RECIRC = 0 0 85 PWM Output DITH = 0, MCAM[1:0] = 11, MCDCx = 15, MCPER = 100, RECIRC = 0

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11.4.1.3.2 Sign Bit (S)

Assuming RECIRC = 0 (the active state of the PWM signal is low), when the S bit for the corresponding channel is cleared, MnC0P (if the PWM channel number is even, n = 0, 1, 2...5, seeTable 11-11) or MnC1P (if the PWM channel number is odd, ,n = 0, 1, 2...5 see Table 11-11), outputs a logic high while in (dual) full H-bridge mode. In half H-bridge mode the state of the S bit has no effect. The PWM output signal is generated on MnC0M (if the PWM channel number is even, n = 0, 1, 2...5, see Table 11-11) or MnC1M (if the PWM channel number is odd, n = 0, 1, 2...5). Assuming RECIRC = 0 (the active state of the PWM signal is low), when the S bit for the corresponding channel is set, MnC0M (if the PWM channel number is even, n = 0, 1, 2...5, seeTable 11-11) or MnC1M (if the PWM channel number is odd, n = 0, 1, 2...5, see Table 11-11), outputs a logic high while in (dual) full H-bridge mode. In half H-bridge mode the state of the S bit has no effect. The PWM output signal is generated on MnC0P (if the PWM channel number is even, n = 0, 1, 2...5, seeTable 11-11) or MnC1P (if the PWM channel number is odd, n = 0, 1, 2...5). Setting RECIRC = 1 will also invert the effect of the S bit such that while S = 0, MnC0P or MnC1P will generate the PWM signal and MnC0M or MnC1M will be a static low output. While S = 1, MnC0M or MnC1M will generate the PWM signal and MnC0P or MnC1P will be a static low output. In this case the active state of the PWM signal will be high. See Table 11-12 for detailed information about the impact of SIGN and RECIRC bit on the PWM output.

11.4.1.3.3 RECIRC Bit

The RECIRC bit controls the flow of the recirculation current of the load. Setting RECIRC = 0 will cause recirculation current to flow through the high side transistors, and RECIRC = 1 will cause the recirculation current to flow through the low side transistors. The RECIRC bit is only active in (dual) full H-bridge modes. Effectively, RECIRC = 0 will cause a static high output on the output terminal not driven by the PWM, RECIRC = 1 will cause a static low output on the output terminals not driven by the PWM. To achieve the same current direction, the S bit behavior is inverted if RECIRC = 1. Figure 11-12, Figure 11-13, Figure 11-14, and Figure 11-15 illustrate the effect of the RECIRC bit in (dual) full H-bridge modes. Table 11-12. Impact of RECIRC and SIGN Bit on the PWM Output Output Mode RECIRC SIGN MnCyM MnCyP (Dual) Full H-Bridge 0 0 PWM1 Output P is static high. (Dual) Full H-Bridge 0 1 1 PWM (Dual) Full H-Bridge 1 0 0 PWM Output M is static low. (Dual) Full H-Bridge 1 1 PWM 1 Half H-Bridge: PWM on MnCyM Don’t care Don’t care PWM — 3 3 The state of the output transistors is not controlled by the motor controller. Half H-Bridge: PWM on MnCyP Don’t care Don’t care — PWM

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RECIRC bit must be changed only while no PWM channel is operated in (dual) full H-bridge mode. Figure 11-12. PWM Active Phase, RECIRC = 0, S = 0 Figure 11-13. PWM Passive Phase, RECIRC = 0, S = 0 VDDM VSSM MnC0P MnC0M Static 0 PWM 1 PWM 1Static 0 VDDM VSSM MnC0P MnC0M Static 0 PWM 0 Static 0 PWM 0

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11.4.1.3.4 Relationship Between RECIRC Bit, S Bit, MCOM Bits, PWM State, and Output

Please refer to Figure 11-16 for the output transistor assignment. Figure 11-16. Output Transistor Assignment Table 11-13 illustrates the state of the output transistors in different states of the PWM motor controller module. ‘—’ means that the state of the output transistor is not controlled by the motor controller. Table 11-13. State of Output Transistors in Various Modes Mode MCOM[1:0] PWM Duty RECIRC S T1 T2 T3 T4 Off Don’t care — Don’t care Don’t care — — — — Half H-Bridge 00 Active Don’t care Don’t care — — OFF ON Half H-Bridge 00 Passive Don’t care Don’t care — — ON OFF Half H-Bridge 01 Active Don’t care Don’t care OFF ON — — Half H-Bridge 01 Passive Don’t care Don’t care ON OFF — — (Dual) Full 10 or 11 Active 0 0 ON OFF OFF ON (Dual) Full 10 or 11 Passive 0 0 ON OFF ON OFF (Dual) Full 10 or 11 Active 0 1 OFF ON ON OFF (Dual) Full 10 or 11 Passive 0 1 ON OFF ON OFF (Dual) Full 10 or 11 Active 1 0 ON OFF OFF ON (Dual) Full 10 or 11 Passive 1 0 OFF ON OFF ON (Dual) Full 10 or 11 Active 1 1 OFF ON ON OFF (Dual) Full 10 or 11 Passive 1 1 OFF ON OFF ON VDDM VSSM MnCyP MnCyM

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11.4.1.3.5 Dither Bit (DITH)

The purpose of the dither mode is to increase the minimum length of output pulses without decreasing the PWM resolution, in order to limit the pulse distortion introduced by the slew rate control of the outputs. If dither mode is selected the output pattern will repeat after two timer counter overflows. For the same output frequency, the shortest output pulse will have twice the length while dither feature is selected. To achieve the same output frame frequency, the prescaler of the MC10B12C module has to be set to twice the division rate if dither mode is selected; e.g., with the same prescaler division rate the repeat rate of the output pattern is the same as well as the shortest output pulse with or without dither mode selected. The DITH bit in control register 0 enables or disables the dither function. DITH = 0: dither function is disabled. When DITH is cleared and assuming left aligned operation and RECIRC = 0, the PWM output will start at a logic low level at the beginning of the PWM period (motor controller timer counter = 0x000). The PWM output remains low until the motor controller timer counter matches the 11-bit PWM duty cycle value, DUTY , contained in D[10:0] in MCDCx. When a match (output compare between motor controller timer counter and DUTY) occurs, the PWM output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reaches the contents of MCPER – 1). After the motor controller timer counter resets to 0x000, the PWM output will return to a logic low level. This completes one PWM period. The PWM period repeats every P counts (as defined by the bits P[10:0] in the motor controller period register) of the motor controller timer counter. If DUTY >= P, the output will be static low. If DUTY = 0x0000, the output will be continuously at a logic high level. The relationship between the motor controller timer counter clock, motor controller timer counter value, and PWM output while DITH = 0 is shown in Figure 11-17. Figure 11-17. PWM Output: DITH = 0, MCAM[1:0] = 01, MCDC = 100, MCPER = 200, RECIRC = 0 DITH = 1: dither function is enabled Please note if DITH = 1, the bit P0 in the motor controller period register will be internally forced to 0 and read always as 0. When DITH is set and assuming left aligned operation and RECIRC = 0, the PWM output will start at a logic low level at the beginning of the PWM period (when the motor controller timer counter = 0x000). The PWM output remains low until the motor controller timer counter matches the 10-bit PWM duty cycle 0 100 0 100 0 PWM Output

200 Counts 200 Counts

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value, DUTY , contained in D[10:1] in MCDCx. When a match (output compare between motor controller timer counter and DUTY) occurs, the PWM output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reaches the value defined by P[10:1] – 1 in MCPER). After the motor controller timer counter resets to 0x000, the PWM output will return to a logic low level. This completes the first half of the PWM period. During the second half of the PWM period, the PWM output will remain at a logic low level until either the motor controller timer counter matches the 10-bit PWM duty cycle value, DUTY , contained in D[10:1] in MCDCx if D0 = 0, or the motor controller timer counter matches the 10-bit PWM duty cycle value + 1 (the value of D[10:1] in MCDCx is increment by 1 and is compared with the motor controller timer counter value) if D0 = 1 in the corresponding duty cycle register. When a match occurs, the PWM output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reaches the value defined by P[10:1] – 1 in MCPER). After the motor controller timer counter resets to 0x000, the PWM output will return to a logic low level. This process will repeat every number of counts of the motor controller timer counter defined by the period register contents (P[10:0]). If the output is neither set to 0% nor to 100% there will be four edges on the PWM output per PWM period in this case. Therefore, the PWM output compare function will alternate between DUTY and DUTY + 1 every half PWM period if D0 in the corresponding duty cycle register is set to 1. The relationship between the motor controller timer counter clock (f TC), motor controller timer counter value, and left aligned PWM output if DITH = 1 is shown in Figure 11-18 and Figure 11-19. Figure 11-20 and Figure 11-21 show right aligned and center aligned PWM operation respectively, with dither feature enabled and D0 = 1. Please note: In the following examples, the MCPER value is defined by the bits P[10:0], which is, if DITH = 1, always an even number. NOTE The DITH bit must be changed only if the motor controller is disabled (all channels disabled or period register cleared) to avoid erroneous waveforms. Figure 11-18. PWM Output: DITH = 1, MCAM[1:0] = 01, MCDC = 31, MCPER = 200, RECIRC = 0 0 15 PWM Output 16 0

Chapter 11 Motor Controller (MC10B12CV2) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 453 Figure 11-19. PWM Output: DITH = 1, MCAM[1:0] = 01, MCDC = 30, MCPER = 200, RECIRC = 0 Figure 11-20. PWM Output: DITH = 1, MCAM[1:0] = 10, MCDC = 31, MCPER = 200, RECIRC = 0 Figure 11-21. PWM Output: DITH = 1, MCAM[1:0] = 11, MCDC = 31, MCPER = 200, RECIRC = 0 PWM Output

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11.4.2 PWM Duty Cycle

The PWM duty cycle for the motor controller channel x can be determined by dividing the decimal representation of bits D[10:0] in MCDCx by the decimal representation of the bits P[10:0] in MCPER and multiplying the result by 100% as shown in the equation below: NOTE x = PWM Channel Number = 0, 1, 2, 3 ... 11. This equation is only valid if DUTY <= MCPER and MCPER is not equal to 0. Whenever D[10:0] >= P[10:0], a constant low level (RECIRC = 0) or high level (RECIRC = 1) will be output.

11.4.3 Motor Controller Counter Clock Source

Figure 11-22 shows how the PWM motor controller timer counter clock source is selected. Figure 11-22. Motor Controller Counter Clock Selection The peripheral bus clock is the source for the motor controller counter prescaler. The motor controller counter clock rate, fTC, is set by selecting the appropriate prescaler value. The prescaler is selected with the MCPRE[1:0] bits in motor controller control register 0 (MCCTL0). The motor controller channel frequency of operation can be calculated using the following formula if DITH = 0: Effective PWM Channel X % Duty Cycle DUTY Motor Controller Timer Counter Prescaler Motor Controller Timer Counter Clock Prescaler Select MPPRE0, MPPRE1 11-Bit Motor Controller Timer Counter Peripheral Bus Clock fBUS Clock Generator CLK Clocks and Reset Generator Module Motor Controller Timer Counter Clock f TC Motor Channel Frequency (Hz) fTC

Chapter 11 Motor Controller (MC10B12CV2) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 455 The motor controller channel frequency of operation can be calculated using the following formula if DITH = 1: NOTE Both equations are only valid if MCPER is not equal to 0. M = 1 for left or right aligned mode, M = 2 for center aligned mode. Table 11-14 shows examples of the motor controller channel frequencies that can be generated based on different peripheral bus clock frequencies and the prescaler value. NOTE Due to the selectable slew rate control of the outputs, clipping may occur on short output pulses.

11.4.4 Output Switching Delay

In order to prevent large peak current draw from the motor power supply, selectable delays can be used to stagger the high logic level to low logic level transitions on the motor controller outputs. The timing delay, t d, is determined by the CD[1:0] bits in the corresponding channel control register (MCMCx) and is selectable between 0, 1, 2, or 3 motor controller timer counter clock cycles. NOTE A PWM channel gets disabled at the next timer counter overflow without notice of the switching delay. Table 11-14. Motor Controller Channel Frequencies (Hz), MCPER = 256, DITH = 0, MCAM = 10, 01 Prescaler Peripheral Bus Clock Frequency

16 MHz 10 MHz 8 MHz 5 MHz 4 MHz

1 62500 39063 31250 19531 15625 1/2 31250 19531 15625 9766 7813 1/4 15625 9766 7813 4883 3906 1/8 7813 4883 3906 2441 1953 Motor Channel Frequency (Hz) fTC

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11.4.5 Operation in Wait Mode

During wait mode, the operation of the motor controller pins are selectable between the following two options: 1. MCSW AI = 1: All module clocks are stopped and the associated port pins are set to their inactive state, which is defined by the state of the RECIRC bit during wait mode. The motor controller module registers stay the same as they were prior to entering wait mode. Therefore, after exiting from wait mode, the associated port pins will resume to the same functionality they had prior to entering wait mode. 2. MCSW AI = 0: The PWM clocks continue to run and the associated port pins maintain the functionality they had prior to entering wait mode both during wait mode and after exiting wait mode.

11.4.6 Operation in Stop and Pseudo-Stop Modes

All module clocks are stopped and the associated port pins are set to their inactive state, which is defined by the state of the RECIRC bit. The motor controller module registers stay the same as they were prior to entering stop or pseudo-stop modes. Therefore, after exiting from stop or pseudo-stop modes, the associated port pins will resume to the same functionality they had prior to entering stop or pseudo-stop modes.

11.5 Reset

The motor controller is reset by system reset. All associated ports are released, all registers of the motor controller module will switch to their reset state as defined in Section 11.3.2, “Register Descriptions”.

11.6 Interrupts

The motor controller has one interrupt source.

11.6.1 Timer Counter Overflow Interrupt

An interrupt will be requested when the MCTOIE bit in the motor controller control register 1 is set and the running PWM frame is finished. The interrupt is cleared by either setting the MCTOIE bit to 0 or to write a 1 to the MCTOIF bit in the motor controller control register 0.

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11.7 Initialization/Application Information

This section provides an example of how the PWM motor controller can be initialized and used by application software. The configuration parameters (e.g., timer settings, duty cycle values, etc.) are not guaranteed to be adequate for any real application. The example software is implemented in assembly language.

11.7.1 Code Example

One way to use the motor controller is: 1. Perform global initialization a) Set the motor controller control registers MCCTL0 and MCCTL1 to appropriate values. i) Prescaler disabled (MCPRE1 = 0, MCPRE0 = 0). ii) Fast mode and dither disabled (FAST = 0, DITH = 0). iii) Recirculation feature in dual full H-bridge mode disabled (RECIRC = 0). All other bits in MCCTL0 and MCCTL1 are set to 0. b) Configure the channel control registers for the desired mode. i) Dual full H-bridge mode (MCOM[1:0] = 11). ii) Left aligned PWM (MCAM[1:0] = 01). iii) No channel delay (MCCD[1:0] = 00). 2. Perform the startup phase a) Clear the duty cycle registers MCDC0 and MCDC1 b) Initialize the period register MCPER, which is equivalent to enabling the motor controller. c) Enable the timer which generates the timebase for the updates of the duty cycle registers. 3. Main program a) Check if pin PB0 is set to “1” and execute the sub program if a timer interrupt is pending. b) Initiate the shutdown procedure if pin PB0 is set to “0”. 4. Sub program a) Update the duty cycle registers Load the duty cycle registers MCDC0 and MCDC1 with new values from the table and clear the timer interrupt flag. The sub program will initiate the shutdown procedure if pin PB0 is set to “0”. b) Shutdown procedure The timer is disabled and the duty cycle registers are cleared to drive an inactive value on the PWM output as long as the motor controller is enabled. The period register is cleared after a certain time, which disables the motor controller. The table address is restored and the timer interrupt flag is cleared.

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; Motor Controller (MC10B8C) setup example ; Timer defines T_START EQU $0040 TSCR1 EQU T_START+$06 TFLG2 EQU T_START+$0F ; Motor Controller defines MC_START EQU $0200 MCCTL0 EQU MC_START+$00 MCCTL1 EQU MC_START+$01 MCPER_HI EQU MC_START+$02 MCPER_LO EQU MC_START+$03 MCCC0 EQU MC_START+$10 MCCC1 EQU MC_START+$11 MCCC2 EQU MC_START+$12 MCCC3 EQU MC_START+$13 MCDC0_HI EQU MC_START+$20 MCDC0_LO EQU MC_START+$21 MCDC1_HI EQU MC_START+$22 MCDC1_LO EQU MC_START+$23 MCDC2_HI EQU MC_START+$24 MCDC2_LO EQU MC_START+$25 MCDC3_HI EQU MC_START+$26 MCDC3_LO EQU MC_START+$27 ; Port defines DDRB EQU $0003 PORTB EQU $0001 ; Flash defines FLASH_START EQU $0100 FCMD EQU FLASH_START+$06 FCLKDIV EQU FLASH_START+$00 FSTAT EQU FLASH_START+$05 FTSTMOD EQU FLASH_START+$02 ; Variables CODE_START EQU $1000 ; start of program code DTYDAT EQU $1500 ; start of motor controller duty cycle data TEMP_X EQU $1700 ; save location for IX reg in ISR TABLESIZE EQU $1704 ; number of config entries in the table MCPERIOD EQU $0250 ; motor controller period ORG CODE_START ; start of code LDS #$1FFF ; set stack pointer MOVW #$000A,TABLESIZE ; number of configurations in the table MOVW TABLESIZE,TEMP_X

Chapter 11 Motor Controller (MC10B12CV2) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 459 ;global motor controller init GLB_INIT: MOVB #$0000,MCCTL0 ; fMC = fBUS, FAST=0, DITH=0 MOVB #$0000,MCCTL1 ; RECIRC=0, MCTOIE=0 MOVW #$D0D0,MCCC0 ; dual full h-bridge mode, left aligned, ; no channel delay MOVW #$0000,MCPER_HI ; disable motor controller ;motor controller startup STARTUP: MOVW #$0000,MCDC0_HI ; define startup duty cycles MOVW #$0000,MCDC1_HI MOVW #MCPERIOD,MCPER_HI ; define PWM period MOVB #$80,TSCR1 ; enable timer MAIN: LDAA PORTB ; if PB=0, activate shutdown ANDA #$01 BEQ MN0 JSR TIM_SR MN0: TST TFLG2 ; poll for timer counter overflow flag BEQ MAIN ; TOF set? JSR TIM_SR ; yes, go to TIM_SR BRA MAIN TIM_SR: LDX TEMP_X ; restore index register X LDAA PORTB ; if PB=0, enter shutdown routine ANDA #$01 BNE SHUTDOWN LDX TEMP_X ; restore index register X BEQ NEW_SEQ ; all mc configurations done? NEW_CFG: LDD DTYDAT,X ; load new config’s STD MCDC0_HI DEX DEX LDD DTYDAT,X STD MCDC1_HI BRA END_SR ; leave sub-routine SHUTDOWN: MOVB #$00,TSCR1 ; disable timer MOVW #$0000,MCDC0_HI ; define startup duty cycle MOVW #$0000,MCDC1_HI ; define startup duty cycle LDAA #$0000 ; ensure that duty cycle registers are ; cleared for some time before disabling ; the motor controller LOOP DECA BNE LOOP MOVW #$0000,MCPER_HI ; define pwm period NEW_SEQ: MOVW TABLESIZE,TEMP_X ; start new tx loop LDX TEMP_X END_SR: STX TEMP_X ; save byte counter MOVB #$80,TFLG2 ; clear TOF RTS ; wait for new timer overflow

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; motor controller duty cycles org DTYDAT DC.B $02, $FF 1; MCDC1_HI, MCDC1_LO DC.B $02, $D0 ; MCDC0_HI, MCDC0_LO DC.B $02, $A0 ; MCDC1_HI, MCDC1_LO DC.B $02, $90 ; MCDC0_HI, MCDC0_LO DC.B $02, $60 ; MCDC1_HI, MCDC1_LO DC.B $02, $25 ; MCDC0_HI, MCDC0_LO 1. The values for the duty cycle table have to be defined for the needs of the target application.

MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 461 Chapter 12 Stepper Stall Detector (SSDV1) Block Description

12.1 Introduction

The stepper stall detector (SSD) block provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (RTZ). During the RTZ event, the pointer is returned to zero using full steps in either clockwise or counter clockwise direction, where only one coil is driven at any point in time. The back electromotive force (EMF) signal present on the non-driven coil is integrated after a blanking time, and its results stored in a 16-bit accumulator. The 16-bit modulus down counter can be used to monitor the blanking time and the integration time. The value in the accumulator represents the change in linked flux (magnetic flux times the number of turns in the coil) and can be compared to a stored threshold. Values above the threshold indicate a moving motor, in which case the pointer can be advanced another full step in the same direction and integration be repeated. Values below the threshold indicate a stalled motor, thereby marking the cessation of the RTZ event. The SSD is capable of multiplexing two stepper motors.

12.1.1 Modes of Operation

• Return to zero modes — Blanking with no drive — Blanking with drive — Conversion — Integration
• Low-power modes

12.1.2 Features

• Programmable full step state
• Programmable integration polarity
• Blanking (recirculation) state
• 16-bit integration accumulator register
• 16-bit modulus down counter with interrupt
• Multiplex two stepper motors

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12.1.3 Block Diagram

Figure 12-1. SSD Block Diagram Coil SINx Coil COSx Bus Clock VDDM COSxP COSxM VSSM 1/2 1/21/21/8 4:1 MUX VDDM VSSM S1 S3 S2 S4 VDDM SINxP SINxM VSSM VDDM VSSM S5 S7 S6 S8 16-bit accumulator register VDDM VSSM DFF 16-bit modulus down counter 16-bit load register sigma-delta converter P A D P A D P A D P A D integrator reference 2:1 MUX x = A or B DAC (analog)

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12.2 External Signal Description

Each SSD signal is the output pin of a half bridge, designed to source or sink current. The H-bridge pins drive the sine and cosine coils of a stepper motor to provide four-quadrant operation. The SSD is capable of multiplexing between stepper motor A and stepper motor B if two motors are connected.

12.2.1 COSxM/COSxP — Cosine Coil Pins for Motor x

These pins interface to the cosine coils of a stepper motor to measure the back EMF for calibration of the pointer reset position.

12.2.2 SINxM/SINxP — Sine Coil Pins for Motor x

These pins interface to the sine coils of a stepper motor to measure the back EMF for calibration of the pointer reset position. Table 12-1. Pin Table1 1 x = A or B indicating motor A or motor B Pin Name Node Coil COSxM Minus COSx COSxP Plus SINxM Minus SINx SINxP Plus

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12.3 Memory Map and Register Definition

This section provides a detailed description of all registers of the stepper stall detector (SSD) block.

12.3.1 Module Memory Map

Table 12-2gives an overview of all registers in the SSDV1 memory map. The SSDV1 occupies eight bytes in the memory space. The register address results from the addition ofbase addressand address offset.The base address is determined at the MCU level and is given in the Device Overview chapter. Theaddress offset is defined at the block level and is given here.

12.3.2 Register Descriptions

This section describes in detail all the registers and register bits in the SSDV1 block. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Table 12-2. SSDV1 Memory Map Address Offset Use Access 0x0000 RTZCTL R/W 0x0001 MDCCTL R/W 0x0002 SSDCTL R/W 0x0003 SSDFLG R/W 0x0004 MDCCNT (High) R/W 0x0005 MDCCNT (Low) R/W 0x0006 ITGACC (High) R 0x0007 ITGACC (Low) R

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12.3.2.1 Return-to-Zero Control Register (RTZCTL)

Read: anytime Write: anytime Module Base + 0x0000 76543210 R ITG DCOIL RCIR POL SMS STEP W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 12-2. Return-to-Zero Control Register (RTZCTL) Table 12-3. RTZCTL Field Descriptions Field Description ITG Integration — During return to zero (RTZE = 1), one of the coils must be recirculated or non-driven determined by the STEP field. If the ITG bit is set, the coil is non-driven, and if the ITG bit is clear, the coil is being recirculated. Table 12-4 shows the condition state of each transistor from Figure 12-1 based on the STEP , ITG, DCOIL and RCIR bits. Regardless of the RTZE bit value, if the ITG bit is set, one end of the non-driven coil connects to the (non-zero) reference input and the other end connects to the integrator input of the sigma-delta converter. Regardless of the RTZE bit value, if the ITG bit is clear, the non-driven coil is in a blanking state, the converter is in a reset state, and the accumulator is initialized to zero. Table 12-5shows the condition state of each switch from Figure 12-1 based on the ITG, STEP and POL bits.

0 Blanking

1 Integration

Drive Coil — During return to zero (RTZE=1), one of the coils must be driven determined by the STEP field. If the DCOIL bit is set, this coil is driven. If the DCOIL bit is clear, this coil is disconnected or drivers turned off. Table 12-4 shows the condition state of each transistor from Figure 12-1 based on the STEP , ITG, DCOIL and RCIR bits.

0 Disconnect Coil

1 Drive Coil

Recirculation in Blanking Mode — During return to zero (RTZE = 1), one of the coils is recirculated prior to integration during the blanking period. This bit determines if the coil is recirculated via VDDM or via VSSM. Table 12-4 shows the condition state of each transistor from Figure 12-1 based on the STEP , ITG, DCOIL and RCIR bits.

0 Recirculation on the high side transistors

1 Recirculation on the low side transistors

Polarity — This bit determines which end of the non-driven coil is routed to the sigma-delta converter during conversion or integration mode.Table 12-5shows the condition state of each switch fromFigure 12-1 based on the ITG, STEP and POL bits.

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Stepper Motor Select — This bit selects one of two possible stepper motors to be used for stall detection. See top level chip description for the stepper motor assignments to the SSD.

0 Stepper Motor A is selected for stall detection

1 Stepper Motor B is selected for stall detection

1:0 STEP Full Step State — This field indicates one of the four possible full step states. Step 0 is considered the east pole or 0° angle, step 1 is the north Pole or 90° angle, step 2 is the west pole or 180° angle, and step 3 is the south pole or 270° angle. For each full step state, Table 12-6shows the current through each of the two coils, and the coil nodes that are multiplexed to the sigma-delta converter during conversion or integration mode. Table 12-4. Transistor Condition States (RTZE = 1) STEP ITG DCOIL RCIR T1 T2 T3 T4 T5 T6 T7 T8 xx 1 0 x OFF OFF OFF OFF OFF OFF OFF OFF 00 0 0 0 OFF OFF OFF OFF ON OFF ON OFF 00 0 0 1 OFF OFF OFF OFF OFF ON OFF ON 00 0 1 0 ON OFF OFF ON ON OFF ON OFF 00 0 1 1 ON OFF OFF ON OFF ON OFF ON 00 1 1 x ON OFF OFF ON OFF OFF OFF OFF 01 0 0 0 ON OFF ON OFF OFF OFF OFF OFF 01 0 0 1 OFF ON OFF ON OFF OFF OFF OFF 01 0 1 0 ON OFF ON OFF ON OFF OFF ON 01 0 1 1 OFF ON OFF ON ON OFF OFF ON 01 1 1 x OFF OFF OFF OFF ON OFF OFF ON 10 0 0 0 OFF OFF OFF OFF ON OFF ON OFF 10 0 0 1 OFF OFF OFF OFF OFF ON OFF ON 10 0 1 0 OFF ON ON OFF ON OFF ON OFF 10 0 1 1 OFF ON ON OFF OFF ON OFF ON 10 1 1 x OFF ON ON OFF OFF OFF OFF OFF 11 0 0 0 ON OFF ON OFF OFF OFF OFF OFF 11 0 0 1 OFF ON OFF ON OFF OFF OFF OFF 11 0 1 0 ON OFF ON OFF OFF ON ON OFF 11 0 1 1 OFF ON OFF ON OFF ON ON OFF 11 1 1 x OFF OFF OFF OFF OFF ON ON OFF Table 12-3. RTZCTL Field Descriptions (continued) Field Description

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12.3.2.2 Modulus Down Counter Control Register (MDCCTL)

Read: anytime Write: anytime. Table 12-5. Switch Condition States (RTZE = 1 or 0) ITG STEP POL S1 S2 S3 S4 S5 S6 S7 S8 0 xx x Open Open Open Open Open Open Open Open 1 00 0 Open Open Open Open Close Open Open Close 1 00 1 Open Open Open Open Open Close Close Open 1 01 0 Open Close Close Open Open Open Open Open 1 01 1 Close Open Open Close Open Open Open Open 1 10 0 Open Open Open Open Open Close Close Open 1 10 1 Open Open Open Open Close Open Open Close 1 11 0 Close Open Open Close Open Open Open Open 1 11 1 Open Close Close Open Open Open Open Open Table 12-6. Full Step States STEP Pole Angle COSINE Coil Current SINE Coil Current Coil Node to Integrator input (Close Switch) Coil Node to Reference input (Close Switch) DCOIL = 0 DCOIL = 1 DCOIL = 0 DCOIL = 1 ITG = 1 POL = 0 ITG = 1 POL = 1 ITG = 1 POL = 0 ITG = 1 POL = 1

0 East 0 ° 0 + I max 0 0 SINxM (S8) SINxP (S6) SINxP (S5) SINxM (S7)

1 North 90 ° 0 0 0 + I max COSxP (S2) COSxM (S4) COSxM (S3) COSxP (S1)

2 West 180 ° 0 – I max 0 0 SINxP (S6) SINxM (S8) SINxM (S7) SINxP (S5)

3 South 270 ° 0 0 0 – I max COSxM (S4) COSxP (S2) COSxP (S1) COSxM (S3)

R MCZIE MODMC RDMCL PRE MCEN AOVIE W FLMC Reset 0 0 0 00000 = Unimplemented or Reserved Figure 12-3. Modulus Down Counter Control Register (MDCCTL)

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12.3.2.3 Stepper Stall Detector Control Register (SSDCTL)

Read: anytime Write: anytime Table 12-7. MDCCTL Field Descriptions Field Description MCZIE Modulus Counter Underflow Interrupt Enable 0 Interrupt disabled. 1 Interrupt enabled. An interrupt will be generated when the modulus counter underflow interrupt flag (MCZIF) is set. MODMC Modulus Mode Enable 0 The modulus counter counts down from the value in the counter register and will stop at 0x0000. 1 Modulus mode is enabled. When the counter reaches 0x0000, the counter is loaded with the latest value written to the modulus counter register. Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset the modulus counter to 0xFFFF. RDMCL Read Modulus Down-Counter Load 0 Reads of the modulus count register (MDCCNT) will return the present value of the count register. 1 Reads of the modulus count register (MDCCNT) will return the contents of the load register. PRE Prescaler 0 The modulus down counter clock frequency is the bus frequency divided by 64. 1 The modulus down counter clock frequency is the bus frequency divided by 512. Note: A change in the prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs. FLMC Force Load Register into the Modulus Counter Count Register — This bit always reads zero. 0 Write zero to this bit has no effect. 1 Write one into this bit loads the load register into the modulus counter count register. MCEN Modulus Down-Counter Enable 0 Modulus down-counter is disabled. The modulus counter (MDCCNT) is preset to 0xFFFF. This will prevent an early interrupt flag when the modulus down-counter is enabled. 1 Modulus down-counter is enabled. AOVIE Accumulator Overflow Interrupt Enable 0 Interrupt disabled. 1 Interrupt enabled. An interrupt will be generated when the accumulator overflow interrupt flag (AOVIF) is set. Module Base + 0x0002 76543210 R RTZE SDCPU SSDWAI FTST ACLKS W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 12-4. Stepper Stall Detector Control Register (SSDCTL)

Chapter 12 Stepper Stall Detector (SSDV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 469 l NOTE A change in the accumulator sample frequency will not be effective until the ITG bit is cleared. Table 12-8. SSDCTL Field Descriptions Field Description RTZE Return to Zero Enable— If this bit is set, the coils are controlled by the SSD and are configured into one of the four full step states as shown in Table 12-6. If this bit is cleared, the coils are not controlled by the SSD. 0 RTZ is disabled. 1 RTZ is enabled. SDCPU Sigma-Delta Converter Power Up — This bit provides on/off control for the sigma-delta converter allowing reduced MCU power consumption. Because the analog circuit is turned off when powered down, the sigma-delta converter requires a recovery time after it is powered up. 0 Sigma-delta converter is powered down. 1 Sigma-delta converter is powered up. SSDWAI SSD Disabled during Wait Mode — When entering Wait Mode, this bit provides on/off control over the SSD allowing reduced MCU power consumption. Because the analog circuit is turned off when powered down, the sigma-delta converter requires a recovery time after exit from Wait Mode. 0 SSD continues to run in WAIT mode. 1 Entering WAIT mode freezes the clock to the prescaler divider, powers down the sigma-delta converter, and if RTZE bit is set, the sine and cosine coils are recirculated via VSSM. FTST Factory Test — This bit is reserved for factory test and reads zero in user mode. 1:0 ACLKS Accumulator Sample Frequency Select — This field sets the accumulator sample frequency by pre-scaling the bus frequency by a factor of 8, 16, 32, or 64. A faster sample frequency can provide more accurate results but cause the accumulator to overflow. Best results are achieved with a frequency between 500 kHz and 2 MHz. Accumulator Sample Frequency = f BUS / (8 x 2ACLKS) Table 12-9. Accumulator Sample Frequency ACLKS Frequency fBUS = 40 MHz fBUS = 25 MHz fBUS = 16 MHz 0f BUS / 8 5.00 MHz 3.12 MHz 2.00 MHz 1f BUS / 16 2.50 MHz 1.56 MHz 1.00 MHz 2f BUS / 32 1.25 MHz 781 kHz 500 kHz 3f BUS / 64 625 kHz 391 kHz 250 kHz

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12.3.2.4 Stepper Stall Detector Flag Register (SSDFLG)

Read: anytime Write: anytime. l

12.3.2.5 Modulus Down-Counter Count Register (MDCCNT)

Read: anytime Write: anytime. Module Base + 0x0003 76543210 R MCZIF 000000 AOVIF W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 12-5. Stepper Stall Detector Flag Register (SSDFLG) Table 12-10. SSDFLG Field Descriptions Field Description MCZIF Modulus Counter Underflow Interrupt Flag — This flag is set when the modulus down-counter reaches 0x0000. If not masked (MCZIE = 1), a modulus counter underflow interrupt is pending while this flag is set. This flag is cleared by writing a ‘1’ to the bit. A write of ‘0’ has no effect. AOVIF Accumulator Overflow Interrupt Flag — This flag is set when the Integration Accumulator has a positive or negative overflow. If not masked (AOVIE = 1), an accumulator overflow interrupt is pending while this flag is set. This flag is cleared by writing a ‘1’ to the bit. A write of ‘0’ has no effect. Module Base + 0x0004 15 14 13 12 11 10 9 8 R MDCCNT W Reset 1 1 1 11111 Figure 12-6. Modulus Down-Counter Count Register High (MDCCNT) Module Base + 0x0005 76543210 R MDCCNT W Reset 1 1 1 11111 Figure 12-7. Modulus Down-Counter Count Register Low (MDCCNT)

Chapter 12 Stepper Stall Detector (SSDV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 471 NOTE A separate read/write for high byte and low byte gives a different result than accessing the register as a word. If the RDMCL bit in the MDCCTL register is cleared, reads of the MDCCNT register will return the present value of the count register. If the RDMCL bit is set, reads of the MDCCNT register will return the contents of the load register. With a 0x0000 write to the MDCCNT register, the modulus counter stays at zero and does not set the MCZIF flag in the SSDFLG register. If modulus mode is not enabled (MODMC = 0), a write to the MDCCNT register immediately updates the load register and the counter register with the value written to it. The modulus counter will count down from this value and will stop at 0x0000. If modulus mode is enabled (MODMC = 1), a write to the MDCCNT register updates the load register with the value written to it. The count register will not be updated with the new value until the next counter underflow. The FLMC bit in the MDCCTL register can be used to immediately update the count register with the new value if an immediate load is desired. The modulus down counter clock frequency is the bus frequency divided by 64 or 512.

12.3.2.6 Integration Accumulator Register (ITGACC)

Read: anytime. Write: Never. NOTE A separate read for high byte and low byte gives a different result than accessing the register as a word. Module Base + 0x0006 15 14 13 12 11 10 9 8 R ITGACC W Reset 0 0 0 00000 Figure 12-8. Integration Accumulator Register High (ITGACC) Module Base + 0x0007 76543210 R ITGACC W Reset 0 0 0 00000 Figure 12-9. Integration Accumulator Register Low (ITGACC)

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This 16-bit field is signed and is represented in two’s complement. It indicates the change in flux while integrating the back EMF present in the non-driven coil during a return to zero event. When ITG is zero, the accumulator is initialized to 0x0000 and the sigma-delta converter is in a reset state. When ITG is one, the accumulator increments or decrements depending on the sigma-delta conversion sample. The accumulator sample frequency is determined by the ACLKS field. The accumulator freezes at 0x7FFF on a positive overflow and freezes at 0x8000 on a negative overflow.

12.4 Functional Description

The stepper stall detector (SSD) has a simple control block to configure the H-bridge drivers of a stepper motor in four different full step states with four available modes during a return to zero event. The SSD has a detect circuit using a sigma-delta converter to measure and integrate changes in flux of the de-energized winding in the stepping motor and the conversion result is accumulated in a 16-bit signed register. The SSD also has a 16-bit modulus down counter to monitor blanking and integration times. DC offset compensation is implemented when using the modulus down counter to monitor integration times.

12.4.1 Return to Zero Modes

There are four return to zero modes as shown in Table 12-11.

12.4.1.1 Blanking with No Drive

In blanking mode with no drive, one of the coils is masked from the sigma-delta converter, and if RTZ is enabled (RTZE = 1), it is set up to recirculate its current. If RTZ is enabled (RTZE = 1), the other coil is disconnected to prevent any loss of flux change that would occur when the motor starts moving before the end of recirculation and start of integration. In blanking mode with no drive, the accumulator is initialized to 0x0000 and the converter is in a reset state.

12.4.1.2 Blanking with Drive

In blanking mode with drive, one of the coils is masked from the sigma-delta converter, and if RTZ is enabled (RTZE = 1), it is set up to recirculate its current. If RTZ is enabled (RTZE = 1), the other coil is driven. In blanking mode with drive, the accumulator is initialized to 0x0000 and the converter is in a reset state. Table 12-11. Return to Zero Modes ITG DCOIL Mode 0 0 Blanking with no drive 0 1 Blanking with drive 1 0 Conversion 1 1 Integration

Chapter 12 Stepper Stall Detector (SSDV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 473

12.4.1.3 Conversion

In conversion mode, one of the coils is routed for integration with one end connected to the (non-zero) reference input and the other end connected to the integrator input of the sigma-delta converter. If RTZ is enabled (RTZE=1), both coils are disconnected. This mode is not useful for stall detection.

12.4.1.4 Integration

In integration mode, one of the coils is routed for integration with one end connected to the (non-zero) reference input and the other end connected to the integrator input of the sigma-delta converter. If RTZ is enabled (RTZE = 1), the other coil is driven. This mode is used to rectify and integrate the back EMF produced by the coils to detect stepped rotary motion. DC offset compensation is implemented when using the modulus down counter to monitor integration time.

12.4.2 Full Step States

During a return to zero (RTZ) event, the stepper motor pointer requires a 90° full motor electrical step with full amplitude pulses applied to each phase in turn. For counter clockwise rotation (CCW), the STEP value is incremented 0, 1, 2, 3, 0 and so on, and for a clockwise rotation the STEP value is decremented 3, 2, 1, 0 and so on. Figure 12-10 shows the current level through each coil for each full step in CCW rotation when DCOIL is set. Figure 12-10. Full Steps (CCW) Figure 12-11 shows the current flow in the SINx and COSx H-bridges when STEP = 0, DCOIL = 1, ITG = 0 and RCIR = 0. 0 1 2 3 Imax+ _ Imax Imax+ _ Imax SINE COIL CURRENT COSINE COIL CURRENT Recirculation

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Figure 12-11. Current Flow when STEP = 0, DCOIL = 1, ITG = 0, RCIR = 0 Figure 12-12 shows the current flow in the SINx and COSx H-bridges when STEP = 1, DCOIL = 1, ITG = 0 and RCIR = 1. Figure 12-12. Current Flow when STEP = 1, DCOIL = 1, ITG = 0, RCIR = 1 Figure 12-13 shows the current flow in the SINx and COSx H-bridges when STEP = 2, DCOIL = 1 and ITG = 1. VDDM COSxP COSxM VSSM VDDM SINxP SINxM VSSM VDDM COSxP COSxM VSSM VDDM SINxP SINxM VSSM

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12.4.3 Operation in Low Power Modes

The SSD block can be configured for lower MCU power consumption in three different ways.

• Stop mode powers down the sigma-delta converter and halts clock to the modulus counter. Exit from Stop enables the sigma-delta converter and the clock to the modulus counter but due to the converter recovery time, the integration result should be ignored.
• Wait mode with SSDW AI bit set powers down the sigma-delta converter and halts the clock to the modulus counter. Exit from Wait enables the sigma-delta converter and clock to the modulus counter but due to the converter recovery time, the integration result should be ignored.
• Clearing SDCPU bit powers down the sigma-delta converter.

12.4.4 Stall Detection Flow

Figure 12-15 shows a flowchart and software setup for stall detection of a stepper motor. To control a second stepper motor, the SMS bit must be toggled during the SSD initialization.

Chapter 12 Stepper Stall Detector (SSDV1) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 477 Figure 12-15. Return-to-Zero Flowchart Advance Pointer Initialize SSD Start Blanking Start Integration Disable SSD End of Blanking? End of Integration? Stall Detection? Using Motor Control module, drive pointer to within 3 full steps of calibrated zero position. 1. Clear (or set) RCIR; clear (or set) POL; clear (or set) SMS; 2. Set MCZIE; clear MODMC; clear (or set) PRE; set MCEN. 3. Set RTZE; set SDCPU; write ACLKS (select sample frequency). 4. Store threshold value in RAM. 1. Clear MCZIF . 2. Write MDCCNT with blanking time value. 3. Clear ITG; clear (or set) DCOIL; increment (or decrement) STEP for CCW (or CW) motion. MDCCNT = 0x0000? or MCZIF = 1? 1. Clear MCZIF . 2. Write MDCCNT with integration time value. 3. Set ITG; set DCOIL. MDCCNT = 0x0000? or MCZIF = 1? Yes No Yes No ITGACC < Threshold (RAM value)? 1. Clear MCZIF . 2. Clear MCEN. 3. Clear ITG. 4. Clear RTZE; clear SDCPU. Yes No

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MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 479 Chapter 13 Inter-Integrated Circuit (IICV3) Block Description Table 13-1. Revision History

13.1 Introduction

The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. This bus is suitable for applications requiring occasional communications over a short distance between a number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for further expansion and system development. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF.

13.1.1 Features

The IIC module has the following key features:

• Compatible with I2C bus standard
• Multi-master operation
• Software programmable for one of 256 different serial clock frequencies
• Software selectable acknowledge bit
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated start signal generation Revision Number Revision Date Sections Affected Description of Changes V01.03 28 Jul 2006 13.7.1.7/13-503 - Update flow-chart of interrupt routine for 10-bit address V01.04 17 Nov 2006 13.3.1.2/13-483 - Revise Table1-5

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• Acknowledge bit generation/detection
• Bus busy detection
• General Call Address detection
• Compliant to ten-bit address

Chapter 13 Inter-Integrated Circuit (IICV3) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 481

13.1.2 Modes of Operation

The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait and stop modes.

13.1.3 Block Diagram

The block diagram of the IIC module is shown in Figure 13-1. Figure 13-1. IIC Block Diagram In/Out Data Shift Register Address Compare SDA Interrupt Clock Control Start Stop Arbitration Control SCL bus_clock IIC Registers

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13.2 External Signal Description

The IICV3 module has two external pins.

13.2.1 IIC_SCL — Serial Clock Line Pin

This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification.

13.2.2 IIC_SDA — Serial Data Line Pin

This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification.

13.3 Memory Map and Register Definition

This section provides a detailed description of all memory and registers for the IIC module.

13.3.1 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Register Name Bit 7 654321 Bit 0 0x0000 IBAD R ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 W 0x0001 IBFD R IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 W 0x0002 IBCR R IBEN IBIE MS/ SL Tx/ Rx TXAK IBSWAIW RSTA 0x0003 IBSR R TCF IAAS IBB IBAL 0S R W IBIF RXAK W 0x0004 IBDR R D7 D6 D5 D4 D3 D2 D1 D0 W 0x0005 IBCR2 R GCEN ADTYPE 000 ADR10 ADR9 ADR8 W = Unimplemented or Reserved Figure 13-2. IIC Register Summary

Chapter 13 Inter-Integrated Circuit (IICV3) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 483

13.3.1.1 IIC Address Register (IBAD)

This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer.

13.3.1.2 IIC Frequency Divider Register (IBFD)

R ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 13-3. IIC Bus Address Register (IBAD) Table 13-2. IBAD Field Descriptions Field Description 7:1 ADR[7:1] Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default mode of IIC bus is slave mode for an address match on the bus. Reserved Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0. Module Base + 0x0001 76543210 R IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 13-4. IIC Bus Frequency Divider Register (IBFD) Table 13-3. IBFD Field Descriptions Field Description 7:0 IBC[7:0] I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown in Table 13-4.

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Table 13-5. Prescale Divider Encoding The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown in the scl2tap column of Table 13-4, all subsequent tap points are separated by 2IBC5-3 as shown in the tap2tap column in Table 13-5. The SCL Tap is used to generated the SCL period and the SDA Tap is used to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time. IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the Table 13-6. Table 13-4. I-Bus Tap and Prescale Values IBC2-0 (bin) SCL Tap (clocks) SDA Tap (clocks) 000 5 1 001 6 1 010 7 2 011 8 2 100 9 3 101 10 3 110 12 4 111 15 4 IBC5-3 (bin) scl2start (clocks) scl2stop (clocks) scl2tap (clocks) tap2tap (clocks) 0 0 0 2741 0 0 1 2742 0 1 0 2964 0 1 1 6968 100 14 17 14 16 101 30 33 30 32 110 62 65 62 64 111 126 129 126 128 Table 13-6. Multiplier Factor IBC7-6 MUL 00 01 01 02 10 04

11 RESERVED

Chapter 13 Inter-Integrated Circuit (IICV3) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 485 Figure 13-5. SCL Divider and SDA Hold The equation used to generate the divider values from the IBFD bits is: SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)} The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 13-7. The equation used to generate the SDA Hold value from the IBFD bits is: SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3} The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is: SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap] SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap] Table 13-7. IIC Divider and Hold Values (Sheet 1 of 6) IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop) MUL=1 SCL Divider SDA Hold SCL SDA SDA SCL START condition STOP condition SCL Hold(start) SCL Hold(stop)

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Table 13-7. IIC Divider and Hold Values (Sheet 2 of 6) IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop)

Chapter 13 Inter-Integrated Circuit (IICV3) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 487 2D 640 97 318 321 2E 768 129 382 385 2F 960 129 478 481 30 640 65 318 321 31 768 65 382 385 32 896 129 446 449 33 1024 129 510 513 34 1152 193 574 577 35 1280 193 638 641 36 1536 257 766 769 37 1920 257 958 961 38 1280 129 638 641 39 1536 129 766 769 3A 1792 257 894 897 3B 2048 257 1022 1025 3C 2304 385 1150 1153 3D 2560 385 1278 1281 3E 3072 513 1534 1537 3F 3840 513 1918 1921 MUL=2 40 40 14 12 22 41 44 14 14 24 42 48 16 16 26 43 52 16 18 28 44 56 18 20 30 45 60 18 22 32 46 68 20 26 36 47 80 20 32 42 48 56 14 20 30 49 64 14 24 34 4A 72 18 28 38 4B 80 18 32 42 4C 88 22 36 46 4D 96 22 40 50 4E 112 26 48 58 4F 136 26 60 70 50 96 18 36 50 51 112 18 44 58 52 128 26 52 66 53 144 26 60 74 54 160 34 68 82 55 176 34 76 90 56 208 42 92 106 57 256 42 116 130 58 160 18 76 82 Table 13-7. IIC Divider and Hold Values (Sheet 3 of 6) IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop)

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MUL=4 80 72 28 24 44 81 80 28 28 48 82 88 32 32 52 83 96 32 36 56 84 104 36 40 60 Table 13-7. IIC Divider and Hold Values (Sheet 4 of 6) IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop)

Chapter 13 Inter-Integrated Circuit (IICV3) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 489 85 112 36 44 64 86 128 40 52 72 87 152 40 64 84 88 112 28 40 60 89 128 28 48 68 8A 144 36 56 76 8B 160 36 64 84 8C 176 44 72 92 8D 192 44 80 100 8E 224 52 96 116 8F 272 52 120 140 90 192 36 72 100 91 224 36 88 116 92 256 52 104 132 93 288 52 120 148 94 320 68 136 164 95 352 68 152 180 96 416 84 184 212 97 512 84 232 260 98 320 36 152 164 99 384 36 184 196 9A 448 68 216 228 9B 512 68 248 260 9C 576 100 280 292 9D 640 100 312 324 9E 768 132 376 388 9F 960 132 472 484 A0 640 68 312 324 A1 768 68 376 388 A2 896 132 440 452 A3 1024 132 504 516 A4 1152 196 568 580 A5 1280 196 632 644 A6 1536 260 760 772 A7 1920 260 952 964 A8 1280 132 632 644 A9 1536 132 760 772 AA 1792 260 888 900 AB 2048 260 1016 1028 AC 2304 388 1144 1156 AD 2560 388 1272 1284 AE 3072 516 1528 1540 AF 3840 516 1912 1924 B0 2560 260 1272 1284 B1 3072 260 1528 1540 Table 13-7. IIC Divider and Hold Values (Sheet 5 of 6) IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop)

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Note:Since the bus frequency is speeding up,the SCL Divider could be expanded by it.Therefore,in the table,when IBC[7:0] is from $00 to $0F,the SCL Divider is revised by the format value1/value2.Value1 is the divider under the low frequency.Value2 is the divider under the high frequency.How to select the divider depends on the bus frequency.When IBC[7:0] is from $10 to $BF,the divider is not changed.

13.3.1.3 IIC Control Register (IBCR)

R IBEN IBIE MS/SL Tx/Rx TXAK IBSWAI W RSTA Reset 0 0 0 00000 = Unimplemented or Reserved Figure 13-6. IIC Bus Control Register (IBCR) Table 13-7. IIC Divider and Hold Values (Sheet 6 of 6) IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop)

Chapter 13 Inter-Integrated Circuit (IICV3) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 491 Wait mode is entered via execution of a CPU W AI instruction. In the event that the IBSW AI bit is set, all clocks internal to the IIC will be stopped and any transmission currently in progress will halt.If the CPU were woken up by a source other than the IIC module, then clocks would restart and the IIC would resume Table 13-8. IBCR Field Descriptions Field Description IBEN I-Bus Enable — This bit controls the software reset of the entire IIC bus module. 0 The module is reset and disabled. This is the power-on reset situation. When low the interface is held in reset but registers can be accessed 1 The IIC bus module is enabled.This bit must be set before any other IBCR bits have any effect If the IIC bus module is enabled in the middle of a byte transfer the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected. Master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle may become corrupt. This would ultimately result in either the current bus master or the IIC bus module losing arbitration, after which bus operation would return to normal. IBIE I-Bus Interrupt Enable 0 Interrupts from the IIC bus module are disabled. Note that this does not clear any currently pending interrupt condition 1 Interrupts from the IIC bus module are enabled. An IIC bus interrupt occurs provided the IBIF bit in the status register is also set. MS/SL Master/Slave Mode Select Bit — Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is generated on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal is generated and the operation mode changes from master to slave.A STOP signal should only be generated if the IBIF flag is set. MS/ SL is cleared without generating a STOP signal when the master loses arbitration.

0 Slave Mode

1 Master Mode

Transmit/Receive Mode Select Bit — This bit selects the direction of master and slave transfers. When addressed as a slave this bit should be set by software according to the SRW bit in the status register. In master mode this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high.

0 Receive

1 Transmit

Transmit Acknowledge Enable— This bit specifies the value driven onto SDA during data acknowledge cycles for both master and slave receivers. The IIC module will always acknowledge address matches, provided it is enabled, regardless of the value of TXAK. Note that values written to this bit are only used when the IIC bus is a receiver, not a transmitter.

0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data

1 No acknowledge signal response is sent (i.e., acknowledge bit = 1) RSTA Repeat Start — Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration.

1 Generate repeat start cycle

Reserved — Bit 1 of the IBCR is reserved for future compatibility. This bit will always read 0. IBSWAI I Bus Interface Stop in Wait Mode

0 IIC bus module clock operates normally

1 Halt IIC bus module clock generation in wait mode

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from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when its internal clocks are stopped. If it were the case that the IBSW AI bit was cleared when the W AI instruction was executed, the IIC internal clocks and interface would remain alive, continuing the operation which was currently underway. It is also possible to configure the IIC such that it will wake up the CPU via an interrupt at the conclusion of the current operation. See the discussion on the IBIF and IBIE bits in the IBSR and IBCR, respectively.

13.3.1.4 IIC Status Register (IBSR)

This status register is read-only with exception of bit 1 (IBIF) and bit 4 (IBAL), which are software clearable. Module Base + 0x0003 76543210 R TCF IAAS IBB IBAL 0S R W IBIF RXAK W Reset 1 0 0 00000 = Unimplemented or Reserved Figure 13-7. IIC Bus Status Register (IBSR) Table 13-9. IBSR Field Descriptions Field Description TCF Data Transferring Bit — While one byte of data is being transferred, this bit is cleared. It is set by the falling edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.

0 Transfer in progress

1 Transfer complete

Addressed as a Slave Bit— When its own specific address (I-bus address register) is matched with the calling address or it receives the general call address with GCEN== 1,this bit is set.The CPU is interrupted provided the IBIE is set.Then the CPU needs to check the SRW bit and set its Tx/ Rx mode accordingly.Writing to the I-bus control register clears this bit.

0 Not addressed

1 Addressed as a slave

0 This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is detected, IBB is cleared and the bus enters idle state.

1 Bus is busy

Arbitration Lost — The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost. Arbitration is lost in the following circumstances: 1. SDA sampled low when the master drives a high during an address or data transmit cycle. 2. SDA sampled low when the master drives a high during the acknowledge bit of a data receive cycle. 3. A start cycle is attempted when the bus is busy. 4. A repeated start cycle is requested in slave mode. 5. A stop condition is detected when the master did not request it. This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit.

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13.3.1.5 IIC Data I/O Register (IBDR)

In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates next byte data receiving. In slave mode, the same functions are available after an address match has occurred.Note that the Tx/Rx bit in the IBCR must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is desired, then reading the IBDR will not initiate the receive. Reading the IBDR will return the last byte received while the IIC is configured in either master receive or slave receive modes. The IBDR does not reflect every byte that is transmitted on the IIC bus, nor can software verify that a byte has been written to the IBDR correctly by reading it back. In master transmit mode, the first byte of data written to IBDR following assertion of MS/ SL is used for the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the required R/ W bit (in position D0). RESERVED Reserved — Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0. SRW Slave Read/Write — When IAAS is set this bit indicates the value of the R/W command bit of the calling address sent from the master This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated. Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master.

0 Slave receive, master writing to slave

1 Slave transmit, master reading from slave

I-Bus Interrupt — The IBIF bit is set when one of the following conditions occurs: — Arbitration lost (IBAL bit set) — Data transfer complete (TCF bit set) — Addressed as slave (IAAS bit set) It will cause a processor interrupt request if the IBIE bit is set. This bit must be cleared by software, writing a one to it. A write of 0 has no effect on this bit. RXAK Received Acknowledge — The value of SDA during the acknowledge bit of a bus cycle. If the received acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the 9th clock.

0 Acknowledge received

1 No acknowledge received

R D7 D6 D5 D4 D3 D2 D1 D0 W Reset 0 0 0 00000 Figure 13-8. IIC Bus Data I/O Register (IBDR) Table 13-9. IBSR Field Descriptions (continued) Field Description

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13.3.1.6 IIC Control Register 2(IBCR2)

Figure 13-9. IIC Bus Control Register 2(IBCR2) This register contains the variables used in general call and in ten-bit address. Read and write anytime

13.4 Functional Description

This section provides a complete functional description of the IICV3.

13.4.1 I-Bus Protocol

The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. Logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. They are described briefly in the following sections and illustrated in Figure 13-10. Module Base + 0x0005 76543210 R GCEN ADTYPE 000 ADR10 ADR9 ADR8 W Reset 0 0 0 00000 Table 13-10. IBCR2 Field Descriptions Field Description GCEN General Call Enable. 0 General call is disabled. The module dont receive any general call data and address. 1 enable general call. It indicates that the module can receive address and any data. ADTYPE Address Type— This bit selects the address length. The variable must be configured correctly before IIC enters slave mode. 0 7-bit address 1 10-bit address 5,4,3 RESERVED Reserved — Bit 5,4 and 3 of the IBCR2 are reserved for future compatibility. These bits will always read 0. 2:0 ADR[10:8] Slave Address [10:8] —These 3 bits represent the MSB of the 10-bit address when address type is asserted (ADTYPE = 1).

Chapter 13 Inter-Integrated Circuit (IICV3) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 495 Figure 13-10. IIC-Bus Transmission Signals

13.4.1.1 START Signal

When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal.As shown inFigure 13-10, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. Figure 13-11. Start and Stop Conditions CL DA Start Signal Ack Bit 123 4567 8 MSB LSB 1 2 34 5 6 78 MSB LSB No CL DA 123 456 7 8 MSB LSB 12 5 6 7 8 MSB LSB Repeated ADR7 ADR6 ADR5 ADR4ADR3 ADR2 ADR1R/W XXX D7 D6 D5 D4 D3 D2 D1 D0 Calling Address Read/ Data Byte ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W New Calling Address XX Ack BitWrite Start Signal Start Signal Ack Bit Calling Address Read/ Write No Ack Bit Read/ Write SDA SCL START Condition STOP Condition

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13.4.1.2 Slave Address Transmission

The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. If the calling address is 10-bit, another byte is followed by the first byte.Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 13-10). No two slaves in the system may have the same address. If the IIC bus is master, it must not transmit an address that is equal to its own slave address. The IIC bus cannot be master and slave at the same time.However, if arbitration is lost during an address cycle the IIC bus will revert to slave mode and operate correctly even if it is being addressed by another master.

13.4.1.3 Data Transfer

As soon as successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device. Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 13-10. There is one clock pulse on SCL for each data bit, the MSB being transferred first. Each data byte has to be followed by an acknowledge bit, which is signalled from the receiving device by pulling the SDA low at the ninth clock. So one complete data byte transfer needs nine clock pulses. If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the SDA line for the master to generate STOP or START signal.Note in order to release the bus correctly,after no-acknowledge to the master,the slave must be immediately switched to receiver and a following dummy reading of the IBDR is necessary.

13.4.1.4 STOP Signal

The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 13-10). The master can generate a STOP even if the slave has generated an acknowledge at which point the slave must release the bus.

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13.4.1.5 Repeated START Signal

As shown in Figure 13-10, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.

13.4.1.6 Arbitration Procedure

The Inter-IC bus is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration.

13.4.1.7 Clock Synchronization

Because wire-AND logic is performed on SCL line, a high-to-low transition on SCL line affects all the devices connected on the bus. The devices start counting their low period and as soon as a device's clock has gone low, it holds the SCL line low until the clock high state is reached.However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 13-11). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods.The first device to complete its high period pulls the SCL line low again. Figure 13-12. IIC-Bus Clock Synchronization SCL1 SCL2 SCL Internal Counter Reset WAIT Start Counting High Period

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13.4.1.8 Handshaking

The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line.

13.4.1.9 Clock Stretching

The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master has driven SCL low the slave can drive SCL low for the required period and then release it.If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched.

13.4.1.10 Ten-bit Address

A ten-bit address is indicated if the first 5 bits of the first address byte are 0x11110. The following rules apply to the first address byte. Figure 13-13. Definition of bits in the first byte . The address type is identified by ADTYPE. When ADTYPE is 0, 7-bit address is applied. Reversely, the address is 10-bit address.Generally, there are two cases of 10-bit address.See the Figure 13-14 and Figure 13-15. Figure 13-14. A master-transmitter addresses a slave-receiver with a 10-bit address Figure 13-15. A master-receiver addresses a slave-transmitter with a 10-bit address. In the Figure 13-15, the first two bytes are the similar to Figure 13-14. After the repeated START(Sr),the first slave address is transmitted again, but the R/W is 1, meaning that the slave is acted as a transmitter. SLAVE ADDRESS R/W BIT DESCRIPTION 0000000 0 General call address 0000010 x Reserved for different bus format 0000011 x Reserved for future purposes 11111XX x Reserved for future purposes 11110XX x 10-bit slave addressing S Slave Add1st 7bits 11110+ADR10+ADR9 R/W

0 A1 Slave Add 2nd byte

ADR[8:1] A2 Data A3 S Slave Add1st 7bits 11110+ADR10+ADR9 R/W ADR[8:1] A2 Sr Slave Add 1st 7bits 11110+ADR10+ADR9 R/W

1 A3 Data A4

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13.4.1.11 General Call Address

To broadcast using a general call, a device must first generate the general call address($00), then after receiving acknowledge, it must transmit data. In communication, as a slave device, provided the GCEN is asserted, a device acknowledges the broadcast and receives data until the GCEN is disabled or the master device releases the bus or generates a new transfer. In the broadcast, slaves always act as receivers. In general call, IAAS is also used to indicate the address match. In order to distinguish whether the address match is the normal address match or the general call address match, IBDR should be read after the address byte has been received. If the data is $00, the match is general call address match. The meaning of the general call address is always specified in the first data byte and must be dealt with by S/W, the IIC hardware does not decode and process the first data byte. When one byte transfer is done, the received data can be read from IBDR. The user can control the procedure by enabling or disabling GCEN.

13.4.2 Operation in Run Mode

This is the basic mode of operation.

13.4.3 Operation in Wait Mode

IIC operation in wait mode can be configured. Depending on the state of internal bits, the IIC can operate normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module enters a power conservation state during wait mode. In the later case, any transmission or reception in progress stops at wait mode entry.

13.4.4 Operation in Stop Mode

The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC register states.

13.5 Resets

The reset state of each individual bit is listed in Section 13.3, “Memory Map and Register Definition,” which details the registers and their bit-fields.

13.6 Interrupts

IICV3 uses only one interrupt vector. Table 13-11. Interrupt Summary Interrupt Offset Vector Priority Source Description

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Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt type by reading the status register. IIC Interrupt can be generated on 1. Arbitration lost condition (IBAL bit set) 2. Byte transfer condition (TCF bit set) 3. Address detect condition (IAAS bit set) The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to the IBF bit in the interrupt service routine.

13.7 Application Information

13.7.1 IIC Programming Examples

13.7.1.1 Initialization Sequence

Reset will put the IIC bus control register to its default status. Before the interface can be used to transfer serial data, an initialization procedure must be carried out, as follows: 1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL frequency from system clock. 2. Update the ADTYPE of IBCR2 to define the address length, 7 bits or 10 bits. 3. Update the IIC bus address register (IBAD) to define its slave address. If 10-bit address is applied IBCR2 should be updated to define the rest bits of address. 4. Set the IBEN bit of the IIC bus control register (IBCR) to enable the IIC interface system. 5. Modify the bits of the IIC bus control register (IBCR) to select master/slave mode, transmit/receive mode and interrupt enable or not. 6. If supported general call, the GCEN in IBCR2 should be asserted.

13.7.1.2 Generation of START

After completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. If the device is connected to a multi-master bus system, the state of the IIC bus busy bit (IBB) must be tested to check whether the serial bus is free. If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent. The data written to the data register comprises the slave calling address and the LSB set to indicate the direction of transfer required from the slave. The bus free time (i.e., the time between a STOP condition and the following START condition) is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system IIC Interrupt — — — IBAL, TCF , IAAS bits in IBSR register When either of IBAL, TCF or IAAS bits is set may cause an interrupt based on arbitration lost, transfer complete or address detect conditions

Chapter 13 Inter-Integrated Circuit (IICV3) Block Description MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 501 clock and the SCL period it may be necessary to wait until the IIC is busy after writing the calling address to the IBDR before proceeding with the following instructions. This is illustrated in the following example. An example of a program which generates the START signal and transmits the first byte of data (slave address) is shown below:

13.7.1.3 Post-Transfer Software Response

Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte communication is finished. The IIC bus interrupt bit (IBIF) is set also; an interrupt will be generated if the interrupt function is enabled during initialization by setting the IBIE bit. Software must clear the IBIF bit in the interrupt routine first. The TCF bit will be cleared by reading from the IIC bus data I/O register (IBDR) in receive mode or writing to IBDR in transmit mode. Software may service the IIC I/O in the main program by monitoring the IBIF bit if the interrupt function is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit because their operation is different when arbitration is lost. Note that when an interrupt occurs at the end of the address cycle the master will always be in transmit mode, i.e. the address is transmitted. If master receive mode is required, indicated by R/W bit in IBDR, then the Tx/Rx bit should be toggled at this stage. During slave mode address cycles (IAAS=1), the SRW bit in the status register is read to determine the direction of the subsequent transfer and the Tx/Rx bit is programmed accordingly.For slave mode data cycles (IAAS=0) the SRW bit is not valid, the Tx/Rx bit in the control register should be read to determine the direction of the current transfer. The following is an example of a software response by a 'master transmitter' in the interrupt routine.

13.7.1.4 Generation of STOP

A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply generate a STOP signal after all the data has been transmitted. The following is an example showing how a stop condition is generated by a master transmitter. CHFLAG BRSET IBSR,#$20,* ;WAIT FOR IBB FLAG TO CLEAR TXSTART BSET IBCR,#$30 ;SET TRANSMIT AND MASTER MODE;i.e. GENERATE START CONDITION MOVB CALLING,IBDR ;TRANSMIT THE CALLING ADDRESS, D0=R/W IBFREE BRCLR IBSR,#$20,* ;WAIT FOR IBB FLAG TO SET ISR BCLR IBSR,#$02 ;CLEAR THE IBIF FLAG BRCLR IBCR,#$20,SLAVE ;BRANCH IF IN SLAVE MODE BRCLR IBCR,#$10,RECEIVE ;BRANCH IF IN RECEIVE MODE BRSET IBSR,#$01,END ;IF NO ACK, END OF TRANSMISSION TRANSMIT MOVB DATABUF ,IBDR ;TRANSMIT NEXT BYTE OF DATA

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If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK) before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must be generated first. The following is an example showing how a STOP signal is generated by a master receiver.

13.7.1.5 Generation of Repeated START

At the end of data transfer, if the master continues to want to communicate on the bus, it can generate another START signal followed by another slave address without first generating a STOP signal. A program example is as shown.

13.7.1.6 Slave Mode

In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the R/W command bit (SRW). Writing to the IBCR clears the IAAS automatically. Note that the only time IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred, interrupts resulting from subsequent data transfers will have IAAS cleared. A data transfer may now be initiated by writing information to IBDR, for slave transmits, or dummy reading from IBDR, in slave receive mode. The slave will drive SCL low in-between byte transfers, SCL is released when the IBDR is accessed in the required mode. In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL line so that the master can generate a STOP signal. MASTX TST TXCNT ;GET VALUE FROM THE TRANSMITING COUNTER BEQ END ;END IF NO MORE DATA BRSET IBSR,#$01,END ;END IF NO ACK MOVB DATABUF ,IBDR ;TRANSMIT NEXT BYTE OF DATA DEC TXCNT ;DECREASE THE TXCNT BRA EMASTX ;EXIT END BCLR IBCR,#$20 ;GENERATE A STOP CONDITION EMASTX RTI ;RETURN FROM INTERRUPT MASR DEC RXCNT ;DECREASE THE RXCNT BEQ ENMASR ;LAST BYTE TO BE READ MOVB RXCNT,D1 ;CHECK SECOND LAST BYTE DEC D1 ;TO BE READ BNE NXMAR ;NOT LAST OR SECOND LAST LAMAR BSET IBCR,#$08 ;SECOND LAST, DISABLE ACK ;TRANSMITTING BRA NXMAR ENMASR BCLR IBCR,#$20 ;LAST ONE, GENERATE ‘STOP’ SIGNAL NXMAR MOVB IBDR,RXBUF ;READ DATA AND STORE RTI RESTART BSET IBCR,#$04 ;ANOTHER START (RESTART) MOVB CALLING,IBDR ;TRANSMIT THE CALLING ADDRESS;D0=R/W

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13.7.1.7 Arbitration Lost

If several masters try to engage the bus simultaneously, only one master wins and the others lose arbitration. The devices which lost arbitration are immediately switched to slave receive mode by the hardware. Their data output to the SDA line is stopped, but SCL continues to be generated until the end of the byte during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with IBAL=1 and MS/SL=0. If one master attempts to start transmission while the bus is being engaged by another master, the hardware will inhibit the transmission; switch the MS/SL bit from 1 to 0 without generating STOP condition; generate an interrupt to CPU and set the IBAL to indicate that the attempt to engage the bus is failed. When considering these cases, the slave service routine should test the IBAL first and the software should clear the IBAL bit if it is set.

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Figure 13-16. Flow-Chart of Typical IIC Interrupt Routine Clear Master Mode Tx/Rx Last Byte Transmitted RXAK=0 End Of Addr Cycle (Master Rx) Write Next Byte To IBDR Switch To Rx Mode Dummy Read From IBDR Generate Stop Signal Read Data From IBDR And Store Set TXAK =1 Generate Stop Signal 2nd Last Byte To Be Read Last Byte To Be Read Arbitration Lost Clear IBAL IAAS=1 IAAS=1 SRW=1 TX/RX Set TX Mode Write Data To IBDR Set RX Mode Dummy Read From IBDR ACK From Receiver Tx Next Byte Read Data From IBDR And Store Switch To Rx Mode Dummy Read From IBDR RTI YN Y Y Y Y Y Y Y N N N N N N N N Y TX RX RX TX (Write) (Read) N IBIF Data Transfer Y Y 10-bit address? N N 7-bit address transfer Y 10-bit address transfer Mode set RX Dummy Read From IBDR N set TX Mode Write Data To IBDR Y IBDR== 11110xx1?

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MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 507 Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.1 Introduction

Freescale’s scalable controller area network (S12MSCANV3) definition is based on the MSCAN12 definition, which is the specific implementation of the MSCAN concept targeted for the M68HC12 microcontroller family. The module is a communication controller implementing the CAN 2.0A/B protocol as defined in the Bosch specification dated September 1991. For users to fully understand the MSCAN specification, it is recommended that the Bosch specification be read first to familiarize the reader with the terms and concepts contained within this document. Though not exclusively intended for automotive applications, CAN protocol is designed to meet the specific requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplified application software. Table 14-1. Revision History Revision Number Revision Date Sections Affected Description of Changes V03.10 19 Aug 2008 14.4.7.4/14-559 14.4.4.5/14-553 14.2/14-510 - Corrected wake-up description - Relocated initialization section - Added note to external pin descriptions for use with integrated physical layer - Minor corrections V03.11 31 Mar 2009 - Orthographic corrections V03.12 09 Aug 2010 Table 14-37 - Added ‘Bosch CAN 2.0A/B’ to bit time settings table

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14.1.1 Glossary

14.1.2 Block Diagram

Figure 14-1. MSCAN Block Diagram Table 14-2. Terminology ACK Acknowledge of CAN message CAN Controller Area Network CRC Cyclic Redundancy Code EOF End of Frame FIFO First-In-First-Out Memory IFS Inter-Frame Sequence SOF Start of Frame CPU bus CPU related read/write data bus CAN bus CAN protocol related serial bus oscillator clock Direct clock from external oscillator bus clock CPU bus related clock CAN clock CAN protocol related clock RXCAN TXCAN Receive/ Transmit Engine Message Filtering and Buffering Control and Status Wake-Up Interrupt Req. Errors Interrupt Req. Receive Interrupt Req. Transmit Interrupt Req. CANCLK Bus Clock Configuration Oscillator Clock MUX Presc. Tq Clk MSCAN Low Pass Filter Wake-UpRegisters

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14.1.3 Features

The basic features of the MSCAN are as follows:

• Implementation of the CAN protocol — Version 2.0A/B — Standard and extended data frames — Zero to eight bytes data length — Programmable bit rate up to 1 Mbps — Support for remote frames
• Five receive buffers with FIFO storage scheme
• Three transmit buffers with internal prioritization using a “local priority” concept
• Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four 16-bit filters, or eight 8-bit filters
• Programmable wake-up functionality with integrated low-pass filter
• Programmable loopback mode supports self-test operation
• Programmable listen-only mode for monitoring of CAN bus
• Programmable bus-off recovery functionality
• Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus-off)
• Programmable MSCAN clock source either bus clock or oscillator clock
• Internal timer for time-stamping of received and transmitted messages
• Three low-power modes: sleep, power down, and MSCAN enable
• Global initialization of configuration registers

14.1.4 Modes of Operation

For a description of the specific MSCAN modes and the module operation related to the system operating modes refer to Section 14.4.4, “Modes of Operation”. 1. Depending on the actual bit timing and the clock jitter of the PLL.

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14.2 External Signal Description

The MSCAN uses two external pins. NOTE On MCUs with an integrated CAN physical interface (transceiver) the MSCAN interface is connected internally to the transceiver interface. In these cases the external availability of signals TXCAN and RXCAN is optional.

14.2.1 RXCAN — CAN Receiver Input Pin

RXCAN is the MSCAN receiver input pin.

14.2.2 TXCAN — CAN Transmitter Output Pin

TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the CAN bus: 0 = Dominant state 1 = Recessive state

14.2.3 CAN System

A typical CAN system with MSCAN is shown inFigure 14-2. Each CAN station is connected physically to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current needed for the CAN bus and has current protection against defective CAN or defective stations. Figure 14-2. CAN System CAN Bus CAN Controller (MSCAN) Transceiver CAN node 1 CAN node 2 CAN node n CANLCANH MCU TXCAN RXCAN

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14.3 Memory Map and Register Definition

This section provides a detailed description of all registers accessible in the MSCAN.

14.3.1 Module Memory Map

Figure 14-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and can be found in the MCU memory map description. The address offset is defined at the module level. The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. The detailed register descriptions follow in the order they appear in the register map.

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Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 CANCTL0 R RXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ W 0x0001 CANCTL1 R CANE CLKSRC LOOPB LISTEN BORM WUPM SLPAK INITAK W 0x0002 CANBTR0 R SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 W 0x0003 CANBTR1 R SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 W 0x0004 CANRFLG R WUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF W 0x0005 CANRIER R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W 0x0006 CANTFLG R0 0 0 00 TXE2 TXE1 TXE0 W 0x0007 CANTIER R 00000 TXEIE2 TXEIE1 TXEIE0 W 0x0008 CANTARQ R 00000 ABTRQ2 ABTRQ1 ABTRQ0 W 0x0009 CANTAAK R 00000 ABTAK2 ABTAK1 ABTAK0 W 0x000A CANTBSEL R 00000 TX2 TX1 TX0 W 0x000B CANIDAC R0 0 IDAM1 IDAM0

0 IDHIT2 IDHIT1 IDHIT0

W 0x000C Reserved R 00000000 W 0x000D CANMISC R 0000000 BOHOLD W 0x000E CANRXERR R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 W = Unimplemented or Reserved Figure 14-3. MSCAN Register Summary

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14.3.2 Register Descriptions

This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. All bits of all registers in this module are completely synchronous to internal clocks during a register read.

14.3.2.1 MSCAN Control Register 0 (CANCTL0)

The CANCTL0 register provides various control bits of the MSCAN module as described below. 0x000F CANTXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 W 0x0010–0x0013 CANIDAR0–3 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x0014–0x0017 CANIDMRx R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0018–0x001B CANIDAR4–7 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x001C–0x001F CANIDMR4–7 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0020–0x002F CANRXFG R See Section 14.3.3, “Programmer’s Model of Message Storage” W 0x0030–0x003F CANTXFG R See Section 14.3.3, “Programmer’s Model of Message Storage” W Module Base + 0x0000 Access: User read/write(1) 76543210 R RXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ W Reset: 00000001 = Unimplemented Figure 14-4. MSCAN Control Register 0 (CANCTL0) Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 14-3. MSCAN Register Summary (continued)

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The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). 1. Read: Anytime Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode) Table 14-3. CANCTL0 Register Field Descriptions Field Description RXFRM(1) Received Frame Flag — This bit is read and clear only. It is set when a receiver has received a valid message correctly, independently of the filter configuration. After it is set, it remains set until cleared by software or reset. Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode.

0 No valid message was received since last clearing this flag

1 A valid message was received since last clearing of this flag

Receiver Active Status — This read-only flag indicates the MSCAN is receiving a message. The flag is controlled by the receiver front end. This bit is not valid in loopback mode.

0 MSCAN is transmitting or idle

1 MSCAN is receiving a message (including when arbitration is lost) (2)

CSWAI(3) CAN Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the CPU bus interface to the MSCAN module.

0 The module is not affected during wait mode

1 The module ceases to be clocked during wait mode

Synchronized Status — This read-only flag indicates whether the MSCAN is synchronized to the CAN bus and able to participate in the communication process. It is set and cleared by the MSCAN.

0 MSCAN is not synchronized to the CAN bus

1 MSCAN is synchronized to the CAN bus

Timer Enable— This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active TX/RX buffer. Right after the EOF of a valid message on the CAN bus, the time stamp is written to the highest bytes (0x000E, 0x000F) in the appropriate buffer (seeSection 14.3.3, “Programmer’s Model of Message Storage”). The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization mode.

0 Disable internal MSCAN timer

1 Enable internal MSCAN timer

(4) Wake-Up Enable — This configuration bit allows the MSCAN to restart from sleep mode or from power down mode (entered from sleep) when traffic on CAN is detected (seeSection 14.4.5.5, “MSCAN Sleep Mode”). This bit must be configured before sleep mode entry for the selected function to take effect.

0 Wake-up disabled — The MSCAN ignores traffic on CAN

1 Wake-up enabled — The MSCAN is able to restart

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14.3.2.2 MSCAN Control Register 1 (CANCTL1)

The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below. SLPRQ(5) Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 14.4.5.5, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry to sleep mode by setting SLPAK = 1 (seeSection 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). SLPRQ cannot be set while the WUPIF flag is set (seeSection 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN detects activity on the CAN bus and clears SLPRQ itself.

0 Running — The MSCAN functions normally

1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle

(6),(7) Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see Section 14.4.4.5, “MSCAN Initialization Mode”). Any ongoing transmission or reception is aborted and synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1 (Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). The following registers enter their hard reset state and restore their default values: CANCTL0 (8), CANRFLG(9), CANRIER(10), CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the error counters are not affected by initialization mode. When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after initialization mode is exited, which is INITRQ = 0 and INITAK = 0.

0 Normal operation

1 MSCAN in initialization mode

1. The MSCAN must be in normal mode for this bit to become set. 2. See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states. 3. In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the in Stop Mode”) 4. The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see Section 14.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required. 5. The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1). 6. The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1). 7. In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before requesting initialization mode. 8. Not including WUPE, INITRQ, and SLPRQ. 9. TSTAT1 and TSTAT0 are not affected by initialization mode. 10. RSTAT1 and RSTAT0 are not affected by initialization mode. Table 14-3. CANCTL0 Register Field Descriptions (continued) Field Description

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Module Base + 0x0001 Access: User read/write(1) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1); CANE is write once 76543210 R CANE CLKSRC LOOPB LISTEN BORM WUPM SLPAK INITAK W Reset: 00010001 = Unimplemented Figure 14-5. MSCAN Control Register 1 (CANCTL1) Table 14-4. CANCTL1 Register Field Descriptions Field Description CANE MSCAN Enable

0 MSCAN module is disabled

1 MSCAN module is enabled

MSCAN Clock Source— This bit defines the clock source for the MSCAN module (only for systems with a clock

0 MSCAN clock source is the oscillator clock

1 MSCAN clock source is the bus clock

Loopback Self Test Mode— When this bit is set, the MSCAN performs an internal loopback which can be used for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN input is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Both transmit and receive interrupts are generated.

0 Loopback self test disabled

1 Loopback self test enabled

Listen Only Mode — This bit configures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN messages with matching ID are received, but no acknowledgement or error frames are sent out (see applications which require “hot plugging” or throughput analysis. The MSCAN is unable to transmit any messages when listen only mode is active.

1 Listen only mode activated

Bus-Off Recovery Mode — This bit configures the bus-off state recovery mode of the MSCAN. Refer to Section 14.5.2, “Bus-Off Recovery,” for details. 0 Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol specification)

1 Bus-off recovery upon user request

Wake-Up Mode — If WUPE in CANCTL0 is enabled, this bit defines whether the integrated low-pass filter is applied to protect the MSCAN from spurious wake-up (see Section 14.4.5.5, “MSCAN Sleep Mode”).

0 MSCAN wakes up on any dominant level on the CAN bus

1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of T

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14.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0)

The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module. SLPAK Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will clear the flag if it detects activity on the CAN bus while in sleep mode.

0 Running — The MSCAN operates normally

1 Sleep mode active — The MSCAN has entered sleep mode

Initialization Mode Acknowledge — This flag indicates whether the MSCAN module is in initialization mode (see Section 14.4.4.5, “MSCAN Initialization Mode”). It is used as a handshake flag for the INITRQ initialization mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode.

1 Initialization mode active — The MSCAN has entered initialization mode

Module Base + 0x0002 Access: User read/write (1) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) 76543210 R SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 W Reset: 00000000 Figure 14-6. MSCAN Bus Timing Register 0 (CANBTR0) Table 14-5. CANBTR0 Register Field Descriptions Field Description 7-6 SJW[1:0] Synchronization Jump Width— The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the CAN bus (see Table 14-6). 5-0 BRP[5:0] Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing (see Table 14-7). Table 14-6. Synchronization Jump Width SJW1 SJW0 Synchronization Jump Width 0 0 1 Tq clock cycle 0 1 2 Tq clock cycles 1 0 3 Tq clock cycles 1 1 4 Tq clock cycles Table 14-4. CANCTL1 Register Field Descriptions (continued) Field Description

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14.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1)

The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module. Table 14-7. Baud Rate Prescaler BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P) 000000 1 000001 2 000010 3 000011 4 :::::: : 111111 6 4 Module Base + 0x0003 Access: User read/write (1) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) 76543210 R SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 W Reset: 00000000 Figure 14-7. MSCAN Bus Timing Register 1 (CANBTR1) Table 14-8. CANBTR1 Register Field Descriptions Field Description SAMP Sampling — This bit determines the number of CAN bus samples taken per bit time. 0 One sample per bit.

1 Three samples per bit

(1). If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit rates, it is recommended that only one sample is taken per bit time (SAMP = 0). 1. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq). 6-4 TSEG2[2:0] Time Segment 2— Time segments within the bit time fix the number of clock cycles per bit time and the location of the sample point (see Figure 14-44). Time segment 2 (TSEG2) values are programmable as shown in Table 14-9. 3-0 TSEG1[3:0] Time Segment 1— Time segments within the bit time fix the number of clock cycles per bit time and the location of the sample point (see Figure 14-44). Time segment 1 (TSEG1) values are programmable as shown in Table 14-10.

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14.3.2.5 MSCAN Receiver Flag Register (CANRFLG)

A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the CANRIER register. Table 14-9. Time Segment 2 Values TSEG22 TSEG21 TSEG20 Time Segment 2 0 0 0 1 Tq clock cycle(1) 1. This setting is not valid. Please refer to Table 14-37 for valid settings. 0 0 1 2 Tq clock cycles ::: : 1 1 0 7 Tq clock cycles 1 1 1 8 Tq clock cycles Table 14-10. Time Segment 1 Values TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 0 0 0 0 1 Tq clock cycle(1) 1. This setting is not valid. Please refer to Table 14-37 for valid settings. 0 0 0 1 2 Tq clock cycles1 0 0 1 0 3 Tq clock cycles1 0 0 1 1 4 Tq clock cycles :::: : 1 1 1 0 15 Tq clock cycles 1 1 1 1 16 Tq clock cycles Module Base + 0x0004 Access: User read/write (1) 76543210 R WUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF W Reset: 00000000 = Unimplemented Figure 14-8. MSCAN Receiver Flag Register (CANRFLG) Bit Time Prescaler value() fCANCLK

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The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). 1. Read: Anytime Write: Anytime when not in initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears flag; write of 0 is ignored 1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. Table 14-11. CANRFLG Register Field Descriptions Field Description WUPIF Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see Section 14.4.5.5, “MSCAN Sleep Mode,”) and WUPE = 1 in CANTCTL0 (seeSection 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set.

0 No wake-up activity observed while in sleep mode

1 MSCAN detected activity on the CAN bus and requested wake-up

CAN Status Change Interrupt Flag — This flag is set when the MSCAN changes its current CAN bus status due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4- bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the system on the actual CAN bus status (see Section 14.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)”). If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the current CSCIF interrupt is cleared again.

0 No change in CAN bus status occurred since last interrupt

1 MSCAN changed current CAN bus status

RSTAT[1:0] Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related CAN bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:

00 RxOK: 0 ≤ receive error counter ≤ 96

01 RxWRN: 96 < receive error counter ≤ 127

10 RxERR: 127 < receive error counter

11 Bus-off

(1): transmit error counter > 255 3-2 TSTAT[1:0] Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is:

00 TxOK: 0 ≤ transmit error counter ≤ 96

01 TxWRN: 96 < transmit error counter ≤ 127

10 TxERR: 127 < transmit error counter ≤ 255

11 Bus-Off: transmit error counter > 255

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14.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER)

This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register. NOTE The CANRIER register is held in the reset state when the initialization mode is active (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. OVRIF Overrun Interrupt Flag— This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set.

0 No data overrun condition

1 A data overrun detected

(2) Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier, matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt is pending while this flag is set.

0 No new message available within the RxFG

1 The receiver FIFO is not empty. A new message is available in the RxFG 1. Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state skips to RxOK too. Refer also to TSTAT[1:0] coding in this register. 2. To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs, reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition. Module Base + 0x0005 Access: User read/write (1) 1. Read: Anytime Write: Anytime when not in initialization mode 76543210 R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W Reset: 00000000 Figure 14-9. MSCAN Receiver Interrupt Enable Register (CANRIER) Table 14-11. CANRFLG Register Field Descriptions (continued) Field Description

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14.3.2.7 MSCAN Transmitter Flag Register (CANTFLG)

The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register. Table 14-12. CANRIER Register Field Descriptions Field Description WUPIE(1) 1. WUPIE and WUPE (see Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) must both be enabled if the recovery mechanism from stop or wait is required. Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CSCIE CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request. 5-4 RSTATE[1:0] Receiver Status Change Enable— These RSTAT enable bits control the sensitivity level in which receiver state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT flags continue to indicate the actual receiver state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by receiver state changes. 01 Generate CSCIF interrupt only if the receiver enters or leaves “bus-off” state. Discard other receiver state changes for generating CSCIF interrupt.

10 Generate CSCIF interrupt only if the receiver enters or leaves “RxErr” or “bus-off”

(2) state. Discard other receiver state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. 2. Bus-off state is only defined for transmitters by the CAN standard (see Bosch CAN 2.0A/B protocol specification). Because the only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK, the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (seeSection 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). 3-2 TSTATE[1:0] Transmitter Status Change Enable— These TSTAT enable bits control the sensitivity level in which transmitter state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by transmitter state changes. 01 Generate CSCIF interrupt only if the transmitter enters or leaves “bus-off” state. Discard other transmitter state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other transmitter state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. OVRIE Overrun Interrupt Enable 0 No interrupt request is generated from this event. 1 An overrun event causes an error interrupt request. RXFIE Receiver Full Interrupt Enable 0 No interrupt request is generated from this event. 1 A receive buffer full (successful message reception) event causes a receiver interrupt request.

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14.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER)

This register contains the interrupt enable bits for the transmit buffer empty interrupt flags. Module Base + 0x0006 Access: User read/write(1) 1. Read: Anytime Write: Anytime when not in initialization mode; write of 1 clears flag, write of 0 is ignored 76543210 R0 0 0 00 TXE2 TXE1 TXE0 W Reset: 00000111 = Unimplemented Figure 14-10. MSCAN Transmitter Flag Register (CANTFLG) Table 14-13. CANTFLG Register Field Descriptions Field Description 2-0 TXE[2:0] Transmitter Buffer Empty— This flag indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort request (see Section 14.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). If not masked, a transmit interrupt is pending while this flag is set. Clearing a TXEx flag also clears the corresponding ABTAKx (see Section 14.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)”). When a TXEx flag is set, the corresponding ABTRQx bit is cleared (see Section 14.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). When listen-mode is active (see Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) the TXEx flags cannot be cleared and no transmission is started. Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared (TXEx = 0) and the buffer is scheduled for transmission.

0 The associated message buffer is full (loaded with a message due for transmission)

1 The associated message buffer is empty (not scheduled)

Module Base + 0x0007 Access: User read/write (1) 76543210 R 00000 TXEIE2 TXEIE1 TXEIE0 W Reset: 00000000 = Unimplemented Figure 14-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)

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The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0).

14.3.2.9 MSCAN Transmitter Message Abort Request Register (CANTARQ)

The CANTARQ register allows abort request of queued messages as described below. NOTE The CANTARQ register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). 1. Read: Anytime Write: Anytime when not in initialization mode Table 14-14. CANTIER Register Field Descriptions Field Description 2-0 TXEIE[2:0] Transmitter Empty Interrupt Enable 0 No interrupt request is generated from this event. 1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request. Module Base + 0x0008 Access: User read/write (1) 1. Read: Anytime Write: Anytime when not in initialization mode 76543210 R 00000 ABTRQ2 ABTRQ1 ABTRQ0 W Reset: 00000000 = Unimplemented Figure 14-12. MSCAN Transmitter Message Abort Request Register (CANTARQ) Table 14-15. CANTARQ Register Field Descriptions Field Description 2-0 ABTRQ[2:0] Abort Request — The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx = 0) be aborted. The MSCAN grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and abort acknowledge flags (ABTAK, see Section 14.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)”) are set and a transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated TXE flag is set.

0 No abort request

1 Abort request pending

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14.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)

The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register. NOTE The CANTAAK register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1).

14.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL)

The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be accessible in the CANTXFG register space. Module Base + 0x0009 Access: User read/write(1) 1. Read: Anytime Write: Unimplemented 76543210 R 00000 ABTAK2 ABTAK1 ABTAK0 W Reset: 00000000 = Unimplemented Figure 14-13. MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) Table 14-16. CANTAAK Register Field Descriptions Field Description 2-0 ABTAK[2:0] Abort Acknowledge — This flag acknowledges that a message was aborted due to a pending abort request from the CPU. After a particular message buffer is flagged empty, this flag can be used by the application software to identify whether the message was aborted successfully or was sent anyway. The ABTAKx flag is cleared whenever the corresponding TXE flag is cleared. 0 The message was not aborted. 1 The message was aborted. Module Base + 0x000A Access: User read/write (1) 1. Read: Find the lowest ordered bit set to 1, all other bits will be read as 0 Write: Anytime when not in initialization mode 76543210 R 00000 TX2 TX1 TX0 W Reset: 00000000 = Unimplemented Figure 14-14. MSCAN Transmit Buffer Selection Register (CANTBSEL)

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The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). The following gives a short programming example of the usage of the CANTBSEL register: To get the next available transmit buffer, application software must read the CANTFLG register and write this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1. Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. This mechanism eases the application software’s selection of the next available Tx buffer.

• LDAA CANTFLG; value read is 0b0000_0110
• STAA CANTBSEL; value written is 0b0000_0110
• LDAA CANTBSEL; value read is 0b0000_0010 If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers.

14.3.2.12 MSCAN Identifier Acceptance Control Register (CANIDAC)

The CANIDAC register is used for identifier acceptance control as described below. Table 14-17. CANTBSEL Register Field Descriptions Field Description 2-0 TX[2:0] Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx bit is cleared and the buffer is scheduled for transmission (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”).

0 The associated message buffer is deselected

1 The associated message buffer is selected, if lowest numbered bit

Module Base + 0x000B Access: User read/write (1) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only 76543210 R0 0 IDAM1 IDAM0 W Reset: 00000000 = Unimplemented Figure 14-15. MSCAN Identifier Acceptance Control Register (CANIDAC)

Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XHZ512 Data Sheet Rev. 1.06 Freescale Semiconductor 527 The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.

14.3.2.13 MSCAN Reserved Register

This register is reserved for factory testing of the MSCAN module and is not available in normal system operating modes. Table 14-18. CANIDAC Register Field Descriptions Field Description 5-4 IDAM[1:0] Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization (see Section 14.4.3, “Identifier Acceptance Filter”).Table 14-19summarizes the different settings. In filter closed mode, no message is accepted such that the foreground buffer is never reloaded. 2-0 IDHIT[2:0] Identifier Acceptance Hit Indicator — The MSCAN sets these flags to indicate an identifier acceptance hit (see Section 14.4.3, “Identifier Acceptance Filter”). Table 14-20 summarizes the different settings. Table 14-19. Identifier Acceptance Mode Settings IDAM1 IDAM0 Identifier Acceptance Mode 0 0 Two 32-bit acceptance filters 0 1 Four 16-bit acceptance filters 1 0 Eight 8-bit acceptance filters 1 1 Filter closed Table 14-20. Identifier Acceptance Hit Indication IDHIT2 IDHIT1 IDHIT0 Identifier Acceptance Hit 0 0 0 Filter 0 hit 0 0 1 Filter 1 hit 0 1 0 Filter 2 hit 0 1 1 Filter 3 hit 1 0 0 Filter 4 hit 1 0 1 Filter 5 hit 1 1 0 Filter 6 hit 1 1 1 Filter 7 hit

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Writing to this register when in special system operating modes can alter the MSCAN functionality.

14.3.2.14 MSCAN Miscellaneous Register (CANMISC)

This register provides additional features.

14.3.2.15 MSCAN Receive Error Counter (CANRXERR)

This register reflects the status of the MSCAN receive error counter. Module Base + 0x000C to Module Base + 0x000D Access: User read/write (1) 1. Read: Always reads zero in normal system operation modes Write: Unimplemented in normal system operation modes 76543210 R 00000000 W Reset: 00000000 = Unimplemented Figure 14-16. MSCAN Reserved Register Module Base + 0x000D Access: User read/write(1) 1. Read: Anytime Write: Anytime; write of ‘1’ clears flag; write of ‘0’ ignored 76543210 R 0000000 BOHOLD W Reset: 00000000 = Unimplemented Figure 14-17. MSCAN Miscellaneous Register (CANMISC) Table 14-21. CANMISC Register Field Descriptions Field Description BOHOLD Bus-off State Hold Until User Request — If BORM is set in MSCAN Control Register 1 (CANCTL1) , this bit indicates whether the module has entered the bus-off state. Clearing this bit requests the recovery from bus-off. Refer to Section 14.5.2, “Bus-Off Recovery,” for details.

0 Module is not bus-off or recovery has been requested by user in bus-off state

1 Module is bus-off and holds this state until user request

Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XHZ512 Data Sheet Rev. 1.06 Freescale Semiconductor 529 NOTE Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality.

14.3.2.16 MSCAN Transmit Error Counter (CANTXERR)

This register reflects the status of the MSCAN transmit error counter. NOTE Reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality. Module Base + 0x000E Access: User read/write(1) 1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented 76543210 R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 W Reset: 00000000 = Unimplemented Figure 14-18. MSCAN Receive Error Counter (CANRXERR) Module Base + 0x000F Access: User read/write(1) 1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented 76543210 R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 W Reset: 00000000 = Unimplemented Figure 14-19. MSCAN Transmit Error Counter (CANTXERR)

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14.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)

On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 14.3.3.1, “Identifier Registers (IDR0–IDR3)”) of incoming messages in a bit by bit manner (see Section 14.4.3, “Identifier Acceptance Filter”). For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only the first two (CANIDAR0/1, CANIDMR0/1) are applied. Module Base + 0x0010 to Module Base + 0x0013 Access: User read/write (1) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) 76543210 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 00000000 Figure 14-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3 Table 14-22. CANIDAR0–CANIDAR3 Register Field Descriptions Field Description 7-0 AC[7:0] Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. Module Base + 0x0018 to Module Base + 0x001B Access: User read/write (1) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) 76543210 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 00000000 Figure 14-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7

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14.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)

The identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.” To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.” Table 14-23. CANIDAR4–CANIDAR7 Register Field Descriptions Field Description 7-0 AC[7:0] Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. Module Base + 0x0014 to Module Base + 0x0017 Access: User read/write (1) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) 76543210 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 00000000 Figure 14-22. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3 Table 14-24. CANIDMR0–CANIDMR3 Register Field Descriptions Field Description 7-0 AM[7:0] Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted.

0 Match corresponding acceptance code register and identifier bits

1 Ignore corresponding acceptance code register bit

Module Base + 0x001C to Module Base + 0x001F Access: User read/write (1) 76543210 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 00000000 Figure 14-23. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7

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14.3.3 Programmer’s Model of Message Storage

The following section details the organization of the receive and transmit message buffers and the associated control registers. To simplify the programmer interface, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Within the last two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an internal timer after successful transmission or reception of a message. This feature is only available for transmit and receiver buffers, if the TIME bit is set (see Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The time stamp register is written by the MSCAN. The CPU can only read these registers. 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 14-25. CANIDMR4–CANIDMR7 Register Field Descriptions Field Description 7-0 AM[7:0] Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted.

Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XHZ512 Data Sheet Rev. 1.06 Freescale Semiconductor 533 Figure 14-24 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 14-25. All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation1. All reserved or unused bits of the receive and transmit buffers always read ‘x’. Table 14-26. Message Buffer Organization Offset Address Register Access 0x00X0 Identifier Register 0 R/W 0x00X1 Identifier Register 1 R/W 0x00X2 Identifier Register 2 R/W 0x00X3 Identifier Register 3 R/W 0x00X4 Data Segment Register 0 R/W 0x00X5 Data Segment Register 1 R/W 0x00X6 Data Segment Register 2 R/W 0x00X7 Data Segment Register 3 R/W 0x00X8 Data Segment Register 4 R/W 0x00X9 Data Segment Register 5 R/W 0x00XA Data Segment Register 6 R/W 0x00XB Data Segment Register 7 R/W 0x00XC Data Length Register R/W 0x00XD Transmit Buffer Priority Register (1) 1. Not applicable for receive buffers R/W 0x00XE Time Stamp Register (High Byte) R 0x00XF Time Stamp Register (Low Byte) R 1. Exception: The transmit buffer priority registers are 0 out of reset.

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Figure 14-24. Receive/Transmit Message Buffer — Extended Identifier Mapping Register Name Bit 7 654321 Bit0 0x00X0 IDR0 R ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 W 0x00X1 IDR1 R ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 W 0x00X2 IDR2 R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 W 0x00X3 IDR3 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W 0x00X4 DSR0 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X5 DSR1 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X6 DSR2 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X7 DSR3 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X8 DSR4 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X9 DSR5 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00XA DSR6 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00XB DSR7 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00XC DLR R DLC3 DLC2 DLC1 DLC0 W

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• For transmit buffers, anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
• For receive buffers, only when RXF flag is set (see Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). Write:
• For transmit buffers, anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
• Unimplemented for receive buffers. Reset: Undefined because of RAM-based implementation

14.3.3.1 Identifier Registers (IDR0–IDR3)

The identifier registers for an extended format identifier consist of a total of 32 bits: ID[28:0], SRR, IDE, and RTR. The identifier registers for a standard format identifier consist of a total of 13 bits: ID[10:0], RTR, and IDE. = Unused, always read ‘x’ Figure 14-25. Receive/Transmit Message Buffer — Standard Identifier Mapping Register Name Bit 7 654321 Bit 0 IDR0 0x00X0 R ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 W IDR1 0x00X1 R ID2 ID1 ID0 RTR IDE (=0) W IDR2 0x00X2 R W IDR3 0x00X3 R W = Unused, always read ‘x’ Figure 14-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued) Register Name Bit 7 654321 Bit0

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14.3.3.1.1 IDR0–IDR3 for Extended Identifier Mapping

R ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 W Reset: xxxxxxxx Figure 14-26. Identifier Register 0 (IDR0) — Extended Identifier Mapping Table 14-27. IDR0 Register Field Descriptions — Extended Field Description 7-0 ID[28:21] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. Module Base + 0x00X1 76543210 R ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 W Reset: xxxxxxxx Figure 14-27. Identifier Register 1 (IDR1) — Extended Identifier Mapping Table 14-28. IDR1 Register Field Descriptions — Extended Field Description 7-5 ID[20:18] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. SRR Substitute Remote Request — This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and is stored as received on the CAN bus for receive buffers. IDE ID Extended — This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send.

0 Standard format (11 bit)

1 Extended format (29 bit)

ID[17:15] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.

Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XHZ512 Data Sheet Rev. 1.06 Freescale Semiconductor 537 Module Base + 0x00X2 76543210 R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 W Reset: xxxxxxxx Figure 14-28. Identifier Register 2 (IDR2) — Extended Identifier Mapping Table 14-29. IDR2 Register Field Descriptions — Extended Field Description 7-0 ID[14:7] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. Module Base + 0x00X3 76543210 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W Reset: xxxxxxxx Figure 14-29. Identifier Register 3 (IDR3) — Extended Identifier Mapping Table 14-30. IDR3 Register Field Descriptions — Extended Field Description 7-1 ID[6:0] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. RTR Remote Transmission Request — This flag reflects the status of the remote transmission request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent.

0 Data frame

1 Remote frame

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14.3.3.1.2 IDR0–IDR3 for Standard Identifier Mapping

R ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 W Reset: xxxxxxxx Figure 14-30. Identifier Register 0 — Standard Mapping Table 14-31. IDR0 Register Field Descriptions — Standard Field Description 7-0 ID[10:3] Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 14-32. Module Base + 0x00X1 76543210 R ID2 ID1 ID0 RTR IDE (=0) W Reset: xxxxxxxx = Unused; always read ‘x’ Figure 14-31. Identifier Register 1 — Standard Mapping Table 14-32. IDR1 Register Field Descriptions Field Description 7-5 ID[2:0] Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 14-31. RTR Remote Transmission Request — This flag reflects the status of the Remote Transmission Request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. ID Extended — This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send.

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14.3.3.2 Data Segment Registers (DSR0-7)

The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received. The number of bytes to be transmitted or received is determined by the data length code in the corresponding DLR register. Module Base + 0x00X2 76543210 R W Reset: xxxxxxxx = Unused; always read ‘x’ Figure 14-32. Identifier Register 2 — Standard Mapping Module Base + 0x00X3 76543210 R W Reset: xxxxxxxx = Unused; always read ‘x’ Figure 14-33. Identifier Register 3 — Standard Mapping Module Base + 0x00X4 to Module Base + 0x00XB 76543210 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W Reset: xxxxxxxx Figure 14-34. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping Table 14-33. DSR0–DSR7 Register Field Descriptions Field Description 7-0 DB[7:0] Data bits 7-0

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14.3.3.3 Data Length Register (DLR)

This register keeps the data length field of the CAN frame.

14.3.3.4 Transmit Buffer Priority Register (TBPR)

This register defines the local priority of the associated message buffer. The local priority is used for the internal prioritization process of the MSCAN and is defined to be highest for the smallest binary number. The MSCAN implements the following internal prioritization mechanisms:

• All transmission buffers with a cleared TXEx flag participate in the prioritization immediately before the SOF (start of frame) is sent. Module Base + 0x00XC 76543210 R DLC3 DLC2 DLC1 DLC0 W Reset: xxxxxxxx = Unused; always read “x” Figure 14-35. Data Length Register (DLR) — Extended Identifier Mapping Table 14-34. DLR Register Field Descriptions Field Description 3-0 DLC[3:0] Data Length Code Bits— The data length code contains the number of bytes (data byte count) of the respective message. During the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 14-35 shows the effect of setting the DLC bits. Table 14-35. Data Length Codes Data Length Code Data Byte CountDLC3 DLC2 DLC1 DLC0 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8

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• The transmission buffer with the lowest local priority field wins the prioritization. In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins.

14.3.3.5 Time Stamp Register (TSRH–TSRL)

If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active transmit or receive buffer right after the EOF of a valid message on the CAN bus (seeSection 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only read the time stamp after the respective transmit buffer has been flagged empty. The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The CPU can only read the time stamp registers. Module Base + 0x00XD Access: User read/write(1) 1. Read: Anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”) Write: Anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”) 76543210 R PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 W Reset: 00000000 Figure 14-36. Transmit Buffer Priority Register (TBPR) Module Base + 0x00XE Access: User read/write(1) 1. Read: Anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”) Write: Unimplemented 76543210 R TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 W Reset: xxxxxxxx Figure 14-37. Time Stamp Register — High Byte (TSRH)

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Module Base + 0x00XF Access: User read/write(1) 1. Read: Anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”) Write: Unimplemented 76543210 R TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 W Reset: xxxxxxxx Figure 14-38. Time Stamp Register — Low Byte (TSRL)

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14.4 Functional Description

14.4.1 General

This section provides a complete functional description of the MSCAN.

14.4.2 Message Storage

Figure 14-39. User Model for Message Buffer Organization MSCAN Rx0 Rx1 CAN Receive / Transmit Engine Memory Mapped I/O CPU bus MSCAN Tx2 TXE2 PRIO Receiver Transmitter RxBG TxBG Tx0 TXE0 PRIO TxBG Tx1 PRIO TXE1 TxFG CPU bus Rx2 Rx3 Rx4 RXF RxFG

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The MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.

14.4.2.1 Message Transmit Background

Modern application layer software is built upon two fundamental assumptions:

• Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration.
• The internal message queue within any CAN node is organized such that the highest priority message is sent out first, if more than one message is ready to be sent. The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer must be reloaded immediately after the previous message is sent. This loading process lasts a finite amount of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a message is finished while the CPU re-loads the second buffer. No buffer would then be ready for transmission, and the CAN bus would be released. At least three transmit buffers are required to meet the first of the above requirements under all circumstances. The MSCAN has three transmit buffers. The second requirement calls for some sort of internal prioritization which the MSCAN implements with the “local priority” concept described in Section 14.4.2.2, “Transmit Structures.”

14.4.2.2 Transmit Structures

The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. The three buffers are arranged as shown in Figure 14-39. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see Section 14.3.3, “Programmer’s Model of Message Storage”). An additional Transmit Buffer Priority Register (TBPR) contains an 8-bit local priority field (PRIO) (see Section 14.3.3.4, “Transmit Buffer Priority Register (TBPR)”). The remaining two bytes are used for time stamping of a message, if required (see Section 14.3.3.5, “Time Stamp Register (TSRH–TSRL)”). To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (TXEx) flag (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the CANTBSEL register (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address space (see Section 14.3.3, “Programmer’s Model of Message Storage”). The algorithmic feature associated with the CANTBSEL register simplifies the transmit buffer selection. In addition, this scheme makes the handler

Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XHZ512 Data Sheet Rev. 1.06 Freescale Semiconductor 545 software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag. The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE flag. A transmit interrupt (seeSection 14.4.7.2, “Transmit Interrupt”) is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer. If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software programs this field when the message is set up. The local priority reflects the priority of this particular message relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO field is defined to be the highest priority. The internal scheduling process takes place whenever the MSCAN arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error. When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers. Because messages that are already in transmission cannot be aborted, the user must request the abort by setting the corresponding abort request bit (ABTRQ) (see Section 14.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”.) The MSCAN then grants the request, if possible, by: 1. Setting the corresponding abort acknowledge flag (ABTAK) in the CANTAAK register. 2. Setting the associated TXE flag to release the buffer. 3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the setting of the ABTAK flag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).

14.4.2.3 Receive Structures

The received messages are stored in a five stage input FIFO. The five message buffers are alternately mapped into a single memory area (see Figure 14-39). The background receive buffer (RxBG) is exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the CPU (see Figure 14-39). This scheme simplifies the handler software because only one address area is applicable for the receive process. All receive buffers have a size of 15 bytes to store the CAN control bits, the identifier (standard or extended), the data contents, and a time stamp, if enabled (see Section 14.3.3, “Programmer’s Model of Message Storage”). The receiver full flag (RXF) (see Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”) signals the status of the foreground receive buffer. When the buffer contains a correctly received message with a matching identifier, this flag is set. On reception, each message is checked to see whether it passes the filter (see Section 14.4.3, “Identifier Acceptance Filter”) and simultaneously is written into the active RxBG. After successful reception of a valid message, the MSCAN shifts the content of RxBG into the receiver FIFO, sets the RXF flag, and 1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also.

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generates a receive interrupt1 (see Section 14.4.7.3, “Receive Interrupt”) to the CPU. The user’s receive handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO. When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt, or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) where the MSCAN treats its own messages exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver. An overrun condition occurs when all receive message buffers in the FIFO are filled with correctly received messages with accepted identifiers and another message is correctly received from the CAN bus with an accepted identifier. The latter message is discarded and an error interrupt with overrun indication is generated if enabled (see Section 14.4.7.5, “Error Interrupt”). The MSCAN remains able to transmit messages while the receiver FIFO is being filled, but all incoming messages are discarded. As soon as a receive buffer in the FIFO is available again, new valid messages will be accepted.

14.4.3 Identifier Acceptance Filter

The MSCAN identifier acceptance registers (see Section 14.3.2.12, “MSCAN Identifier Acceptance Control Register (CANIDAC)”) define the acceptable patterns of the standard or extended identifier (ID[10:0] or ID[28:0]). Any of these bits can be marked ‘don’t care’ in the MSCAN identifier mask registers (see Section 14.3.2.18, “MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)”). A filter hit is indicated to the application software by a set receive buffer full flag (RXF = 1) and three bits in the CANIDAC register (see Section 14.3.2.12, “MSCAN Identifier Acceptance Control Register (CANIDAC)”). These identifier hit flags (IDHIT[2:0]) clearly identify the filter section that caused the acceptance. They simplify the application software’s task to identify the cause of the receiver interrupt. If more than one hit occurs (two or more filters match), the lower hit has priority. A very flexible programmable generic identifier acceptance filter has been introduced to reduce the CPU interrupt loading. The filter is programmable to operate in four different modes:

• Two identifier acceptance filters, each to be applied to: — The full 29 bits of the extended identifier and to the following bits of the CAN 2.0B frame: – Remote transmission request (RTR) – Identifier extension (IDE) – Substitute remote request (SRR) — The 11 bits of the standard identifier plus the RTR and IDE bits of the CAN 2.0A/B messages. This mode implements two filters for a full length CAN 2.0B compliant extended identifier. Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters. 1. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also.

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Figure 14-41. 16-bit Maskable Identifier Acceptance Filters ID28 ID21 IDR0 ID10 ID3 IDR0 ID20 ID15 IDR1 ID2 IDE IDR1 ID14 ID7 IDR2 ID10 ID3 IDR2 ID6 RTR IDR3 ID10 ID3 IDR3 AC7 AC0 CANIDAR0 AM7 AM0 CANIDMR0 AC7 AC0 CANIDAR1 AM7 AM0 CANIDMR1 ID Accepted (Filter 0 Hit) AC7 AC0 CANIDAR2 AM7 AM0 CANIDMR2 AC7 AC0 CANIDAR3 AM7 AM0 CANIDMR3 ID Accepted (Filter 1 Hit) CAN 2.0B Extended Identifier CAN 2.0A/B Standard Identifier

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14.4.3.1 Protocol Violation Protection

The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features:

• The receive and transmit error counters cannot be written or otherwise manipulated.
• All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK handshake bits in the CANCTL0/CANCTL1 registers (see Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) serve as a lock to protect the following registers: — MSCAN control 1 register (CANCTL1) — MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1) — MSCAN identifier acceptance control register (CANIDAC) — MSCAN identifier acceptance registers (CANIDAR0–CANIDAR7) — MSCAN identifier mask registers (CANIDMR0–CANIDMR7)
• The TXCAN is immediately forced to a recessive state when the MSCAN goes into the power down mode or initialization mode (see Section 14.4.5.6, “MSCAN Power Down Mode,” and Section 14.4.4.5, “MSCAN Initialization Mode”).
• The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which provides further protection against inadvertently disabling the MSCAN.

14.4.3.2 Clock System

Figure 14-43 shows the structure of the MSCAN clock generation circuitry. Figure 14-43. MSCAN Clocking Scheme The clock source bit (CLKSRC) in the CANCTL1 register (14.3.2.2/14-515) defines whether the internal CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock. The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the clock is required. If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. Bus Clock Oscillator Clock MSCAN CANCLK CLKSRC CLKSRC Prescaler (1 .. 64) Time quanta clock (Tq)

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The synchronization jump width (see the Bosch CAN 2.0A/B specification for details) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are set by programming the MSCAN bus timing registers (CANBTR0, CANBTR1) (seeSection 14.3.2.3, “MSCAN Bus Timing Register 0 (CANBTR0)” and Section 14.3.2.4, “MSCAN Bus Timing Register 1 (CANBTR1)”). Table 14-37gives an overview of the Bosch CAN 2.0A/B specification compliant segment settings and the related parameter values. NOTE It is the user’s responsibility to ensure the bit time settings are in compliance with the CAN standard.

14.4.4 Modes of Operation

14.4.4.1 Normal System Operating Modes

The MSCAN module behaves as described within this specification in all normal system operating modes. Write restrictions exist for some registers. Table 14-36. Time Segment Syntax Syntax Description SYNC_SEG System expects transitions to occur on the CAN bus during this period. Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point. Sample Point A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample. Table 14-37. Bosch CAN 2.0A/B Compliant Bit Time Segment Settings Time Segment 1 TSEG1 Time Segment 2 TSEG2 Synchronization Jump Width SJW

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14.4.4.2 Special System Operating Modes

The MSCAN module behaves as described within this specification in all special system operating modes. Write restrictions which exist on specific registers in normal modes are lifted for test purposes in special modes.

14.4.4.3 Emulation Modes

In all emulation modes, the MSCAN module behaves just like in normal system operating modes as described within this specification.

14.4.4.4 Listen-Only Mode

In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames and valid remote frames, but it sends only “recessive” bits on the CAN bus. In addition, it cannot start a transmission. If the MAC sub-layer is required to send a “dominant” bit (ACK bit, overload flag, or active error flag), the bit is rerouted internally so that the MAC sub-layer monitors this “dominant” bit, although the CAN bus may remain in recessive state externally.

14.4.4.5 MSCAN Initialization Mode

The MSCAN enters initialization mode when it is enabled (CANE=1). When entering initialization mode during operation, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations, the MSCAN immediately drives TXCAN into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when initialization mode is entered. The recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going message can cause an error condition and can impact other CAN bus devices. In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the configuration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message filters. See Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0),” for a detailed description of the initialization mode.

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Figure 14-45. Initialization Request/Acknowledge Cycle Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay (see Figure 14-45). If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the INITAK flag is set. The application software must use INITAK as a handshake indication for the request (INITRQ) to go into initialization mode. NOTE The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and INITAK = 1) is active.

14.4.5 Low-Power Options

If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving. If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption is reduced by stopping all clocks except those to access the registers from the CPU side. In power down mode, all clocks are stopped and no power is consumed. Table 14-38 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSW AI and SLPRQ/SLPAK bits. SYNC SYNC Bus Clock Domain CAN Clock Domain CPU Init Request INIT Flag INITAK Flag INITRQ sync. INITAK sync. INITRQ INITAK

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14.4.5.1 Operation in Run Mode

As shown in Table 14-38, only MSCAN sleep mode is available as low power option when the CPU is in run mode.

14.4.5.2 Operation in Wait Mode

The W AI instruction puts the MCU in a low power consumption stand-by mode. If the CSW AI bit is set, additional power can be saved in power down mode because the CPU clocks are stopped. After leaving this power down mode, the MSCAN restarts and enters normal mode again. While the CPU is in wait mode, the MSCAN can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode).

14.4.5.3 Operation in Stop Mode

The STOP instruction puts the MCU in a low power consumption stand-by mode. In stop mode, the MSCAN is set in power down mode regardless of the value of the SLPRQ/SLPAK and CSW AI bits (Table 14-38).

14.4.5.4 MSCAN Normal Mode

This is a non-power-saving mode. Enabling the MSCAN puts the module from disabled mode into normal mode. In this mode the module can either be in initialization mode or out of initialization mode. See Section 14.4.4.5, “MSCAN Initialization Mode”. Table 14-38. CPU vs. MSCAN Operating Modes CPU Mode MSCAN Mode Normal Reduced Power Consumption Sleep Power Down Disabled (CANE=0) RUN CSWAI = X(1) SLPRQ = 0 SLPAK = 0 1. ‘X’ means don’t care. CSWAI = X SLPRQ = 1 SLPAK = 1 CSWAI = X SLPRQ = X SLPAK = X WAIT CSWAI = 0 SLPRQ = 0 SLPAK = 0 CSWAI = 0 SLPRQ = 1 SLPAK = 1 CSWAI = 1 SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X STOP CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X

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14.4.5.5 MSCAN Sleep Mode

The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a fixed synchronization delay and its current activity:

• If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted successfully or aborted) and then goes into sleep mode.
• If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle.
• If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode. Figure 14-46. Sleep Request / Acknowledge Cycle NOTE The application software must avoid setting up a transmission (by clearing one or more TXEx flag(s)) and immediately request sleep mode (by setting SLPRQ). Whether the MSCAN starts transmitting or goes into sleep mode directly depends on the exact sequence of operations. If sleep mode is active, the SLPRQ and SLPAK bits are set (Figure 14-46). The application software must use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode. When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks that allow register accesses from the CPU side continue to run. If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. TXCAN remains in a recessive state. If RXF = 1, the message can be read and RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does not take place while in sleep mode. It is possible to access the transmit buffers and to clear the associated TXE flags. No message abort takes place while in sleep mode. SYNC SYNC Bus Clock Domain CAN Clock Domain MSCAN in Sleep Mode CPU Sleep Request SLPRQ Flag SLPAK Flag SLPRQ sync. SLPAK sync. SLPRQ SLPAK

Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XHZ512 Data Sheet Rev. 1.06 Freescale Semiconductor 557 If the WUPE bit in CANCTL0 is not asserted, the MSCAN will mask any activity it detects on CAN. RXCAN is therefore held internally in a recessive state. This locks the MSCAN in sleep mode. WUPE must be set before entering sleep mode to take effect. The MSCAN is able to leave sleep mode (wake up) only when:

• CAN bus activity occurs and WUPE = 1 or
• the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active. After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it continues counting the 128 occurrences of 11 consecutive recessive bits.

14.4.5.6 MSCAN Power Down Mode

The MSCAN is in power down mode (Table 14-38) when

• CPU is in stop mode or
• CPU is in wait mode and the CSW AI bit is set When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN immediately drives TXCAN into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when power down mode is entered. The recommended procedure is to bring the MSCAN into Sleep mode before the STOP or W AI instruction (if CSW AI is set) is executed. Otherwise, the abort of an ongoing message can cause an error condition and impact other CAN bus devices. In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. This causes some fixed delay before the module enters normal mode again.

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14.4.5.7 Disabled Mode

The MSCAN is in disabled mode out of reset (CANE=0). All module clocks are stopped for power saving, however the register map can still be accessed as specified.

14.4.5.8 Programmable Wake-Up Function

The MSCAN can be programmed to wake up from sleep or power down mode as soon as CAN bus activity is detected (see control bit WUPE in MSCAN Control Register 0 (CANCTL0). The sensitivity to existing CAN bus action can be modified by applying a low-pass filter function to the RXCAN input line (see control bit WUPM in Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines. Such glitches can result from—for example—electromagnetic interference within noisy environments.

14.4.6 Reset Initialization

The reset state of each individual bit is listed in Section 14.3.2, “Register Descriptions,” which details all the registers and their bit-fields.

14.4.7 Interrupts

This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated flags. Each interrupt is listed and described separately.

14.4.7.1 Description of Interrupt Operation

The MSCAN supports four interrupt vectors (see Table 14-39), any of which can be individually masked (for details see Section 14.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)” to Section 14.3.2.8, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”). Refer to the device overview section to determine the dedicated interrupt vector addresses.

14.4.7.2 Transmit Interrupt

At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx flag of the empty message buffer is set. Table 14-39. Interrupt Vectors Interrupt Source CCR Mask Local Enable Wake-Up Interrupt (WUPIF) I bit CANRIER (WUPIE) Error Interrupts Interrupt (CSCIF , OVRIF) I bit CANRIER (CSCIE, OVRIE) Receive Interrupt (RXF) I bit CANRIER (RXFIE) Transmit Interrupts (TXE[2:0]) I bit CANTIER (TXEIE[2:0])

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14.4.7.3 Receive Interrupt

A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the foreground buffer.

14.4.7.4 Wake-Up Interrupt

A wake-up interrupt is generated if activity on the CAN bus occurs during MSCAN sleep or power-down mode. NOTE This interrupt can only occur if the MSCAN was in sleep mode (SLPRQ = 1 and SLPAK = 1) before entering power down mode, the wake-up option is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).

14.4.7.5 Error Interrupt

An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition occurrs. MSCAN Receiver Flag Register (CANRFLG) indicates one of the following conditions:

• Overrun — An overrun condition of the receiver FIFO as described in Section 14.4.2.3, “Receive Structures,” occurred.
• CAN Status Change — The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rx- warning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change, which caused the error condition, is indicated by the TSTAT and RSTAT flags (seeSection 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)” and Section 14.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)”).

14.4.7.6 Interrupt Acknowledge

Interrupts are directly associated with one or more status flags in either the MSCAN Receiver Flag Register (CANRFLG) or the MSCAN Transmitter Flag Register (CANTFLG). Interrupts are pending as long as one of the corresponding flags is set. The flags in CANRFLG and CANTFLG must be reset within the interrupt handler to handshake the interrupt. The flags are reset by writing a 1 to the corresponding bit position. A flag cannot be cleared if the respective condition prevails. NOTE It must be guaranteed that the CPU clears only the bit causing the current interrupt. For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt flags. These instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine.

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14.5 Initialization/Application Information

14.5.1 MSCAN initialization

The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the configuration registers in initialization mode 3. Clear INITRQ to leave initialization mode If the configuration of registers which are only writable in initialization mode shall be changed: 1. Bring the module into sleep mode by setting SLPRQ and awaiting SLPAK to assert after the CAN bus becomes idle. 2. Enter initialization mode: assert INITRQ and await INITAK 3. Write to the configuration registers in initialization mode 4. Clear INITRQ to leave initialization mode and continue

14.5.2 Bus-Off Recovery

The bus-off recovery is user configurable. The bus-off state can either be left automatically or on user request. For reasons of backwards compatibility, the MSCAN defaults to automatic recovery after reset. In this case, the MSCAN will become error active again after counting 128 occurrences of 11 consecutive recessive bits on the CAN bus (see the Bosch CAN 2.0 A/B specification for details). If the MSCAN is configured for user request (BORM set in MSCAN Control Register 1 (CANCTL1)), the recovery from bus-off starts after both independent events have become true:

• 128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored
• BOHOLD in MSCAN Miscellaneous Register (CANMISC) has been cleared by the user These two events may occur in any order.

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15.1 Introduction

This block guide provides an overview of the serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs.

15.1.1 Glossary

IR: InfraRed IrDA: Infrared Design Associate IRQ: Interrupt Request LIN: Local Interconnect Network LSB: Least Significant Bit MSB: Most Significant Bit NRZ: Non-Return-to-Zero RZI: Return-to-Zero-Inverted RXD: Receive Pin SCI : Serial Communication Interface TXD: Transmit Pin Table 15-1. Revision History Version Number Revision Date Effective Date Author Description of Changes 05.03 12/25/2008 remove redundancy comments in Figure1-2 05.04 08/05/2009 fix typo, SCIBDL reset value be 0x04, not 0x00 05.05 06/03/2010 fix typo, Table 15-4,SCICR1 Even parity should be PT=0 fix typo, on page 15-583,should be BKDIF,not BLDIF

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15.1.2 Features

The SCI includes these distinctive features:

• Full-duplex or single-wire operation
• Standard mark/space non-return-to-zero (NRZ) format
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
• 13-bit baud rate selection
• Programmable 8-bit or 9-bit data format
• Separately enabled transmitter and receiver
• Programmable polarity for transmitter and receiver
• Programmable transmitter output parity
• Two receiver wakeup methods: — Idle line wakeup — Address mark wakeup
• Interrupt-driven operation with eight flags: — Transmitter empty — Transmission complete — Receiver full — Idle receiver input — Receiver overrun — Noise error — Framing error — Parity error — Receive wakeup on active edge — Transmit collision detect supporting LIN — Break Detect supporting LIN
• Receiver framing error detection
• Hardware parity checking
• 1/16 bit-time noise detection

15.1.3 Modes of Operation

The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes.

• Run mode
• Wait mode
• Stop mode

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15.1.4 Block Diagram

Figure 15-1 is a high level block diagram of the SCI module, showing the interaction of various function blocks. Figure 15-1. SCI Block Diagram SCI Data Register RXD Data In Data Out TXD Receive Shift RegisterInfrared Decoder Receive & Wakeup Control Data Format Control Transmit Control Baud Rate Generator Bus Clock Transmit Shift Register SCI Data Register Receive Interrupt Generation Transmit Interrupt Generation Infrared Encoder IDLE RDRF/OR TC TDRE BRKD BERR RXEDG SCI Interrupt Request

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15.2 External Signal Description

The SCI module has a total of two external pins.

15.2.1 TXD — Transmit Pin

The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled.

15.2.2 RXD — Receive Pin

The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high. This input is ignored when the receiver is disabled and should be terminated to a known voltage.

15.3 Memory Map and Register Definition

This section provides a detailed description of all the SCI registers.

15.3.1 Module Memory Map and Register Definition

The memory map for the SCI module is given below inFigure 15-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register.

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15.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register locations do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order. Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 SCIBDH1 R IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 W 0x0001 SCIBDL1 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W 0x0002 SCICR11 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W 0x0000 SCIASR12 R RXEDGIF 0000 BERRV BERRIF BKDIF W 0x0001 SCIACR12 R RXEDGIE 00000 BERRIE BKDIE W 0x0002 SCIACR22 R 00000 BERRM1 BERRM0 BKDFE W 0x0003 SCICR2 R TIE TCIE RIE ILIE TE RE RWU SBK W 0x0004 SCISR1 R TDRE TC RDRF IDLE OR NF FE PF W 0x0005 SCISR2 R AMAP TXPOL RXPOL BRK13 TXDIR RAF W 0x0006 SCIDRH RR 8 000000 W 0x0007 SCIDRL R R 7R 6R 5R 4R 3R 2R 1R 0 W T 7T 6T 5T 4T 3T 2T 1T 0 1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one. = Unimplemented or Reserved Figure 15-2. SCI Register Summary

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15.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL)

Read: Anytime, if AMAP = 0. If only SCIBDH is written to, a read will not return the correct data until SCIBDL is written to as well, following a write to SCIBDH. Write: Anytime, if AMAP = 0. NOTE Those two registers are only visible in the memory map if AMAP = 0 (reset condition). The SCI baud rate register is used by to determine the baud rate of the SCI, and to control the infrared modulation/demodulation submodule. Module Base + 0x0000 76543210 R IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 W Reset 0 0 0 00000 Figure 15-3. SCI Baud Rate Register (SCIBDH) Module Base + 0x0001 76543210 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W Reset 0 0 0 00100 Figure 15-4. SCI Baud Rate Register (SCIBDL) Table 15-2. SCIBDH and SCIBDL Field Descriptions Field Description IREN Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule.

0 IR disabled

1 IR enabled

6:5 TNP[1:0] Transmitter Narrow Pulse Bits— These bits enable whether the SCI transmits a 1/16, 3/16, 1/32 or 1/4 narrow pulse. See Table 15-3. 4:0 7:0 SBR[12:0] SCI Baud Rate Bits — The baud rate for the SCI is determined by the bits in this register. The baud rate is calculated two different ways depending on the state of the IREN bit. The formulas for calculating the baud rate are: When IREN = 0 then, SCI baud rate = SCI bus clock / (16 x SBR[12:0]) When IREN = 1 then, SCI baud rate = SCI bus clock / (32 x SBR[12:1]) Note: The baud rate generator is disabled after reset and not started until the TE bit or the RE bit is set for the first time. The baud rate generator is disabled when (SBR[12:0] = 0 and IREN = 0) or (SBR[12:1] = 0 and IREN = 1). Note: Writing to SCIBDH has no effect without writing to SCIBDL, because writing to SCIBDH puts the data in a temporary location until SCIBDL is written to.

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15.3.2.2 SCI Control Register 1 (SCICR1)

Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NOTE This register is only visible in the memory map if AMAP = 0 (reset condition). Table 15-3. IRSCI Transmit Pulse Width TNP[1:0] Narrow Pulse Width 11 1/4 10 1/32 01 1/16 00 3/16 Module Base + 0x0002 76543210 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W Reset 0 0 0 00000 Figure 15-5. SCI Control Register 1 (SCICR1) Table 15-4. SCICR1 Field Descriptions Field Description LOOPS Loop Select Bit— LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function.

0 Normal operation enabled

1 Loop operation enabled

The receiver input is determined by the RSRC bit. SCISWAI SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode.

0 SCI enabled in wait mode

1 SCI disabled in wait mode

Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register input. See Table 15-5.

0 Receiver input internally connected to transmitter output

1 Receiver input connected externally to transmitter

M Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long.

0 One start bit, eight data bits, one stop bit

1 One start bit, nine data bits, one stop bit

Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received data character or an idle condition on the RXD pin.

0 Idle line wakeup

1 Address mark wakeup

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Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions.

0 Idle character bit count begins after start bit

1 Idle character bit count begins after stop bit

Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position.

0 Parity function disabled

1 Parity function enabled

Parity Type Bit— PT determines whether the SCI generates and checks for even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.

0 Even parity

1 Odd parity

Table 15-5. Loop Functions LOOPS RSRC Function 0 x Normal operation 1 0 Loop mode with transmitter output internally connected to receiver input 1 1 Single-wire mode with TXD pin connected to receiver input Table 15-4. SCICR1 Field Descriptions (continued) Field Description

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15.3.2.3 SCI Alternative Status Register 1 (SCIASR1)

Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Module Base + 0x0000 76543210 R RXEDGIF 0 0 0 0 BERRV BERRIF BKDIF W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 15-6. SCI Alternative Status Register 1 (SCIASR1) Table 15-6. SCIASR1 Field Descriptions Field Description RXEDGIF Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.

0 No active receive on the receive input has occurred

1 An active edge on the receive input has occurred

Bit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.

0 A low input was sampled, when a high was expected

1 A high input reassembled, when a low was expected

Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.

0 No mismatch detected

1 A mismatch has occurred

Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing a “1” to it.

0 No break signal was received

1 A break signal was received

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15.3.2.4 SCI Alternative Control Register 1 (SCIACR1)

Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Module Base + 0x0001 76543210 R RXEDGIE 00000 BERRIE BKDIE W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 15-7. SCI Alternative Control Register 1 (SCIACR1) Table 15-7. SCIACR1 Field Descriptions Field Description RSEDGIE Receive Input Active Edge Interrupt Enable— RXEDGIE enables the receive input active edge interrupt flag, RXEDGIF , to generate interrupt requests.

0 RXEDGIF interrupt requests disabled

1 RXEDGIF interrupt requests enabled

Bit Error Interrupt Enable — BERRIE enables the bit error interrupt flag, BERRIF , to generate interrupt requests.

0 BERRIF interrupt requests disabled

1 BERRIF interrupt requests enabled

Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF , to generate interrupt requests.

0 BKDIF interrupt requests disabled

1 BKDIF interrupt requests enabled

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15.3.2.5 SCI Alternative Control Register 2 (SCIACR2)

Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Module Base + 0x0002 76543210 R 00000 BERRM1 BERRM0 BKDFE W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 15-8. SCI Alternative Control Register 2 (SCIACR2) Table 15-8. SCIACR2 Field Descriptions Field Description 2:1 BERRM[1:0] Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 15-9. BKDFE Break Detect Feature Enable — BKDFE enables the break detect circuitry.

0 Break detect circuit disabled

1 Break detect circuit enabled

Table 15-9. Bit Error Mode Coding BERRM1 BERRM0 Function 0 0 Bit error detect circuit is disabled 0 1 Receive input sampling occurs during the 9th time tick of a transmitted bit (refer to Figure 15-19) 1 0 Receive input sampling occurs during the 13th time tick of a transmitted bit (refer to Figure 15-19) 1 1 Reserved

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15.3.2.6 SCI Control Register 2 (SCICR2)

Read: Anytime Write: Anytime Module Base + 0x0003 76543210 R TIE TCIE RIE ILIE TE RE RWU SBK W Reset 0 0 0 00000 Figure 15-9. SCI Control Register 2 (SCICR2) Table 15-10. SCICR2 Field Descriptions Field Description TIE Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests.

0 TDRE interrupt requests disabled

1 TDRE interrupt requests enabled

Transmission Complete Interrupt Enable Bit— TCIE enables the transmission complete flag, TC, to generate interrupt requests.

0 TC interrupt requests disabled

1 TC interrupt requests enabled

Receiver Full Interrupt Enable Bit— RIE enables the receive data register full flag, RDRF , or the overrun flag, OR, to generate interrupt requests.

0 RDRF and OR interrupt requests disabled

1 RDRF and OR interrupt requests enabled

Idle Line Interrupt Enable Bit — ILIE enables the idle line flag, IDLE, to generate interrupt requests.

0 IDLE interrupt requests disabled

1 IDLE interrupt requests enabled

Transmitter Enable Bit — TE enables the SCI transmitter and configures the TXD pin as being controlled by the SCI. The TE bit can be used to queue an idle preamble.

0 Transmitter disabled

1 Transmitter enabled

Receiver Enable Bit — RE enables the SCI receiver.

0 Receiver disabled

1 Receiver enabled

Receiver Wakeup Bit — Standby state 0 Normal operation. 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. SBK Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits).

0 No break characters

1 Transmit break characters

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15.3.2.7 SCI Status Register 1 (SCISR1)

The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.It is permissible to execute other instructions between the two steps as long as it does not compromise the handling of I/O, but the order of operations is important for flag clearing. Read: Anytime Write: Has no meaning or effect Module Base + 0x0004 76543210 R TDRE TC RDRF IDLE OR NF FE PF W Reset 1 1 0 00000 = Unimplemented or Reserved Figure 15-10. SCI Status Register 1 (SCISR1) Table 15-11. SCISR1 Field Descriptions Field Description TDRE Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data register low (SCIDRL).

0 No byte transferred to transmit shift register

1 Byte transferred to transmit shift register; transmit data register empty

Transmit Complete Flag— TC is set low when there is a transmission in progress or when a preamble or break character is loaded. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted.When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data, preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of the TC flag (transmission not complete).

0 Transmission in progress

1 No transmission in progress

Receive Data Register Full Flag — RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data register low (SCIDRL).

0 Data not available in SCI data register

1 Received data available in SCI data register

Idle Line Flag — IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M =1) appear on the receiver input. Once the IDLE flag is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL).

0 Receiver input is either active now or has never become active since the IDLE flag was last cleared

1 Receiver input has become idle

Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag.

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Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected. Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low (SCIDRL).

0 No overrun

1 Overrun

Note: OR flag may read back as set when RDRF flag is clear. This may happen if the following sequence of events occurs: 1. After the first frame is received, read status register SCISR1 (returns RDRF set and OR flag clear); 2. Receive second frame without reading the first frame in the data register (the second frame is not received and OR flag is set); 3. Read data register SCIDRL (returns first frame and clears RDRF flag in the status register); 4. Read status register SCISR1 (returns RDRF clear and OR set). Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received. NF Noise Flag — NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1), and then reading SCI data register low (SCIDRL).

0 No noise

1 Noise

Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register low (SCIDRL).

0 No framing error

1 Framing error

Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL).

0 No parity error

1 Parity error

Table 15-11. SCISR1 Field Descriptions (continued) Field Description

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15.3.2.8 SCI Status Register 2 (SCISR2)

Read: Anytime Write: Anytime Module Base + 0x0005 76543210 R AMAP TXPOL RXPOL BRK13 TXDIR RAF W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 15-11. SCI Status Register 2 (SCISR2) Table 15-12. SCISR2 Field Descriptions Field Description AMAP Alternative Map — This bit controls which registers sharing the same address space are accessible. In the reset condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and status registers and hides the baud rate and SCI control Register 1.

0 The registers labelled SCIBDH (0x0000),SCIBDL (0x0001), SCICR1 (0x0002) are accessible

1 The registers labelled SCIASR1 (0x0000),SCIACR1 (0x0001), SCIACR2 (0x00002) are accessible

Transmit Polarity— This bit control the polarity of the transmitted data. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity.

0 Normal polarity

1 Inverted polarity

Receive Polarity — This bit control the polarity of the received data. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit.

0 Break character is 10 or 11 bit long

1 Break character is 13 or 14 bit long

Transmitter Pin Data Direction in Single-Wire Mode — This bit determines whether the TXD pin is going to be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire mode of operation.

0 TXD pin to be used as an input in single-wire mode

1 TXD pin to be used as an output in single-wire mode

Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character.

0 No reception in progress

1 Reception in progress

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15.3.2.9 SCI Data Registers (SCIDRH, SCIDRL)

Read: Anytime; reading accesses SCI receive data register Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect NOTE If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same value is transmitted until T8 is rewritten In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIDRH), then SCIDRL. Module Base + 0x0006 76543210 RR 8 000000 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 15-12. SCI Data Registers (SCIDRH) Module Base + 0x0007 76543210 R R 7R 6R 5R 4R 3R 2R 1R 0 W T7 T6 T5 T4 T3 T2 T1 T0 Reset 0 0 0 00000 Figure 15-13. SCI Data Registers (SCIDRL) Table 15-13. SCIDRH and SCIDRL Field Descriptions Field Description SCIDRH Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1). SCIDRH Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1). SCIDRL 7:0 R[7:0] T[7:0] R7:R0 — Received bits seven through zero for 9-bit or 8-bit data formats T7:T0 — Transmit bits seven through zero for 9-bit or 8-bit formats

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15.4 Functional Description

This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 15-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. Figure 15-14. Detailed SCI Block Diagram SCI Data Receive Shift Register SCI Data Register Transmit Shift Register Register Baud Rate Generator SBR12:SBR0 Bus Transmit Control÷16 Receive and Wakeup Data Format Control Control PF FE NF RDRF IDLE TIE OR TCIE TDRE TC RAF LOOPS RWU RE PE ILT PT WAKE M Clock ILIE RIE RXD RSRC SBK LOOPS TE RSRC IREN R16XCLK Ir_RXD TXDIr_TXD R16XCLK R32XCLK TNP[1:0] IREN Transmit Encoder Receive Decoder SCRXD SCTXD Infrared Infrared TC TDRE RDRF/OR IDLE Active Edge Detect Break Detect RXD BKDFE BERRM[1:0] BKDIE BKDIF RXEDGIE RXEDGIF BERRIE BERRIF SCI Interrupt Request LIN Transmit Collision Detect

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15.4.1 Infrared Interface Submodule

This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer specification defines a half-duplex infrared communication link for exchange data. The full standard includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 Kbits/s and 115.2 Kbits/s. The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse for every zero bit. No pulse is transmitted for every one bit. When receiving data, the IR pulses should be detected using an IR photo diode and transformed to CMOS levels by the IR receive decoder (external from the MCU). The narrow pulses are then stretched by the infrared submodule to get back to a serial bit stream to be received by the SCI.The polarity of transmitted pulses and expected receive pulses can be inverted so that a direct connection can be made to external IrDA transceiver modules that uses active low pulses. The infrared submodule receives its clock sources from the SCI. One of these two clocks are selected in the infrared submodule in order to generate either 3/16, 1/16, 1/32 or 1/4 narrow pulses during transmission. The infrared block receives two clock sources from the SCI, R16XCLK and R32XCLK, which are configured to generate the narrow pulse width during transmission. The R16XCLK and R32XCLK are internal clocks with frequencies 16 and 32 times the baud rate respectively. Both R16XCLK and R32XCLK clocks are used for transmitting data. The receive decoder uses only the R16XCLK clock.

15.4.1.1 Infrared Transmit Encoder

The infrared transmit encoder converts serial bits of data from transmit shift register to the TXD pin. A narrow pulse is transmitted for a zero bit and no pulse for a one bit. The narrow pulse is sent in the middle of the bit with a duration of 1/32, 1/16, 3/16 or 1/4 of a bit time. A narrow high pulse is transmitted for a zero bit when TXPOL is cleared, while a narrow low pulse is transmitted for a zero bit when TXPOL is set.

15.4.1.2 Infrared Receive Decoder

The infrared receive block converts data from the RXD pin to the receive shift register. A narrow pulse is expected for each zero received and no pulse is expected for each one received. A narrow high pulse is expected for a zero bit when RXPOL is cleared, while a narrow low pulse is expected for a zero bit when RXPOL is set. This receive decoder meets the edge jitter requirement as defined by the IrDA serial infrared physical layer specification.

15.4.2 LIN Support

This module provides some basic support for the LIN protocol. At first this is a break detect circuitry making it easier for the LIN software to distinguish a break character from an incoming data stream. As a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions.

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15.4.3 Data Format

The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 15-15 below. Figure 15-15. SCI Data Formats Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. Clearing the M bit in SCI control register 1 configures the SCI for 8-bit data characters. A frame with eight data bits has a total of 10 bits. Setting the M bit configures the SCI for nine-bit data characters. A frame with nine data bits has a total of 11 bits. When the SCI is configured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits. Table 15-14. Example of 8-Bit Data Formats Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 8001 1 7011 17 1

1 The address bit identifies the frame as an address

Table 15-15. Example of 9-Bit Data Formats Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 9001 1 8011 18 1 1 01 Bit 5 Start Bit Bit 0 Bit 1 Next STOP Bit Start Bit 8-Bit Data Format (Bit M in SCICR1 Clear) Start Bit Bit 0 NEXT STOP Bit START Bit 9-Bit Data Format (Bit M in SCICR1 Set) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 2 Bit 3 Bit 4 Bit 6 Bit 7 POSSIBLE PARITY Bit Possible Parity Bit Standard SCI Data Infrared SCI DataStandard SCI Data Infrared SCI Data

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15.4.4 Baud Rate Generation

A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver has an acquisition rate of 16 samples per bit time. Baud rate generation is subject to one source of error:

• Integer division of the bus clock may not give the exact target frequency. Table 15-16 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz. When IREN = 0 then, SCI baud rate = SCI bus clock / (16 * SCIBR[12:0])

Table 15-16. Baud Rates (Example: Bus Clock = 25 MHz) Bits SBR[12:0] Receiver Clock (Hz) Transmitter Clock (Hz) Target Baud Rate Error (%) 41 609,756.1 38,109.8 38,400 .76 81 308,642.0 19,290.1 19,200 .47 163 153,374.2 9585.9 9,600 .16 326 76,687.1 4792.9 4,800 .15 651 38,402.5 2400.2 2,400 .01 1302 19,201.2 1200.1 1,200 .01 2604 9600.6 600.0 600 .00 5208 4800.0 300.0 300 .00

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15.4.5 Transmitter

Figure 15-16. Transmitter Block Diagram

15.4.5.1 Transmitter Character Length

The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When transmitting 9-bit data, bit T8 in SCI data register high (SCIDRH) is the ninth bit (bit 8).

15.4.5.2 Character Transmission

To transmit data, the MCU writes the data bits to the SCI data registers (SCIDRH/SCIDRL), which in turn are transferred to the transmitter shift register. The transmit shift register then shifts a frame out through the TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. PE PT H876543210L 11-Bit Transmit Register Stop Start TIE TDRE TCIE SBK TC Parity Generation MSB SCI Data RegistersLoad from SCIDR Shift Enable Preamble (All 1s) Break (All 0s) Transmitter Control M Internal Bus SBR12:SBR0 Baud Divider ÷ 16Bus Clock TE SCTXD TXPOL LOOPS LOOP RSRC CONTROL To Receiver Transmit Collision Detect TDRE IRQ TC IRQ SCTXD SCRXD (From Receiver)TCIE BERRIF BER IRQ BERRM[1:0]

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The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is zero. Writing to the SCIBDH has no effect without also writing to SCIBDL. b) Write to SCICR1 to configure word length, parity, and other configuration bits (LOOPS,RSRC,M,W AKE,ILT,PE,PT). c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2 register bits (TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK). A preamble or idle character will now be shifted out of the transmitter shift register. 2. Transmit Procedure for each byte: a) Poll the TDRE flag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind that the TDRE bit resets to one. b) If the TDRE flag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not result until the TDRE flag has been cleared. 3. Repeat step 2 for each subsequent transmission. NOTE The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDRH/L, which happens, generally speaking, a little over half-way through the stop bit of the previous frame. Specifically, this transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the previous frame. Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. Hardware supports odd or even parity. When parity is enabled, the most significant bit (MSB) of the data character is the parity bit. The transmit data register empty flag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request.

Chapter 15 Serial Communication Interface (S12SCIV5) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 583 When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle. If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles with minimum idle line time, use this sequence between messages: 1. Write the last byte of the first message to SCIDRH/L. 2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift register. 3. Queue a preamble by clearing and then setting the TE bit. 4. Write the first byte of the second message to SCIDRH/L.

15.4.5.3 Break Characters

Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. The SCI recognizes a break character when there are 10 or 11(M = 0 or M = 1) consecutive zero received. Depending if the break detect feature is enabled or not receiving a break character has these effects on SCI registers. If the break detect feature is disabled (BKDFE = 0):

• Sets the framing error flag, FE
• Sets the receive data register full flag, RDRF
• Clears the SCI data registers (SCIDRH/L)
• May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF (see 3.4.4 and 3.4.5 SCI Status Register 1 and 2) If the break detect feature is enabled (BKDFE = 1) there are two scenarios The break is detected right from a start bit or is detected during a byte reception.
• Sets the break detect interrupt flag, BKDIF
• Does not change the data register full flag, RDRF or overrun flag OR
• Does not change the framing error flag FE, parity error flag PE.
• Does not clear the SCI data registers (SCIDRH/L)
• May set noise flag NF, or receiver active flag RAF. 1. A Break character in this context are either 10 or 11 consecutive zero received bits

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Figure 15-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later during the transmission. At the expected stop bit position the byte received so far will be transferred to the receive buffer, the receive data register full flag will be set, a framing error and if enabled and appropriate a parity error will be set. Once the break is detected the BRKDIF flag will be set. Figure 15-17. Break Detection if BRKDFE = 1 (M = 0)

15.4.5.4 Idle Characters

An idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1. If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted. NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out through the TXD pin. Setting TE after the stop bit appears on TXD causes data previously written to the SCI data register to be lost. Toggle the TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin Start Bit Position Stop Bit Position BRKDIF = 1 FE = 1 BRKDIF = 1 RXD_1 RXD_2 123 4567 8 91 0 123 4567 8 91 0 Zero Bit Counter Zero Bit Counter . . . . . .

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15.4.5.5 LIN Transmit Collision Detection

This module allows to check for collisions on the LIN bus. Figure 15-18. Collision Detect Principle If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the transmitted and the received data stream at a point in time and flag any mismatch. The timing checks run when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received data is detected the following happens:

• The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1)
• The transmission is aborted and the byte in transmit buffer is discarded.
• the transmit data register empty and the transmission complete flag will be set
• The bit error interrupt flag, BERRIF, will be set.
• No further transmissions will take place until the BERRIF is cleared. Figure 15-19. Timing Diagram Bit Error Detection If the bit error detect feature is disabled, the bit error interrupt flag is cleared. NOTE The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt flag may be set incorrectly. TXD Pin RXD Pin LIN Physical InterfaceSynchronizer Stage Bus Clock Receive Shift Register Transmit Shift Register LIN Bus Compare Sample Bit Error Point Output Transmit Shift Register 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 0 Input Receive Shift Register BERRM[1:0] = 0:1 BERRM[1:0] = 1:1 Compare Sample Points Sampling Begin Sampling Begin Sampling End Sampling End

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15.4.6 Receiver

Figure 15-20. SCI Receiver Block Diagram

15.4.6.1 Receiver Character Length

The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCIDRH) is the ninth bit (bit 8).

15.4.6.2 Character Reception

During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set, All 1s M WAKE ILT PE PT RE H876543210L 11-Bit Receive Shift Register Stop Start Data Wakeup Parity Checking MSB SCI Data Register ILIE RWU RDRF OR NF FE PE Internal Bus Bus SBR12:SBR0 Baud DividerClock IDLE RAF Recovery Logic RXPOL LOOPS Loop RSRC Control SCRXD From TXD Pin or Transmitter Idle IRQ RDRF/OR IRQ Break Detect Logic Active Edge Detect Logic BRKDFE BRKDIE BRKDIF RXEDGIE RXEDGIF Break IRQ RX Active Edge IRQ RIE

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15.4.6.3 Data Sampling

The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 15-21) is re-synchronized:

• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. Figure 15-21. Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Figure 15-17 summarizes the results of the start bit verification samples. If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. Table 15-17. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag

000 Y es 0

001 Y es 1

010 Y es 1

011 No 0

100 Y es 1

101 No 0

110 No 0

111 No 0

Qualification Start Bit Data Sampling 11 111111 0 0 0 0 000 LSB Verification

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To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 15-18 summarizes the results of the data bit samples. NOTE The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit (logic 0). To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10.Table 15-19 summarizes the results of the stop bit samples. Table 15-18. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 Table 15-19. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0

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In Figure 15-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. Figure 15-24. Start Bit Search Example 3 Figure 15-25 shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag. Figure 15-25. Start Bit Search Example 4 Reset RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT13 RT12 RT11 RT16 RT15 RT14 RT4 RT3 RT2 RT1 RT5 RT6 RT7 RT8 RT9 Samples RT Clock RT Clock Count Actual Start Bit RXD 10 111 0 0 0 0 LSB Perceived Start Bit Reset RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT10 RT9 RT8 RT14 RT13 RT12 RT11 RT15 RT16 RT1 RT2 RT3 Samples RT Clock RT Clock Count Perceived and Actual Start Bit RXD 11 111 0 0 1 LSB 11 1 1

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15.4.6.4 Framing Errors

If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set. Reset RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 Samples RT Clock RT Clock Count Start Bit RXD 11 111 0 1 0 LSB 11 1 1 1 00 000 00 0 No Start Bit Found Reset RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT10 RT9 RT8 RT14 RT13 RT12 RT11 RT15 RT16 RT1 RT2 RT3 Samples RT Clock RT Clock Count Start Bit RXD 11 111 0 0 0 LSB 11 1 1 0 11 0

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15.4.6.5 Baud Rate Tolerance

A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic zero. As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Re synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times.

15.4.6.5.1 Slow Data Tolerance

Figure 15-28 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. Figure 15-28. Slow Data Let’s take RTr as receiver RT clock and RTt as transmitter RT clock. For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles = 151 RTr cycles to start data sampling of the stop bit. With the misaligned character shown inFigure 15-28, the receiver counts 151 RTr cycles at the point when the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles to start data sampling of the stop bit. With the misaligned character shown inFigure 15-28, the receiver counts 167 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: MSB Stop RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 Data Samples Receiver RT Clock

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15.4.6.5.2 Fast Data Tolerance

Figure 15-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. Figure 15-29. Fast Data For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown inFigure 15-29, the receiver counts 154 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 10 RTr cycles = 170 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown inFigure 15-29, the receiver counts 170 RTr cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is:

15.4.6.6 Receiver Wakeup

To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag. The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. The W AKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message. The W AKE bit enables either idle line wakeup or address mark wakeup. Idle or Next FrameStop RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 Data Samples Receiver RT Clock

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15.4.6.6.1 Idle Input line Wakeup (WAKE = 0)

In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another idle character appears on the RXD pin. Idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register full flag, RDRF. The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ILT is in SCI control register 1 (SCICR1).

15.4.6.6.2 Address Mark Wakeup (WAKE = 1)

In this wakeup method, a logic 1 in the most significant bit (MSB) position of a frame clears the RWU bit and wakes up the SCI. The logic 1 in the MSB position marks a frame as an address frame that contains addressing information. All receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow.Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another address frame appears on the RXD pin. The logic 1 MSB of an address frame clears the receiver’s RWU bit before the stop bit is received and sets the RDRF flag. Address mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. NOTE With the W AKE bit clear, setting the RWU bit after the RXD pin has been idle can cause the receiver to wake up immediately.

15.4.7 Single-Wire Operation

Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting. Figure 15-30. Single-Wire Operation (LOOPS = 1, RSRC = 1) RXD Transmitter Receiver TXD

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15.4.8 Loop Operation

In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the SCI. Figure 15-31. Loop Operation (LOOPS = 1, RSRC = 0) Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1). NOTE In loop operation data from the transmitter is not recognized by the receiver if RXPOL and TXPOL are not the same.

15.5 Initialization/Application Information

15.5.1 Reset Initialization

See Section 15.3.2, “Register Descriptions”.

15.5.2 Modes of Operation

15.5.2.1 Run Mode

Normal mode of operation. To initialize a SCI transmission, see Section 15.4.5.2, “Character Transmission”. RXD Transmitter Receiver TXD

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15.5.2.2 Wait Mode

SCI operation in wait mode depends on the state of the SCISW AI bit in the SCI control register 1 (SCICR1).

• If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode.
• If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE. If SCISW AI is set, any transmission or reception in progress stops at wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and resets the SCI.

15.5.2.3 Stop Mode

The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI. The receive input active edge detect circuit is still active in stop mode. An active edge on the receive input can be used to bring the CPU out of stop mode.

15.5.3 Interrupt Operation

This section describes the interrupt originated by the SCI block.The MCU must service the interrupt requests. Table 15-20 lists the eight interrupt sources of the SCI. Table 15-20. SCI Interrupt Sources Interrupt Source Local Enable Description TDRE SCISR1[7] TIE Active high level. Indicates that a byte was transferred from SCIDRH/L to the transmit shift register. TC SCISR1[6] TCIE Active high level. Indicates that a transmit is complete. RDRF SCISR1[5] RIE Active high level. The RDRF interrupt indicates that received data is available in the SCI data register. OR SCISR1[3] Active high level. This interrupt indicates that an overrun condition has occurred. IDLE SCISR1[4] ILIE Active high level. Indicates that receiver input has become idle. RXEDGIF SCIASR1[7] RXEDGIE Active high level. Indicates that an active edge (falling for RXPOL = 0, rising for RXPOL = 1) was detected. BERRIF SCIASR1[1] BERRIE Active high level. Indicates that a mismatch between transmitted and received data in a single wire application has happened. BKDIF SCIASR1[0] BRKDIE Active high level. Indicates that a break character has been received.

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15.5.3.1 Description of Interrupt Operation

The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port.

15.5.3.1.1 TDRE Description

The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1 with TDRE set and then writing to SCI data register low (SCIDRL).

15.5.3.1.2 TC Description

The TC interrupt is set by the SCI when a transmission has been completed. Transmission is completed when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be transmitted. No stop bit is transmitted when sending a break character and the TC flag is set (providing there is no more data queued for transmission) when the break character has been shifted out. A TC interrupt indicates that there is no transmission in progress. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL).TC is cleared automatically when data, preamble, or break is queued and ready to be sent.

15.5.3.1.3 RDRF Description

The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL).

15.5.3.1.4 OR Description

The OR interrupt is set when software fails to read the SCI data register before the receive shift register receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL).

15.5.3.1.5 IDLE Description

The IDLE interrupt is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1) appear on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL).

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15.5.3.1.6 RXEDGIF Description

The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1.

15.5.3.1.7 BERRIF Description

The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single wire application like LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This flag is also cleared if the bit error detect feature is disabled.

15.5.3.1.8 BKDIF Description

The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This flag is also cleared if break detect feature is disabled.

15.5.4 Recovery from Wait Mode

The SCI interrupt request can be used to bring the CPU out of wait mode.

15.5.5 Recovery from Stop Mode

An active edge on the receive input can be used to bring the CPU out of stop mode.

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16.1 Introduction

The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven.

16.1.1 Glossary of Terms

16.1.2 Features

The SPI includes these distinctive features:

• Master mode and slave mode
• Bidirectional mode
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Double-buffered data register
• Serial clock with programmable polarity and phase
• Control of SPI operation during wait mode

16.1.3 Modes of Operation

The SPI functions in three modes: run, wait, and stop. SPI Serial Peripheral Interface SS Slave Select SCK Serial Clock MOSI Master Output, Slave Input MISO Master Input, Slave Output MOMI Master Output, Master Input SISO Slave Input, Slave Output

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• Run mode This is the basic mode of operation.
• Wait mode SPI operation in wait mode is a configurable low power mode, controlled by the SPISW AI bit located in the SPICR2 register. In wait mode, if the SPISW AI bit is clear, the SPI operates like in run mode. If the SPISW AI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master.
• Stop mode The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. This is a high level description only, detailed descriptions of operating modes are contained in Section 16.4.7, “Low Power Mode Options”.

16.1.4 Block Diagram

Figure 16-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.

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16.2 External Signal Description

This section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. The SPI module has a total of four external pins.

16.2.1 MOSI — Master Out/Slave In Pin

This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave.

16.2.2 MISO — Master In/Slave Out Pin

This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master. SPI Control Register 1 SPI Control Register 2 SPI Baud Rate Register SPI Status Register SPI Data Register Shifter Port Control Logic MOSI SCK Interrupt Control SPI MSB LSB LSBFE=1 LSBFE=0 LSBFE=0 LSBFE=1 Data In LSBFE=1 LSBFE=0 Data Out Baud Rate Generator PrescalerBus Clock Counter Clock Select SPPR 3 3SPR Baud Rate Phase + Polarity Control Master Slave SCK In SCK OutMaster Baud Rate Slave Baud Rate Phase + Polarity Control Control Control CPOL CPHA BIDIROE SPC0 Shift Sample ClockClock MODFSPIF SPTEF SPI Request Interrupt SS

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16.2.3 SS — Slave Select Pin

This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when it is configured as a master and it is used as an input to receive the slave select signal when the SPI is configured as slave.

16.2.4 SCK — Serial Clock Pin

In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.

16.3 Memory Map and Register Definition

This section provides a detailed description of address space and registers used by the SPI.

16.3.1 Module Memory Map

The memory map for the SPI is given in Figure 16-2. The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have no effect. Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 SPICR1 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFEW 0x0001 SPICR2 R 000 MODFEN BIDIROE 0 SPISWAI SPC0W 0x0002 SPIBR R0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0W 0x0003 SPISR R SPIF 0 SPTEF MODF 0 0 0 0 W 0x0004 Reserved R W 0x0005 SPIDR R Bit 7 6 5 4 3 2 1 Bit 0W 0x0006 Reserved R W 0x0007 Reserved R W = Unimplemented or Reserved Figure 16-2. SPI Register Summary

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16.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.

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16.3.2.1 SPI Control Register 1 (SPICR1)

Read: Anytime Write: Anytime Module Base +0x0000 76543210 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE W Reset 0 0 0 00100 Figure 16-3. SPI Control Register 1 (SPICR1) Table 16-1. SPICR1 Field Descriptions Field Description SPIE SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled. SPE SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset. 0 SPI disabled (lower power consumption). 1 SPI enabled, port pins are dedicated to SPI functions. SPTIE SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set. 0 SPTEF interrupt disabled. 1 SPTEF interrupt enabled. MSTR SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode. Switching the SPI from master to slave or vice versa forces the SPI system into idle state. 0 SPI is in slave mode. 1 SPI is in master mode. CPOL SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Active-high clocks selected. In idle state SCK is low. 1 Active-low clocks selected. In idle state SCK is high. CPHA SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock. 1 Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock. SSOE Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as shown in Table 16-2. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. LSBFE LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in bit 7. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Data is transferred most significant bit first. 1 Data is transferred least significant bit first.

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16.3.2.2 SPI Control Register 2 (SPICR2)

Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 16-2. SS Input / Output Selection MODFEN SSOE Master Mode Slave Mode

00 SS not used by SPI SS input

01 SS not used by SPI SS input

10 SS input with MODF feature SS input

11 SS is slave select output SS input

W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 16-4. SPI Control Register 2 (SPICR2) Table 16-3. SPICR2 Field Descriptions Field Description MODFEN Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on theSS port pin configuration, refer to Table 16-4. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. SS port pin is not used by the SPI. 1 SS port pin with MODF feature. BIDIROE Output Enable in the Bidirectional Mode of Operation— This bit controls the MOSI and MISO output buffer of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0 set, a change of this bit will abort a transmission in progress and force the SPI into idle state. 0 Output buffer disabled. 1 Output buffer enabled. SPISWAI SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode. 0 SPI clock operates normally in wait mode. 1 Stop SPI clock generation when in wait mode. SPC0 Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 16-4. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.

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16.3.2.3 SPI Baud Rate Register (SPIBR)

Read: Anytime Write: Anytime; writes to the reserved bits have no effect The baud rate divisor equation is as follows: BaudRateDivisor = (SPPR + 1) • 2(SPR + 1) Eqn. 16-1 The baud rate can be calculated with the following equation: Baud Rate = BusClock / BaudRateDivisor Eqn. 16-2 NOTE For maximum allowed baud rates, please refer to the SPI Electrical Specification in the Electricals chapter of this data sheet. Table 16-4. Bidirectional Pin Configurations Pin Mode SPC0 BIDIROE MISO MOSI Master Mode of Operation Normal 0 X Master In Master Out Bidirectional 1 0 MISO not used by SPI Master In

1 Master I/O

Normal 0 X Slave Out Slave In Bidirectional 1 0 Slave In MOSI not used by SPI

1 Slave I/O

W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 16-5. SPI Baud Rate Register (SPIBR) Table 16-5. SPIBR Field Descriptions Field Description 6–4 SPPR[2:0] SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 16-6. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. 2–0 SPR[2:0] SPI Baud Rate Selection Bits— These bits specify the SPI baud rates as shown inTable 16-6. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.

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1 0 0 1 1 1 1280 19.53 kbit/s 1 0 1 0 0 0 12 2.08333 Mbit/s 1 0 1 0 0 1 24 1.04167 Mbit/s 1 0 1 0 1 0 48 520.83 kbit/s 1 0 1 0 1 1 96 260.42 kbit/s 1 0 1 1 0 0 192 130.21 kbit/s 1 0 1 1 0 1 384 65.10 kbit/s 1 0 1 1 1 0 768 32.55 kbit/s 1 0 1 1 1 1 1536 16.28 kbit/s 1 1 0 0 0 0 14 1.78571 Mbit/s 1 1 0 0 0 1 28 892.86 kbit/s 1 1 0 0 1 0 56 446.43 kbit/s 1 1 0 0 1 1 112 223.21 kbit/s 1 1 0 1 0 0 224 111.61 kbit/s 1 1 0 1 0 1 448 55.80 kbit/s 1 1 0 1 1 0 896 27.90 kbit/s 1 1 0 1 1 1 1792 13.95 kbit/s 1 1 1 0 0 0 16 1.5625 Mbit/s 1 1 1 0 0 1 32 781.25 kbit/s 1 1 1 0 1 0 64 390.63 kbit/s 1 1 1 0 1 1 128 195.31 kbit/s 1 1 1 1 0 0 256 97.66 kbit/s 1 1 1 1 0 1 512 48.83 kbit/s 1 1 1 1 1 0 1024 24.41 kbit/s 1 1 1 1 1 1 2048 12.21 kbit/s Table 16-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate

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16.3.2.4 SPI Status Register (SPISR)

Read: Anytime Write: Has no effect Module Base +0x0003 76543210 R SPIF 0 SPTEF MODF 0000 W Reset 0 0 1 00000 = Unimplemented or Reserved Figure 16-6. SPI Status Register (SPISR) Table 16-7. SPISR Field Descriptions Field Description SPIF SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI data register. This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI data register. 0 Transfer not yet complete. 1 New data copied to SPIDR. SPTEF SPI Transmit Empty Interrupt Flag— If set, this bit indicates that the transmit data register is empty. To clear this bit and place data into the transmit data register, SPISR must be read with SPTEF = 1, followed by a write to SPIDR. Any write to the SPI data register without reading SPTEF = 1, is effectively ignored. 0 SPI data register not empty. 1 SPI data register empty. MODF Mode Fault Flag— This bit is set if the SS input becomes low while the SPI is configured as a master and mode fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in Section 16.3.2.2, “SPI Control Register 2 (SPICR2)”. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred.

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16.3.2.5 SPI Data Register (SPIDR)

Read: Anytime; normally read only when SPIF is set Write: Anytime The SPI data register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data. Received data in the SPIDR is valid when SPIF is set. If SPIF is cleared and a byte has been received, the received byte is transferred from the receive shift register to the SPIDR and SPIF is set. If SPIF is set and not serviced, and a second byte has been received, the second received byte is kept as valid byte in the receive shift register until the start of another transmission. The byte in the SPIDR does not change. If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced before the start of a third transmission, the byte in the receive shift register is transferred into the SPIDR and SPIF remains set (see Figure 16-8). If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced after the start of a third transmission, the byte in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 16-9). Module Base +0x0005 76543210 R Bit 7 6 5 4322 Bit 0 W Reset 0 0 0 00000 Figure 16-7. SPI Data Register (SPIDR)

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16.4 Functional Description

The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven. The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are dedicated to the SPI function as:

• Slave select ( SS)
• Serial clock (SCK)
• Master out/slave in (MOSI)
• Master in/slave out (MISO) The main element of the SPI system is the SPI data register. The 8-bit data register in the master and the 8-bit data register in the slave are linked by the MOSI and MISO pins to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the master SPI data register becomes the output data for the slave, and data read from the master SPI data register after a transfer operation is the input data from the slave. A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register. When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. This 8-bit data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes. A single SPI register address is used for reading data from the read data buffer and for writing data to the transmit data register. The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1 (SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see Section 16.4.3, “Transmission Formats”). The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected. NOTE A change of CPOL or MSTR bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided.

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16.4.1 Master Mode

The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI data register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock.

• Serial clock The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator and determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral.
• MOSI, MISO pin In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits. SS pin If MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. If MODFEN is set and SSOE is cleared, theSS pin is configured as input for detecting mode fault error. If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state. This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If the SPI interrupt enable bit (SPIE) is set when the MODF flag becomes set, then an SPI interrupt sequence is also requested. When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control register 1 (see Section 16.4.3, “Transmission Formats”). NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode will abort a transmission in progress and force the SPI into idle state. The remote slave cannot detect this, therefore the master must ensure that the remote slave is returned to idle state.

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16.4.2 Slave Mode

The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear.

• Serial clock In slave mode, SCK is the SPI clock input from the master.
• MISO, MOSI pin In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI control register 2.
• SS pin The SS pin is the slave select input. Before a data transmission occurs, theSS pin of the slave SPI must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle state. The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin is high impedance, and, if SS is low, the first bit in the SPI data register is driven out of the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register occurs. Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the eighth shift, the transfer is considered complete and the received data is transferred into the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status register is set. NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with SPC0 set in slave mode will corrupt a transmission in progress and must be avoided.

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16.4.3 Transmission Formats

During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select line can be used to indicate multiple-master bus contention. Figure 16-10. Master/Slave Transfer Block Diagram

16.4.3.1 Clock Phase and Polarity Controls

Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.

16.4.3.2 CPHA = 0 Transfer Format

The first edge on the SCK line is used to clock the first data bit of the slave into the master and the first data bit of the master into the slave. In some peripherals, the first bit of the slave’s data is available at the slave’s data out pin as soon as the slave is selected. In this format, the first SCK edge is issued a half cycle after SS has become low. A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit. After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and shifted on even numbered edges. SHIFT REGISTER SHIFT REGISTER BAUD RATE GENERATOR MASTER SPI SLAVE SPI MOSI MOSI MISO MISO SCK SCK SS SSVDD

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Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th (last) SCK edge:

• Data that was previously in the master SPI data register should now be in the slave data register and the data that was in the slave data register should be in the master.
• The SPIF flag in the SPI status register is set, indicating that the transfer is complete. Figure 16-11 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. Figure 16-11. SPI Clock Format 0 (CPHA = 0) tL Begin End SCK (CPOL = 0) SAMPLE I CHANGE O SEL SS (O) Transfer SCK (CPOL = 1) MSB first (LSBFE = 0): LSB first (LSBFE = 1): MSB LSB LSB MSB Bit 5 Bit 2 Bit 6 Bit 1 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 CHANGE O SEL SS (I) MOSI pin MISO pin Master only MOSI/MISO tT If next transfer begins here for tT, tl, tL Minimum 1/2 SCK tI tL tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. 1 234 56 789 1 0 1 1 1 2 1 3 1 4 1 5 1 6SCK Edge Number End of Idle State Begin of Idle State

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16.4.3.3 CPHA = 1 Transfer Format

Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the 8-cycle transfer operation. The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the slave to transfer its first data bit to the serial data input pin of the master. A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges. Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th SCK edge:

• Data that was previously in the SPI data register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master.
• The SPIF flag bit in SPISR is set indicating that the transfer is complete. Figure 16-12 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI.

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Figure 16-12. SPI Clock Format 1 (CPHA = 1) The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data line.

• Back-to-back transfers in master mode In master mode, if a transmission has completed and a new data byte is available in the SPI data register, this byte is sent out immediately without a trailing and minimum idle time. The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the last SCK edge. tL tT for tT, tl, tL Minimum 1/2 SCK tI tL If next transfer begins here Begin End SCK (CPOL = 0) SAMPLE I CHANGE O SEL SS (O) Transfer SCK (CPOL = 1) MSB first (LSBFE = 0): LSB first (LSBFE = 1): MSB LSB LSB MSB Bit 5 Bit 2 Bit 6 Bit 1 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 CHANGE O SEL SS (I) MOSI pin MISO pin Master only MOSI/MISO tL = Minimum leading time before the first SCK edge, not required for back-to-back transfers tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers 1 234 56 789 1 0 1 1 1 2 1 3 1 4 1 5 1 6SCK Edge Number End of Idle State Begin of Idle State

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16.4.4 SPI Baud Rate Generation

Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate. The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 16-3. BaudRateDivisor = (SPPR + 1) • 2(SPR + 1) Eqn. 16-3 When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc. When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 16-6 for baud rate calculations for all bit conditions, based on a 25 MHz bus clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease I DD current. NOTE For maximum allowed baud rates, please refer to the SPI Electrical Specification in the Electricals chapter of this data sheet.

16.4.5 Special Features

16.4.5.1 SS Output

The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in Table 16-2. The mode fault feature is disabled while SS output is enabled. NOTE Care must be taken when using the SS output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters.

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16.4.5.2 Bidirectional Mode (MOMI or SISO)

The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Table 16-8). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI. The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register.

• The SCK is output for the master mode and input for the slave mode.
• The SS is the input or output for the master mode, and it is always the input for the slave mode.
• The bidirectional mode does not affect SCK and SS functions. NOTE In bidirectional master mode, with mode fault enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode. In this case MISO becomes occupied by the SPI and MOSI is not used. This must be considered, if the MISO pin is used for another purpose. Table 16-8. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Slave Mode MSTR = 0 Normal Mode SPC0 = 0 Bidirectional Mode SPC0 = 1 SPI MOSI MISO Serial Out Serial In SPI MOSI MISO Serial In Serial Out SPI MOMISerial Out Serial In BIDIROE SPI SISO Serial In Serial Out BIDIROE

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16.4.6 Error Conditions

The SPI has one error condition:

• Mode fault error

16.4.6.1 Mode Fault Error

If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation, the MODF bit in the SPI status register is set automatically, provided the MODFEN bit is set. In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state. If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system configured in slave mode. The mode fault flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to SPI control register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again. NOTE If a mode fault error occurs and a received data byte is pending in the receive shift register, this data byte will be lost.

16.4.7 Low Power Mode Options

16.4.7.1 SPI in Run Mode

In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled.

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16.4.7.2 SPI in Wait Mode

SPI operation in wait mode depends upon the state of the SPISW AI bit in SPI control register 2.

• If SPISW AI is clear, the SPI operates normally when the CPU is in wait mode
• If SPISW AI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. – If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. – If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master. This keeps the slave synchronized to the master and the SCK. If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt willnot be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. In slave mode, a received byte pending in the receive shift register will be lost when entering wait or stop mode. An SPIF flag and SPIDR copy is generated only if wait mode is entered or exited during a tranmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur.

16.4.7.3 SPI in Stop Mode

Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. The stop mode is not dependent on the SPISW AI bit.

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16.4.7.4 Reset

The reset values of registers and signals are described in Section 16.3, “Memory Map and Register Definition” , which details the registers and their bit fields.

• If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset.
• Reading from the SPIDR after reset will always read a byte of zeros.

16.4.7.5 Interrupts

The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is a description of how the SPI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.

16.4.7.5.1 MODF

MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 16-2). After MODF is set, the current transfer is aborted and the following bit is changed:

• MSTR = 0, The master bit in SPICR1 resets. The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing process which is described in Section 16.3.2.4, “SPI Status Register (SPISR)”.

16.4.7.5.2 SPIF

SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process, which is described in Section 16.3.2.4, “SPI Status Register (SPISR)”.

16.4.7.5.3 SPTEF

SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process, which is described inSection 16.3.2.4, “SPI Status Register (SPISR)”.

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17.1 Introduction

The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts. Refer to Figure 17-1 for a simplified block diagram.

17.1.1 Glossary

17.1.2 Features

The PIT includes these features:

• Four timers implemented as modulus down-counters with independent time-out periods.
• Time-out periods selectable between 1 and 2 24 bus clock cycles. Time-out equals m*n bus clock cycles with 1 <= m <= 256 and 1 <= n <= 65536.
• Timers that can be enabled individually.
• Four time-out interrupts.
• Four time-out trigger output signals available to trigger peripheral modules.
• Start of timer channels can be aligned to each other.

17.1.3 Modes of Operation

Refer to the SoC guide for a detailed explanation of the chip modes.

• Run mode This is the basic mode of operation.
• Wait mode Acronyms and Abbreviations PIT Periodic Interrupt Timer ISR Interrupt Service Routine CCR Condition Code Register SoC System on Chip micro time bases clock periods of the 16-bit timer modulus down-counters, which are generated by the 8-bit modulus down-counters.

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PIT operation in wait mode is controlled by the PITSW AI bit located in the PITCFLMT register. In wait mode, if the bus clock is globally enabled and if the PITSW AI bit is clear, the PIT operates like in run mode. In wait mode, if the PITSW AI bit is set, the PIT module is stalled.

• Stop mode In full stop mode or pseudo stop mode, the PIT module is stalled.
• Freeze mode PIT operation in freeze mode is controlled by the PITFRZ bit located in the PITCFLMT register. In freeze mode, if the PITFRZ bit is clear, the PIT operates like in run mode. In freeze mode, if the PITFRZ bit is set, the PIT module is stalled.

17.1.4 Block Diagram

Figure 17-1 shows a block diagram of the PIT. Figure 17-1. PIT Block Diagram

17.2 External Signal Description

The PIT module has no external pins. Time-Out 0 Time-Out 1 Time-Out 2 Time-Out 3 16-Bit Timer 1 16-Bit Timer 3 16-Bit Timer 0 16-Bit Timer 2 Bus Clock Micro Time Base 0 Micro Time Base 1 Interrupt 0 Trigger 0Interface Interrupt 1 Trigger 1Interface Interrupt 2 Trigger 2Interface Interrupt 3 Trigger 3Interface 8-Bit Micro Timer 0 8-Bit Micro Timer 1

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17.3 Memory Map and Register Definition

This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 PITCFLMT R PITE PITSWAI PITFRZ 0000 0 W PFLMT1 PFLMT0 0x0001 PITFLT R 0000000 0 W PFLT3 PFLT2 PFLT1 PFLT0 0x0002 PITCE R 0000 PCE3 PCE2 PCE1 PCE0 W 0x0003 PITMUX R 0000 PMUX3 PMUX2 PMUX1 PMUX0 W 0x0004 PITINTE R 0000 PINTE3 PINTE2 PINTE1 PINTE0 W 0x0005 PITTF R 0000 PTF3 PTF2 PTF1 PTF0 W 0x0006 PITMTLD0 R PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0 W 0x0007 PITMTLD1 R PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0 W 0x0008 PITLD0 (High) R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 W 0x0009 PITLD0 (Low) R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x000A PITCNT0 (High) R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x000B PITCNT0 (Low) R PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 W 0x000C PITLD1 (High) R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 W = Unimplemented or Reserved Figure 17-2. PIT Register Summary (Sheet 1 of 2)

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PITLD1 (Low) R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x000E PITCNT1 (High) R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x000F PITCNT1 (Low) R PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 W 0x0010 PITLD2 (High) R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 W 0x0011 PITLD2 (Low) R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x0012 PITCNT2 (High) R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x0013 PITCNT2 (Low) R PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 W 0x0014 PITLD3 (High) R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 W 0x0015 PITLD3 (Low) R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x0016 PITCNT3 (High) R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x0017 PITCNT3 (Low) R PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 W Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 17-2. PIT Register Summary (Sheet 2 of 2)

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17.3.0.1 PIT Control and Force Load Micro Timer Register (PITCFLMT)

Read: Anytime Write: Anytime; writes to the reserved bits have no effect Module Base + 0x0000 76543210 R PITE PITSWAI PITFRZ 00000 W PFLMT1 PFLMT0 Reset 0 0 0 00000 = Unimplemented or Reserved Figure 17-3. PIT Control and Force Load Micro Timer Register (PITCFLMT) Table 17-1. PITCFLMT Field Descriptions Field Description PITE PIT Module Enable Bit — This bit enables the PIT module. If PITE is cleared, the PIT module is disabled and flag bits in the PITTF register are cleared. When PITE is set, individually enabled timers (PCE set) start down-counting with the corresponding load register values. 0 PIT disabled (lower power consumption). 1 PIT is enabled. PITSWAI PIT Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.

0 PIT operates normally in wait mode

1 PIT clock generation stops and freezes the PIT module when in wait mode

PIT Counter Freeze while in Freeze Mode Bit — When during debugging a breakpoint (freeze mode) is encountered it is useful in many cases to freeze the PIT counters to avoid e.g. interrupt generation. The PITFRZ bit controls the PIT operation while in freeze mode.

0 PIT operates normally in freeze mode

1 PIT counters are stalled when in freeze mode

1:0 PFLMT[1:0] PIT Force Load Bits for Micro Timer 1:0 — These bits have only an effect if the corresponding micro timer is active and if the PIT module is enabled (PITE set). Writing a one into a PFLMT bit loads the corresponding 8-bit micro timer load register into the 8-bit micro timer down-counter. Writing a zero has no effect. Reading these bits will always return zero. Note: A micro timer force load affects all timer channels that use the corresponding micro time base.

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17.3.0.2 PIT Force Load Timer Register (PITFLT)

Read: Anytime Write: Anytime; writes to the reserved bits have no effect

17.3.0.3 PIT Channel Enable Register (PITCE)

Read: Anytime Write: Anytime; writes to the reserved bits have no effect Module Base + 0x0001 76543210 R 00000000 W PFLT3 PFLT2 PFLT1 PFLT0 Reset 0 0 0 00000 = Unimplemented or Reserved Figure 17-4. PIT Force Load Timer Register (PITFLT) Table 17-2. PITFLT Field Descriptions Field Description 3:0 PFLT[3:0] PIT Force Load Bits for Timer 3-0 — These bits have only an effect if the corresponding timer channel (PCE set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding 16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will always return zero. Module Base + 0x0002 76543210 R 0000 PCE3 PCE2 PCE1 PCE0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 17-5. PIT Channel Enable Register (PITCE) Table 17-3. PITCE Field Descriptions Field Description 3:0 PCE[3:0] PIT Enable Bits for Timer Channel 3:0 — These bits enable the PIT channels 3-0. If PCE is cleared, the PIT channel is disabled and the corresponding flag bit in the PITTF register is cleared. When PCE is set, and if the PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts down-counting. 0 The corresponding PIT channel is disabled. 1 The corresponding PIT channel is enabled.

Chapter 17 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 631

17.3.0.4 PIT Multiplex Register (PITMUX)

Read: Anytime Write: Anytime; writes to the reserved bits have no effect

17.3.0.5 PIT Interrupt Enable Register (PITINTE)

Read: Anytime Write: Anytime; writes to the reserved bits have no effect Module Base + 0x0003 76543210 R 0000 PMUX3 PMUX2 PMUX1 PMUX0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 17-6. PIT Multiplex Register (PITMUX) Table 17-4. PITMUX Field Descriptions Field Description 3:0 PMUX[3:0] PIT Multiplex Bits for Timer Channel 3:0— These bits select if the corresponding 16-bit timer is connected to micro time base 1 or 0. If PMUX is modified, the corresponding 16-bit timer is immediately switched to the other micro time base. 0 The corresponding 16-bit timer counts with micro time base 0. 1 The corresponding 16-bit timer counts with micro time base 1. Module Base + 0x0004 76543210 R 0000 PINTE3 PINTE2 PINTE1 PINTE0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 17-7. PIT Interrupt Enable Register (PITINTE) Table 17-5. PITINTE Field Descriptions Field Description 3:0 PINTE[3:0] PIT Time-out Interrupt Enable Bits for Timer Channel 3:0 — These bits enable an interrupt service request whenever the time-out flag PTF of the corresponding PIT channel is set. When an interrupt is pending (PTF set) enabling the interrupt will immediately cause an interrupt. To avoid this, the corresponding PTF flag has to be cleared first. 0 Interrupt of the corresponding PIT channel is disabled. 1 Interrupt of the corresponding PIT channel is enabled.

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17.3.0.6 PIT Time-Out Flag Register (PITTF)

Read: Anytime Write: Anytime (write to clear); writes to the reserved bits have no effect

17.3.0.7 PIT Micro Timer Load Register 0 to 1 (PITMTLD0–1)

Read: Anytime Write: Anytime Module Base + 0x0005 76543210 R 0000 PTF3 PTF2 PTF1 PTF0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 17-8. PIT Time-Out Flag Register (PITTF) Table 17-6. PITTF Field Descriptions Field Description 3:0 PTF[3:0] PIT Time-out Flag Bits for Timer Channel 3:0 — PTF is set when the corresponding 16-bit timer modulus down-counter and the selected 8-bit micro timer modulus down-counter have counted to zero. The flag can be cleared by writing a one to the flag bit. Writing a zero has no effect. If flag clearing by writing a one and flag setting happen in the same bus clock cycle, the flag remains set. The flag bits are cleared if the PIT module is disabled or if the corresponding timer channel is disabled. 0 Time-out of the corresponding PIT channel has not yet occurred. 1 Time-out of the corresponding PIT channel has occurred. Module Base + 0x0006 76543210 R PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0 W Reset 0 0 0 00000 Figure 17-9. PIT Micro Timer Load Register 0 (PITMTLD0) Module Base + 0x0007 76543210 R PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0 W Reset 0 0 0 00000 Figure 17-10. PIT Micro Timer Load Register 1 (PITMTLD1)

Chapter 17 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 633 Table 17-7. PITMTLD0–1 Field Descriptions Field Description 7:0 PMTLD[7:0] PIT Micro Timer Load Bits 7:0— These bits set the 8-bit modulus down-counter load value of the micro timers. Writing a new value into the PITMTLD register will not restart the timer. When the micro timer has counted down to zero, the PMTLD register value will be loaded. The PFLMT bits in the PITCFLMT register can be used to immediately update the count register with the new value if an immediate load is desired.

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17.3.0.8 PIT Load Register 0 to 3 (PITLD0–3)

Read: Anytime Write: Anytime Module Base + 0x0008, 0x0009 1 5 1 4 1 3 1 2 1 1 1 09876543210 R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W Reset 000000 0000000000 Figure 17-11. PIT Load Register 0 (PITLD0) Module Base + 0x000C, 0x000D 1 5 1 4 1 3 1 2 1 1 1 09876543210 R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W Reset 000000 0000000000 Figure 17-12. PIT Load Register 1 (PITLD1) Module Base + 0x0010, 0x0011 1 5 1 4 1 3 1 2 1 1 1 09876543210 R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W Reset 000000 0000000000 Figure 17-13. PIT Load Register 2 (PITLD2) Module Base + 0x0014, 0x0015 1 5 1 4 1 3 1 2 1 1 1 09876543210 R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W Reset 000000 0000000000 Figure 17-14. PIT Load Register 3 (PITLD3) Table 17-8. PITLD0–3 Field Descriptions Field Description 15:0 PLD[15:0] PIT Load Bits 15:0 — These bits set the 16-bit modulus down-counter load value. Writing a new value into the PITLD register must be a 16-bit access, to ensure data consistency. It will not restart the timer. When the timer has counted down to zero the PTF time-out flag will be set and the register value will be loaded. The PFLT bits in the PITFLT register can be used to immediately update the count register with the new value if an immediate load is desired.

Chapter 17 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 635

17.3.0.9 PIT Count Register 0 to 3 (PITCNT0–3)

Read: Anytime Write: Has no meaning or effect Module Base + 0x000A, 0x000B 1 5 1 4 1 3 1 2 1 1 1 09876543210 R PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT Reset 000000 0000000000 Figure 17-15. PIT Count Register 0 (PITCNT0) Module Base + 0x000E, 0x000F 1 5 1 4 1 3 1 2 1 1 1 09876543210 R PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT Reset 000000 0000000000 Figure 17-16. PIT Count Register 1 (PITCNT1) Module Base + 0x0012, 0x0013 1 5 1 4 1 3 1 2 1 1 1 09876543210 R PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT Reset 000000 0000000000 Figure 17-17. PIT Count Register 2 (PITCNT2) Module Base + 0x0016, 0x0017 1 5 1 4 1 3 1 2 1 1 1 09876543210 R PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT Reset 000000 0000000000 Figure 17-18. PIT Count Register 3 (PITCNT3) Table 17-9. PITCNT0–3 Field Descriptions Field Description 15:0 PCNT[15:0] PIT Count Bits 15-0 — These bits represent the current 16-bit modulus down-counter value. The read access for the count register must take place in one clock cycle as a 16-bit access.

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17.4 Functional Description

Figure 17-19 shows a detailed block diagram of the PIT module. The main parts of the PIT are status, control and data registers, two 8-bit down-counters, four 16-bit down-counters and an interrupt/trigger interface. Figure 17-19. PIT Detailed Block Diagram

17.4.1 Timer

As shown in Figure 17-1and Figure 17-19, the 24-bit timers are built in a two-stage architecture with four 16-bit modulus down-counters and two 8-bit modulus down-counters. The 16-bit timers are clocked with two selectable micro time bases which are generated with 8-bit modulus down-counters. Each 16-bit timer is connected to micro time base 0 or 1 via the PMUX[3:0] bit setting in the PIT Multiplex (PITMUX) register. A timer channel is enabled if the module enable bit PITE in the PIT control and force load micro timer (PITCFLMT) register is set and if the corresponding PCE bit in the PIT channel enable (PITCE) register is set. Two 8-bit modulus down-counters are used to generate two micro time bases. As soon as a micro time base is selected for an enabled timer channel, the corresponding micro timer modulus down-counter will load its start value as specified in the PITMTLD0 or PITMTLD1 register and will start down-counting. Whenever the micro timer down-counter has counted to zero the PITMTLD register is reloaded and the connected 16-bit modulus down-counters count one cycle. PITMLD0 Register 8-Bit Micro Timer 0 PITCFLMT Register PITLD0 Register PITMLD1 Register 8-Bit Micro Timer 1 PITMUX Register PITFLT Register PITCNT0 Register Timer 0PMUX0 PFLT04 PITTF Register PITINTE Register Interrupt / Hardware Trigger Interrupt Request PITLD1 Register PITCNT1 Register Timer 1[1] PFLT1 PITLD2 Register PITCNT2 Register Timer 2[2] PFLT2 PITLD3 Register PITCNT3 Register Timer 3 PMUX3 PFLT3 time-out 0 time- out 1 time- out 2 Time-Out 3 PFLMT [1] [0] PMUX Trigger Interface Bus Clock PIT_24B4C

Chapter 17 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 637 Whenever a 16-bit timer counter and the connected 8-bit micro timer counter have counted to zero, the PITLD register is reloaded and the corresponding time-out flag PTF in the PIT time-out flag (PITTF) register is set, as shown in Figure 17-20. The time-out period is a function of the timer load (PITLD) and micro timer load (PITMTLD) registers and the bus clock f BUS: time-out period = (PITMTLD + 1) * (PITLD + 1) / fBUS. For example, for a 40 MHz bus clock, the maximum time-out period equals: 256 * 65536 * 25 ns = 419.43 ms. The current 16-bit modulus down-counter value can be read via the PITCNT register. The micro timer down-counter values cannot be read. The 8-bit micro timers can individually be restarted by writing a one to the corresponding force load micro timer PFLMT bits in the PIT control and force load micro timer (PITCFLMT) register. The 16-bit timers can individually be restarted by writing a one to the corresponding force load timer PFLT bits in the PIT forceload timer (PITFLT) register. If desired, any group of timers and micro timers can be restarted at the same time by using one 16-bit write to the adjacent PITCFLMT and PITFLT registers with the relevant bits set, as shown in Figure 17-20. Figure 17-20. PIT Trigger and Flag Signal Timing

17.4.2 Interrupt Interface

Each time-out event can be used to trigger an interrupt service request. For each timer channel, an individual bit PINTE in the PIT interrupt enable (PITINTE) register exists to enable this feature. If PINTE Bus Clock 02 1 08-Bit Micro 2 1 0 2 1 0 2 1 2 1 0 PITCNT Register 0001 000000 0001 0000 8-Bit Force Load 2 1 02 1 0 PTF Flag1 PITTRIG 16-Bit Force Load 0001 0000 0001 Time-Out PeriodTime-Out Period After Restart Timer Counter Note 1. The PTF flag clearing depends on the software

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is set, an interrupt service is requested whenever the corresponding time-out flag PTF in the PIT time-out flag (PITTF) register is set. The flag can be cleared by writing a one to the flag bit. NOTE Be careful when resetting the PITE, PINTE or PITCE bits in case of pending PIT interrupt requests, to avoid spurious interrupt requests.

17.4.3 Hardware Trigger

The PIT module contains four hardware trigger signal lines PITTRIG[3:0], one for each timer channel. These signals can be connected on SoC level to peripheral modules enabling e.g. periodic ATD conversion (please refer to the SoC Guide for the mapping of PITTRIG[3:0] signals to peripheral modules). Whenever a timer channel time-out is reached, the corresponding PTF flag is set and the corresponding trigger signal PITTRIG triggers a rising edge. The trigger feature requires a minimum time-out period of two bus clock cycles because the trigger is asserted high for at least one bus clock cycle. For load register values PITLD = 0x0001 and PITMTLD = 0x0002 the flag setting, trigger timing and a restart with force load is shown in Figure 17-20.

17.5 Initialization/Application Information

17.5.1 Startup

Set the configuration registers before the PITE bit in the PITCFLMT register is set. Before PITE is set, the configuration registers can be written in arbitrary order.

17.5.2 Shutdown

When the PITCE register bits, the PITINTE register bits or the PITE bit in the PITCFLMT register are cleared, the corresponding PIT interrupt flags are cleared. In case of a pending PIT interrupt request, a spurious interrupt can be generated. Two strategies, which avoid spurious interrupts, are recommended: 1. Reset the PIT interrupt flags only in an ISR. When entering the ISR, the I mask bit in the CCR is set automatically. The I mask bit must not be cleared before the PIT interrupt flags are cleared. 2. After setting the I mask bit with the SEI instruction, the PIT interrupt flags can be cleared. Then clear the I mask bit with the CLI instruction to re-enable interrupts.

17.5.3 Flag Clearing

A flag is cleared by writing a one to the flag bit. Always use store or move instructions to write a one in certain bit positions. Do not use the BSET instructions. Do not use any C-constructs that compile to BSET instructions. “BSET flag_register, #mask” must not be used for flag clearing because BSET is a read-modify-write instruction which writes back the “bit-wise or” of the flag_register and the mask into the flag_register. BSET would clear all flag bits that were set, independent from the mask. For example, to clear flag bit 0 use: MOVB #$01,PITTF.

MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 639 Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1)

18.1 Introduction

The PWM definition is based on the HC12 PWM definitions. It contains the basic features from the HC11 with some of the enhancements incorporated on the HC12: center aligned output mode and four available clock sources.The PWM module has eight channels with independent control of left and center aligned outputs on each channel. Each of the eight channels has a programmable period and duty cycle as well as a dedicated counter. A flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs.

18.1.1 Features

The PWM block includes these distinctive features:

• Eight independent PWM channels with programmable period and duty cycle
• Dedicated counter for each PWM channel
• Programmable PWM enable/disable for each channel
• Software selection of PWM duty pulse polarity for each channel
• Period and duty cycle are double buffered. Change takes effect when the end of the effective period is reached (PWM counter reaches zero) or when the channel is disabled.
• Programmable center or left aligned outputs on individual channels
• Eight 8-bit channel or four 16-bit channel PWM resolution
• Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
• Programmable clock select logic
• Emergency shutdown

18.1.2 Modes of Operation

There is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is useful for emulation.

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18.1.3 Block Diagram

Figure 18-1 shows the block diagram for the 8-bit 8-channel PWM block. Figure 18-1. PWM Block Diagram

18.2 External Signal Description

The PWM module has a total of 8 external pins.

18.2.1 PWM7 — PWM Channel 7

This pin serves as waveform output of PWM channel 7 and as an input for the emergency shutdown feature.

18.2.2 PWM6 — PWM Channel 6

This pin serves as waveform output of PWM channel 6. Period and Duty Counter Channel 6 Clock Select PWM Clock Period and Duty Counter Channel 5 Period and Duty Counter Channel 4 Period and Duty Counter Channel 3 Period and Duty Counter Channel 2 Period and Duty Counter Channel 1Alignment Polarity Control PWM8B8C PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 Enable PWM Channels Period and Duty Counter Channel 7 Period and Duty Counter Channel 0 PWM0 PWM7 Bus Clock

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 641

18.2.3 PWM5 — PWM Channel 5

This pin serves as waveform output of PWM channel 5.

18.2.4 PWM4 — PWM Channel 4

This pin serves as waveform output of PWM channel 4.

18.2.5 PWM3 — PWM Channel 3

This pin serves as waveform output of PWM channel 3.

18.2.6 PWM3 — PWM Channel 2

This pin serves as waveform output of PWM channel 2.

18.2.7 PWM3 — PWM Channel 1

This pin serves as waveform output of PWM channel 1.

18.2.8 PWM3 — PWM Channel 0

This pin serves as waveform output of PWM channel 0.

18.3 Memory Map and Register Definition

This section describes in detail all the registers and register bits in the PWM module. The special-purpose registers and register bit functions that are not normally available to device end users, such as factory test control registers and reserved registers, are clearly identified by means of shading the appropriate portions of address maps and register diagrams. Notes explaining the reasons for restricting access to the registers and functions are also explained in the individual register descriptions.

18.3.1 Module Memory Map

This section describes the content of the registers in the PWM module. The base address of the PWM module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. The figure below shows the registers associated with the PWM and their relative offset from the base address. The register detail description follows the order they appear in the register map. Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented functions are indicated by shading the bit. .

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Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level.

18.3.2 Register Descriptions

This section describes in detail all the registers and register bits in the PWM module. Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 PWME R PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 W 0x0001 PWMPOL R PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 W 0x0002 PWMCLK R PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 W 0x0003 PWMPRCLK PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0 W 0x0004 PWMCAE R CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 W 0x0005 PWMCTL R CON67 CON45 CON23 CON01 PSWAI PFRZ W 0x0006 PWMTST1 R 00 0 00000 W 0x0007 PWMPRSC1 R 00 0 00000 W 0x0008 PWMSCLA R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0009 PWMSCLB R Bit 7 6 5 4 3 2 1 Bit 0 W 0x000A PWMSCNTA R 00 0 00000 W = Unimplemented or Reserved Figure 18-2. PWM Register Summary (Sheet 1 of 3)

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 643 0x000B PWMSCNTB R 00 0 00000 W 0x000C PWMCNT0 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x000D PWMCNT1 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x000E PWMCNT2 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x000F PWMCNT3 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x0010 PWMCNT4 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x0011 PWMCNT5 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x0012 PWMCNT6 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x0013 PWMCNT7 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x0014 PWMPER0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0015 PWMPER1 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0016 PWMPER2 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0017 PWMPER3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0018 PWMPER4 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0019 PWMPER5 R Bit 7 6 5 4 3 2 1 Bit 0 W Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 18-2. PWM Register Summary (Sheet 2 of 3)

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18.3.2.1 PWM Enable Register (PWME)

Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. NOTE The first PWM cycle after enabling the channel can be irregular. 0x001A PWMPER6 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001B PWMPER7 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001C PWMDTY0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001D PWMDTY1 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001E PWMDTY2 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001F PWMDTY3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0010 PWMDTY4 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0021 PWMDTY5 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0022 PWMDTY6 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0023 PWMDTY7 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0024 PWMSDN R PWMIF PWMIE PWMLVL

0 PWM7IN

1 Intended for factory test purposes only. Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 18-2. PWM Register Summary (Sheet 3 of 3)

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 645 An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit.In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled. While in run mode, if all eight PWM channels are disabled (PWME7–0 = 0), the prescaler counter shuts off for power savings. Read: Anytime Write: Anytime Module Base + 0x0000 76543210 R PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 W Reset 0 0 0 00000 Figure 18-3. PWM Enable Register (PWME) Table 18-1. PWME Field Descriptions Field Description PWME7 Pulse Width Channel 7 Enable 0 Pulse width channel 7 is disabled. 1 Pulse width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit 7 when its clock source begins its next cycle. PWME6 Pulse Width Channel 6 Enable 0 Pulse width channel 6 is disabled. 1 Pulse width channel 6 is enabled. The pulse modulated signal becomes available at PWM output bit6 when its clock source begins its next cycle. If CON67=1, then bit has no effect and PWM output line 6 is disabled. PWME5 Pulse Width Channel 5 Enable 0 Pulse width channel 5 is disabled. 1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM output bit 5 when its clock source begins its next cycle. PWME4 Pulse Width Channel 4 Enable 0 Pulse width channel 4 is disabled. 1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output bit4 is disabled. PWME3 Pulse Width Channel 3 Enable 0 Pulse width channel 3 is disabled. 1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when its clock source begins its next cycle. PWME2 Pulse Width Channel 2 Enable 0 Pulse width channel 2 is disabled. 1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output bit2 is disabled.

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18.3.2.2 PWM Polarity Register (PWMPOL)

The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. Read: Anytime Write: Anytime NOTE PPOLx register bits can be written anytime. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition

18.3.2.3 PWM Clock Select Register (PWMCLK)

Each PWM channel has a choice of two clocks to use as the clock source for that channel as described below. PWME1 Pulse Width Channel 1 Enable 0 Pulse width channel 1 is disabled. 1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock source begins its next cycle. PWME0 Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled. 1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line0 is disabled. Module Base + 0x0001 76543210 R PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 W Reset 0 0 0 00000 Figure 18-4. PWM Polarity Register (PWMPOL) Table 18-2. PWMPOL Field Descriptions Field Description 7–0 PPOL[7:0] Pulse Width Channel 7–0 Polarity Bits

0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is

reached.

1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is

reached. Table 18-1. PWME Field Descriptions (continued) Field Description

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 647 Read: Anytime Write: Anytime NOTE Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition.

18.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)

This register selects the prescale clock source for clocks A and B independently. Module Base + 0x0002 76543210 R PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 W Reset 0 0 0 00000 Figure 18-5. PWM Clock Select Register (PWMCLK) Table 18-3. PWMCLK Field Descriptions Field Description PCLK7 Pulse Width Channel 7 Clock Select 0 Clock B is the clock source for PWM channel 7. 1 Clock SB is the clock source for PWM channel 7. PCLK6 Pulse Width Channel 6 Clock Select 0 Clock B is the clock source for PWM channel 6. 1 Clock SB is the clock source for PWM channel 6. PCLK5 Pulse Width Channel 5 Clock Select 0 Clock A is the clock source for PWM channel 5. 1 Clock SA is the clock source for PWM channel 5. PCLK4 Pulse Width Channel 4 Clock Select 0 Clock A is the clock source for PWM channel 4. 1 Clock SA is the clock source for PWM channel 4. PCLK3 Pulse Width Channel 3 Clock Select 0 Clock B is the clock source for PWM channel 3. 1 Clock SB is the clock source for PWM channel 3. PCLK2 Pulse Width Channel 2 Clock Select 0 Clock B is the clock source for PWM channel 2. 1 Clock SB is the clock source for PWM channel 2. PCLK1 Pulse Width Channel 1 Clock Select 0 Clock A is the clock source for PWM channel 1. 1 Clock SA is the clock source for PWM channel 1. PCLK0 Pulse Width Channel 0 Clock Select 0 Clock A is the clock source for PWM channel 0. 1 Clock SA is the clock source for PWM channel 0.

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Read: Anytime Write: Anytime NOTE PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. s Module Base + 0x0003 76543210 PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 18-6. PWM Prescale Clock Select Register (PWMPRCLK) Table 18-4. PWMPRCLK Field Descriptions Field Description 6–4 PCKB[2:0] Prescaler Select for Clock B— Clock B is one of two clock sources which can be used for channels 2, 3, 6, or 7. These three bits determine the rate of clock B, as shown in Table 18-5. 2–0 PCKA[2:0] Prescaler Select for Clock A— Clock A is one of two clock sources which can be used for channels 0, 1, 4 or 5. These three bits determine the rate of clock A, as shown in Table 18-6. Table 18-5. Clock B Prescaler Selects PCKB2 PCKB1 PCKB0 Value of Clock B 0 0 0 Bus clock 0 0 1 Bus clock / 2 0 1 0 Bus clock / 4 0 1 1 Bus clock / 8 1 0 0 Bus clock / 16 1 0 1 Bus clock / 32 1 1 0 Bus clock / 64 1 1 1 Bus clock / 128 Table 18-6. Clock A Prescaler Selects PCKA2 PCKA1 PCKA0 Value of Clock A 0 0 0 Bus clock 0 0 1 Bus clock / 2 0 1 0 Bus clock / 4 0 1 1 Bus clock / 8 1 0 0 Bus clock / 16 1 0 1 Bus clock / 32 1 1 0 Bus clock / 64 1 1 1 Bus clock / 128

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 649

18.3.2.5 PWM Center Align Enable Register (PWMCAE)

The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See detailed description of the PWM output modes. Read: Anytime Write: Anytime NOTE Write these bits only when the corresponding channel is disabled.

18.3.2.6 PWM Control Register (PWMCTL)

The PWMCTL register provides for various control of the PWM module. Read: Anytime Write: Anytime There are three control bits for concatenation, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. When channels 6 and 7are concatenated, channel 6 registers become the high order bytes of the double byte channel. When channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel Module Base + 0x0004 76543210 R CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 W Reset 0 0 0 00000 Figure 18-7. PWM Center Align Enable Register (PWMCAE) Table 18-7. PWMCAE Field Descriptions Field Description 7–0 CAE[7:0] Center Aligned Output Modes on Channels 7–0 0 Channels 7–0 operate in left aligned output mode. 1 Channels 7–0 operate in center aligned output mode. Module Base + 0x0005 76543210 R CON67 CON45 CON23 CON01 PSWAI PFRZ W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 18-8. PWM Control Register (PWMCTL)

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2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. See Section 18.4.2.7, “PWM 16-Bit Functions”for a more detailed description of the concatenation PWM Function. NOTE Change these bits only when both corresponding channels are disabled. Table 18-8. PWMCTL Field Descriptions Field Description CON67 Concatenate Channels 6 and 7 0 Channels 6 and 7 are separate 8-bit PWMs. 1 Channels 6 and 7 are concatenated to create one 16-bit PWM channel. Channel 6 becomes the high order byte and channel 7 becomes the low order byte. Channel 7 output pin is used as the output for this 16-bit PWM (bit 7 of port PWMP). Channel 7 clock select control-bit determines the clock source, channel 7 polarity bit determines the polarity, channel 7 enable bit enables the output and channel 7 center aligned enable bit determines the output mode. CON45 Concatenate Channels 4 and 5 0 Channels 4 and 5 are separate 8-bit PWMs. 1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high order byte and channel 5 becomes the low order byte. Channel 5 output pin is used as the output for this 16-bit PWM (bit 5 of port PWMP). Channel 5 clock select control-bit determines the clock source, channel 5 polarity bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit determines the output mode. CON23 Concatenate Channels 2 and 3 0 Channels 2 and 3 are separate 8-bit PWMs. 1 Channels 2 and 3 are concatenated to create one 16-bit PWM channel. Channel 2 becomes the high order byte and channel 3 becomes the low order byte. Channel 3 output pin is used as the output for this 16-bit PWM (bit 3 of port PWMP). Channel 3 clock select control-bit determines the clock source, channel 3 polarity bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit determines the output mode. CON01 Concatenate Channels 0 and 1 0 Channels 0 and 1 are separate 8-bit PWMs. 1 Channels 0 and 1 are concatenated to create one 16-bit PWM channel. Channel 0 becomes the high order byte and channel 1 becomes the low order byte. Channel 1 output pin is used as the output for this 16-bit PWM (bit 1 of port PWMP). Channel 1 clock select control-bit determines the clock source, channel 1 polarity bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit determines the output mode. PSWAI PWM Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling the input clock to the prescaler. 0 Allow the clock to the prescaler to continue while in wait mode. 1 Stop the input clock to the prescaler whenever the MCU is in wait mode. PFREZ PWM Counters Stop in Freeze Mode — In freeze mode, there is an option to disable the input clock to the prescaler by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode, the input clock to the prescaler is disabled. This feature is useful during emulation as it allows the PWM function to be suspended. In this way, the counters of the PWM can be stopped while in freeze mode so that once normal program flow is continued, the counters are re-enabled to simulate real-time operations. Since the registers can still be accessed in this mode, to re-enable the prescaler clock, either disable the PFRZ bit or exit freeze mode. 0 Allow PWM to continue while in freeze mode. 1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation.

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 651

18.3.2.7 Reserved Register (PWMTST)

This register is reserved for factory testing of the PWM module and is not available in normal modes. Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality.

18.3.2.8 Reserved Register (PWMPRSC)

This register is reserved for factory testing of the PWM module and is not available in normal modes. Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality.

18.3.2.9 PWM Scale A Register (PWMSCLA)

PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two. Clock SA = Clock A / (2 * PWMSCLA) Module Base + 0x0006 76543210 R 00000000 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 18-9. Reserved Register (PWMTST) Module Base + 0x0007 76543210 R 00000000 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 18-10. Reserved Register (PWMPRSC)

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When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA). Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLA value)

18.3.2.10 PWM Scale B Register (PWMSCLB)

PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is generated by taking clock B, dividing it by the value in the PWMSCLB register and dividing that by two. Clock SB = Clock B / (2 * PWMSCLB) NOTE When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB). Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLB value).

18.3.2.11 Reserved Registers (PWMSCNTx)

The registers PWMSCNTA and PWMSCNTB are reserved for factory testing of the PWM module and are not available in normal modes. Module Base + 0x0008 76543210 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 00000 Figure 18-11. PWM Scale A Register (PWMSCLA) Module Base + 0x0009 76543210 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 00000 Figure 18-12. PWM Scale B Register (PWMSCLB)

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 653 Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to these registers when in special modes can alter the PWM functionality.

18.3.2.12 PWM Channel Counter Registers (PWMCNTx)

Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. The counter can be read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts from 0 to the value in the period register - 1. In center aligned output mode, the counter counts from 0 up to the value in the period register and then back down to 0. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. The counter is also cleared at the end of the effective period (see details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the PWMCNTx register. For more detailed information on the operation of the counters, seeSection 18.4.2.4, “PWM Timer Counters”. In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur. Read: Anytime Module Base + 0x000A, 0x000B 76543210 R 00000000 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 18-13. Reserved Registers (PWMSCNTx) Module Base + 0x000C = PWMCNT0, 0x000D = PWMCNT1, 0x000E = PWMCNT2, 0x000F = PWMCNT3 Module Base + 0x0010 = PWMCNT4, 0x0011 = PWMCNT5, 0x0012 = PWMCNT6, 0x0013 = PWMCNT7 76543210 R Bit 7 6 5 4 3 2 1 Bit 0 W 00000000 Reset 0 0 0 00000 Figure 18-14. PWM Channel Counter Registers (PWMCNTx)

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Write: Anytime (any value written causes PWM counter to be reset to $00).

18.3.2.13 PWM Channel Period Registers (PWMPERx)

There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM channel. The period registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs:

• The effective period ends
• The counter is written (counter resets to $00)
• The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active period due to the double buffering scheme. See Section 18.4.2.3, “PWM Period and Duty” for more information. To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA, or SB) and multiply it by the value in the period register for that channel:
• Left aligned output (CAEx = 0)
• PWMxPeriod=ChannelClockPeriod*PWMPERxCenterAlignedOutput(CAEx=1) PWMx Period = Channel Clock Period * (2 * PWMPERx) For boundary case programming values, please refer to Section 18.4.2.8, “PWM Boundary Cases”. Read: Anytime Write: Anytime Module Base + 0x0014 = PWMPER0, 0x0015 = PWMPER1, 0x0016 = PWMPER2, 0x0017 = PWMPER3 Module Base + 0x0018 = PWMPER4, 0x0019 = PWMPER5, 0x001A = PWMPER6, 0x001B = PWMPER7 76543210 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 1 1 1 11111 Figure 18-15. PWM Channel Period Registers (PWMPERx)

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 655

18.3.2.14 PWM Channel Duty Registers (PWMDTYx)

There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state. The duty registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs:

• The effective period ends
• The counter is written (counter resets to $00)
• The channel is disabled In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform, not some variation in between. If the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active duty due to the double buffering scheme. See Section 18.4.2.3, “PWM Period and Duty” for more information. NOTE Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. If the polarity bit is one, the output starts high and then goes low when the duty count is reached, so the duty registers contain a count of the high time. If the polarity bit is zero, the output starts low and then goes high when the duty count is reached, so the duty registers contain a count of the low time. To calculate the output duty cycle (high time as a% of period) for a particular channel:
• Polarity = 0 (PPOL x =0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
• Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% For boundary case programming values, please refer to Section 18.4.2.8, “PWM Boundary Cases”. Read: Anytime Module Base + 0x001C = PWMDTY0, 0x001D = PWMDTY1, 0x001E = PWMDTY2, 0x001F = PWMDTY3 Module Base + 0x0020 = PWMDTY4, 0x0021 = PWMDTY5, 0x0022 = PWMDTY6, 0x0023 = PWMDTY7 76543210 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 1 1 1 11111 Figure 18-16. PWM Channel Duty Registers (PWMDTYx)

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Write: Anytime

18.3.2.15 PWM Shutdown Register (PWMSDN)

The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency cases. For proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks. Read: Anytime Write: Anytime Module Base + 0x0024 76543210 R PWMIF PWMIE PWMLVL = Unimplemented or Reserved Figure 18-17. PWM Shutdown Register (PWMSDN) Table 18-9. PWMSDN Field Descriptions Field Description PWMIF PWM Interrupt Flag — Any change from passive to asserted (active) state or from active to passive state will be flagged by setting the PWMIF flag = 1. The flag is cleared by writing a logic 1 to it. Writing a 0 has no effect. 0 No change on PWM7IN input.

1 Change on PWM7IN input

PWM Interrupt Enable — If interrupt is enabled an interrupt to the CPU is asserted. 0 PWM interrupt is disabled. 1 PWM interrupt is enabled. PWMRSTRT PWM Restart — The PWM can only be restarted if the PWM channel input 7 is de-asserted. After writing a logic 1 to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes next “counter == 0” phase. Also, if the PWM7ENA bit is reset to 0, the PWM do not start before the counter passes $00. The bit is always read as “0”. PWMLVL PWM Shutdown Output Level If active level as defined by the PWM7IN input, gets asserted all enabled PWM channels are immediately driven to the level defined by PWMLVL.

0 PWM outputs are forced to 0

1 Outputs are forced to 1. PWM7IN PWM Channel 7 Input Status — This reflects the current status of the PWM7 pin. PWM7INL PWM Shutdown Active Input Level for Channel 7 — If the emergency shutdown feature is enabled (PWM7ENA = 1), this bit determines the active level of the PWM7channel.

0 Active level is low

1 Active level is high

PWM Emergency Shutdown Enable— If this bit is logic 1, the pin associated with channel 7 is forced to input and the emergency shutdown feature is enabled. All the other bits in this register are meaningful only if PWM7ENA = 1. 0 PWM emergency feature disabled. 1 PWM emergency feature is enabled.

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 657

18.4 Functional Description

18.4.1 PWM Clock Select

There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter. Similarly, clock SB uses clock B as an input and divides it further with a reloadable counter. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB. Each PWM channel has the capability of selecting one of two clocks, either the pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB). The block diagram in Figure 18-18 shows the four different clocks and how the scaled clocks are created.

18.4.1.1 Prescale

The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode (freeze mode signal active) the input clock to the prescaler is disabled. This is useful for emulation in order to freeze the PWM. The input clock can also be disabled when all eight PWM channels are disabled (PWME7-0 = 0). This is useful for reducing power by disabling the prescale counter. Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock A and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. The value selected for clock A is determined by the PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK register. The value selected for clock B is determined by the PCKB2, PCKB1, PCKB0 bits also in the PWMPRCLK register.

18.4.1.2 Clock Scale

The scaled A clock uses clock A as an input and divides it further with a user programmable value and then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user programmable value and then divides this by 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB.

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06

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Figure 18-18. PWM Clock Select Block Diagram 128248 1 6 3 2 6 4 PCKB2 PCKB1 PCKB0 M U X Clock A Clock B Clock SA Clock A/2, A/4, A/6,....A/512 Prescale Scale Divide byPFRZ Freeze Mode Signal Bus Clock Clock Select M U X PCLK0 Clock to PWM Ch 0 M U X PCLK2 Clock to PWM Ch 2 M U X PCLK1 Clock to PWM Ch 1 M U X PCLK4 Clock to PWM Ch 4 M U X PCLK5 Clock to PWM Ch 5 M U X PCLK6 Clock to PWM Ch 6 M U X PCLK7 Clock to PWM Ch 7 M U X PCLK3 Clock to PWM Ch 3 Load DIV 2PWMSCLB Clock SB Clock B/2, B/4, B/6,....B/512 M U X PCKA2 PCKA1 PCKA0 PWME7-0 Count = 1 Load DIV 2PWMSCLA Count = 18-Bit Down Counter 8-Bit Down Counter Prescaler Taps:

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 659 Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value in the PWMSCLA register. NOTE Clock SA = Clock A / (2 * PWMSCLA) When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock SB. Thus, clock SB equals clock B divided by two times the value in the PWMSCLB register. NOTE Clock SB = Clock B / (2 * PWMSCLB) When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for this case will be E divided by 4. A pulse will occur at a rate of once every 255x4 E cycles. Passing this through the divide by two circuit produces a clock signal at an E divided by 2040 rate. Similarly, a value of $01 in the PWMSCLA register when clock A is E divided by 4 will produce a clock at an E divided by 8 rate. Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded. Otherwise, when changing rates the counter would have to count down to $01 before counting at the proper rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or PWMSCLB is written prevents this. NOTE Writing to the scale registers while channels are operating can cause irregularities in the PWM outputs.

18.4.1.3 Clock Select

Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock choices are clock A or clock SA. For channels 2, 3, 6, and 7 the choices are clock B or clock SB. The clock selection is done with the PCLKx control bits in the PWMCLK register. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs.

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18.4.2 PWM Channel Timers

The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period. The starting polarity of the output is also selectable on a per channel basis. Shown below inFigure 18-19 is the block diagram for the PWM timer. Figure 18-19. PWM Timer Channel Block Diagram

18.4.2.1 PWM Enable

Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. An exception to this is when channels are NOTE The first PWM cycle after enabling the channel can be irregular. Clock Source T R Q Q PPOLx From Port PWMP Data Register PWMEx To Pin Driver Gate 8-bit Compare = PWMDTYx 8-bit Compare = PWMPERx CAExT R Q Q 8-Bit Counter PWMCNTx M U X M U X (Clock Edge Sync) Up/Down Reset

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 661 On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count.

18.4.2.2 PWM Polarity

Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown on the block diagram as a mux select of either the Q output or the Q output of the PWM output flip flop. When one of the bits in the PWMPOL register is set, the associated PWM channel output is high at the beginning of the waveform, then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached.

18.4.2.3 PWM Period and Duty

Dedicated period and duty registers exist for each channel and are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs:

• The effective period ends
• The counter is written (counter resets to $00)
• The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer. A change in duty or period can be forced into effect “immediately” by writing the new value to the duty and/or period registers and then writing to the counter. This forces the counter to reset and the new duty and/or period values to be latched. In addition, since the counter is readable, it is possible to know where the count is with respect to the duty value and software can be used to make adjustments NOTE When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur. Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time.

18.4.2.4 PWM Timer Counters

Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see Section 18.4.1, “PWM Clock Select” for the available clock sources and rates). The counter compares to two registers, a duty register and a period register as shown in Figure 18-19. When the PWM counter matches the duty register, the output flip-flop changes state, causing the PWM waveform to also change state. A match between the PWM counter and the period register behaves differently depending on what output mode is selected as shown in Figure 18-19 and described in Section 18.4.2.5, “Left Aligned Outputs” and Section 18.4.2.6, “Center Aligned Outputs”.

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Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When a channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the PWMCNTx register. This allows the waveform to continue where it left off when the channel is re-enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset on the next selected clock. NOTE If the user wants to start a new “clean” PWM waveform without any “history” from the old waveform, the user must write to channel counter (PWMCNTx) prior to enabling the PWM channel (PWMEx = 1). Generally, writes to the counter are done prior to enabling a channel in order to start from a known state. However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is similar to writing the counter when the channel is disabled, except that the new period is started immediately with the output set according to the polarity bit. NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur. The counter is cleared at the end of the effective period (seeSection 18.4.2.5, “Left Aligned Outputs” and Section 18.4.2.6, “Center Aligned Outputs” for more details).

18.4.2.5 Left Aligned Outputs

The PWM timer provides the choice of two types of outputs, left aligned or center aligned. They are selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the corresponding PWM output will be left aligned. In left aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two registers, a duty register and a period register as shown in the block diagram in Figure 18-19. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register resets the counter and the output flip-flop, as shown in Figure 18-19, as well as performing a load from the double buffer period and duty register to the associated registers, as described in Section 18.4.2.3, “PWM Period and Duty”. The counter counts from 0 to the value in the period register – 1. Table 18-10. PWM Timer Counter Conditions Counter Clears ($00) Counter Counts Counter Stops When PWMCNTx register written to any value When PWM channel is enabled (PWMEx = 1). Counts from last value in PWMCNTx. When PWM channel is disabled (PWMEx = 0) Effective period ends

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 663 NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. Figure 18-20. PWM Left Aligned Output Waveform To calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register for that channel.

• PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx
• PWMx Duty Cycle (high time as a% of period): — Polarity = 0 (PPOLx = 0)
• Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% As an example of a left aligned output, consider the following case: Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/4 = 2.5 MHz PWMx Period = 400 ns PWMx Duty Cycle = 3/4 *100% = 75% The output waveform generated is shown in Figure 18-21. PWMDTYx Period = PWMPERx PPOLx = 0 PPOLx = 1

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Figure 18-21. PWM Left Aligned Output Example Waveform

18.4.2.6 Center Aligned Outputs

For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00. The counter compares to two registers, a duty register and a period register as shown in the block diagram in Figure 18-19. When the PWM counter matches the duty register, the output flip-flop changes state, causing the PWM waveform to also change state. A match between the PWM counter and the period register changes the counter direction from an up-count to a down-count. When the PWM counter decrements and matches the duty register again, the output flip-flop changes state causing the PWM output to also change state. When the PWM counter decrements and reaches zero, the counter direction changes from a down-count back to an up-count and a load from the double buffer period and duty registers to the associated registers is performed, as described inSection 18.4.2.3, “PWM Period and Duty”. The counter counts from 0 up to the value in the period register and then back down to 0. Thus the effective period is PWMPERx*2. NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. Figure 18-22. PWM Center Aligned Output Waveform Period = 400 ns E = 100 ns Duty Cycle = 75% PPOLx = 0 PPOLx = 1 PWMDTYx PWMDTYx Period = PWMPERx*2 PWMPERxPWMPERx

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 665 To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.

• PWMx Frequency = Clock (A, B, SA, or SB) / (2*PWMPERx)
• PWMx Duty Cycle (high time as a% of period): — Polarity = 0 (PPOLx = 0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100%

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As an example of a center aligned output, consider the following case: Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/8 = 1.25 MHz PWMx Period = 800 ns PWMx Duty Cycle = 3/4 *100% = 75% Shown in Figure 18-23 is the output waveform generated. Figure 18-23. PWM Center Aligned Output Example Waveform

18.4.2.7 PWM 16-Bit Functions

The PWM timer also has the option of generating 8-channels of 8-bits or 4-channels of 16-bits for greater PWM resolution. This 16-bit channel option is achieved through the concatenation of two 8-bit channels. The PWMCTL register contains four control bits, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. Channels 6 and 7 are concatenated with the CON67 bit, channels 4 and 5 are concatenated with the CON45 bit, channels 2 and 3 are concatenated with the CON23 bit, and channels 0 and 1 are concatenated with the CON01 bit. NOTE Change these bits only when both corresponding channels are disabled. When channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double byte channel, as shown in Figure 18-24. Similarly, when channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel clock select control bits. That is channel 7 when channels 6 and 7 are concatenated, channel 5 when channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order 8-bit channel as also shown inFigure 18-24. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low order 8-bit channel as well. E = 100 ns DUTY CYCLE = 75% E = 100 ns PERIOD = 800 ns

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 667 Figure 18-24. PWM 16-Bit Mode Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output is disabled. In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. PWMCNT6 PWCNT7 PWM7 Clock Source 7 High Low Period/Duty Compare PWMCNT4 PWCNT5 PWM5 Clock Source 5 High Low Period/Duty Compare PWMCNT2 PWCNT3 PWM3 Clock Source 3 High Low Period/Duty Compare PWMCNT0 PWCNT1 PWM1 Clock Source 1 High Low Period/Duty Compare

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Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order CAEx bit. The high order CAEx bit has no effect. Table 18-11 is used to summarize which channels are used to set the various control bits when in 16-bit mode.

18.4.2.8 PWM Boundary Cases

Table 18-12summarizes the boundary conditions for the PWM regardless of the output mode (left aligned or center aligned) and 8-bit (normal) or 16-bit (concatenation).

18.5 Resets

The reset state of each individual bit is listed within the Section 18.3.2, “Register Descriptions” which details the registers and their bit-fields. All special functions or modes which are initialized during or just following reset are described within this section.

• The 8-bit up/down counter is configured as an up counter out of reset.
• All the channels are disabled and all the counters do not count. Table 18-11. 16-bit Concatenation Mode Summary CONxx PWMEx PPOLx PCLKx CAEx PWMx Output CON67 PWME7 PPOL7 PCLK7 CAE7 PWM7 CON45 PWME5 PPOL5 PCLK5 CAE5 PWM5 CON23 PWME3 PPOL3 PCLK3 CAE3 PWM3 CON01 PWME1 PPOL1 PCLK1 CAE1 PWM1 Table 18-12. PWM Boundary Cases PWMDTYx PWMPERx PPOLx PWMx Output $00 (indicates no duty) >$00 1 Always low $00 (indicates no duty) >$00 0 Always high XX $00 1 (indicates no period) 1 Counter = $00 and does not count.

1 Always high

XX $00 1 (indicates no period)

0 Always low

= PWMPERx XX 1 Always high >= PWMPERx XX 0 Always low

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18.6 Interrupts

The PWM module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt flag PWMIF is set whenever the input level of the PWM7 channel changes while PWM7ENA = 1 or when PWMENA is being asserted while the level at PWM7 is active. In stop mode or wait mode (with the PSW AI bit set), the emergency shutdown feature will drive the PWM outputs to their shutdown output levels but the PWMIF flag will not be set. A description of the registers involved and affected due to this interrupt is explained inSection 18.3.2.15, “PWM Shutdown Register (PWMSDN)”. The PWM block only generates the interrupt and does not service it. The interrupt signal name is PWM interrupt signal.

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MC9S12XHZ512 Data Sheet, Rev. 1.06 Freescale Semiconductor 671 Chapter 19 Enhanced Capture Timer (ECT16B8CV3)

19.1 Introduction

The HCS12 enhanced capture timer module has the features of the HCS12 standard timer module enhanced by additional features in order to enlarge the field of applications, in particular for automotive ABS applications. This design specification describes the standard timer as well as the additional features. The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. A full access for the counter registers or the input capture/output compare registers will take place in one clock cycle. Accessing high byte and low byte separately for all of these registers will not yield the same result as accessing them in one word.

19.1.1 Features

• 16-bit buffer register for four input capture (IC) channels. Table 19-1. Revision History Revision Number Revision Date Sections Affected Description of Changes V03.06 05 Aug 2009 19.3.2.15/19-69 19.3.2.16/19-69 19.3.2.24/19-70 19.3.2.29/19-70 19.4.1.1.2/19-71 update register PACTL bit4 PEDGE PT7 to IC7 update register PAFLG bit0 PAIF PT7 to IC7,update bit1 PAOVF PT3 to IC3 update register ICSYS bit3 TFMOD PTx to ICx update register PBFLG bit1 PBOVF PT1 to IC1 update IC Queue Mode description. V03.07 26 Aug 2009 19.3.2.2/19-680 19.3.2.3/19-680 19.3.2.4/19-681 - Add description, ?a counter overflow when TTOV[7] is set?, to be the condition of channel 7 override event. - Phrase the description of OC7M to make it more explicit V03.08 04 May 2010 19.3.2.8/19-684 19.3.2.11/19-68 - Add Table 19-11 TCRE descripgion part,add Note and Figure 19-17

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• Four 8-bit pulse accumulators with 8-bit buffer registers associated with the four buffered IC channels. Configurable also as two 16-bit pulse accumulators.
• 16-bit modulus down-counter with 8-bit prescaler.
• Four user-selectable delay counters for input noise immunity increase.

19.1.2 Modes of Operation

• Stop — Timer and modulus counter are off since clocks are stopped.
• Freeze — Timer and modulus counter keep on running, unless the TSFRZ bit in the TSCR1 register is set to one.
• Wait — Counters keep on running, unless the TSW AI bit in the TSCR1 register is set to one.
• Normal — Timer and modulus counter keep on running, unless the TEN bit in the TSCR1 register or the MCEN bit in the MCCTL register are cleared.

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19.1.3 Block Diagram

Figure 19-1. ECT Block Diagram

19.2 External Signal Description

The ECT module has a total of eight external pins.

19.2.1 IOC7 — Input Capture and Output Compare Channel 7

This pin serves as input capture or output compare for channel 7.

19.2.2 IOC6 — Input Capture and Output Compare Channel 6

This pin serves as input capture or output compare for channel 6. Prescaler 16-bit Counter 16-Bit Pulse Accumulator B IOC0 IOC2 IOC1 IOC5 IOC3 IOC4 IOC6 IOC7 PA Input Interrupt PA Overflow Interrupt Timer Overflow Interrupt Timer Channel 0 Interrupt Timer Channel 7 Interrupt Registers Bus Clock Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 16-Bit Pulse Accumulator A PB Overflow Interrupt Modulus Counter Interrupt 16-Bit Modulus Counter Input Capture Output Compare Input Capture Input Capture Input Capture Input Capture Input Capture Input Capture Input Capture Output Compare Output Compare Output Compare Output Compare Output Compare Output Compare Output Compare

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19.2.3 IOC5 — Input Capture and Output Compare Channel 5

This pin serves as input capture or output compare for channel 5.

19.2.4 IOC4 — Input Capture and Output Compare Channel 4

This pin serves as input capture or output compare for channel 4.

19.2.5 IOC3 — Input Capture and Output Compare Channel 3

This pin serves as input capture or output compare for channel 3.

19.2.6 IOC2 — Input Capture and Output Compare Channel 2

This pin serves as input capture or output compare for channel 2.

19.2.7 IOC1 — Input Capture and Output Compare Channel 1

This pin serves as input capture or output compare for channel 1.

19.2.8 IOC0 — Input Capture and Output Compare Channel 0

This pin serves as input capture or output compare for channel 0. NOTE For the description of interrupts see Section 19.4.3, “Interrupts”.

19.3 Memory Map and Register Definition

This section provides a detailed description of all memory and registers.

19.3.1 Module Memory Map

The memory map for the ECT module is given below in theTable 19-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the ECT module and the address offset for each register.

19.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.

Chapter 19 Enhanced Capture Timer (ECT16B8CV3) MC9S12XHZ512 Data Sheet Rev. 1.06 Freescale Semiconductor 675 Register Name Bit 7 654321 Bit 0 0x0000 TIOS R IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 W 0x0001 CFORC R 0000000 0 W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 0x0002 OC7M R OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 W 0x0003 OC7D R OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 W 0x0004 TCNT (High) R TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 W 0x0005 TCNT (Low) R TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 W 0x0006 TSCR1 R TEN TSWAI TSFRZ TFFCA PRNT 000 W 0x0007 TTOF R TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 W 0x0008 TCTL1 R OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 W 0x0009 TCTL2 R OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 W 0x000A TCTL3 R EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A W 0x000B TCTL4 R EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A W 0x000C TIE R C7I C6I C5I C4I C3I C2I C1I C0I W = Unimplemented or Reserved Figure 19-2. ECT Register Summary (Sheet 1 of 5)

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R TOI 000 TCRE PR2 PR1 PR0 W 0x000E TFLG1 R C7F C6F C5F C4F C3F C2F C1F C0F W 0x000F TFLG2 R TOF 000000 0 W 0x0010 TC0 (High) R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x0011 TC0 (Low) R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0012 TC1 (High) R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x0013 TC1 (Low) R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0014 TC2 (High) R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x0015 TC2 (Low) R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0016 TC3 (High) R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x0017 TC3 (Low) R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0018 TC4 (High) R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x0019 TC4 (Low) R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x001A TC5 (High) R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x001B TC5 (Low) R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved Figure 19-2. ECT Register Summary (Sheet 2 of 5)

Chapter 19 Enhanced Capture Timer (ECT16B8CV3) MC9S12XHZ512 Data Sheet Rev. 1.06 Freescale Semiconductor 677 0x001C TC6 (High) R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x001D TC6 (Low) R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x001E TC7 (High) R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x001F TC7 (Low) R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0020 PACTL PAEN PAMOD PEDGE CLK1 CLK0 PA0VI PAI W 0x0021 PAFLG R 000000 PA0VF PAIF W 0x0022 PACN3 R PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8) W 0x0023 PACN2 R PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 W 0x0024 PACN1 R PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8) W 0x0025 PACN0 R PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 W 0x0026 MCCTL R MCZI MODMC RDMCL MCEN MCPR1 MCPR0 W ICLAT FLMC 0x0027 MCFLG R MCZF 0 0 0 POLF3 POLF2 POLF1 POLF0 W 0x0028 ICPAR R 0000 PA3EN PA2EN PA1EN PA0EN W 0x0029 DL YCT R DL Y7 DL Y6 DL Y5 DL Y4 DL Y3 DL Y2 DL Y1 DL Y0 W 0x002A ICOVW R NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0 W Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved Figure 19-2. ECT Register Summary (Sheet 3 of 5)

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R SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ W 0x002C OCPD R OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 W 0x002D TIMTST R Timer Test Register W 0x002E PTPSR R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 W 0x002F PTMCPSR R PTMPS7 PTMPS6 PTMPS5 PTMPS4 PTMPS3 PTMPS2 PTMPS1 PTMPS0 W 0x0030 PBCTL PBEN 0000 PBOVI W 0x0031 PBFLG R 000000 PBOVF W 0x0032 PA3H R PA3H7 PA3H6 PA3H5 PA3H4 PA3H3 PA3H2 PA3H1 PA3H0 W 0x0033 PA2H R PA2H7 PA2H6 PA2H5 PA2H4 PA2H3 PA2H2 PA2H1 PA2H0 W 0x0034 PA1H R PA1H7 PA1H6 PA1H5 PA1H4 PA1H3 PA1H2 PA1H1 PA1H0 W 0x0035 PA0H R PA0H7 PA0H6 PA0H5 PA0H4 PA0H3 PA0H2 PA0H1 PA0H0 W 0x0036 MCCNT (High) R MCCNT15 MCCNT14 MCCNT13 MCCNT12 MCCNT11 MCCNT10 MCCNT9 MCCNT8W 0x0037 MCCNT (Low) R MCCNT7 MCCNT6 MCCNT5 MCCNT4 MCCNT3 MCCNT2 MCCNT1 MCCNT0W 0x0038 TC0H (High) R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 W 0x0039 TC0H (Low) R TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved Figure 19-2. ECT Register Summary (Sheet 4 of 5)

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19.3.2.1 Timer Input Capture/Output Compare Select Register (TIOS)

Read or write: Anytime All bits reset to zero. 0x003A TC1H (High) R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 W 0x003B TC1H (Low) R TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 W 0x003C TC2H (High) R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 W 0x003D TC2H (Low) R TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 W 0x003E TC3H (High) R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 W 0x003F TC3H (Low) R TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 W Module Base + 0x0000 76543210 R IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 W Reset 00000000 Figure 19-3. Timer Input Capture/Output Compare Register (TIOS) Table 19-2. TIOS Field Descriptions Field Description 7:0 IOS[7:0] Input Capture or Output Compare Channel Configuration 0 The corresponding channel acts as an input capture. 1 The corresponding channel acts as an output compare. Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved Figure 19-2. ECT Register Summary (Sheet 5 of 5)

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19.3.2.2 Timer Compare Force Register (CFORC)

Read or write: Anytime but reads will always return 0x0000 (1 state is transient). All bits reset to zero.

19.3.2.3 Output Compare 7 Mask Register (OC7M)

Read or write: Anytime All bits reset to zero. Module Base + 0x0001 76543210 R 00000000 W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 Reset 00000000 Figure 19-4. Timer Compare Force Register (CFORC) Table 19-3. CFORC Field Descriptions Field Description 7:0 FOC[7:0] Force Output Compare Action for Channel 7:0— A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not get set. Note: A channel 7 event, which can be a counter overflow when TTOV[7] is set or A successful channel 7 output compare overrides any channel 6:0 compares. If a forced output compare on any channel occurs at the same time as the successful output compare, then the forced output compare action will take precedence and the interrupt flag will not get set. Module Base + 0x0002 76543210 R OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 W Reset 00000000 Figure 19-5. Output Compare 7 Mask Register (OC7M)

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19.3.2.4 Output Compare 7 Data Register (OC7D)

Read or write: Anytime All bits reset to zero.

19.3.2.5 Timer Count Register (TCNT)

Table 19-4. OC7M Field Descriptions Field Description 7:0 OC7M[7:0] Output Compare Mask Action for Channel 7:0 A channel 7 event, which can be a counter overflow when TTOV[7] is set or a successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set,the output compare action reflects the corresponding OC7D bit. 0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on a channel 7 event, even if the corresponding pin is setup for output compare. 1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a channel 7 event. Note: The corresponding channel must also be setup for output compare (IOSx = 1 andOCPDx = 0) for data to be transferred from the output compare 7 data register to the timer port. Module Base + 0x0003 76543210 R OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 W Reset 00000000 Figure 19-6. Output Compare 7 Data Register (OC7D) Table 19-5. OC7D Field Descriptions Field Description 7:0 OC7D[7:0] Output Compare 7 Data Bits — A channel 7 event, which can be a counter overflow when TTOV[7] is set or A channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register. Module Base + 0x0004 15 14 13 12 11 10 9 8 R TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 W Reset 00000000 Figure 19-7. Timer Count Register High (TCNT)

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Read: Anytime Write: Writable in special modes. All bits reset to zero.

19.3.2.6 Timer System Control Register 1 (TSCR1)

Read or write: Anytime except PRNT bit is write once All bits reset to zero. Module Base + 0x0005 76543210 R TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 W Reset 00000000 Figure 19-8. Timer Count Register Low (TCNT) Table 19-6. TCNT Field Descriptions Field Description 15:0 TCNT[15:0] Timer Counter Bits— The 16-bit main timer is an up counter. A read to this register will return the current value of the counter. Access to the counter register will take place in one clock cycle. Note: A separate read/write for high byte and low byte in test mode will give a different result than accessing them as a word. The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock. Module Base + 0x0006 76543210 R TEN TSWAI TSFRZ TFFCA PRNT 000 W Reset 00000000 = Unimplemented or Reserved Figure 19-9. Timer System Control Register 1 (TSCR1) Table 19-7. TSCR1 Field Descriptions Field Description TEN Timer Enable 0 Disables the main timer, including the counter. Can be used for reducing power consumption. 1 Allows the timer to function normally. Note: If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator since the ÷64 is generated by the timer prescaler. TSWAI Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait. 1 Disables the timer counter, pulse accumulators and modulus down counter when the MCU is in wait mode. Timer interrupts cannot be used to get the MCU out of wait.

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19.3.2.7 Timer Toggle On Overflow Register 1 (TTOV)

Read or write: Anytime All bits reset to zero. TSFRZ Timer and Modulus Counter Stop While in Freeze Mode 0 Allows the timer and modulus counter to continue running while in freeze mode. 1 Disables the timer and modulus counter whenever the MCU is in freeze mode. This is useful for emulation. The pulse accumulators do not stop in freeze mode. TFFCA Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally. 1 A read from an input capture or a write to the output compare channel registers causes the corresponding channel flag, CxF , to be cleared in the TFLG1 register. Any access to the TCNT register clears the TOF flag in the TFLG2 register. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register. Any access to the MCCNT register clears the MCZF flag in the MCFLG register. This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses. Note: The flags cannot be cleared via the normal flag clearing mechanism (writing a one to the flag) when TFFCA = 1. PRNT Precision Timer 0 Enables legacy timer. Only bits DL Y0 and DL Y1 of the DL YCT register are used for the delay selection of the delay counter. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection. MCPR0 and MCPR1 bits of the MCCTL register are used for modulus down counter prescaler selection. 1 Enables precision timer. All bits in the DL YCT register are used for the delay selection, all bits of the PTPSR register are used for Precision Timer Prescaler Selection, and all bits of PTMCPSR register are used for the prescaler Precision Timer Modulus Counter Prescaler selection. Module Base + 0x0007 76543210 R TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 W Reset 00000000 Figure 19-10. Timer Toggle On Overflow Register 1 (TTOV) Table 19-8. TTOV Field Descriptions Field Description 7:0 TOV[7:0] Toggle On Overflow Bits — TOV97:0] toggles output compare pin on timer counter overflow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override events. 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled. Table 19-7. TSCR1 Field Descriptions (continued) Field Description

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19.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)

Read or write: Anytime All bits reset to zero. NOTE To enable output action by OMx and OLx bits on timer port, the corresponding bit in OC7M should be cleared.The settings for these bits can be seen in Table 19-11 Module Base + 0x0008 76543210 R OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 W Reset 00000000 Figure 19-11. Timer Control Register 1 (TCTL1) Module Base + 0x0009 76543210 R OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 W Reset 00000000 Figure 19-12. Timer Control Register 2 (TCTL2) Table 19-9. TCTL1/TCTL2 Field Descriptions Field Description OM[7:0] 7, 5, 3, 1 OMx — Output Mode OLx — Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is one, the pin associated with OCx becomes an output tied to OCx. See Table 19-10. OL[7:0] 6, 4, 2, 0 Table 19-10. Compare Result Output Action OMx OLx Action 0 0 No output compare action on the timer output signal 0 1 Toggle OCx output line 1 0 Clear OCx output line to zero 1 1 Set OCx output line to one

Chapter 19 Enhanced Capture Timer (ECT16B8CV3) MC9S12XHZ512 Data Sheet Rev. 1.06 Freescale Semiconductor 685 Table 19-11. The OC7 and OCx event priority Note: in Table 19-11,the IOS7 and IOSx should be set to 1 IOSx is the register TIOS bit x, OC7Mx is the register OC7M bit x, TCx is timer Input Capture/Output Compare register, IOCx is channel x, OMx/OLx is the register TCTL1/TCTL2, OC7Dx is the register OC7D bit x. IOCx = OC7Dx+ OMx/OLx, means that both OC7 event and OCx event will change channel x value.

19.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)

Read or write: Anytime All bits reset to zero. OC7M7=0 OC7M7=1 OC7Mx=1 OC7Mx=0 OC7Mx=1 OC7Mx=0 TC7=TCx TC7>TCx TC7=TCx TC7>TCx TC7=TCx TC7>TCx TC7=TCx TC7>TCx IOCx=OC7Dx IOC7=OM7/O IOCx=OC7Dx +OMx/OLx IOC7=OM7/O IOCx=OMx/OLx IOC7=OM7/OL7 IOCx=OC7Dx IOC7=OC7D7 IOCx=OC7Dx +OMx/OLx IOC7=OC7D7 IOCx=OMx/OLx IOC7=OC7D7 Module Base + 0x000A 76543210 R EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A W Reset 00000000 Figure 19-13. Timer Control Register 3 (TCTL3) Module Base + 0x000B 76543210 R EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A W Reset 00000000 Figure 19-14. Timer Control Register 4 (TCTL4)

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19.3.2.10 Timer Interrupt Enable Register (TIE)

Read or write: Anytime All bits reset to zero. The bits C7I–C0I correspond bit-for-bit with the flags in the TFLG1 status register. Table 19-12. TCTL3/TCTL4 Field Descriptions Field Description EDG[7:0]B 7, 5, 3, 1 Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector circuits for each input capture channel. The four pairs of control bits in TCTL4 also configure the input capture edge control for the four 8-bit pulse accumulators PAC0–PAC3.EDG0B and EDG0A in TCTL4 also determine the active edge for the 16-bit pulse accumulator PACB. SeeTable 19-13.EDG[7:0]A 6, 4, 2, 0 Table 19-13. Edge Detector Circuit Configuration EDGxB EDGxA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge (rising or falling) Module Base + 0x000C 76543210 R C7I C6I C5I C4I C3I C2I C1I C0I W Reset 00000000 Figure 19-15. Timer Interrupt Enable Register (TIE) Table 19-14. TIE Field Descriptions Field Description 7:0 C[7:0]I Input Capture/Output Compare “x” Interrupt Enable 0 The corresponding flag is disabled from causing a hardware interrupt. 1 The corresponding flag is enabled to cause an interrupt.

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19.3.2.11 Timer System Control Register 2 (TSCR2)

Read or write: Anytime All bits reset to zero. Module Base + 0x000D 76543210 R TOI 000 TCRE PR2 PR1 PR0 W Reset 00000000 = Unimplemented or Reserved Figure 19-16. Timer System Control Register 2 (TSCR2)

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Figure 19-17. The TCNT cycle diagram under TCRE=1 condition Table 19-15. TSCR2 Field Descriptions Field Description TOI Timer Overflow Interrupt Enable 0 Timer overflow interrupt disabled. 1 Hardware interrupt requested when TOF flag set. TCRE Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful channel 7 output compare. This mode of operation is similar to an up-counting modulus counter. 0 Counter reset disabled and counter free runs. 1 Counter reset by a successful output compare on channel 7. Note: If register TC7 = 0x0000 and TCRE = 1, then the TCNT register will stay at 0x0000 continuously. If register TC7 = 0xFFFF and TCRE = 1, the TOF flag will never be set when TCNT is reset from 0xFFFF to 0x0000. Note: TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to 0, TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it will last only one bus cycle then reset to 0. for a more detail explanation please refer to Figure 19-17. Note: in Figure 19-17,if PR[2:0] is equal to 0, one prescaler counter equal to one bus clock 2:0 PR[2:0] Timer Prescaler Select— These three bits specify the division rate of the main Timer prescaler when the PRNT bit of register TSCR1 is set to 0. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. See Table 19-16. Table 19-16. Prescaler Selection PR2 PR1 PR0 Prescale Factor 000 1 001 2 010 4 011 8 100 1 6 101 3 2 110 6 4 1 1 1 128 TC7 0 1 ----- TC7-1 TC7 0 TC7 event TC7 event prescaler counter 1 bus clock

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19.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)

Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flags cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero. TFLG1 indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (reference TFFCA bit in Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”). Use of the TFMOD bit in the ICSYS register in conjunction with the use of the ICOVW register allows a timer interrupt to be generated after capturing two values in the capture and holding registers, instead of generating an interrupt for every capture.

19.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)

Read: Anytime Module Base + 0x000E 76543210 R C7F C6F C5F C4F C3F C2F C1F C0F W Reset 00000000 Figure 19-18. Main Timer Interrupt Flag 1 (TFLG1) Table 19-17. TFLG1 Field Descriptions Field Description 7:0 C[7:0]F Input Capture/Output Compare Channel “x” Flag — A CxF flag is set when a corresponding input capture or output compare is detected. C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be set by 8-bit pulse accumulators PAC3–PAC0. If the delay counter is enabled, the CxF flag will not be set until after the delay. Module Base + 0x000F 76543210 R TOF 0000000 W Reset 00000000 = Unimplemented or Reserved Figure 19-19. Main Timer Interrupt Flag 2 (TFLG2)

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Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flag cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero. TFLG2 indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”).

19.3.2.14 Timer Input Capture/Output Compare Registers 0–7

Table 19-18. TFLG2 Field Descriptions Field Description TOF Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Module Base + 0x0010 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 00000000 Figure 19-20. Timer Input Capture/Output Compare Register 0 High (TC0) Module Base + 0x0011 76543210 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W Reset 00000000 Figure 19-21. Timer Input Capture/Output Compare Register 0 Low (TC0) Module Base + 0x0012 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 00000000 Figure 19-22. Timer Input Capture/Output Compare Register 1 High (TC1)

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R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W Reset 00000000 Figure 19-29. Timer Input Capture/Output Compare Register 4 Low (TC4) Module Base + 0x001A 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 00000000 Figure 19-30. Timer Input Capture/Output Compare Register 5 High (TC5) Module Base + 0x001B 76543210 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W Reset 00000000 Figure 19-31. Timer Input Capture/Output Compare Register 5 Low (TC5) Module Base + 0x001C 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 00000000 Figure 19-32. Timer Input Capture/Output Compare Register 6 High (TC6) Module Base + 0x001D 76543210 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W Reset 00000000 Figure 19-33. Timer Input Capture/Output Compare Register 6 Low (TC6) Module Base + 0x001E 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 00000000 Figure 19-34. Timer Input Capture/Output Compare Register 7 High (TC7)

Chapter 19 Enhanced Capture Timer (ECT16B8CV3) MC9S12XHZ512 Data Sheet Rev. 1.06 Freescale Semiconductor 693 Read: Anytime Write anytime for output compare function. Writes to these registers have no meaning or effect during input capture. All bits reset to zero. Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. 19.3.2.15 16-Bit Pulse Accumulator A Control Register (PACTL) Read: Anytime Write: Anytime All bits reset to zero. Module Base + 0x001F 76543210 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W Reset 00000000 Figure 19-35. Timer Input Capture/Output Compare Register 7 Low (TC7) Module Base + 0x0020 76543210 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI W Reset 00000000 = Unimplemented or Reserved Figure 19-36. 16-Bit Pulse Accumulator Control Register (PACTL) Table 19-19. PACTL Field Descriptions Field Description PAEN Pulse Accumulator A System Enable — PAEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled. 0 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable bits in ICPAR are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled. 1 16-Bit Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and PACN2 registers contents are respectively the high and low byte of the PACA. PA3EN and PA2EN control bits in ICPAR have no effect. Pulse Accumulator Input Edge Flag (PAIF) function is enabled. The PACA shares the input pin with IC7. PAMOD Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1).

0 Event counter mode

1 Gated time accumulation mode

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Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). Refer toTable 19-20. For PAMOD bit = 0 (event counter mode).

0 Falling edges on IC7 pin cause the count to be incremented

1 Rising edges on IC7 pin cause the count to be incremented

For PAMOD bit = 1 (gated time accumulation mode). 0 IC7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on IC7 sets the PAIF flag. 1 IC7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on IC7 sets the PAIF flag. If the timer is not active (TEN = 0 in TSCR1), there is no divide-by-64 since the ÷64 clock is generated by the timer prescaler. 3:2 CLK[1:0] Clock Select Bits — For the description of PACLK please refer to Figure 19-72. If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. The change from one selected clock to the other happens immediately after these bits are written. Refer to Table 19-21. PAOVI Pulse Accumulator A Overflow Interrupt Enable

0 Interrupt inhibited

1 Interrupt requested if PAOVF is set

Pulse Accumulator Input Interrupt Enable

1 Interrupt requested if PAIF is set

Table 19-20. Pin Action PAMOD PEDGE Pin Action 0 0 Falling edge 0 1 Rising edge 1 0 Divide by 64 clock enabled with pin high level 1 1 Divide by 64 clock enabled with pin low level Table 19-21. Clock Selection CLK1 CLK0 Clock Source 0 0 Use timer prescaler clock as timer counter clock 0 1 Use PACLK as input to timer counter clock 1 0 Use PACLK/256 as timer counter clock frequency 1 1 Use PACLK/65536 as timer counter clock frequency Table 19-19. PACTL Field Descriptions (continued) Field Description

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