HCPL-0601 | DigiCamel IC Datasheet

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HCPL-0600_04 FAIRCHILD | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 13

Technical content

DESCRIPTION

The HCPL-0600/0601 optocouplers consist of an AlGaAS LED, optically coupled to a very high speed integrated photo-detector logic gate with a strobable output. The devices are housed in a compact small-outline package. This output features an open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40°C to +85°C. A maximum input signal of 5 mA will provide a minimum output sink current of 13 mA (fan out of 8). An internal noise shield provides superior common mode rejection of typically 10 kV/µs.

FEATURES

Compact SO8 package
Very high speed-10 MBit/s
Superior CMR-10 kV/µs
Fan-out of 8 over -40°C to +85°C
Logic gate output
Strobable output
Wired OR-open collector
U.L. recognized (File # E90700)

APPLICATIONS

Ground loop elimination
LSTTL to TTL, LSTTL or 5-volt CMOS
Line receiver, data transmission
Data multiplexing
Switching power supplies
Pulse transformer replacement
Computer-peripheral interface TRUTH TABLE (Positive Logic) A 0.1 µF bypass capacitor must be connected between pins 8 and 5. (See note 1) Input Enable Output HHL LHH HLH LLH HN CL LN CH NOTE All dimensions are in inches (millimeters) Lead Coplanarity : 0.004 (0.10) MAX 0.202 (5.13) Pin 1 0.019 (0.48) 0.182 (4.63) 0.021 (0.53) TYP 0.244 (6.19) 0.224 (5.69) 0.143 (3.63) 0.123 (3.13) 0.008 (0.20) 0.003 (0.08) 0.010 (0.25) 0.006 (0.16) SEATI NG PLANE 0.164 (4.16) 0.144 (3.66) 4 5 8N/C VCC VE VO GND N/C VF Single-channel circuit drawing

© 2004 Fairchild Semiconductor Corporation *6.3 mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value is 5.0 mA or less ABSOLUTE MAXIMUM RATINGS (No derating required up to 85°C) Parameter Symbol Value Units Storage Temperature T STG -40 to +125 °C Operating Temperature T OPR -40 to +85 °C Lead Solder Temperature T SOL 260 for 10 sec °C EMITTER DC/Average Forward Input Current I F 50 mA Enable Input Voltage Not to exceed VCC by more than 500 mV V E 5.5 V Reverse Input Voltage V R 5.0 V Power Dissipation P I 45 mW DETECTOR Supply Voltage V CC (1 minute max) 7.0 V Output Current I O 50 mA Output Voltage V O 7.0 V Collector Output Power Dissipation P O 85 mW RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Units Input Current, Low Level I FL 0 250 µA Input Current, High Level I FH *6.3 15 mA Supply Voltage, Output V CC 4.5 5.5 V Enable Voltage, Low Level V EL 0 0.8 V Enable Voltage, High Level V EH 2.0 V CC V Operating Temperature T A -40 +85 °C Fan Out (TTL load) N 8

ELECTRICAL CHARACTERISTICS

A = -40°C to +85°C Unless otherwise speciﬁed.) INDIVIDUAL COMPONENT CHARACTERISTICS Parameter Test Conditions Symbol Min Typ** Max Unit EMITTER F = 10 mA) V F

1.8 VInput Forward Voltage T

A =25°C 1.75 Input Reverse Breakdown Voltage (I R = 10 µA) B VR 5.0 V Input Capacitance (V F = 0, f = 1 MHz) C IN 60 pF Input Diode Temperature Coefﬁcient (I F = 10 mA) VF/ TA -1.4 mV/ °C DETECTOR High Level Supply Current (V CC = 5.5 V, I F = 0 mA) E = 0.5 V) I CCH 71 0 m A Low Level Supply Current (V CC = 5.5 V, I F = 10 mA) E = 0.5 V) I CCL 91 3 m A Low Level Enable Current (V CC = 5.5 V, V E = 0.5 V) I EL -0.8 -1.6 mA High Level Enable Current (V CC = 5.5 V, V E = 2.0 V) I EH -0.6 -1.6 mA High Level Enable Voltage (V CC = 5.5 V, I F = 10 mA) V EH 2.0 V Low Level Enable Voltage (V CC = 5.5 V, I F = 10 mA) (Note 2) V EL 0.8 V SWITCHING CHARACTERISTICS A = -40°C to +85°C, V CC = 5 V, I F = 7.5 mA Unless otherwise speciﬁed.) AC Characteristics Test Conditions Device Symbol Min Typ Max Unit Propagation Delay Time to Output High Level (Note 3) (T A =25°C) All T PLH 20 45 75 ns(R L = 350 Ω , C L = 15 pF) (Fig. 12) 100 Propagation Delay Time to Output Low Level (Note 4) (T A =25°C) All T PHL 25 45 75 ns(R L = 350 Ω , C L = 15 pF) (Fig. 12) 100 Pulse Width Distortion (R L = 350 Ω , C L = 15 pF) (Fig. 12) All |T PHL PLH | 3 35 ns Output Rise Time (10-90%) L = 350 Ω , C L = 15 pF) (Note 5) (Fig. 12) All t r 50 ns Output Fall Time (90-10%) L = 350 Ω , C L = 15 pF) (Note 6) (Fig. 12) All t f 12 ns Enable Propagation Delay Time to Output High Level F = 7.5 mA, V EH = 3.5 V) L = 350 Ω , C L = 15 pF) (Note 7) (Fig. 13) All t ELH 20 ns Enable Propagation Delay Time to Output Low Level F = 7.5 mA, V EH = 3.5 V) L = 350 Ω , C L = 15 pF) (Note 8) (Fig. 13) All t EHL 20 ns Common Mode Transient Immunity (at Output High Level) L = 350 Ω ) (T A =25°C) F = 0 mA, V OH (Min.) = 2.0 V) (Note 9)(Fig. 14) CM | = 10 V HCPL-0600 |CM H 10,000 V/µs|VCM | = 50 V HCPL-0601 5000 10,000 Common Mode Transient Immunity (at Output Low Level) (IF = 7.5 mA, VOL (Max.) = 0.8 V) (Note 10)(Fig. 14) |VCM | = 10 V HCPL-0600 |CM H | 10,000 V/µs|VCM | = 50 V HCPL-0601 5000 10,000

1/7/04Page 4 of 13© 2004 Fairchild Semiconductor Corporation All typical values are at VCC = 5 V, TA = 25°C 1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins of each device. 2. Enable Input - No pull up resistor required as the device has an internal pull up resistor. 3. t PLH - Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse. 4. tPHL - Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse. 5. tr - Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse. 6. tf - Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse. 7. tELH - Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse. 8. tEHL - Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse. 9. CM H - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., VOUT > 2.0 V). Measured in volts per microsecond (V/µs). 10. CML - The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state 11. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together. TRANSFER CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise speciﬁed.) DC Characteristics Test Conditions Symbol Min Typ Max Unit High Level Output Current (VCC = 5.5 V, VO = 5.5 V) (IF = 250 µA, VE = 2.0 V) (Note 2)IOH 100 µA Low Level Output Voltage (VCC = 5.5 V, IF = 5 mA) (VE = 2.0 V, IOL = 13 mA) (Note 2) VOL .35 0.6 V Input Threshold Current (VCC = 5.5 V, VO = 0.6 V, VE = 2.0 V, IOL = 13 mA) IFT 35 m A ISOLATION CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise speciﬁed.) Characteristics Test Conditions Symbol Min Typ** Max Unit Input-Output Insulation Leakage Current (Relative humidity = 45%) (TA = 25°C, t = 5 s) (VI-O = 3000 VDC) (Note 11) II-O 1.0* µA Withstand Insulation Test Voltage (RH < 50%, TA = 25°C) (Note 11) ( t = 1 min.)VISO 2500 V RMS Resistance (Input to Output) (V I-O = 500 V) (Note 11) RI-O 1012 Ω Capacitance (Input to Output) (f = 1 MHz) (Note 11) C I-O 0.6 pF NOTES

1/7/04Page 5 of 13© 2004 Fairchild Semiconductor Corporation HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 TYPICAL PERFORMANCE CURVES Fig. 1 Forward Current vs. Input Forward Voltage VF - FORWARD VOLTAGE (V) IF - FORWARD CURRENT (mA) Fig. 2 Output Voltage vs. Forward Current IOH - HIGH LEVEL OUTPUT CURRENT ( µA) ITH - INPUT THRESHOLD CURRENT (mA) Fig. 3 Input Threshold Current vs. Temperature TA - TEMPERATURE (˚C) TA - TEMPERATURE (˚C) Fig. 4 High Level Output Current vs. Temperature IF - FORWARD INPUT CURRENT (mA) V o - OUTPUT VOLTAGE (V) 0.001 0.01 0.1 100 TA = 85°C TA = 70°C TA = 25°C TA = 0°C TA = -40°C 012345 TA = 25¡C VCC = 5V RL = 350Ω RL = 1kΩ - 4 0 - 2 00 2 04 06 08 0 1 0 0 VCC = 5V VO = 0.6V RL = 350Ω RL = 1KΩ - 4 0 - 2 00 2 04 06 08 0 1 0 0 VO = VCC = 5.5V VE = 2V IF = 250 A

1/7/04Page 6 of 13© 2004 Fairchild Semiconductor Corporation Fig. 5 Low Level Output Voltage vs. Temperature TA - TEMPERATURE (˚C) TA - TEMPERATURE (˚C) TA - TEMPERATURE (˚C) V OL - LOW LEVEL OUTPUT VOLTAGE (V) TP - PROPAGATION DELAY (ns) Fig. 6 Low Level Output Current vs. Temperature IOL - LOW LEVEL OUTPUT CURRENT (mA) TP - PROPAGATION DELAY (ns) Fig. 7 Propagation Delay vs. Temperature Fig. 8 Propagation Delay vs. Pulse Input Current IF - PULSE INPUT CURRENT (mA) - 4 0 - 2 00 2 04 06 08 0 1 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 VCC = 5.5V VE = 2V IF = 5mA IO = 12.8mA IO = 9.6mA IO = 6.4mA IO = 16mA - 4 0 - 2 00 2 04 06 08 0 1 0 0 VCC = 5V VE = 2V VOL = 0.6V IF = 10-15mA IF = 5mA - 4 0 - 2 00 2 04 06 08 0 1 0 0 100 VCC = 5V IF = 7.5mA tPLH R L = 1kΩ tPLH R L = 350Ω tPHL RL = 350Ω & 1kΩ 5 7 9 11 13 15 VCC = 5V TA = 25°C tPLH R L = 1kΩ tPLH R L = 350Ω tPHL RL = 350Ω & 1kΩ

1/7/04Page 7 of 13© 2004 Fairchild Semiconductor Corporation HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 Fig. 9 Typical Enable Propagation Delay vs. Temparature TA - TEMPERATURE (˚C) T A - TEMPERATURE (˚C) TA - TEMPERATURE (˚C) tE - ENABLE PROPAGATION DELAY (ns) Fig. 10 Typical Rise and Fall Time vs. Temperature tf - FALL TIME (ns) Fig. 11 Typical Pulse Width Distortion vs. Temperature PWD - PULSE WIDTH DISTORTION (ns) - 4 0 - 2 00 2 04 06 08 0 1 0 0 VCC = 5V VEH = 3V VEL = 0V IF = 7.5mA tELH R L = 1kΩ tELH R L = 350Ω tEHL RL = 350Ω & 1kΩ - 4 0 - 2 00 2 04 06 08 0 1 0 0 120 160 200 240 VCC = 5V IF = 7.5mA tr R L = 1kΩ tr R L = 350Ω tf R L = 350Ω & 1kΩ - 4 0 - 2 00 2 04 06 08 0 1 0 0 VCC = 5V IF = 7.5mA R L = 1kΩ R L = 350Ω

1/7/04Page 8 of 13© 2004 Fairchild Semiconductor Corporation 47Ω PHLt FI = 7.5 mA 1.5 V 90% 10% 7.5 mA +5V 1.5 V 3.0 V 1.5 V 4 5 Pulse Generator tr = 5ns Z = 50Ω O +5V GND PLHt I = 3.75 mAF Output O(V ) Input (I )F Output (V )O ft rt CCV Output (V )O LR C L(I ) Input F Monitor OZ = 50Ω Pulse Gen erator tr = 5ns (V )E Input M onitor GND VCC O(V ) Output LR LC (V ) Output O Input (V )E EHLt ELH bypass .1 f bypass .1µf Fig. 12 Test Circuit and WTest C ircuit and WT aveform s for tPLH , tPHL , tr and tf. Fig. 13 Test Circuit tTest C ircuit tT EHL and tELH . t

1/7/04Page 9 of 13© 2004 Fairchild Semiconductor Corporation HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601 +5V Peak GND VCC O(V ) Output 350Ω VCM FFV A B Pulse Gen IF CMV OV Switching Pos. (A), I = 0F OV (Max) CM 0.5 V OV Switching Pos. (B), I = 7.5 mAF H CM L V (Min)O bypass .1µf Fig. 14 Test Circuit Common Mode TTest C ircuit C om m on M ode TT ransient Immunity

ORDERING INFORMATION

Identiﬁer R1 .R1 Tape and Reel (500 per Reel) R2 .R2 Tape and Reel (2500 per Reel) 43 5 Deﬁnitions

1 Fairchild logo

2 Device number

3 VDE mark (Note: Only appears on parts ordered with VDE

option – See order entry table) 4 One digit year code, e.g., ‘3’

5 Two digit work week ranging from ‘01’ to ‘53’

6 Assembly package code

0.3 MAX

8.3 ± 0.1 3.5 ± 0.2 0.1 MAX 6.4 ± 0.2 5.2 ± 0.2 Ø 1.5 + 0.1/-0 Ramp up = 2–10°C/sec • Peak reflow temperature: 245°C (package surface temperature)

Time of temperature higher than 183°C for 120–180 seconds
One time soldering reflow is recommended 230°C, 10–30 s Time (Minute) 300 250 200 150 100 Temperature (°C) Time above 183°C, 120–180 sec 245°C peak

FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 1/7/04Page 13 of 13© 2004 Fairchild Semiconductor Corporation HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS HCPL-0600 HCPL-0601

Product Information

HCPL-0601 specifications and overview.

Summary

HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS

Description

HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS

Source title HCPL-0601 Datasheet(PDF) - Fairchild Semiconductor

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