HCPL-2200 HP | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 11
Technical content
Features
- 2.5 kV/µs Minimum Common Mode Rejection (CMR) at V CM = 400 V (HCPL-2219)
- Compatible with LSTTL, TTL, and CMOS Logic
- Wide VCC Range (4.5 to 20 V)
- 2.5 Mbd Guaranteed over Temperature
- Low Input Current (1.6 mA)
- Three State Output (No Pullup Resistor Required)
- Guaranteed Performance from 0 °C to 85°C
- Hysteresis
- Safety Approval UL Recognized -2500 V rms for 1 minute CSA Approved VDE 0884 Approved with VIORM = 630 V peak (HCPL-2219 Option 060 Only)
- MIL-STD-1772 Version Available (HCPL-5200/1)
Applications
- Isolation of High Speed Logic Systems
- Computer-Peripheral Interfaces
- Microprocessor System Interfaces Functional Diagram
- Ground Loop Elimination
- Pulse Transformer Replacement
- Isolated Buss Driver
- High Speed Line Receiver
Description
optically coupled logic gates that combine a GaAsP LED and an integrated high gain photo detector. The detector has a three state output stage and has a detector threshold with hysteresis. The three state output eliminates the need for a pullup resistor and allows for direct drive of data busses. The hysteresis provides differential mode noise immunity and eliminates the potential for output signal chatter. A superior internal shield on the HCPL-2219 guarantees common mode transient immunity of 2.5 kV/µs at a common mode voltage of 400 volts. A 0.1 µF bypass capacitor must be connected between pins 5 and 8. 4 5 8NC ANODE CATHODE NC GND VCC VO SHIELD TRUTH TABLE (POSITIVE LOGIC) LED ON OFF ON OFF ENABLE H H L L VE OUTPUT Z Z H L 5965-3596E H
The Electrical and Switching Characteristics of the HCPL- 2200/2219 are guaranteed over the temperature range of 0°C to 85°C and a V CC range of 4.5 volts to 20 volts. Low IF and wide VCC range allow compatibility with TTL, LSTTL, and CMOS logic and result in lower power consump- tion compared to other high speed optocouplers. Logic signals are transmitted with a typical propagation delay of 160 nsec. Selection Guide Small-Outline Widebody Minimum CMR 8-Pin DIP (300 Mil) SO-8 (400 Mil) Hermetic Input On- Single Dual Single Single Single and Dual dV/dt V CM Current Channel Channel Channel Channel Channel (V/µs) (V) (mA) Package Package Package Package Packages 1,000 50 1.6 HCPL-2200 [1] HCPL-0201 HCNW2201 HCPL-2201 HCPL-2202
1.8 HCPL-2231
2,500 400 1.6 HCPL-2219 [1] 5,000[2] 300[2] 1.6 HCPL-2211 HCPL-0211 HCNW2211 HCPL-2212
1.8 HCPL-2232
1,000 50 2.0 HCPL-52XX HCPL-62XX Notes: 1. HCPL-2200/2219 devices include output enable/disable functionality. 2. Minimum CMR of 10 kV/ µs with VCM = 1000 V can be achieved with input current, I F, of 5 mA.
Ordering Information
Specify Part Number followed by Option Number (if desired). Example: HCPL-2219#XXX 060 = VDE 0884 VIORM = 630 Vpeak Option* 300 = Gull Wing Surface Mount Option 500 = Tape and Reel Packaging Option Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for information. *For HCPL-2219 only. Schematic The HCPL-2200/2219 are useful for isolating high speed logic interfaces, buffering of input and output lines, and implementing isolated line receivers in high noise environments.
1.080 ± 0.320 (0.043 ± 0.013) 2.54 ± 0.25 (0.100 ± 0.010) 0.51 (0.020) MIN. 0.65 (0.025) MAX. 4.70 (0.185) MAX. 2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED. 5° TYP. 0.254+ 0.076 - 0.051 (0.010+ 0.003) - 0.002) 7.62 ± 0.25 (0.300 ± 0.010) 6.35 ± 0.25 (0.250 ± 0.010) 9.65 ± 0.25 (0.380 ± 0.010) HP XXXXZ YYWW DATE CODE 5678 4321 OPTION CODE* UL RECOGNITION UR TYPE NUMBER Package Outline Drawings 8-Pin DIP Package 8-Pin DIP Package with Gull Wing Surface Mount Option 300 0.635 ± 0.25 (0.025 ± 0.010) 12° NOM. 9.65 ± 0.25 (0.380 ± 0.010) 0.635 ± 0.130 (0.025 ± 0.005) 7.62 ± 0.25 (0.300 ± 0.010) 5678 4321 9.65 ± 0.25 (0.380 ± 0.010) 6.350 ± 0.25 (0.250 ± 0.010) 1.016 (0.040) 1.194 (0.047) 1.194 (0.047) 1.778 (0.070) 9.398 (0.370) 9.906 (0.390) 4.826 (0.190) TYP. 0.381 (0.015) 0.635 (0.025) PAD LOCATION (FOR REFERENCE ONLY) 1.080 ± 0.320 (0.043 ± 0.013) 4.19 (0.165)MAX. 1.780 (0.070) MAX.1.19 (0.047) MAX. 2.54 (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). 0.254+ 0.076 - 0.051 (0.010+ 0.003) - 0.002)
Note: Use of nonchlorine activated fluxes is highly recommended. Maximum Solder Reflow Thermal Profile 240 ΔT = 115°C, 0.3°C/SEC ΔT = 100°C, 1.5°C/SEC ΔT = 145°C, 1°C/SEC TIME – MINUTES TEMPERATURE – °C 220 200 180 160 140 120 100 260 12 3 456789 1 0 1 1 1 2 Regulatory Information The HCPL-2200/2219 have been approved by the following organizations: UL Recognized under UL 1577, Component Recognition Program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. VDE Approved according to VDE 0884/06.92. (HCPL-2219 Option
060 Only)
Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Min. External Air Gap L(IO1) 7.1 mm Measured from input terminals to output terminals, (External Clearance) shortest distance through air. Min. External L(IO2) 7.4 mm Measured from input terminals to output terminals, Tracking Path shortest distance path along body. (External Creepage) Minimum Internal 0.08 mm Through insulation distance, conductor to conductor, Plastic Gap usually the direct distance between the photoemitter (Internal Clearance) and photodetector inside the optocoupler cavity. Tracking Resistance CTI 200 V DIN IEC 112/VDE 0303 Part 1 (Comparative Tracking Index) Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 - surface mount classification is Class A in accordance with CECC 00802.
VDE 0884 Insulation Related Characteristics (HCPL-2219 OPTION 060 ONLY) Description Symbol Characteristic Units Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 300 V rms I-IV for rated mains voltage ≤ 450 V rms I-III Climatic Classification 55/85/21 Pollution Degree (DIN VDE 0110/1.89) 2 Maximum Working Insulation Voltage V IORM 630 V peak Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with t m = 1 sec, V PR 1181 V peak Partial Discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and sample test, V PR 945 V peak tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage, tini = 10 sec) V IOTM 6000 V peak Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure 12, Thermal Derating curve.) Case Temperature T S 175 °C Input Current I S,INPUT 230 mA Output Power P S,OUTPUT 600 mW Insulation Resistance at TS, VIO = 500 V R S ≥ 109 Ω *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, (VDE 0884), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply Voltage V CC 4.5 20 V Enable Voltage High V EH 2.0 20 V Enable Voltage Low V EL 0 0.8 V Forward Input Current I F(ON) 1.6* 5 mA Forward Input Current I F(OFF) – 0.1 mA Operating Temperature T A 08 5 [1] °C Fan Out N 4 TTL Loads *The initial switching threshold is 1.6 mA or less. It is recommended that 2.2 mA be used to permit at least a 20% CTR degradation guardband. Absolute Maximum Ratings (No Derating Required up to 70 °C) Parameter Symbol Min. Max. Units Note Storage Temperature T S -55 125 °C Operating Temperature T A -40 85 °C1 Average Forward Input Current I F(AVG) 10 mA Peak Transient Input Current I F(TRAN) 1.0 A (≤ 1 µs Pulse Width, 300 pps) Reverse Input Voltage V R 5V Average Output Current I O 25 mA Supply Voltage V CC 02 0 V Three State Enable Voltage V E -0.5 20 V Output Voltage V O -0.5 20 V Total Package Power Dissipation P T 210 mW 1 Lead Solder Temperature 260 °C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings section
For 0°C ≤ TA[1] ≤ 85°C, 4.5 V ≤ VCC ≤ 20 V, 1.6 mA ≤ IF(ON) ≤ 5 mA, 2.0 V ≤ VEH ≤ 20 V , 0.0 V ≤ VEL ≤ 0.8 V , 0 mA ≤ IF(OFF) ≤ 0.1 mA. All Typicals at TA = 25°C, VCC = 5 V, IF(ON) = 3 mA unless otherwise specified. See Note 7 . Logic Low V OL 0.5 V I OL = 6.4 mA (4 TTL Loads) 1 Output Voltage Logic High V OH 2.4 * V I OH = -2.6 mA *V OH = VCC - 2.1 V 2 Output Voltage Output Leakage I OHH 100 µAV O = 5.5 V I F = 5 mA Current (VOUT > VCC)V CC = 4.5 V Logic High Enable V EH 2.0 V Voltage Logic Low Enable V EL 0.8 V Voltage Logic High Enable I EH 20 µAV EN = 2.7 V Current Logic Low Enable I EL -0.32 mA V EN = 0.4 V Current Logic Low Supply I CCL IF = 0 mA Current I O = Open VE = Don’t Care Logic High Supply I CCH IF = 5 mA Current I O = Open VE = Don’t Care High Impedance I OZL -20 µAV O = 0.4 V V EN = 2 V, IF = 5 mA IOZH 20 µAV O = 2.4 V V EN = 2 V, 100 µAV O = 5.5 V 500 µAV O = 20 V Logic Low Short I OSL 2 Circuit Output Current Logic High Short I OSH IF = 5 mA, 2 Circuit Output V O = GND Current Input Current I HYS 0.12 mA V CC = 5 V 3 Hysteresis Input Forward V F 1.5 1.7 V T A = 25°CI F = 5 mA 4 1.75 Input Reverse BV R 5V I R = 10 µA Breakdown Voltage Input Diode Δ VF -1.7 mV/ °CI F = 5 mA Temperature Δ TA Coefficient Input Capacitance C IN 60 pF f = 1 MHz, V F = 0 V, Pins 2 and 3 mA V O = VCC = 5.5 V I F = 0 mA25 500 µA V O = 20 V 100 µAV EN = 5.5 V 250 µAV EN = 20 V0.004 6.0 mA V CC = 5.5 V4.5 5.25 6.0 mA V CC = 20 V 4.5 mA V CC = 5.5 V2.7 3.1 State Output Current mA V O = VCC = 20 V40 mA V CC = 5.5 V-10 mA V CC = 20 V-25 Voltage 7.5 mA V CC = 20 V IF = 5 mA
Switching Specifications (AC) All Typicals at TA = 25°C, VCC = 5 V, IF(ON) = 3 mA unless otherwise specified. Propagation Delay Time to t PHL 210 ns Without Peaking Capacitor 5, 6 4, 5 160 300 With Peaking Capacitor Propagation Delay Time to t PLH 170 ns Without Peaking Capacitor 5, 6 4, 5 115 300 With Peaking Capacitor Output Enable Time to t PZH 25 ns 7, 9 Logic High Output Enable Time to t PZL 28 ns 7, 8 Logic Low Output Disable Time from t PHZ 105 ns 7, 9 Logic High Output Disable Time from t PLZ 60 ns 7, 8 Logic Low Output Rise Time (10-90%) t r 55 ns 5, 10 Output Fall Time (90-10%) t f 15 ns 5, 10 Parameter Sym. Device Min. Units Test Conditions Fig. Note Logic High |CM H|I F = 1.6 mA 11 6 Common Mode V CC = 5 V Transient T A = 25°C Immunity Logic Low |CM L|V F = 0 V 11 6 Common Mode V CC = 5 V Transient T A = 25°C Immunity Logic Low Output Level Logic High Output Level HCPL-2200 1,000 V/ µs| V CM| = 50 V HCPL-2219 2,500 V/ µs| V CM| = 400 V HCPL-2200 1,000 V/ µs| V CM| = 50 V HCPL-2219 2,500 V/ µs| V CM| = 400 V Package Characteristics Input-Output Momentary V ISO 2500 V rms RH ≤ 50%, t = 1 min., 3, 8 Withstand Voltage* T A = 25°C Input-Output Resistance R I-O 1012 Ω VI-O = 500 VDC 3 Input-Output Capacitance C I-O 0.6 pF f = 1 MHz, V I-O = 0 VDC 3 *The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number 5963-2203E.
Figure 2. Typical Logic High Output Figure 3. Output Voltage vs. Forward Figure 4. Typical Input Diode Forward Figure 1. Typical Logic Low Output
- Derate total package power dissipa-
temperature at a rate of 4.5 mW/ °C.
- Duration of output short circuit time
- Device considered a two-terminal
1.3 V point on the leading edge of the
- When the peaking capacitor is omitted,
logic high state (V O > 2.0 V).
- Use of a 0.1 µF bypass capacitor
- In accordance with UL1577, each
Characteristics Table, if applicable. Figure 5. Test Circuit for t ALL DIODES ARE 1N916 OR 1N3064.