HCNW137

HCPL-2602 HP | Alldatasheet

Document overview

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Technical content

Features

• 1000 V/µs Minimum Common Mode Rejection (CMR) at V CM = 50 V for HCPL-2602 and 3.5 kV/µs Minimum CMR at VCM = 300 V for HCPL-2612
• Line Termination Included – No Extra Circuitry Required
• Accepts a Broad Range of Drive Conditions
• LED Protection Minimizes LED Efficiency Degradation
• High Speed: 10 MBd (Limited by Transmission Line in Many Applications)
• Guaranteed AC and DC Performance over Temperature: 0 °C to 70°C
• External Base Lead Allows “LED Peaking” and LED Current Adjustment
• Safety Approval UL Recognized – 2500 V rms for 1 Minute CSA Approved
• MIL-STD-1772 Version Available (HCPL-1930/1) A 0.1 µF bypass capacitor must be connected between pins 5 and 8.

Applications

• Isolated Line Receiver
• Computer-Peripheral Interface
• Microprocessor System Interface
• Digital Isolation for A/D, D/A Conversion
• Current Sensing
• Instrument Input/Output Isolation
• Ground Loop Elimination
• Pulse Transformer Replacement
• Power Transistor Isolation in Motor Drives

Description

The HCPL-2602/12 are optically coupled line receivers that combine a GaAsP light emitting diode, an input current regulator and an integrated high gain photo detector. The input regulator serves as a line termination for line receiver applications. It clamps the line voltage and regulates the LED current so line reflections do not interfere with circuit performance. The regulator allows a typical LED current of 8.5 mA before it starts to shunt excess current. The output of the detector IC is IN– IN+ GND V VCC O VE NC CATHODE LED ON OFF ON OFF ON OFF ENABLE H H L L NC NC OUTPUT L H H H L H TRUTH TABLE (POSITIVE LOGIC) SHIELD 5965-3585E

Minimum CMR 8-Pin DIP (300 Mil) Small-Outline SO-8 (400 Mil) Hermetic On- Single Dual Single Dual Single Single and dV/dt V CM Current Output Channel Channel Channel Channel Channel Dual Channel (V/µs) (V) (mA) Enable Package Package Package Package Package Packages NA NA 5 YES 6N137 HCPL-0600 HCNW137 NO HCPL-2630 HCPL-0630 5,000 50 YES HCPL-2601 HCPL-0601 HCNW2601 NO HCPL-2631 HCPL-0631 10,000 1,000 YES HCPL-2611 HCPL-0611 HCNW2611 NO HCPL-4661 HCPL-0661 1,000 50 YES HCPL-2602 [1] 3,500 300 YES HCPL-2612 [1] 1,000 50 3 YES HCPL-261A HCPL-061A NO HCPL-263A HCPL-063A 1,000[2] 1,000 YES HCPL-261N HCPL-061N NO HCPL-263N HCPL-063N 1,000 50 12.5 [3] HCPL-193X HCPL-56XX HCPL-66XX Notes: 1. HCPL-2602/2612 devices include input current regulator. 2. 15 kV/µs with VCM = 1 kV can be achieved using HP application circuit. 3. Enable is available for single channel products only, except for HCPL-193X devices. an open collector Schottky clamped transistor. An enable input gates the detector. The internal detector shield provides a guaranteed common mode transient immunity specification of 1000 V/µs for the 2602, and 3500 V/µs for the 2612. DC specifications are defined similar to TTL logic. The optocoupler ac and dc operational parameters are guaranteed from 0°C to 70°C allowing trouble-free interfacing with digital logic circuits. An input current of 5 mA will sink an eight gate fan-out (TTL) at the output. The HCPL-2602/12 are useful as line receivers in high noise environments that conventional line receivers cannot tolerate. The higher LED threshold voltage provides improved immunity to differential noise and the internally shielded detector provides orders of magnitude improvement in common mode rejection with little or no sacrifice in speed. Input

Ordering Information

Specify Part Number followed by Option Number (if desired). Example: HCPL-2602#XXX 300 = Gull Wing Surface Mount Option 500 = Tape and Reel Packaging Option Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for information. Schematic SHIELD VI USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND 8 IS REQUIRED (SEE NOTE 1). IF ICC VCC VO GND IO VE IE II 90 Ω

8-Pin DIP Package with Gull Wing Surface Mount Option 300 8-Pin DIP Package Package Outline Drawings 9.65 ± 0.25 (0.380 ± 0.010) HP XXXX YYWW DATE CODE 1.080 ± 0.320 (0.043 ± 0.013) 2.54 ± 0.25 (0.100 ± 0.010) 0.51 (0.020) MIN. 0.65 (0.025) MAX. 4.70 (0.185) MAX. 2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). 5678 4321 5° TYP. TYPE NUMBER UL RECOGNITION UR 0.254+ 0.076 - 0.051 (0.010+ 0.003) - 0.002) 7.62 ± 0.25 (0.300 ± 0.010) 6.35 ± 0.25 (0.250 ± 0.010) 0.635 ± 0.25 (0.025 ± 0.010) 12° NOM. 9.65 ± 0.25 (0.380 ± 0.010) 0.635 ± 0.130 (0.025 ± 0.005) 7.62 ± 0.25 (0.300 ± 0.010) 5678 4321 9.65 ± 0.25 (0.380 ± 0.010) 6.350 ± 0.25 (0.250 ± 0.010) 1.016 (0.040) 1.194 (0.047) 1.194 (0.047) 1.778 (0.070) 9.398 (0.370) 9.906 (0.390) 4.826 (0.190) TYP. 0.381 (0.015) 0.635 (0.025) PAD LOCATION (FOR REFERENCE ONLY) 1.080 ± 0.320 (0.043 ± 0.013) 4.19 (0.165)MAX. 1.780 (0.070) MAX.1.19 (0.047) MAX. 2.54 (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). 0.254+ 0.076 - 0.051 (0.010+ 0.003) - 0.002)

Note: Use of nonchlorine activated fluxes is highly recommended. 240 ΔT = 115°C, 0.3°C/SEC ΔT = 100°C, 1.5°C/SEC ΔT = 145°C, 1°C/SEC TIME – MINUTES TEMPERATURE – °C 220 200 180 160 140 120 100 260 12 3 456789 1 0 1 1 1 2 Solder Reflow Temperature Profile (Gull Wing Surface Mount Option 300 Parts) Regulatory Information The HCPL-2602/2612 have been approved by the following organizations: UL Recognized under UL 1577, Component Recognition Program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Min. External Air Gap L(I01) 7.1 mm Measured from input terminals to output terminals, (External Clearance) shortest distance through air. Min. External Tracking L(I02) 7.4 mm Measured from input terminals to output terminals, Path (External Creepage) shortest distance path along body. Min. Internal Plastic 0.08 mm Through insulation distance, conductor to conductor, Gap (Internal Clearance) usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Tracking Resistance CTI 200 V DIN IEC 112/VDE 0303 Part 1 (Comparative Tracking Index) Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 - surface mount classification is Class A in accordance with CECC 00802.

Recommended Operating Conditions Parameter Symbol Min. Max. Units Input Current, Low Level I IL 0 250 µA Input Current, High Level I IH 5* 60 mA Supply Voltage, Output V CC 4.5 5.5 V High Level Enable Voltage V EH 2.0 V CC V Low Level Enable Voltage V EL 0 0.8 V Fan Out (@ RL = 1 kΩ ) N 5 TTL Loads Output Pull-up Resistor R L 330 4 K Ω Operating Temperature T A 07 0 °C *The initial switching threshold is 5 mA or less. It is recommended that an input current between 6.3 mA and 10 mA be used to obtain best performance and to provide at least 20% LED degradation guardband. Absolute Maximum Ratings (No Derating Required up to 85 °C) Parameter Symbol Min. Max. Units Storage Temperature T S -55 125 °C Operating Temperature T A -40 85 °C Forward Input Current I I 60 mA Reverse Input Current I IR 60 mA Input Current, Pin 4 -10 10 mA Supply Voltage (1 Minute Maximum) V CC 7V Enable Input Voltage (Not to Exceed VCC by V E VCC + 0.5 V more than 500 mV) Output Collector Current I O 50 mA Output Collector Voltage (Selection for Higher V O 7V Output Voltages up to 20 V is Available.) Output Collector Power Dissipation P O 40 mW Lead Solder Temperature T LS 260°C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings section

Electrical Characteristics

Over recommended temperature (TA = 0°C to +70°C) unless otherwise specified. See note 1. High Level Output I OH 5.5 100 µAV CC = 5.5 V, VO = 5.5 V, 1 Current I I = 250 µA, VE = 2.0 V Low Level Output V OL 0.35 0.6 V V CC = 5.5 V, II = 5 mA, 2, 4, Voltage V E = 2.0 V, 5, 14 IOL (Sinking) = 13 mA High Level Supply I CCH 7.5 10 mA V CC = 5.5 V, II = 0 mA, Current V E = 0.5 V Low Level Supply I CCL 10 13 mA V CC = 5.5 V, II = 60 mA, Current V E = 0.5 V High Level Enable I EH -0.7 -1.6 mA V CC = 5.5 V, VE = 2.0 V Current Low Level Enable I EL -0.9 -1.6 mA V CC = 5.5 V, VE = 0.5 V Current High Level Enable V EH 2.0 V 10 Voltage Low Level Enable V EL 0.8 V Voltage 2.0 2.4 I I = 5 mA Input Voltage V I V3 2.3 2.7 I I = 60 mA Input Reverse V R 0.75 0.95 V I R = 5 mA Voltage Input Capacitance C IN 90 pF V I = 0 V, f = 1 MHz *All typicals at VCC = 5 V, TA = 25°C.

Over recommended temperature (TA = 0°C to +70°C), VCC = 5 V, II = 7.5 mA, unless otherwise specified. Parameter Symbol Device Min. Typ.* Max. Units Test Conditions Fig. Note Propagation Delay 75 ns T A = 25°C Time to High Output t PLH 20 48 6, 7, 8 3 Level 100 ns Propagation Delay 75 ns T A = 25°C Time to Low Output t PHL 25 50 6, 7, 8 4 Level 100 ns RL = 350 Ω Pulse Width |t PHL-tPLH| 3.5 35 ns C L = 15 pF 9 13 Distortion Propagation Delay t PSK 40 ns 12, Skew 13 Output Rise Time t r 24 ns 12 (10-90%) Output Fall Time t f 10 ns 12 (90-10%) Propagation Delay t ELH 30 ns R L = 350 Ω , CL = 15 pF, Time of Enable from V EL = 0 V, VEH = 3 V 10, 11 5 VEH to VEL Propagation Delay t EHL 20 ns R L = 350 Ω , CL = 15 pF, Time of Enable from V EL = 0 V, VEH = 3 V 10, 11 6 VEL to VEH Common Mode HCPL-2602 1000 10,000 V CM = 50 V V O(MIN) = 2 V, Transient |CM H|V / µsR L = 350 Ω, 13 7, 9, Immunity at High HCPL-2612 3500 15,000 V CM = 300 V I I = 0 mA, 10 Output Level TA = 25°C Common Mode HCPL-2602 1000 10,000 V CM = 50 V V O(MAX) = 0.8 V, Transient |CM L|V / µsR L = 350 Ω, 13 8, 9 Immunity at Low HCPL-2612 3500 15,000 V CM = 300 V I I = 7.5 mA, 10 Output Level TA = 25°C *All typicals at VCC = 5 V, TA = 25°C. Package Characteristics All Typicals at TA = 25°C Input-Output Momentary V ISO 2500 V rms RH ≤ 50%, t = 1 min., 2, 11 Withstand Voltage* TA = 25°C Input-Output Resistance R I-O 1012 Ω VI-O = 500 Vdc 2 Input-Output Capacitance C I-O 0.6 pF f = 1 MHz 2 *The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”

Figure 13. Test Circuit for Common Mode Transient Immunity and Typical Figure 12. Typical Rise and Fall Time

1 CCV

0 V SWITCH AT A: I = 0 mAI

Figure 15. Recommended Printed Circuit Board Layout. Figure 14. Typical Input Threshold

1 R L = 4 kΩ

The primary objectives to fulfill when connecting an optocoupler to a transmission line are to provide a minimum, but not excessive, LED current and to properly terminate the line. The internal regulator in the HCPL- 2602/12 simplifies this task. Excess current from variable drive conditions such as line length variations, line driver differences, and power supply fluctuations are shunted by the regulator. In fact, with the LED current regulated, the line current can be increased to improve the immunity of the system to differential-mode-noise and to enhance the data rate capability. The designer must keep in mind the 60 mA input current maximum rating of the HCPL-2602/12 in such cases, and may need to use series limiting or shunting to prevent overstress. Design of the termination circuit is also simplified; in most cases the transmission line can simply be connected directly to the input terminals of the HCPL-2602/12 without the need for additional series or shunt resistors. If reversing line drive is used it may be desirable to use two HCPL- 2602/12 or an external Schottky diode to optimize data rate. Polarity Non-Reversing Drive High data rates can be obtained with the HCPL-2602/12 with polarity non-reversing drive. Figure (a) illustrates how a 74S140 line driver can be used with the HCPL-2602/12 and shielded, twisted pair or coax cable without any additional components. There are some reflections due to the “active termination,” but they do not interfere with circuit performance because the regulator clamps the line voltage. At longer line lengths, t PLH increases faster than tPHL since the switching threshold is not exactly halfway between asymptotic line conditions. If optimum data rate is desired, a series resistor and peaking capacitor can be used to equalize t PLH and tPHL. In general, the peaking capacitance should be as large as possible; however, if it is too large it may keep the regulator from achieving turn-off during the negative (or zero) excursions of the input signal. A safe rule: make C ≤ 16t where: C = peaking capacitance in picofarads t = data bit interval in nanoseconds Polarity Reversing Drive A single HCPL-2602/12 can also be used with polarity reversing drive (Figure b). Current reversal is obtained by way of the substrate isolation diode (substrate to collector). Some reduction of data rate occurs, however, because the substrate diode stores charge, which must be removed when the current changes to the forward direction. The effect of this is a longer t PHL. This effect can be eliminated and data rate improved considerably by use of a Schottky diode on the input of the HCPL-2602/12. For optimum noise rejection as well as balanced delays, a split- phase termination should be used along with a flip-flop at the output (Figure c). The result of current reversal in split-phase operation is seen in Figure (c) with switches A and B both OPEN. The coupler inputs are then connected in ANTI-SERIES; however, because of the higher steady-state termination voltage, in comparison to the single HCPL-2602/12 termination, the forward current in the substrate diode is lower and consequently there is less junction charge to deal with when switching. Closing switch B with A open is done mainly to enhance common mode rejection, but also reduces propagation delay slightly because line-to-line capacitance offers a slight peaking effect. With switches A and B both CLOSED, the shield acts as a current return path which prevents either input substrate diode from becoming reversed biased. Thus the data rate is optimized as shown in Figure (c). Improved Noise Rejection Use of additional logic at the output of two HCPL-2602/12s, operated in the split phase termination, will greatly improve system noise rejection in addition to balancing propagation delays as discussed earlier. A NAND flip-flop offers infinite common mode rejection (CMR) for NEGATIVELY sloped common mode transients but requires t PHL > tPLH for proper operation. A NOR flip-flop has infinite CMR for POSITIVELY sloped transients but requires t PHL < tPLH for proper operation. An exclusive-OR flip- flop has infinite CMR for common mode transients of EITHER polarity and operates with either t PHL >t PLH or tPHL <t PLH. With the line driver and transmission line shown in Figure (c), t PHL > tPLH, so NAND gates are preferred in the R-S flip-flop. A higher drive amplitude or

Figure b. Polarity Reversing, Single Ended. Figure a. Polarity Non-Reversing. Figure c. Polarity Reversing, Split Phase. Figure d. Flip-Flop Configurations. < 1 < 1

different circuit configuration could make tPHL <t PLH, in which case NOR gates would be pre- ferred. If it is not known whether t PHL > tPLH or tPHL < tPLH, or if the drive conditions may vary over the boundary for these conditions, the exclusive-OR flip-flop of Figure (d) should be used. RS-422 and RS-423 Line drivers designed for RS-422 and RS-423 generally provide adequate voltage and current for operating the HCPL-2602/12. Most drivers also have characteristics allowing the HCPL-2602/12 to be connected directly to the driver terminals. Worst case drive conditions, however, would require current shunting to prevent overstress of the HCPL-2602/12. Propagation Delay, Pulse- Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propaga- tion delay from low to high (t PLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 6). Pulse-width distortion (PWD) results when t PLH and tPHL differ in value. PWD is defined as the difference between t PLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, t PSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t PLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 16, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, t PSK is the difference between the shortest propagation delay, either t PHL or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 17 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 17 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The t PSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulse-width distortion and propagation delay skew over the recommended temperature, input current, and power supply ranges.