HCF1305-2R2-R

MIC24054 MICROCHIP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 39

Technical content

Features

• HyperLight Load® Efficiency: Up to 80% at 10 mA
• Hyper Speed Control® architecture enables - High Delta V Operation (VIN = 19V and VOUT = 0.8V) - Small Output Capacitance
• Input Voltage Range: 4.5V to 19V
• Output Current Up to 9A
• Up to 95% Efficiency
• Adjustable Output Voltage from 0.8V to 5.5V
• ±1% FB Accuracy
• Any Capacitor™ stable: Zero-to-High ESR
• 600 kHz Switching Frequency
• Power Good (PG) Output
• Foldback Current-Limit and “Hiccup” Mode Short-Circuit Protection
• Safe Start-Up into Pre-Biased Loads
• –40°C to +125°C Junction Temperature Range
• Available in a 28-lead 5 mm x 6 mm VQFN Package

Applications

• Servers and Work Stations
• Routers, Switches, and Telecom Equipment
• Base Stations General Description The MIC24054 is a constant-frequency, synchronous DC/DC buck regulator that features adaptive on-time control architecture. The MIC24054 operates over a supply range of 4.5V to 19V. It has an internal linear regulator that provides a regulated 5V to power the internal control circuitry. The MIC24054 operates at a constant 600 kHz switching frequency in continuous conduction mode and can be used to provide up to 9A of output current. The output voltage is adjustable down to 0.8V. Microchip’s HyperLight Load ® architecture provides the same high-efficiency and ultra-fast transient response as the Hyper Speed Control ® architecture under medium to heavy loads, but also maintains high efficiency under light load conditions by transitioning to variable frequency, discontinuous mode operation. The MIC24054 offers a full suite of protection features to ensure protection of the IC during fault conditions. These include undervoltage lockout to ensure proper operation under power-sag conditions, thermal shutdown, internal soft-start to reduce the inrush current, foldback current limit and “hiccup mode” short-circuit protection. The MIC24054 includes a power good (PG) output to allow simple sequencing. The 9A Hyper Speed Control part, MIC24053, is also available from Microchip. Package Type MIC24054 28-Lead VQFN (JL) (Top View) 12V , 9A High-Efficiency SuperSwitcher™ II Buck Regulator

DS20007043B-page 2  2025-2026 Microchip Technology Inc. and its subsidiaries Typical Application Circuit Functional Block Diagram Efficiency (VIN = 12V) vs. Output Current 100 02468 1 0 EFFICIENCY (%) OUTPUT CURRENT (A) 0.8V 0.9V 1V 1.2V 1.5V 1.8V 2.5V 3.3V

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 3 MIC24054

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † Operating Ratings ‡ † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. ‡ Notice: The device is not guaranteed to function outside its operating ratings. Note 1: Device is ESD sensitive. Handling precautions are recommended. Human body model, 1.5 kΩ in series with 100 pF. 2: PD(MAX) = (TJ(MAX) – TA)/θJA, where θJA depends upon the printed circuit layout. A 5 square inch 4 layer, 0.62”, FR-4 PCB with 2 oz. finish copper weight per layer is used for the θJA.

ELECTRICAL CHARACTERISTICS

PVIN = VIN = VEN = 12V, VBST – VSW = 5V; TA = +25°C, unless otherwise noted. Bold values valid for –40°C ≤ TJ ≤ +125°C. Note 1 Parameter Min. Typ. Max. Units Conditions Power Supply Input Input Voltage Range (VIN, PVIN) 4.5 — 19 V — Quiescent Supply Current — 450 750 µA V FB = 1.5V (non-switching) Shutdown Supply Current — 5 10 µA V EN = 0V VDD Supply Voltage VDD Output Voltage 4.8 5 5.4 V V IN = 7V to 19V, IDD = 25 mA VDD UVLO Threshold 3.7 4.2 4.5 V VDD Rising VDD UVLO Hysteresis — 400 — mV — Dropout Voltage (VIN – VDD) — 380 600 mV I DD = 25 mA DC/DC Controller Output Voltage Adjust Range (VOUT) 0.8 — 5.5 V — Reference Feedback Reference Voltage 0.792 0.8 0.808 V 0°C ≤ TJ ≤ +85°C (±1.0%) Load Regulation — 0.25 — % I OUT = 3A to 9A (Continuous Mode) Line Regulation — 0.25 — % V IN = 4.5V to 19V

DS20007043B-page 4  2025-2026 Microchip Technology Inc. and its subsidiaries FB Bias Current — 50 500 nA V FB = 0.8V Enable Control EN Logic Level High 1.8 — — V — EN Logic Level Low — — 0.6 V — EN Bias Current — 6 30 µA V EN = 12V Oscillator Switching Frequency 450 600 750 kHz Note 2, VOUT = 2.5V Maximum Duty Cycle — 82 — % Note 3, VFB = 0V Minimum Duty Cycle — 0 — % V FB = 1.0V Minimum Off-Time — 300 — ns — Soft-Start Soft-Start Time — 3 — ms — Short-Circuit Protection Current-Limit Threshold 12.5 21 25 A VFB = 0.8V, TJ = +25°C 11.25 21 25 VFB = 0.8V, TJ = +125°C Short-Circuit Current — 8 — A V FB = 0V Internal FETs Top-MOSFET RDS(ON) — 20.6 — mΩ I SW = 3A Bottom-MOSFET RDS(ON) — 7.5 — mΩ I SW = 3A SW Leakage Current — — 60 µA V EN = 0V VIN Leakage Current — — 25 µA V EN = 0V Power Good (PG) PG Threshold Voltage 85 92 95 %VOUT Sweep VFB from Low to High PG Hysteresis — 5.5 — %V OUT Sweep VFB from High to Low PG Delay Time — 100 — µs Sweep V FB from Low to High PG Low Voltage — 70 200 mV Sweep V FB < 0.9 x VNOM, IPG = 1 mA Thermal Protection Overtemperature Shutdown — 160 — °C T J rising Overtemperature Shutdown Hysteresis — 15 — °C — Note 1: Specification for packaged product only. 2: Measured in test mode. 3: The maximum duty cycle is limited by the fixed mandatory off-time (tOFF) of typically 300 ns. ELECTRICAL CHARACTERISTICS (CONTINUED) PVIN = VIN = VEN = 12V, VBST – VSW = 5V; TA = +25°C, unless otherwise noted. Bold values valid for –40°C ≤ TJ ≤ +125°C. Note 1 Parameter Min. Typ. Max. Units Conditions

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 5 MIC24054 TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Maximum Junction Temperature T J(MAX) — — +150 °C — Junction Temperature Range TJ –40 — +125 °C — Storage Temperature Range TS –65 — +150 °C — Lead Temperature TLEAD — — +260 °C Soldering, 10 sec. Package Thermal Resistance Thermal Resistance, VQFN 28-Ld θ JA — 28 — °C/W —

DS20007043B-page 6  2025-2026 Microchip Technology Inc. and its subsidiaries

2.0 TYPICAL PERFORMANCE CURVES

FIGURE 2-1: VIN Operating Supply Current vs. Input Voltage. FIGURE 2-2: VIN Shutdown Current vs. Input Voltage. FIGURE 2-3: VDD Output Voltage vs. Input Voltage. FIGURE 2-4: Feedback Voltage vs. Input Voltage. FIGURE 2-5: Total Regulation vs. Input Voltage. FIGURE 2-6: Output Current Limit vs. Input Voltage. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0.0 0.2 0.4 0.6 0.8 1.0 4 7 10 13 16 19 INPUT VOLTAGE (V) SUPPLY CURRENT (mA) VOUT = 1.8V IOUT = 0A SWITCHING 4 7 10 13 16 19 SHUTDOWN CURRENT (μA) INPUT VOLTAGE(V) VEN = 0V REN = OPEN 4 7 10 13 16 19 INPUT VOLTAGE (V) VDD VOLTAGE (V) VFB = 0.9V IDD = 10mA 0.792 0.796 0.800 0.804 0.808 4 7 10 13 16 19 INPUT VOLTAGE (V) FEEDBACK VOLTAGE (V) VOUT = 1.8V IOUT = 2A -1.0% -0.5% 0.0% 0.5% 1.0% 4 7 10 13 16 19 INPUT VOLTAGE (V) TOTAL REGULATION (%) VOUT = 1.8V IOUT = 2A to 9A 4 7 10 13 16 19 INPUT VOLTAGE (V) CURRENT LIMIT (A) VOUT = 1.8V

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 15 MIC24054

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin Number Pin Name Description

1 PVDD

5V Internal Linear Regulator output. PVDD supply is the power MOSFET gate drive supply voltage and created by internal LDO from VIN. When VIN < +5.5V, PVDD should be tied to the PVIN pins. A 2.2 µF ceramic capacitor from the PVDD pin to PGND (Pin 2) must be placed next to the IC. 2, 5, 6, 7, 8, 21 PGND Power Ground. PGND is the ground path for the MIC24054 buck converter power stage. The PGND pins connect to the source of the low-side N-channel MOSFET, gate driver supply ground of the low-side N-channel MOSFET, the negative terminals of input capacitors, and the negative terminals of output capacitors. The loop for the power ground should be as small as possible and separate from the signal ground (SGND) loop. 3 NC No connect. 4, 9, 10, 11, 12 SW Switch Node output. Internal connection for the high-side MOSFET source and low-side MOSFET drain. Due to the high speed switching on this pin, the SW pin should be routed away from sensitive nodes. 13,14,15, 16,17,18,19 PVIN High-Side N-internal MOSFET Drain Connection input. The PVIN operating voltage range is from 4.5V to 19V. Input capacitors between the PVIN pins and the power ground (PGND) are required and keep the connection short.

20 BST

Bootstrap output. Bootstrapped voltage to the high-side N-channel MOSFET driver. A Schottky diode is connected between the PVDD pin and the BST pin. A boost capacitor of 0.1 μF is connected between the BST pin and the SW pin. Adding a small resistor at the BST pin can slow down the turn-on time of high-side N-Channel MOSFETs. 22 CS Current Sense input. The CS pin senses current by monitoring the voltage across the low-side MOSFET during the OFF-time. The current sensing is necessary for short-circuit protection and zero current cross comparator. In order to sense the current accurately, connect the low-side MOSFET drain to SW using a Kelvin connection. The CS pin is also the high-side MOSFET’s output driver return.

23 SGND

Signal Ground. SGND must be connected directly to the ground planes. Do not route the SGND pin to the PGND pad on the top layer, see PCB layout guidelines for details. 24 FB Feedback input. Input to the transconductance amplifier of the control loop. The FB pin is regulated to 0.8V. A resistor divider connecting the feedback to the output is used to adjust the desired output voltage. 25 PG Power Good output. Open drain output. The PG pin is externally tied with a resistor to VDD. A high output is asserted when VOUT > 92% of nominal. 26 EN Enable input. A logic level control of the output. The EN pin is CMOS-compatible. Logic high = enable, logic low = shutdown. In the off state, supply current of the device is greatly reduced (typically 5 µA). The EN pin should not be left floating. 27 VIN Power Supply Voltage input. Requires bypass capacitor to SGND.

28 VDD

5V Internal Linear Regulator output. VDD supply is the supply bus for the IC control circuit. VDD is created by internal LDO from VIN. When VIN < +5.5V, VDD should be tied to the PVIN pins. A 1 µF ceramic capacitor from the VDD pin to the SGND pin must be place next to the IC.

DS20007043B-page 16  2025-2026 Microchip Technology Inc. and its subsidiaries

4.0 FUNCTIONAL DESCRIPTION

The MIC24054 is an adaptive ON-time synchronous step-down DC/DC regulator with an internal 5V linear regulator and a Power Good (PG) output. It is designed to operate over a wide input voltage range from 4.5V to 19V and provides a regulated output voltage at up to 9A of output current. An adaptive ON-time control scheme is employed in to obtain a constant switching frequency and to simplify the control compensation. Overcurrent protection is implemented without the use of an external sense resistor. The device includes an internal soft-start function that reduces the power supply input surge current at start-up by controlling the output voltage rise time.

4.1 Theory of Operation

The MIC24054 is able to operate in either continuous mode or discontinuous mode. The operating mode is determined by the output of the Zero Cross comparator (ZC) as shown in the Functional Block Diagram.

4.2 Continuous Mode

In continuous mode, the output voltage is sensed by the MIC24054 feedback pin (FB) via the voltage divider R1 and R2, and compared to a 0.8V reference voltage VREF at the error comparator through a low gain transconductance (g m) amplifier. If the feedback voltage decreases and the output of the gm amplifier is below 0.8V, then the error comparator will trigger the control logic and generate an ON-time period. The ON-time period length is predetermined by the “Fixed tON Estimation” circuitry: EQUATION 4-1: At the end of the ON-time period, the internal high-side driver turns off the high-side MOSFET and the low-side driver turns on the low-side MOSFET. The OFF-time period length depends upon the feedback voltage in most cases. When the feedback voltage decreases and the output of the g m amplifier is below 0.8V, the ON-time period is triggered and the OFF-time period ends. If the OFF-time period determined by the feedback voltage is less than the minimum OFF-time tOFF(MIN), which is about 300 ns, the MIC24054 control logic will apply the t OFF(MIN) instead. t OFF(MIN) is required to maintain enough energy in the boost capacitor (CBST) to drive the high-side MOSFET. The maximum duty cycle is obtained from the 300 ns tOFF(MIN): EQUATION 4-2: It is not recommended to use MIC24054 with a OFF-time close to t OFF(MIN) during steady-state operation. Also, as VOUT increases, the internal ripple injection will increase and reduce the line regulation performance. Therefore, the maximum output voltage of the MIC24054 should be limited to 5.5V and the maximum external ripple injection should be limited to 200 mV. Please refer to the Setting Output Voltage section for more details. The actual ON-time and resulting switching frequency will vary with the part-to-part variation in the rise and fall times of the internal MOSFETs, the output load current, and variations in the V DD voltage. Also, the minimum tON results in a lower switching frequency in high VIN to VOUT applications, such as 18V to 1.0V. The minimum tON measured on the MIC24054 evaluation board is about 100 ns. During load transients, the switching frequency is changed due to the varying OFF-time. To illustrate the control loop operation, we will analyze both the steady-state and load transient scenarios. Figure 4-1 shows the MIC24054 control loop timing during steady-state operation. During steady-state, the gm amplifier senses the feedback voltage ripple, which is proportional to the output voltage ripple and the inductor current ripple, to trigger the ON-time period. The ON-time is predetermined by the t ON estimator. The termination of the OFF-time is controlled by the feedback voltage. At the valley of the feedback voltage ripple, which occurs when V FB falls below V REF, the OFF period ends and the next ON-time period is triggered through the control logic circuitry. FIGURE 4-1: Control Loop Timing. tON ESTIMATED  VOUT Where: VOUT = The desired output voltage. VIN = The power stage input voltage. DMAX tS tOFF MIN – tS tS Where: tS = 1/600 kHz = 1.66 µs

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 17 MIC24054 Figure 4-2 shows the operation of the MIC24054 during a load transient. The output voltage drops due to the sudden load increase, which causes the VFB to be less than V REF. This will cause the error comparator to trigger an ON-time period. At the end of the ON-time period, a minimum OFF-time, tOFF(MIN), is generated to charge C BST because the feedback voltage is still below VREF. Then, the next ON-time period is triggered due to the low feedback voltage. Therefore, the switching frequency changes during the load transient, but returns to the nominal fixed frequency once the output has stabilized at the new load current level. With the varying duty cycle and switching frequency, the output recovery time is fast and the output voltage deviation is small in MIC24054 converter. FIGURE 4-2: Load Transient Response. Unlike true current-mode control, the MIC24054 uses the output voltage ripple to trigger an ON-time period. The output voltage ripple is proportional to the inductor current ripple if the ESR of the output capacitor is large enough. The MIC24054 control loop has the advantage of eliminating the need for slope compensation. In order to meet stability requirements, the MIC24054 feedback voltage ripple should be in phase with the inductor current ripple and large enough to be sensed by the g m amplifier and the error comparator. The recommended feedback voltage ripple is 20 mV~100 mV. If a low-ESR output capacitor is selected, then the feedback voltage ripple may be too small to be sensed by the g m amplifier and the error comparator. Also, the output voltage ripple and the feedback voltage ripple are not necessarily in phase with the inductor current ripple if the ESR of the output capacitor is very low. In these cases, ripple injection is required to ensure proper operation. Please refer to the Ripple Injection section for more details about the ripple injection technique.

4.3 Discontinuous Mode

In continuous mode, the inductor current is always greater than zero; however, at light loads, the MIC24054 is able to force the inductor current to operate in discontinuous mode. Discontinuous mode is where the inductor current falls to zero, as indicated by trace (IL) shown in Figure 4-3. During this period, the efficiency is optimized by shutting down all the non-essential circuits and minimizing the supply current. The MIC24054 wakes up and turns on the high-side MOSFET when the feedback voltage (V FB) drops below 0.8V. The MIC24054 has a zero crossing comparator that monitors the inductor current by sensing the voltage drop across the low-side MOSFET during its ON-time. If the VFB > 0.8V and the inductor current goes slightly negative, then the MIC24054 automatically powers down most of the IC circuitry and goes into a low-power mode. Once the MIC24054 goes into discontinuous mode, both LSD and HSD are low, which turns off the high-side and low-side MOSFETs. The load current is supplied by the output capacitors and V OUT drops. If the drop of VOUT causes VFB to go below VREF, then all the circuits will wake up into normal continuous mode. First, the bias currents of most circuits reduced during the discontinuous mode are restored, then a tON pulse is triggered before the drivers are turned on to avoid any possible glitches. Finally, the high-side driver is turned on. Figure 4-3 shows the control loop timing in discontinuous mode. FIGURE 4-3: Control Loop Timing (Discontinuous Mode). During discontinuous mode, the bias current of most circuits are reduced. As a result, the total power supply current during discontinuous mode is only about 450 µA, allowing the MIC24054 to achieve high efficiency in light load applications.

DS20007043B-page 18  2025-2026 Microchip Technology Inc. and its subsidiaries

4.4 VDD Regulator

The MIC24054 provides a 5V regulated output for input voltage (VIN) ranging from 5.5V to 19V. When VIN < 5.5V, VDD should be tied to the PVIN pins to bypass the internal linear regulator.

4.5 Soft-Start

Soft-start reduces the power supply input surge current at start-up by controlling the output voltage rise time. The input surge appears while the output capacitor is charged up. A slower output rise time draws a lower input surge current. The MIC24054 implements an internal digital soft-start by making the 0.8V reference voltage (V REF) ramp from 0% to 100% in about 3 ms with 9.7 mV steps. Therefore, the output voltage is controlled to increase slowly by a stair-case V FB ramp. Once the soft-start cycle ends, the related circuitry is disabled to reduce current consumption. VDD must be powered up at the same time or after VIN to make the soft-start function correctly.

4.6 Current Limit

The MIC24054 uses the R DS(ON) of the internal low-side power MOSFET to sense overcurrent conditions. This method avoids adding cost, board space, and power losses taken by a discrete current sense resistor. The low-side MOSFET is used because it displays much lower parasitic oscillations during switching than the high-side MOSFET. In each switching cycle of the MIC24054 converter, the inductor current is sensed by monitoring the low-side MOSFET in the OFF period. If the inductor current is greater than 14A, then the MIC24054 turns off the high-side MOSFET and a soft-start sequence is triggered. This mode of operation is called “hiccup mode” and its purpose is to protect the downstream load in case of a hard short. The load current-limit threshold has a foldback characteristic related to the feedback voltage as shown in Figure 4-4. FIGURE 4-4: Current-Limit Foldback Characteristics.

4.7 Power Good (PG)

The Power Good (PG) pin is an open-drain output that indicates logic-high when the output is nominally 92% of its steady state voltage. A pull-up resistor of more than 10 kΩ should be connected from PG to VDD.

4.8 MOSFET Gate Driver

The Functional Block Diagram shows a bootstrap circuit, consisting of D1 (a Schottky diode is recommended) and CBST. This circuit supplies energy to the high-side drive circuit. Capacitor C BST is charged, while the low-side MOSFET is on, and the voltage on the SW pin is approximately 0V. When the high-side MOSFET driver is turned on, energy from CBST is used to turn the MOSFET on. As the high-side MOSFET turns on, the voltage on the SW pin increases to approximately VIN. Diode D1 is reverse-biased and CBST floats high while continuing to keep the high-side MOSFET on. The bias current of the high-side driver is less than 10 mA, so a 0.1 μF to 1 μF is sufficient to hold the gate voltage with minimal droop for the power stroke (high-side switching) cycle (i.e. ΔBST = 10 mA x 1.67 μs/0.1 μF = 167 mV). When the low-side MOSFET is turned back on, CBST is recharged through D1. A small resistor R G, which is in series with C BST, can be used to slow down the turn-on time of the high-side N-channel MOSFET. The drive voltage is derived from the V DD supply voltage. The nominal low-side gate drive voltage is VDD and the nominal high-side gate drive voltage is approximately V DD – V DIODE, where V DIODE is the voltage drop across D1. An approximate 30 ns delay between the high-side and low-side driver transitions is used to prevent current from simultaneously flowing unimpeded through both MOSFETs. FEEDBACK VOLTAGE (V) CURRENT LIMIT THRESHOLD (A)

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 19 MIC24054

5.0 APPLICATION INFORMATION

5.1 Inductor Selection

Values for inductance, peak, and RMS currents are required to select the output inductor. The input and output voltages and the inductance value determine the peak-to-peak inductor ripple current. Generally, higher inductance values are used with higher input voltages. Larger peak-to-peak ripple currents will increase the power dissipation in the inductor and MOSFETs. Larger output ripple currents will also require more output capacitance to smooth out the larger ripple current. Smaller peak-to-peak ripple currents require a larger inductance value and, therefore, a larger and more expensive inductor. A good compromise between size, loss, and cost is to set the inductor ripple current to be equal to 20% of the maximum output current. The inductance value is calculated by Equation 5-1: EQUATION 5-1: The peak-to-peak inductor current ripple is: EQUATION 5-2: The peak inductor current is equal to the average output current plus one half of the peak-to-peak inductor current ripple. EQUATION 5-3: The RMS inductor current is used to calculate the I 2R losses in the inductor. EQUATION 5-4: Maximizing efficiency requires the proper selection of core material and minimizing the winding resistance. The high frequency operation of the MIC24054 requires the use of ferrite materials for all but the most cost sensitive applications. Lower cost iron powder cores may be used, but the increase in core loss will reduce the efficiency of the power supply. This is especially noticeable at low output power. The winding resistance decreases efficiency at the higher output current levels. The winding resistance must be minimized although this usually comes at the expense of a larger inductor. The power dissipated in the inductor is equal to the sum of the core and copper losses. At higher output loads, the core losses are usually insignificant and can be ignored. At lower output currents, the core losses can be a significant contributor. Core loss information is usually available from the magnetics vendor. Copper loss in the inductor is calculated by Equation 5-5: EQUATION 5-5: The resistance of the copper wire, R WIND, increases with the temperature. The value of the winding resistance used should be at the operating temperature. EQUATION 5-6: Where: fSW = Switching frequency, 600 kHz 20% = Ratio of AC ripple current to DC output current VIN(MAX) = Maximum power stage input voltage IL RMS  IOUT MAX 

2 IL PP 

PIND CU  IL RMS 

2 RWIND=

Where: TH = Temperature of wire under full load T20C = Ambient temperature RWIND(20C) = Room temperature winding resistance (usually specified by the manufacturer)

DS20007043B-page 20  2025-2026 Microchip Technology Inc. and its subsidiaries

5.2 Output Capacitor Selection

The type of the output capacitor is usually determined by its equivalent series resistance (ESR). Voltage and RMS current capability are two other important factors for selecting the output capacitor. Recommended capacitor types are tantalum, low-ESR aluminum electrolytic, OS-CON, and POSCAP. The output capacitor’s ESR is usually the main cause of the output ripple. The output capacitor ESR also affects the control loop from a stability point of view. The maximum value of ESR is calculated: EQUATION 5-7: The total output ripple is a combination of the ESR and output capacitance. The total ripple is calculated in Equation 5-8: EQUATION 5-8: As described in the Theory of Operation section, the MIC24054 requires at least 20 mV peak-to-peak ripple at the FB pin to make the g m amplifier and the error comparator behave properly. Also, the output voltage ripple should be in phase with the inductor current. Therefore, the output voltage ripple caused by the output capacitors value should be much smaller than the ripple caused by the output capacitor ESR. If low-ESR capacitors, such as ceramic capacitors, are selected as the output capacitors, a ripple injection method should be applied to provide the enough feedback voltage ripple. Please refer to the Ripple Injection section for more details. The voltage rating of the capacitor should be twice the output voltage for a tantalum and 20% greater for aluminum electrolytic or OS-CON. The output capacitor RMS current is calculated below: EQUATION 5-9: The power dissipated in the output capacitor is: EQUATION 5-10:

5.3 Input Capacitor Selection

The input capacitor for the power stage input V IN should be selected for ripple current rating and voltage rating. Tantalum input capacitors may fail when subjected to high inrush currents, caused by turning the input supply on. A tantalum input capacitor’s voltage rating should be at least two times the maximum input voltage to maximize reliability. Aluminum electrolytic, OS-CON, and multilayer polymer film capacitors can handle the higher inrush currents without voltage de-rating. The input voltage ripple will primarily depend on the input capacitor’s ESR. The peak input current is equal to the peak inductor current, so: EQUATION 5-11: The input capacitor must be rated for the input current ripple. The RMS value of input capacitor current is determined at the maximum output current. Assuming the peak-to-peak inductor current ripple is low: EQUATION 5-12: The power dissipated in the input capacitor is: EQUATION 5-13: ESR C OUT  VOUT PP  Where: ΔVOUT(PP) = Peak-to-peak output voltage ripple ΔIL(PP) = Peak-to-peak inductor current ripple VOUT PP  = IL PP    Where: COUT = Output capacitance value fSW = Switching frequency ICOUT RMS  IL PP  PDISS COUT  ICOUT RMS 

2 ESR COUT=

VIN IL PK  ESR CIN= PDISS CIN  ICIN RMS 

2 ESR CIN=

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 21 MIC24054

5.4 Ripple Injection

The V FB ripple required for proper operation of the MIC24054 gm amplifier and error comparator is 20 mV to 100 mV. However, the output voltage ripple is generally designed as 1% to 2% of the output voltage. For a low output voltage, such as a 1V, the output voltage ripple is only 10 mV to 20 mV, and the feedback voltage ripple is less than 20 mV. If the feedback voltage ripple is so small that the gm amplifier and error comparator can’t sense it, then the MIC24054 will lose control and the output voltage is not regulated. In order to have some amount of V FB ripple, a ripple injection method is applied for low output voltage ripple applications. The applications are divided into three situations according to the amount of the feedback voltage ripple: 1. Enough ripple at the feedback voltage due to the large ESR of the output capacitors. As shown in Figure 5-1, the converter is stable without any ripple injection. The feedback voltage ripple is: EQUATION 5-14: FIGURE 5-1: Enough Ripple at FB. 2. Inadequate ripple at the feedback voltage due to the small ESR of the output capacitors. The output voltage ripple is fed into the FB pin through a feed-forward capacitor (C FF) in this situation, as shown in Figure 5-2. The typical CFF value is between 1 nF and 100 nF. With the feed-forward capacitor, the feedback voltage ripple is very close to the output voltage ripple: EQUATION 5-15: FIGURE 5-2: Inadequate Ripple at FB. 3. Virtually no ripple at the FB pin voltage due to the very low ESR of the output capacitors. In this situation, the output voltage ripple is less than 20 mV. Therefore, additional ripple is injected into the FB pin from the switching node SW via a resistor Rinj and a capacitor Cinj, as shown in Figure 5-3. The injected ripple is: EQUATION 5-16: EQUATION 5-17: FIGURE 5-3: Invisible Ripple at FB. In Equation 5-16 and Equation 5-17, it is assumed that the time constant associated with C FF must be much greater than the switching period: EQUATION 5-18: VFB PP  R2 Where: ΔIL(PP) = Peak-to-peak inductor current ripple VFB PP  = Where: VIN = Power stage input voltage D = Duty cycle fSW = Switching frequency τ = (R1//R2//Rinj) × CFF KDIV R1//R2 - - -1«=

DS20007043B-page 22  2025-2026 Microchip Technology Inc. and its subsidiaries If the voltage divider resistors R1 and R2 are in the kΩ range, a C FF of 1 nF to 100 nF can easily satisfy the large time constant requirements. Also, a 100 nF injection capacitor Cinj is used in order to be considered as short for a wide range of the frequencies. The process of sizing the ripple injection resistor and capacitors is: Step 1. Select C FF to feed all output ripples into the Feedback pin and make sure the large time constant assumption is satisfied. Typical choice of CFF is 1 nF to 100 nF if R1 and R2 are in the kΩ range. Step 2. Select Rinj according to the expected feedback voltage ripple using Equation 5-17: EQUATION 5-19: Then the value of Rinj is obtained as: EQUATION 5-20: Step 3. Select Cinj as 100 nF, which could be considered as short for a wide range of the frequencies.

5.5 Setting Output Voltage

The MIC24054 requires two resistors to set the output voltage as shown in Figure 5-4. FIGURE 5-4: Voltage Divider Configuration. It is recommended to use a bleeder resistor (VOUT to GND) of 27 kΩ for better regulation at output voltages below 1V. The output voltage is determined by Equation 5-21: EQUATION 5-21: If R1 is too large, it may allow noise to be introduced into the voltage feedback loop. If R1 is too small, it will decrease the efficiency of the power supply, especially at light loads. Once R1 is selected, R2 can be calculated using Equation 5-22. EQUATION 5-22: In addition to the external ripple injection added at the FB pin, internal ripple injection is added at the inverting input of the comparator inside the MIC24054, as shown in Figure 5-5. The inverting input voltage V INJ is clamped to 1.2V. As V OUT is increased, the swing of VINJ will be clamped. The clamped V INJ reduces the line regulation because it is reflected as a DC error on the FB terminal. Therefore, the maximum output voltage of the MIC24054 should be limited to 5.5V to avoid this problem. FIGURE 5-5: Internal Ripple Injection. KDIV VFB PP  VIN Rinj R1//R2  1 KDIV  = VOUT VFB 1 R1  = R2 VFB R1

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 23 MIC24054

5.6 Thermal Measurements

Measuring the IC’s case temperature is recommended to ensure it is within its operating limits. Although this might seem like a very elementary task, it is easy to get erroneous results. The most common mistake is to use the standard thermal couple that comes with a thermal meter. This thermal couple wire gauge is large, typically 22 gauge, and behaves like a heatsink, resulting in a lower case measurement. Two methods of temperature measurement are using a smaller thermal couple wire or an infrared thermometer. If a thermal couple wire is used, then it must be constructed of 36 gauge wire or higher then (smaller wire size) to minimize the wire heat-sinking effect. In addition, the thermal couple tip must be covered in either thermal grease or thermal glue to make sure that the thermal couple junction is making good contact with the case of the IC. Omega brand thermal couple (5SC-TT-K-36-36) is adequate for most applications. Wherever possible, an infrared thermometer is recommended. The measurement spot size of most infrared thermometers is too large for an accurate reading on a small form factor ICs. However, a IR thermometer from Optris has a 1 mm spot size, which makes it a good choice for measuring the hottest point on the case. An optional stand makes it easy to hold the beam on the IC for long periods of time.

DS20007043B-page 24  2025-2026 Microchip Technology Inc. and its subsidiaries

6.0 PCB LAYOUT GUIDELINES

PCB layout is critical to achieve reliable, stable, and efficient performance. A ground plane is required to control EMI and minimize the inductance in power, signal and return paths. To minimize EMI and output noise, the following guidelines should be followed to ensure proper operation of the MIC24054. 6.1 IC

• A 2.2 μF ceramic capacitor, which is connected to the PVDD pin, must be located right at the IC. The PVDD pin is very noise sensitive and placement of the capacitor is very critical. Use wide traces to connect to the PVDD and PGND pins.
• A 1 μF ceramic capacitor must be placed right between VDD and the signal ground SGND. The SGND pin must be connected directly to the ground planes. Do not route the SGND pin to the PGND Pad on the top layer.
• Place the IC close to the point-of-load (POL).
• Use wide traces to route the input and output power lines.
• Signal and power grounds should be kept separate and connected at only one location.

6.2 Input Capacitor

• Place the input capacitors on the same side of the board and as close to the IC as possible.
• Keep both the PVIN pin and PGND connections short.
• Place several vias to the ground plane close to the input capacitor ground terminal.
• Use either X7R or X5R dielectric input capacitors. Do not use Y5V or Z5U type capacitors.
• Do not replace the ceramic input capacitor with any other type of capacitor. Any type of capacitor can be placed in parallel with the input capacitor.
• If a Tantalum input capacitor is placed in parallel with the input capacitor, it must be recommended for switching regulator applications and the operating voltage must be derated by 50%.
• In “Hot-Plug” applications, a Tantalum or Electrolytic bypass capacitor must be used to limit the overvoltage spike seen on the input supply with power is suddenly applied.

6.3 Inductor

• Keep the inductor connection to the switch node (SW) short.
• Do not route any digital lines underneath or close to the inductor.
• Keep the switch node (SW) away from the feedback (FB) pin.
• The CS pin should be connected directly to the SW pin to accurate sense the voltage across the low-side MOSFET.
• To minimize noise, place a ground plane underneath the inductor.
• The inductor can be placed on the opposite side of the PCB with respect to the IC. It does not matter whether the IC or inductor is on the top or bottom as long as there is enough air flow to keep the power components within their temperature limits. The input and output capacitors must be placed on the same side of the board as the IC.

6.4 Output Capacitor

• Use a wide trace to connect the output capacitor ground terminal to the input capacitor ground terminal.
• Phase margin will change as the output capacitor value and ESR changes. Contact the factory if the output capacitor is different from what is shown in the BOM.
• The feedback trace should be separate from the power trace and connected as close as possible to the output capacitor. Sensing a long high current load trace can degrade the DC load regulation.

6.5 Optional RC Snubber

• Place the RC snubber on either side of the board and as close to the SW pin as possible.

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 25 MIC24054

7.0 EVALUATION BOARD SCHEMATIC

FIGURE 7-1: Schematic of MIC24054 Evaluation Board (J11, R13, R15 are for Testing Purposes).

DS20007043B-page 26  2025-2026 Microchip Technology Inc. and its subsidiaries FIGURE 7-2: Schematic of MIC24054 Evaluation Board (J11, R13, R15 are for Testing Purposes) Optimized for Smaller Footprint. TABLE 7-1: BILL OF MATERIALS Item Part Number Manufacturer Description Qty. C1 Open — — — C2, C3 12103C475KAT2A AVX 4.7 µF Ceramic Capacitor, X7R, Size 1210, 25V 2GRM32DR71E475KA61K Murata C3225X7R1E475K TDK C13, C15 Open — — — C4, C5 12106D107MAT2A AVX 100 µF Ceramic Capacitor, X5R, Size 1210, 6.3V 2GRM32ER60J107ME20L Murata C3225X5R0J107M TDK

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 27 MIC24054 C6, C7, C10 06035C104KAT2A AVX 0.1 µF Ceramic Capacitor, X7R, Size 0603, 50V 3GRM188R71H104KA93D Murata C1608X7R1H104K TDK 0603ZC105KAT2A AVX 1.0 µF Ceramic Capacitor, X7R, Size 0603, 10V 1GRM188R71A105KA61D Murata C1608X7R1A105K TDK 0603ZD225KAT2A AVX 2.2 µF Ceramic Capacitor, X5R, Size 0603, 10V 1GRM188R61A225KE34D Murata C1608X5R1A225K TDK C12 06035C472KAZ2A AVX 4.7 nF Ceramic Capacitor, X7R, Size 0603, 50V 1GRM188R71H472K Murata C1608X7R1H472K TDK C14 B41851F7227M EPCOS 220 µF Aluminum Capacitor, 35V 1 C11, C16 Open — — — SD103AWS MCC 40V, 350 mA, Schottky Diode, SOD323 1SD103AWS-7 Diodes Inc. SD103AWS Vishay L1 HCF1305-2R2-R Cooper Bussmann 2.2 µH Inductor, 15A Saturation Current 1 R1 CRCW06032R21FKEA Vishay Dale 2.21Ω Resistor, Size 0603, 1% 1 R2 CRCW06032R00FKEA Vishay Dale 2.00Ω Resistor, Size 0603, 1% 1 R3 CRCW060319K6FKEA Vishay Dale 19.6 kΩ Resistor, Size 0603, 1% 1 R4 CRCW06032K49FKEA Vishay Dale 2.49 kΩ Resistor, Size 0603, 1% 1 R5 CRCW060320K0FKEA Vishay Dale 20.0 kΩ Resistor, Size 0603, 1% 3 R6, R14, R17 CRCW060310K0FKEA Vishay Dale 10.0 kΩ Resistor, Size 0603, 1% 1 R7 CRCW06034K99FKEA Vishay Dale 4.99 kΩ Resistor, Size 0603, 1% 1 R8 CRCW06032K87FKEA Vishay Dale 2.87 kΩ Resistor, Size 0603, 1% 1 R9 CRCW06032K006FKEA Vishay Dale 2.00 kΩ Resistor, Size 0603, 1% 1 R10 CRCW06031K18FKEA Vishay Dale 1.18 kΩ Resistor, Size 0603, 1% 1 R11 CRCW0603806RFKEA Vishay Dale 806Ω Resistor, Size 0603, 1% 1 R12 CRCW0603475RFKEA Vishay Dale 475Ω Resistor, Size 0603, 1% 1 R13 CRCW06030000FKEA Vishay Dale 0Ω Resistor, Size 0603, 5% 1 R15 CRCW060349R9FKEA Vishay Dale 49.9Ω Resistor, Size 0603, 1% 1 R16, R18 CRCW06031R21FKEA Vishay Dale 1.21Ω Resistor, Size 0603, 1% 2 R20 Open — — — All Reference designators ending with “A” Open — — — U1 MIC24054YJL Microchip Technology Inc. 12V, 9A High-Efficiency Buck Regulator 1 TABLE 7-1: BILL OF MATERIALS (CONTINUED) Item Part Number Manufacturer Description Qty.

DS20007043B-page 28  2025-2026 Microchip Technology Inc. and its subsidiaries

8.0 RECOMMENDED PCB LAYOUT

FIGURE 8-1: Top Layer. FIGURE 8-2: Mid-Layer 1 (Ground Plane).

DS20007043B-page 30  2025-2026 Microchip Technology Inc. and its subsidiaries

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

Note: If the full seven-character YYWWNNN code cannot fit on the package, the following truncated codes are used based on the available marking space:

6 Characters = YWWNNN; 5 Characters = WWNNN; 4 Characters = WNNN; 3 Characters = NNN;

2 Characters = NN; 1 Character = N

Example28-Lead VQFN* XXX XXXXXXXX WNNN MIC 24054YJL 6LB1 Legend: XX...X Product code or customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package.

• , ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark). Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. Underbar (_) and/or Overbar (‾) symbol may not be to scale.

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 31 MIC24054 BA 0.05 C 0.05 C

0.07 C A B

0.05 C C TOP VIEW SIDE VIEW BOTTOM VIEW 0.10 C 0.08 C Sheet 1 of 2 28X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 28-Lead Very Thin Plastic Quad Flat, No Lead Package (PKA) - 5x6x0.9 mm Body [VQFN] With Multiple Exposed Pads and Fused Terminals; Micrel Legacy QFN56-28LD-PL-1 SEATING PLANE Microchip Technology Drawing C04-1120 Rev A (DATUM A) (DATUM B) NOTE 1 NOTE 1 D E (A3) A e 28X b (K4) (K5) (K3) (K4) (K2) (L2) (K1) (L3) N N e 2 E5 D4 0.60

DS20007043B-page 32  2025-2026 Microchip Technology Inc. and its subsidiaries For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M Sheet 2 of 2 28-Lead Very Thin Plastic Quad Flat, No Lead Package (PKA) - 5x6x0.9 mm Body [VQFN] With Multiple Exposed Pads and Fused Terminals; Micrel Legacy QFN56-28LD-PL-1 Microchip Technology Drawing C04-1120 Rev A Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Terminal Thickness Pitch Standoff Units Dimension Limits A b e E N

0.65 BSC

0.20 REF

2.90 0.35 0.25 0.00 0.80 0.30 0.40 2.95 0.02 0.85

6.00 BSC

3.00 0.45 0.35 0.05 0.85 MAX K1 0.25 REFTerminal to Exposed Pad Overall Length Exposed Pad Length D D2 2.15

5.00 BSC

2.20 2.25 K2 0.575 REFBody Edge to Exposed Pad K3 0.035 REFExposed Pad to Exposed Pad K4 0.40 REFExposed Pad Offset Terminal Length L2 0.45 REF Terminal Length L3 0.15 REF Exposed Pad Width E3 1.575 1.60 1.625 Exposed Pad Length D3 1.35 1.40 1.45 Exposed Pad Length D4 3.65 3.70 3.75 K5 0.35 REFExposed Pad to Exposed Pad Exposed Pad Width E4 2.45 Exposed Pad Width E5 2.90 2.40 2.50 2.85 2.95

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 33 MIC24054 RECOMMENDED LAND PATTERN Dimension Limits Units Center Pad Length Contact Pitch MILLIMETERS E MAXNOM BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: EV EV Center Pad Width X2 3.70 Center Pad Width X3 2.20 Center Pad Width X4 0.90 1.60 2.83 Dimension Limits Units C2Contact Pad Spacing MILLIMETERS MIN MAX 5.80 Contact Pad Length Contact Pad Width 0.40 0.30 NOM C1Contact Pad Spacing 4.80 Contact Pad to Contact Pad G2 0.35 Thermal Via Diameter V Thermal Via Pitch EV 0.30 1.00 Contact Pad to Center Pad G1 0.12 Center Pad Length Y3 ØV E Contact Pad to Center Pad 0.60 Center Pad to Center Pad G3 0.35 Center Pad to Center Pad 0.13 Contact Pad to Center Pad 0.35 SILK SCREEN 28-Lead Very Thin Plastic Quad Flat, No Lead Package (PKA) - 5x6x0.9 mm Body [VQFN] With Multiple Exposed Pads and Fused Terminals; Micrel Legacy QFN56-28LD-PL-1 Microchip Technology Drawing C04-3120 Rev A

DS20007043B-page 34  2025-2026 Microchip Technology Inc. and its subsidiaries NOTES:

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 35 MIC24054 APPENDIX A: REVISION HISTORY Revision B (January 2026)

• Corrected the trademark symbol placement for SuperSwitcher™. Revision A (September 2025)
• Converted Micrel document MIC24054 to Micro- chip data sheet DS20007043A.
• Minor text changes throughout.

DS20007043B-page 36  2025-2026 Microchip Technology Inc. and its subsidiaries NOTES:

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 37 MIC24054 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Examples: a) MIC24054YJL-TR: MIC24054, –40°C to +125°C Temp. Range, 28-Lead VQFN, 1,000/Reel Device: MIC24054: 12V, 9A High-Efficiency SuperSwitcher™ II Buck Regulator Temperature Range: Y = –40°C to +125°C Package: JL = 28-Lead 5 mm x 6 mm VQFN Media Type: TR = 1,000/Reel Note: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package avail- ability with the Tape and Reel option. Part Number X XX -XX Device Temp. Range Package Media Type

DS20007043B-page 38  2025-2026 Microchip Technology Inc. and its subsidiaries NOTES:

 2025-2026 Microchip Technology Inc. and its subsidiaries DS20007043B-page 39 Microchip Information Trademarks The “Microchip” name and logo, the “M” logo, and other names, logos, and brands are registered and unregistered trademarks of Microchip Technology Incorporated or its affiliates and/or subsidiaries in the United States and/or other countries (“Microchip Trademarks”). Information regarding Microchip Trademarks can be found at https://www.microchip.com/en-us/about/legalinformation/microchip- trademarks. ISBN: 979-8-3371-2641-8 Legal Notice This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at www.microchip.com/en-us/support/design-help/client-support-services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY , AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip products:

• Microchip products meet the specifications contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions.
• Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products.