HCA10008 INTERSIL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 13

Technical content

Features

  • Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Configurations
  • Bootstrap Supply Max Voltage to 95VDC
  • Drives 1000pF Load at 1MHz in Free Air at 50oC with Rise and Fall Times of Typically 10ns
  • User Programmable Dead Time
  • On-Chip Charge Pump and Bootstrap Upper Bias Supplies
  • DIS (Disable) Overrides Input Control
  • Input Logic Thresholds Compatible with 5V to 15V Logic Levels
  • Very Low Power Consumption
  • Undervoltage Protection

Applications

  • Medium/Large Voice Coil Motors
  • Full Bridge Power Supplies
  • Class D Audio Power Amplifiers
  • High Performance Motor Controls
  • Noise Cancellation Systems
  • Battery Powered Vehicles
  • Peripherals
  • U.P .S.
  • Related Literature - AN9405 Application Note for the HIP4081A and the HCA10008

Ordering Information

(oC) PACKAGE PKG. NO. HCA10008 -40 to 85 20 Ld SOIC (W) M20.3 1BHB BHI DIS VSS BLI ALI HDEL AHI LDEL AHB BHO BLO BLS VDD BHS VCC ALS ALO AHS AHO Data Sheet August 1999

Functional Block Diagram(1/2 HCA10008) 80V GND LOAD HCA10008 GND 12V AHI ALI BLI BHI BLO BHS BHO ALO AHS AHO TRUTH TABLE INPUT OUTPUT ALI, BLI AHI, BHI U/V DIS ALO, BLO AHO, BHO XXX100 1X0010 010001 000000 XX1X00 NOTE: X signifies that input can be either a “1” or “0”. CHARGE PUMP VDD AHI DIS ALI HDEL LDEL VSS TURN-ON DELAY TURN-ON DELAY DRIVER DRIVER AHB AHO AHS VCC ALO ALS C BF TO VDD (PIN 16) C BS D BS HIGH VOLTAGE BUS ≤ 80VDC +12VDC LEVEL SHIFT AND LATCH BIAS SUPPLY UNDER- VOLTAGE HCA10008

Typical Application(PWM Mode Switching)

1 BHB

1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than V DD ). An internal 100µA pull-up to VDD will hold BHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input. 3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than V DD ). An internal 100µA pull-up to VDD will hold DIS high if this pin is not driven. 4V SS Chip negative supply, generally will be ground. 5 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than V DD ). An internal 100µA pull-up to VDD will hold BLI high if this pin is not driven. 6 ALI A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than V DD ). An internal 100µA pull-up to VDD will hold ALI high if this pin is not driven. 7 AHI A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than V DD ). An internal 100µA pull-up to VDD will hold AHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input. 8 HDEL High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V. 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to V SS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V. 10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 11 AHO A High-side Output. Connect to gate of A High-side power MOSFET. 12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 15 V CC Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes. 16 V DD Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). Decouple this pin to VSS (Pin 4). 17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 20 BHO B High-side Output. Connect to gate of B High-side power MOSFET. HCA10008

Absolute Maximum Ratings Thermal Information Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25oC to 125oC) Voltage on AHS, BHS . . .-6.0V (Transient) to 70V (-55oC to 125oC) AHS, BHS -0.3V to VAHS, BHS +VDD NOTE: All Voltages relative to V SS , unless otherwise specified. Operating Conditions AHS, BHS +5V to VAHS, BHS +15V Thermal Resistance (Typical, Note 1) θJA (oC/W) (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsVDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS TJ = 25oC TJS = -40oCT O 125oC UNITSMIN TYP MAX MIN MAX SUPPLY CURRENTS AND CHARGE PUMPS V VCC Quiescent Current I CC All Inputs = 0V, IALO = IBLO = 0 - 0.1 10 - 20 µA VCC Operating Current I CCO f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA AHB, BHB Quiescent Current Qpump Output Current IAHB , IBHB All Inputs = 0V, IAHO = IBHO = 0 VDD = VCC = VAHB = VBHB = 10V -50 -30 -11 -60 -10 µA AHS, BHS, AHB, BHB Leakage Current IHLK VBHS = VAHS = 80V, VAHB = VBHB = 93V - 0.02 1.0 - 10 µA AHB-AHS, BHB-BHS Qpump Output Voltage VAHB -VAHS VBHB -VBHS INPUT PINS: ALI, BLI, AHI, BHI, AND DIS Low Level Input Voltage V IL Full Operating Conditions - - 1.0 - 0.8 V High Level Input Voltage V IH Full Operating Conditions 2.5 - - 2.7 - V Input Voltage Hysteresis - 35 - - - mV Low Level Input Current I IL VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 µA High Level Input Current I IH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage V HDEL , VLDEL HCA10008

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Electrical SpecificationsVDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS TJ = 25oC TJS = -40oCT O 125oC UNITSMIN TYP MAX MIN MAX Switching SpecificationsVDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, C L = 1000pF PARAMETER SYMBOL TEST CONDITIONS TJ = 25oC TJS = -40oC TO 125oC UNITSMIN TYP MAX MIN MAX Lower Turn-Off Propagation Delay (ALI-ALO, BLI-BLO) TLPHL -3 0 6 0-8 0 n s Upper Turn-Off Propagation Delay (AHI-AHO, BHI-BHO) THPHL -3 5 7 0-9 0 n s Lower Turn-On Propagation Delay (ALI-ALO, BLI-BLO) TLPLH R HDEL = RLDEL = 10K - 45 70 - 90 ns Upper Turn-On Propagation Delay (AHI-AHO, BHI-BHO) THPLH R HDEL = RLDEL = 10K - 60 90 - 110 ns Rise Time T R -1 0 2 5-3 5 n s Fall Time T F -1 0 2 5-3 5 n s Turn-On Input Pulse Width T PWIN-ON R HDEL = RLDEL = 10K 50 - - 50 - ns Turn-Off Input Pulse Width T PWIN-OFF R HDEL = RLDEL = 10K 40 - - 40 - ns Turn-On Output Pulse Width T PWOUT -ON R HDEL = RLDEL = 10K 40 - - 40 - ns Turn-Off Output Pulse Width T PWOUT -OFF R HDEL = RLDEL = 10K 30 - - 30 - ns Disable Turn-Off Propagation Delay (DIS - Lower Outputs) TDISLOW -4 5 7 5-9 5 n s Disable Turn-Off Propagation Delay (DIS - Upper Outputs) TDISHIGH - 55 85 - 105 ns Disable to Lower Turn-On Propagation Delay (DIS - ALO and BLO) TDLPLH -4 0 7 0-9 0 n s Refresh Pulse Width (ALO and BLO) T REF-PW 240 410 550 200 600 ns Disable to Upper Enable (DIS - AHO and BHO) T UEN - 450 620 - 690 ns HCA10008

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 HCA10008 Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M α M20.3 (JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.4961 0.5118 12.60 13.00 3 E 0.2914 0.2992 7.40 7.60 4 e 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N2 0 2 0 7 α 0o 8o 0o 8o - Rev. 0 12/93