HC908JB16AD FREESCALE | Alldatasheet

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Rev. 1, 8/2002 Addendum to MC68HC908JB16 Te c h n i c a l D a t a Addendum This addendum provides update and additional information to the MC68HC908JB16 Technical Data, Rev. 1 (Motorola document number MC68HC908JB16/D), pertaining to the following:

  • MC68HC908JB16 – Update to V REG LVI trip point – 20-pin SOIC package  MC68HC908JB12  MC68HC08JB16 MC68HC908JB16 This section updates data sheet information and introduces the 20-pin SOIC package for the MC68HC908JB16. VREG LVI Trip Point Page 318, entry for minimum VREG LVI trip point voltage has been updated. From: To: Characteristic Symbol Min Typ Max Unit VREG LVI trip point voltage V LVR 2.0 2.2 2.6 V VREG LVI trip point voltage V LVR 1.9 2.2 2.6 V Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MCU Block Diagram Figure 3 shows the structure of the MC68HC908JB12. Memory Map Figure 4 shows the memory map of the MC68HC908JB12. not apply to the MC68HC908JB12. Table 1. Summary of MC68HC908JB12 and MC68HC908JB16 Differences Dual Clock Generator Module Not implemented. $0051–$0059 unimplemented. Available in 32-pin LQFP only.

  1. The pin assignments are identical for both devices; see data sheet.

Freescale Semiconductor, Inc.

Figure 3. MC68HC908JB12 Block Diagram (2) Pins have integrated pullup device. (3) Pins have software configurable pullup device. (4) Pins are open-drain when configured as output. (6) Pins available on 28-pin package only. (7) On 20-pin package, PTD0 and PTD1 are bonded as a single PTD0/1 pin. Freescale Semiconductor, Inc.

128 Bytes

384 Bytes

448 Bytes

48 Bytes

Figure 4. MC68HC908JB12 Memory Map Freescale Semiconductor, Inc.

PTE4/D– pins are shown in Table 2. Order Numbers These are MC order numbers for MC68HC908JB12. Table 2. Pullup Control on PTE3/D+ and PTE4/D– Pins 1 0 X 1 Do not set this configuration.

  1. External interrupt function is also enabled on PTE4/D– pin.

Table 3. MC68HC908JB12 Order Numbers Freescale Semiconductor, Inc.

ROM device, with exceptions outlined below. MCU Block Diagram Figure 5 shows the block diagram of the MC68HC08JB16. Memory Map Figure 6 shows the memory map of the MC68HC08JB16. and the FLASH block protect register respectively. Table 4. Summary of MC68HC08JB16 and MC68HC908JB16 Differences programming/erasing.Monitor ROM 2 ($FE10–$FFCF) Used for testing purposes only. Dual Clock Generator Module Currently not available. Availa ble in 32-pin LQFP only. 32-pin LQFP currently not available.

  1. The pin assignments are identical for both devices; see data sheet.

Freescale Semiconductor, Inc.

Figure 5. MC68HC08JB16 Block Diagram (2) Pins have integrated pullup device. (3) Pins have software configurable pull-up device. (4) Pins are open-drain when configured as output. (5) Pins available on 32-pin package only. (6) Pins available on 28-pin package only. Freescale Semiconductor, Inc.

Figure 6. MC68HC08JB16 Memory Map Freescale Semiconductor, Inc.

must be submitted to the ROM Processing Center (RPC). Table 5. ROM MC Order Numbers Freescale Semiconductor, Inc.

Addendum to MC68HC908JB16 Technical Data NOTES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Rev. 1 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...