HC646

TC74HC646AP TOSHIBA | Alldatasheet

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TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC OCTAL BUS TRANSCEIVER / REGISTER (3-STATE) The TC74HC646A is high speed CMOS OCTAL BUS TRANSCEIVER /REGISTERs fabricated with silicon gate C’MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. This device is bus transceiver with 3-state outputs, D-type oo S flip-flops, and control circuitry arranged for multiplexed at transmission of data directly from the internal registers. G@ <r AAT yu When the direction input (DIR) is held high, the Al thru A8 24 To yuee become inputs and the B1 thru B8 becom outputs. When the 40 Wu DIR input is held low, the Al thru A8 become output and the B1 thru B8 become inputs. Mi aannaneerra The enable input G is held high, both the A Bus and B Bus eight : 1.509 (Typ.) become high impedance The select inputs (SAB, SBA) can muiltiplex stored and real- time (transparent mode) data. Data on the A Bus or B Bus can be clocked into the registers PIN ASSIGNMENT on the positive going transition of either CAB or CBA clock inputs, respectively. CAB 1 24 Voc All inputs are equipped with protection circuits against static SAB 2 23 CBA discharge or transient excess voltage. DIR 3 22 SBA Al 4 21 G FEATURES: a2 5 20 BI © High Speeds: fay = 73MHZz (typ.) A3 6 19 B2 at Voc = 5V A4 7 18 B3 « Low Power Dissipation +++ loc = 4A(Max.) at Ta = 25°C AS 8 17 Ba « Output Drive Capability----+-----15 LSTTL Loads A7 10 15 B6 « Symmetrical Output Impedance---| lon | =lo = 6MA(Min.) A8 11 14 B7 + Balanced Propagation Delays totH=tpHL GND 12 13 B8 « Wide Operating Voltage Range--- Vcc (opr.) = 2V~6V ¢ Pin and Function Compatible with 74LS646 (TOP VIEW) IEC LOGIC SYMBOL APPLICATION NOTES james Cte i DIR~"T—73EN) (Bal 1) Do not apply a signal to any bus SBA Ga ts terminal when it is in the out put SAB“) PG 0) mode. Damage may result. as ial ee a BI 2) All floating (high impedance) bus Lea, terminals must have their input 19) rages Ma cas re levels fixed by means of pull up or AB fee Bs Hl de iste pull down resistors. Pas a ret Asm es “55 AT Gytp ber 87 ase rey ees 88 980508EBA2 fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook 98-08-18 1/7

[S [om [cas|coa[sae[sea] a] 8 [furan Sid INPUTS | INPUTS |The output functions of A and B Busses are x x x x f Zz 4 disabled. x Both A and B Busses are used as inputs to S| Filx]x x x the internal flip-flops. Data on the Bus will be stored on the rising edge of the Clock. * INPUTS |OUTPUTS The data on the A bus are displayed on the xX |X L x L L B bus. H H L L The data on the A Bus are displayed on the Ff] xttee x H H B Bus, and are stored into the A storage L flip-flops on the rising edge of CAB. The data in the A storage flip-flops are x |x H x x on | displayed on the B Bus. The data on the A Bus are stored into the Pixel a x L L A storage flip-flops on the rising edge of H H CAB, and the stored data propagate directly onto the B Bus. OUTPUTS) INPUTS The data on the B bus are displayed on the X*] X x L L L A bus. H H L L The data on the B Bus are displayed on the xX*) FF] xX L H H A Bus, and are stored into the B storage L L flip-flops on the rising edge of CBA. The data in the B storage flip-flops are x x x Je] on | x displayed on the A Bus. The data on the B Bus are stored into the B x*| F] x L L storage flip-flops on the rising edge of CBA, H H and the stored data propagate directly onto the A Bus. Notes: X : Don’t Care Qn : The data stored into the internal flip-flops by most recent low to high transition of the clock inputs. Z : High Impedance _ * The clocks are not internally gated with either G or DIR. Therefore, data on the A and/or B Busses may be clocked into the storage flip-flops at any time. 980508EBA2" The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may resut from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1998-08-18 2/7

a om a a 7 sap sea YH IMEEM LU ZZ CBA LLL i I ea . <r ZZ et US UE SFSULUU ESE ST 1a orien ere B : Output B: Input B:Z : Don't Care Z: High Impedance SYSTEM DIAGRAM ic > =D: DIR [>o RE»: cas Do—d> CBA [>o d> SAB eA SBA $B Al po D ' Loe} | | RY 4 | —*] 1 ag sawie as AVE" Foe

PARAMETER VALUE UNIT *500mW in the range of Ta= Supply Voltage Range ~ 40°C ~65°C. From Ta=65°C PoC input Vorage [Vn | —O5~Veex0S | _v_| 1 ABC derating facto DC Input Voltage Vin 0.5~Vec +0.5 Vv o OmW/ °C shall Fe applied DC Output Voltage =0.5~Vec + 0.5 until 300mW. DC Output Current DC Vee! Ground Current Storage Temperature —65~150 RECOMMENDED OPERATING CONDITIONS Supply Voltage a Input Voltage Output Voltage Operating Temperature —40~85 0~ 1000 (Vcc = 2.0V) Input Rise and Fall Time tr, tf O~ 500(Vcc = 4.5V) 0~ 400(Vcc = 6.0V) DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION V 7a=25°6 Ta = 40-85°C| unit cc [C5 [an [rve. [wa | wan [ax High - Level 2.0] 1.50 1.50 2.0 0.50 0.50 Low - Level I 20uA 78 44 78 44 High-Level | Vow J Wins [Oke “| 60/59 | 60 59 v utput Volkage WwOrMiL Teu=—6 mA] 45] 4.18 | 431 4.13 lop = 202A 28 08 Low Level Vo. | Mine ose 6.0 0:0 v utput Voltage VinorVin [=e ma | 45 0.17 | 0.26 0.33 3 - State Output Vin=ViworV, Gifvsistecurrent | ox | Varavicoréye | 60] - | - [+05] — [2501 [input Leakage Current [hin | Vin = Vcc or GND [6o| — | = [zo1[ = |z10| “4 Viv = Vcc or GND. [eo{ — [ = [40 | = | 40.0 | 1998-08-18 4/7

TIMING REQUIREMENTS ( Input t, = t;= 6ns) Ta = ~40-85°C TEST CONDITION uinarr—f oir JUN Minimum Pulse Width tw 32 R 98 (CK) tw 6.0 3 16 2.0 65 Minimum Set—up Time t 4.5 13 6.0 u 2.0 5 5 Minimum Hold Time th 45 5 5 6.0 5 5 2.0 6 5 Clock Frequency f 4.5 31 25 MHz 6.0 36 29 AC ELECTRICAL CHARACTERISTICS ( Input t,=t,=6ns) TEST Ta =25°C Ta = ~40-85°C PARAMETER CONDITION [EL(BFVec(W)|-MIN, | TYP. [MAX.| MIN. [MAX. | tr 2.0 25 | 60 75 Output Transition Time te 45 7 12 15 THE 6.0 6 | 10 13 2.0 74 | 150 790 . . 45 21 | 30 38 Propagation Delay Time town 6.0 18 26 32 _ t 2.0 91 | 190 240 BUS—B HL 6.0 22 | 32 41 2.0 98 | 210 265 . - 45 28 | 42 53 Propagation Delay Time town 6.0 24 36 45 _ tone 2.0 716 | 250 315 (CAB, CBA~ BUS) . 150 | 45 33 | “50 63 6.0 23 | 43 54 2.0 81 | 170 215 . . 45 23 | 34 43 Propagation Delay Time tow 6.0 20 29 37 _ ton 2.0 98 | 210 265 (SAB, SBA~ BUS) . 150 | 4:5 28 | (42 53 6.0 24 | 36 45 2.0 384 | 175 220 . 45 24 | 35 44 Output Enable Time toz RLetk 6.0 20 30 37 _ =1kQ - tou 2.0 702 | 215 270 6.0 25 | 37 46 Output Disable Time toz RL=1ka 20 go) 1 a0 (G, DIR—BUS) tonz 6.0 20 30 37 1998-08-18 5/7

AC ELECTRICAL CHARACTERISTICS ( Input t, = t= 6ns ) (Con’d) a= 40-85 SYMBOL | TEST CONDITION] CL | V, UNIT : 2.0| 6 19 5 Maximum Clock Frequency | fax 45] 31 67 25 6.0 | 36 79 29 Input Capacitance Pow fo 8 to T= | 0 | Output Capacitance Povo fo = 8 P= = TT Power Dissipation fSroctance=” [coin] | | oT | - I I Note (1) Cpp is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: Icc (opr) = Cop + Vec + fin + lec / 8 (per bit) 1998-08-18 6/7

DIP 24PIN OUTLINE DRAWING (DIP24-P-300-2.54) Unit in mm i Fy 38 | 6 $9 7 id ae 8 30.3MAx 29.830.2 9520.4 [ o.ssrve z= 1401 _|)05:01 sry Weight : 1.50g (Typ.) TOOT OTST