HC646

M74HC646 STMICROELECTRONICS | Alldatasheet

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HC648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.) HC646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE) B1R (Plastic Package) ORDER CODES : M74HCXXXM1R M74HCX XXB1R M1R (Micro Package) INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) GAB, GAB, CAB, A, B SAB, SBA, CBA .HIGH SPEED f MAX = 73 MHz (TYP.) AT VCC =5V .LOW POWER DISSIPATION ICC =4 µA (MAX.) AT TA =2 5°C .HIGH NOISE IMMUNITY VNIH =V NIL=2 8%V CC (MIN.) .OUTPUT DRIVE CAPABILITY

15 LSTTL LOADS

.SYMMETRICAL OUTPUT IMPEDANCE IOH =IOL = 6 mA (MIN.) .BALANCED PROPAGATION DELAYS tPLH =tPHL .WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V .PIN AND FUNCTION COMPATIBLE WITH 54/74LS646/648

DESCRIPTION

The M74HC646/648 are high speed CMOS OCTAL BUS TRANSCEIVERS AND REGISTERS, (3- STATE) fabricated in silicon gate C2MOS technol- ogy. They have the same high speed performance of LSTTL combined with true CMOS low power con- sumption. These devices consist of bus transceiver circuits with 3-state output, D-type flip-flops, and control cir- cuitry arranged for multiplexed transmission of data directly from the input bus or from the internal reg- isters. Data on the Aor B bus will be clocked into the registers on the low-to-high transition of the appro- priate clock pin (Clock AB - or Clock BA). Enable(G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select controls (Select AB select BA) can multi- plex stored and real-time (transparent mode) data. The direction control determines which bus will re- ceive data when enable G is active (low). In the isolation mode (enable G high), ”A” data may be stored in one register and/or ”B” data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. All inputs are equipped with protection circuits

LOGIC DIAGRAM (HC648) Note :In case of M54/74HC646 outpu t inverter marke d * at A bus and B bus are eliminated. TIMING CHART M74HC646/648

HC646 (The truth table for HC648 is the same as this, but with the outputs inverted) G DIR CAB CBA SAB SBA A B FUNCTION HX INPUTS INPUTS Both the A bus and the B bus are inputs X X X X Z Z The output functions of the A and B bus are disabled X X INPUTS INPUTS Both the A and B bus are used for inputs to the internal flip-flops. Data at the bus will be stored on low to high transition of the clock inputs LH INPUTS OUTPUTS The A bus are inputs and the B bus are outputs X X* L X L L The data at the A bus are displayed at the B bus HH X* L X L L The data at the A bus are displayed at the B bus. The data of the A bus are stored to the internal flip-flop on low to high transition of th clock pulse. HH X X* H X X Qn The data stored to the internal flip-flop are dispayed at the B bus X* H X L L The data at the A bus are stored to the internal flip- flop on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the B bus HH LL OUTPUTS INPUTS The B bus are inputs and the A bus are outputs X* X X L L L The data at the B bus are displayed at the A bus HH X* X L L L The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flip- flop on low to high transition of the clock pulse HH X* X X H Qn X The data stored to the internal flip-flops are displayed at the A bus x* X H L L the data at the B bus are stored to the internal flip- flop on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the A bus HH X : DON’T CARE Z : HIGH IMPEDANCE Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS * : THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO HIGH TRANSITION OF THE CLOCK INPUTS M74HC646/648

PIN No SYMBOL NAME AND FUNCTION

1 CLOCK AB A to B Clock Input (LOW to HIGH, Edge-Trigged)

2 SELECT AB Select A to B Source Input

3 GAB Direction Control Input

4, 5, 6, 7, 8, 9, 10, 11 A1 to A8 A data Inputs/Outputs 20, 19, 18, 17, 16, 15, 14, 13 B1 to B8 B Data Inputs/Outputs

21 G Output Enable Input (Active LOW)

22 SELECT BA Select B to A Source Input

23 CLOCK BA B to A Clock Input (LOW to HIGH, Edge-Triggered)

12 GND Ground (0V)

CC Positive Supply Voltage IEC LOGIC SYMBOLS HC646 HC648 M74HC646/648

Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7 V VI DC Input Voltage -0.5 to V CC + 0.5 V VO DC Output Voltage -0.5 to V CC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Source Sink Current Per Output Pin ± 35 mA ICC or IGND DC V CC or Ground Current ± 70 mA P D Power Dissipation 500 (*) mW Tstg Storage Temperature -65 to +150 oC TL Lead Temperature (10 sec) 300 oC Absolute MaximumRatings are those values beyond whichdamage tothe device may occu r. Functional operation under these condition isnotimplied. (*) 500 mW:≅ 65 oC derate to 300 mW by 10mW/oC: 65oCt o 8 5oC RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit VCC Supply Voltage 2 to 6 V VI Input Voltage 0 to V CC V VO Output Voltage 0 to V CC V Top Operating Temperature -40 to +85 oC tr,tf Input Rise and Fall Time V CC = 2 V 0 to 1000 ns VCC = 4.5 V 0 to 500 VCC = 6 V 0 to 400 M74HC646/648

(V) TA =2 5oC -40 to 85 oC VIH High Level Input Voltage 2.0 1.5 1.5 V4.5 3.15 3.15 6.0 4.2 4.2 V IL Low Level Input Voltage 2.0 0.5 0.5 V4.5 1.35 1.35 6.0 1.8 1.8 V OH High Level Output Voltage 2.0 VI = VIH or V IL IO =-20µA 1.9 2.0 1.9 V 4.5 4.4 4.5 4.4 6.0 5.9 6.0 5.9 4.5 I O =-6.0 mA 4.18 4.31 4.13 VOL Low Level Output Voltage 2.0 VI = VIH or V IL IO =2 0µA 0.0 0.1 0.1 V 4.5 0.0 0.1 0.1 6.0 0.0 0.1 0.1 II Input Leakage Current 6.0 V I =V CC or GND ±0.1 ±1 µA IOZ 3 State Output Off State Current 6.0 VI =V IH or VIL VO =V CC or GND ±0.5 ±5.0 µA ICC Quiescent Supply Current 6.0 V I =V CC or GND 4 40 µA AC ELECTRICAL CHARACTERISTICS (CL =5 0p F ,I n p u ttr =t f =6n s ) Symbol Parameter Test Conditions Value UnitVCC (V) C L (pF) TA =2 5oC -40 to 85 oC tTLH tTHL Output Transition Time 2.0 25 60 75 ns4.5 7 12 15 6.0 6 10 13 tPLH tPHL Propagation Delay Time (BUS - BUS) 2.0 74 150 190 ns4.5 21 30 38 6.0 18 26 32 2.0 150 91 190 240 ns4.5 26 38 48 6.0 22 32 41 t PLH tPHL Propagation Delay Time (CLOCK - BUS) 2.0 98 210 265 ns4.5 28 42 53 6.0 24 36 45 2.0 150 116 250 315 ns4.5 33 50 63 6.0 28 43 54 M74HC646/648

AC ELECTRICAL CHARACTERISTICS (CL =5 0p F ,I n p u ttr =t f =6n s ) Symbol Parameter Test Conditions Value UnitVCC (V) C L (pF) TA =2 5oC -40 to 85 oC tPLH tPHL Propagation Delay Time (SELECT - BUS) 2.0 81 170 215 ns4.5 23 34 43 6.0 20 29 37 2.0 150 98 210 265 ns4.5 28 42 53 6.0 24 36 45 tPZL tPZH 3-State Output Enable Time (G, DIR) 2.0

50 R L =1K Ω

ns4.5 24 35 44 6.0 20 30 37 2.0 150 R L =1K Ω 102 215 270 ns4.5 29 43 54 6.0 25 37 46 tPLZ tPHZ Output Disable Time (G, DIR) 2.0 ns4.5 23 35 44 6.0 20 30 37 fMAX Maximum Clock Frequency 2.0 6 19 4.8 MHz4.5 30 67 24 6.0 35 79 28 tW(H) tW(L) Minimum Clock Pulse Width 2.0 30 75 95 ns4.5 7 15 19 6.0 6 13 16 ts Minimum Set-up Time 2.0 16 50 65 ns4.5 4 10 13 6.0 3 9 11 th Minimum Hold Time 2.0 ns4.5 5 5 6.0 5 5 C IN Input Capacitance 5 10 10 pF C I/O Bus Terminal Capacitance 10 pF C PD (*) Power Dissipation Capacitance for HC646 for HC648 38 pF (*) CPD is defined as the value of the IC’s internal equivalent capac itance which is calculated from the operating current consump tion without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC (opr) = CPD •VCC •fIN +ICC /8 (per bit) M74HC646/648

SWITCHING CHARACTERISTICS TEST CIRCUIT AND WAVEFORM WAVEFORM 1 WAVEFORM 2 WAVEFORM 3 WAVEFORM 4 WAVEFORM 5 M74HC646/648

• INPUT TRANSITION TIME IS THE SAME AS THAT IN CASE OF SWITCHINGCHARACTERISTICSTEST. TEST WAVEFORM I CC (Opr.) M74HC646/648

Plastic DIP24 (0.25) MECHANICAL DATA DIM. mm inch a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 D 32.2 1.268 E 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 27.94 1.100 F 14.1 0.555 I 4.445 0.175 L 3.3 0.130 P043A M74HC646/648

DIM. mm inch A 2.65 0.104 a1 0.10 0.20 0.004 0.007 a2 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45 ° (typ.) D 15.20 15.60 0.598 0.614 E 10.00 10.65 0.393 0.420 e 1.27 0.05 e3 13.97 0.55 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 S8 ° (max.) F C L E A e D b 24 13 11 2 s M74HC646/648

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronicsproducts are not authorized foruse ascritical componentsin life support devices or systems without express written approval of SGS-THOMSON Microelectonics.  1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A M74HC646/648