HC6094 INTERSIL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 9

Technical content

Features

  • 14-Bit 5 MSPS DAC
  • Programmable Gain Stages
  • Anti-Aliasing and Reconstruction Filters

Applications

  • FDM DMT ADSL
  • CAP ADSL
  • EC DMT ADSL
  • Communications Receiver

Description

The HC6094 performs the Analog processing for the ADSL chip set. The transmit chain has a 14 Bit DAC, a third-order Chebyshev reconstruction filter and a programmable attenu- ator (-12 to 0dB) capable of driving a 220Ω differential load. The receiver chain has a high impedance input stage, pro- grammable gain stage (0 to 24dB), additional programmable gain (-9 to 18dB) and a third-order Chebyshev anti-aliasing filter for driving an off-chip A/D. Laser trimmable thin-film resistors are used to set the filter cutoff frequency and DAC linearity. The transmit and receive signal chains are specified at 65dB MTPR. Pinout HC6094 (MQFP) TOP VIEW

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. NO. HC6094IN -40 to 85 44 Ld MQFP Q44.10x10 12 13 14 15 16 17 2221201918 39 38 37 36 35 34 44 43 42 41 40 VSSA_ATT VDDA_TX VSSA_TX ARTN VDDD_RX CS SDI RST SCLK GNDD__RX GNDA_RX D11 D10 D0 (LSB) RXO+ RXO- VSSA_RX VDDA_RX PGAI- PGAI+ PGAO+ PGAO- RXI+ RXI- D12 D13 (MSB) VDDD_TX CLK GNDD_TX CTLIN CTLOUT GNDA_TX VDDA_ATT TXO- TXO+ CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1999 File Number 4260.2 [ /Title (HC60 94) /Sub- ject (ADSL Ana- log Front End Chip) /Autho r () /Key- words (Har- ris Semi- con- ductor, Tele- com, SLICs, SLACs , Tele- phone, Tele- phony, WLL, Wire- less Local Loop, PBX, Pri- vate Branch Exchan ge, NT1+, CO, Cen- OBSOLETE PRODUCT NO RECOMMENDED REPLA CEMENT Call Central Applications 1-800-442-7747or email: centapp@harris.com

SHIFT REGISTER AND LATCHES D0-D13 SCLK SDI CS TX O± RST RXI±RXO + PGA2 PGA1 DAC PGA0 1.1MHz LPF 1ST ORDER 1.1MHz LPF 2ND ORDER 1.1MHz LPF 1ST ORDER 1.1MHz LPF 2ND ORDER PGAO ±PGAI ± TRANSMITTERCLK LATCH -12 TO 0dB -9 TO 18dB 0 TO 24dB RECEIVER SHIFT REGISTER AND LATCHES D0-D13 SCLK SDI CS TX O± RST RXI±RXO ± PGA2 PGA1 DAC PGA0 R L = 220 CLK PGA OUTPGA IN CTLIN CTLOUT VSSA_TX VDDD_TX, RX GNDD_TX, RX VDDA_TX, RX VSSA_TX, RX +5V +5V -5V GNDA_RX, TX 1.1MHz LPF 1ST ORDER 1.1MHz LPF 2ND ORDER 1.1MHz LPF 1ST ORDER 1.1MHz LPF 2ND ORDER R L = 2000 -12 TO 0dB -9 TO 18dB 0 TO 24dB HC6094

Absolute Maximum Ratings TA =2 5oC Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) θJA (oC/W) Maximum Junction Temperature (T (Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsVDD =5 V ,VSS = -5V, RL Open, Over Temperature Range; Unless Otherwise Specified. Designed for±5% Power Supply. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OVERALL Supply Currents I DD VDD (Note 2) - 66 - mA ISS VSS (Note 3) - -79 - mA ICC VCC -0 - µA Power Dissipation PD Quiescent, No Load - 725 - mW DIGITAL INTERFACE Input Voltage Thresholds V IL - - 0.8 V VIH 2.7 - - V Input Currents I IL VIN = 0V -10.0 0 10.0 µA IIH VIN = VDD -10.0 0 10.0 µA Serial Clock Period T1 0.1 - 5.0 µs CS Active Before Shift Edge T2 T1/2 -10 - - ns Write Data Valid After Shift Edge T3 - - 10 ns CS Inactive After Latch Edge T4 T1 - 10 - T1 +10 ns Write Data Hold After Latch Edge T5 T1/2 -5 - T1/2 +5 ns DAC Setup Time t S - - 100 ns DAC Hold Time t H - - 100 ns 14-BIT DAC Resolution/Monotonicity 14 - - Bits Integral Linearity I LE Measured at TX Outputs - ±1.5 - LSB Differential Linearity D LE - ±0.9 - LSB Max Sample Rate 4.416 - - Ms/s TRANSMITTER OUTPUT Output Drive TXOD Sink or Source 30 55 - mA Differential Output Swing TXOS R L = 220Ω 11.7 12.03 12.3 V PP Differential Balance TXDB Gain Match Between Outputs - 0.5 - % Transmit Output Offset TXOFF Max Gain Single Ended (Note 4) -200 25 200 mV Multi-Tone Power Ratio TXMTPR R L = 220Ω -6 5 - d B Power Supply Rejection PSRR Input Referred - V DD 40 65 - dB Input Referred - VSS 55 84 - dB HC6094

Gain Error TXPG R L = 220Ω , 0dB Setting -0.22 +0.02 0.22 dB R L= 220Ω , Each Step Relative to 0dB -0.15 0.02 0.15 dB TRANSMITTER FREQUENCY RESPONSE Gain Ripple Peak to Peak GP Across 1.104MHz Bandwidth - 0.2 0.6 dB Stopband Attenuation GS At 2.65MHz 14 17 - dB Floor Attenuation GM At 9.94MHz - 58 - dB RECEIVER INPUT (PGA1 AND PGA2) Input Swing RXIS Differential - - 12 V PP Input Impedance RXRIN PGA1 1.0 - M Ω PGA2 1.0 12 - k Ω Common Mode Rejection RXCMRR 1.1MHz - 90 - dB Common Mode Range RXCMIR -0.25 - 0.25 V Continuous Input Voltage V SS -0.5 V DD +0.5 V RECEIVER OUTPUT (INCLUDING PGA1 OUT) Differential Output Swing RXOS RX OUT (RL = 2000Ω ) 12.0 15.8 - V PP PGA1 OUT (RL = 2000Ω ) 12.0 16.0 - V PP Differential Balance RXDB End to End (RX IN to RXOUT ) - 0.5 - % PGA1 Output Offset RXOFF Max Gain Single Ended (Note 4) -200 40 200 mV PGA2 Output Offset RXOFF Max Gain Single Ended (Note 4) -200 30 200 mV Multi-Tone Power Ratio RXMTPR R L = 2000Ω -6 5 - d B Power Supply Rejection PSRR Input Referred - V DD 45 69 - dB Input Referred - VSS 55 84 - dB RECEIVER GAIN STAGE Absolute Gain Error RXPG Any Step (RX IN to RXOUT ) -0.3 0.01 0.3 dB RECEIVER FREQUENCY RESPONSE Gain Ripple Peak to Peak GP Across 1.104MHz Bandwidth - 0.4 0.6 dB Stopband Attenuation GS At 2.65MHz 14 19.4 - dB Floor Attenuation GM At 9.94MHz - 53 - dB TRANSMITTER AND RECEIVER FILTER CUTOFF FREQUENCY TX Filter F C TX FC -0.15dB point 1.104 1.18 1.25 MHz RX Filter FC RX FC -0.15dB point 1.104 1.125 1.16 MHz NOTES: 2. VDD = 5V typical, supply range±5%. 3. VSS = -5V typical, supply range±5%. 4. Single ended operation for reference only. Probed to these limits, but not packaged tested. Electrical SpecificationsVDD =5 V ,VSS = -5V, RL Open, Over Temperature Range; Unless Otherwise Specified. Designed for±5% Power Supply. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS HC6094

Definitions 1. Supply currents/power dissipation measured in a quiescent (static) state with RL open. 2. Logic input levels and timing are verified by using them as conditions for testing DAC and filter. 3. Digital input currents are measured at 0V and V CC . 4. DAC resolution and monotonicity guaranteed by ILE and DLE tests. 5. DAC ILE is relative to best fit straight line. 6. Output drive current is the output current at 0V for each output when they are driven to ± Full Scale. 7. Output offset measured with V IN = 0V differential for the RX, and the DAC at mid scale for the TX. 8. PSRR is the change in differential input voltage vs. change in supply voltage at DC. 9. T X Gain is calculated as 20*Log((TXoutDACFS - TXoutDACZS )/12V) at DC. 10. RX input swing is verified by using this as condition for gain testing. 11. RX Input Impedance is calculated asΔVIN/ΔIIN where VIN is the maximum input voltages, with the PGA set to 0dB. 12. RX CMRR is calculated as 20*Log(VOUT /VIN)-PGA Gain. VIN is set to 250mVPEAK (CMIR) at 1.1MHz, and PGA gain is set to maximum. 13. RX Gain is calculated as 20*Log(dVOUT /dVIN), where VIN is set to give a nominal± Output Swing, or the maximum input swing, whichever is smaller. It is tested DC. 14. Filter Gain/Attenuation is relative to low frequency passband gain. TX tested by driving the DAC (with sinX/X correction), R X tested by driving PGA2. Wafer probe will use special test points to bypass the DAC for laser trimming. 15. MTPR - (Multi-Tone Power Ratio). A DMT waveform is generated which has a specific crest factor or peak to average ratio (PAR) with specific carriers missing. The waveform is then passed through the TX or RX chain. The total integrated power of the notch at the location of the missing carriers is measured with respect to the adjacent carriers. Notch depth is mea- sured for several DMT waveforms with different PARs. The notch depths for each DMT waveform are averaged to give an MTPR number. HC6094

control register, and D7-D0 supply the data.

0000 A 0A 1A 2A 3 D 0D 1D 2D 3D 4D 5D 6D 7

FIGURE 1. SERIAL CONTROL FIGURE 2. SERIAL INTERFACE FIGURE 3. DAC INTERFACE

REGISTER A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7 RX Gain 1 0 X X PGA1 Gain PGA2 Gain TX Gain 0 0 X X PGA0 Gain TX PGA0 GAIN D2 D1 D0 GAIN IN dB 1 1 X -12 1 0 1 -10 100 - 8 011 - 6 010 - 4 001 - 2 000 0 RX PGA1 GAIN D3 D2 D1 D0 GAIN IN dB 0000 0 0001 3 0010 6 0011 9 0100 1 2 0101 1 5 0110 1 8 0111 2 1 1XXX 2 4 NOTE: PGA1 is an inverting amplifier. RX PGA2 GAIN D7 D6 D5 D4 GAIN IN dB 0000 - 9 0001 - 6 0010 - 3 0011 0 0100 3 0101 6 0110 9 0111 1 2 1XX0 1 5 1XX1 1 8 G P -GP G S 2.651.104 9.94 G M FREQUENCY (MHz) AVERAGE PASSBAND GAIN HC6094

43, 44 D13-D12 Digital Input bits 13 and 12. D13 is MSB. 1-12 D11-D0 Digital Input bits 11 thru 0. D0 is LSB. 13, 14 RXO ± Receiver differential outputs. 15 VSSA_RX Receiver -5V supply. 16 VDDA_RX Receiver +5V supply. 17, 18 PGAI ± PGA2 differential inputs. 19, 20 PGAO ± PGA1 differential outputs. 21, 22 RXI ± Receiver differential inputs (PGA1 inputs). 23 GNDA_RX Receiver ground. 24 GNDD_RX Serial interface ground. 25 SCLK Serial interface clock pin. RST Serial interface reset pin. 27 SDI Serial interface data input. CS Serial interface chip select. 29 VDDD_RX Shift register Digital +5V supply. 30 ARTN Analog return (ground). 31 VSSA_TX Transmitter -5V supply. 32 VDDA_TX Transmitter +5V supply. 33 VSSA_ATT Attenuator -5V supply. 34, 35 TXO ± Transmitter differential outputs. 36 VDDA_ATT Attenuator +5V supply. 37 GNDA_TX Analog ground for transmitter. 38 CTLOUT Control Amplifier Output. Provides precision control of the current sources. Typically connected to CTLIN. 39 CTLIN Input to the Current Source Base Rail. Typically connected to CTLOUT. Requires a 0.1 µF capacitor to VSSA_TX. Allows external decoupling of the current sources. 40 GNDD_TX Digital Ground. 41 CLK DAC input latch clock. 42 VDDD_TX DAC digital +5V supply. HC6094

Metric Plastic Quad Flatpack Packages (MQFP/PQFP) D E E1 -A- PIN 1 A2 A1 A 5o-16o 5o-16o 0o-7o 0.40 0.016MIN L 0o MIN PLANE B 0.005/0.009 0.13/0.23WITH PLATING BASE METAL SEATING 0.005/0.007 0.13/0.17 -B- e 0.008

0.20 A-B SD SC M

0.10 0.004 -C- -D- -H- Q44.10x10 (JEDEC MO-108AA-2 ISSUE A)

44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

A - 0.093 - 2.35 - A1 0.004 0.010 0.10 0.25 - A2 0.077 0.083 1.95 2.10 - B 0.012 0.018 0.30 0.45 6 B1 0.012 0.016 0.30 0.40 - D 0.510 0.530 12.95 13.45 3 D1 0.390 0.398 9.90 10.10 4, 5 E 0.510 0.530 12.95 13.45 3 E1 0.390 0.398 9.90 10.10 4, 5 L 0.026 0.037 0.65 0.95 - N4 4 4 47 e 0.032 BSC 0.80 BSC - Rev. 1 1/94 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane . 4. Dimensions D1 and E1 to be determined at datum plane 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. -C- -H- HC6094