HC55142

HC55120 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

Ultra Low Active Power (OHT) < 60mW
Single/Dual Battery Operation
Automatic Silent Battery Selection
Power Management/Shutdown
Battery Tracking Anti Clipping
Single 5V Supply with 3V Compatible Logic
Zero Crossing Ring Control - Zero Voltage On/Zero Current Off
Tip/Ring Disconnect
Pulse Metering Capability
4 Wire Loopback
Programmable Current Feed
Programmable Resistive Feed
Programmable Loop Detect Threshold
Programmable On-Hook and Off-Hook Overheads
Programmable Overhead for Pulse Metering
Programmable Polarity Reversal Time
Selectable Transmit Gain 0dB/-6dB
2 Wire Impedance Set by Single Network
Loop and Ground Key Detectors
On-Hook Transmission
Common Pinout
HC55121 - Polarity Reversal
HC55130 - -63dB Longitudinal Balance
HC55140 - Polarity Reversal - Ground Start - Line Voltage Measurement - 2 Wire Loopback - -63dB Longitudinal Balance
HC55142 - Polarity Reversal - Ground Start - Line Voltage Measurement - 2.2V RMS Pulse Metering - 2 Wire Loopback
HC55150 - Polarity Reversal - Line Voltage Measurement - 2.2V RMS Pulse Metering - 2 Wire Loopback

Applications

Related Literature - AN9871, User’s Guide for UniSLIC14 Eval Board RRLY DT DR TIP RING VBH VCC RING AND TEST RELAY DRIVERS RING TRIP DETECTOR VBL BGND BATTERY SELECTION AND BIAS NETWORK ZERO CURRENT 2-WIRE INTERFACE CROSSING TRLY1 TRLY2 VTX VRX GKD_ LVM ROH RD CDC RDC_RAC ZT C H LOOP CURRENT DETECTOR PTG ILIM STATE DECODER AND DETECTOR LOGIC GKD/LOOP LENGTH DETECTOR RSYNC_REV SHD 4-WIRE INTERFACE VF SIGNAL PATH LINE FEED CONTROL CRT_REV_ LVMPOLARITY REVERSAL PULSE METERING SPM SIGNAL PATH AGND Data Sheet June 2000

Ordering Information

(mA) POLARITY REVERSAL GND START GND KEY LINE VOLTAGE MEASUREMENT PULSE METERING

2 TEST

2 WIRE

(oC) PKG. NO. HC55120CB 30 • 53dB 0 to 70 M28.3 SOIC HC55120CM 30 • 53dB 0 to 70 N28.45 PLCC HC55121IB 30 •• • • 53dB -40 to M28.3 SOIC HC55121IM 30 •• • • 53dB -40 to N28.45 PLCC HC55130IB 45 63dB -40 to M28.3 SOIC HC55130IM 45 63dB -40 to N28.45 PLCC HC55131IM 45 • 63dB -40 to N32.45x55 PLCC HC55140IB 45 •• • • • 63dB -40 to M28.3 SOIC HC55140IM 45 •• • • • 63dB -40 to N28.45 PLCC HC55141IM 45 •• • • • • 63dB -40 to N32.45x55 PLCC HC55142IB 45 •• • • • • 63dB -40 to M28.3 SOIC HC55142IM 45 •• • • • • 63dB -40 to N28.45 PLCC HC55143IM 45 •• • • •• • 63dB -40 to N32.45x55 PLCC HC55150CB 45 •• • • 55dB 0 to 70 M28.3 SOIC HC55150CM 45 •• • • 55dB 0 to 70 N28.45 PLCC HC55151CM 45 •• • • • 55dB 0 to 70 N32.45x55 PLCC HC5514XEVAL1 Evaluation board † Available by placing SLIC in Test mode. Device Operating Modes C3 C2 C1 DESCRIPTION HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1 0 0 0 Open Circuit 4-Wire Loopback 0 1 1 Test Forward Active

2 Wire Loopback and

••• 1 0 0 Tip Open Ground Start •• 1 1 0 Reverse Active • ••• 1 1 1 Test Reverse Active Line Voltage Measurement
•• HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Absolute Maximum RatingsTA =2 5oC Thermal Information Temperature, Humidity Power Supply (-40oC ≤ TA ≤ 85oC) Relay Driver Digital Inputs, Outputs (C1, C2, C3, C4, C5, SHD, GKD_ LVM) Tipx and Ringx Terminals (-40 oC ≤ TA ≤85oC) Thermal Resistance (Typical, Note 1) θJA Continuous Power Dissipation at 85oC oC (PLCC, SOIC - Lead Tips Only) Der ate above 70oC Tip and Ring Terminals Tipx or Ringx, Pulse < 250ns, TREP > 10s 20A CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Typical Operating Conditions These represent the conditions under which the device was developed and are suggested as guidelines. PARAMETER CONDITIONS MIN TYP MAX UNITS Ambient Temperature HC55120, HC55150/1 0 - 70 oC HC55121, HC55130/1, HC55140/1, HC55142/3 -40 - 85 oC VBH with Respect to GND -58 - -8 V VBL with Respect to GND VBH -0 V VCC with Respect to GND 4.75 - 5.25 V HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

OFF-HOOK LONGITUDINAL BALANCE MIN MIN MIN MIN MIN MIN Longitudinal to Metallic (Note 7) Forward and Reverse IEEE 455 - 1985, RLR , RLT = 368Ω Normal Polarity: Forward Only Forward Only 0.2kHz < f < 1.0kHz, 0oC to 70oC - - - dB 53 NA NA NA NA 55 1.0kHz < f < 3.4kHz, 0oC to 70oC - - - dB 53 NA NA NA NA 55 0.2kHz < f < 1.0kHz, -40oC to 85oC - - - dB NA 53 63 63 63 NA 1.0kHz < f < 3.4kHz, -40oC to 85oC - - - dB NA 53 58 58 58 NA Reverse Polarity 0.2kHz < f < 3.4kHz, (Figure 4) --- d B N A 5 3 N A 5 8 5 8 5 5 MIN MIN MIN MIN MIN MIN Longitudinal to Metallic (Note 7) Forward and Reverse R LR , RLT = 300Ω , Normal Polarity: Forward Only Forward Only 0.2kHz < f < 1.0kHz, 0oC to 70oC - - - dB 53 NA NA NA NA 55 1.0kHz < f < 3.4kHz, 0oC to 70oC - - - dB 53 NA NA NA NA 55 0.2kHz < f < 1.0kHz, -40oC to 85oC - - - dB NA 53 63 63 63 NA 1.0kHz < f < 3.4kHz, -40oC to 85oC - - - dB NA 53 58 58 58 NA Reverse Polarity 0.2kHz < f < 3.4kHz, (Figure 4) --- d B N A 5 3 N A 5 8 5 8 5 5 MIN MIN MIN MIN MIN MIN Longitudinal to 4-Wire (Note 9) (Forward and Reverse) Normal Polarity: Forward Only Forward Only 0.2kHz < f < 1.0kHz, 0oC to 70oC - - - dB 53 NA NA NA NA 61 1.0kHz < f < 3.4kHz, 0oC to 70oC - - - dB 53 NA NA NA NA 61 0.2kHz < f < 1.0kHz, -40oC to 85oC - - - dB NA 53 63 63 63 NA 1.0kHz < f < 3.4kHz, -40oC to 85oC - - - dB NA 53 58 58 58 NA Reverse Polarity 0.2kHz < f < 3.4kHz, (Figure 4) - - dB NA 53 NA 58 58 61 Metallic to Longitudinal (Note 10) Forward and Reverse FCC Part 68, Para 68.310 (Note 8) 0.2kHz < f < 3.4kHz, (Figure 5) 40 50 - dB Forward Only • Forward Only ••• 4-Wire to Longitudinal (Note 11) Forward and Reverse 0.2kHz < f < 3.4kHz, (Figure 5) 40 - - dB Forward Only

Forward Only ••• to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1 HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

•••PTG = Open (Note 19, Figure 8) -0.2 - 0.2 dB Forward Only Forward OnlyPTG = GND (Note 20, Figure 8) -6.22 -6.02 -5.82 dB 4-Wire to 2-Wire Forward and Reverse 0dBm, 1kHz (Note 21, Figure 8) -0.2 - 0.2 dB Forward Only • Forward Only ••• GAIN TRACKING (Ref = -10dBm, at 1.0kHz) 2-Wire to 4-Wire Forward and Reverse -40dBm to +3dBm (Note 22, Figure 8) -0.1 - 0.1 dB Forward Only • Forward Only •••-55dBm to -40dBm (Note 22, Figure 8) -0.2 - 0.2 dB 4-Wire to 2-Wire Forward and Reverse -40dBm to +3dBm (Note 23, Figure 8) -0.1 - 0.1 dB Forward Only • Forward Only •••-55dBm to -40dBm (Note 23, Figure 8) -0.2 - 0.2 dB NOISE Idle Channel Noise at 2-Wire C-Message Weighting - 10.5 13 dBrnC Forward Only Forward Only •••Forward and Reverse Psophometric Weighting (Note 24, Note 30, Figure 9) - -79.5 -77 dBmp Idle Channel Noise at 4-Wire C-Message Weighting - 10.5 13 dBrnC Forward Only • Forward Only •••Forward and Reverse Psophometrical Weighting (Note 25, Note 30, Figure 9) - -79.5 -77 dBmp HARMONIC DISTORTION 2-Wire to 4-Wire Forward and Reverse 0dBm, 0.3kHz to 3.4kHz (Note 26, Figure 7) - -67 -50 dB Forward Only • Forward Only ••• 4-Wire to 2-Wire Forward and Reverse 0dBm, 0.3kHz to 3.4kHz (Note 27, Figure 8) - -67 -50 dB Forward Only
Forward Only •••

FIGURE 10. CONSTANT LOOP CURRENT TOLERANCE FIGURE 11. TIPX VOLTAGE

BATTERY FEED CHARACTERISTICS Constant Loop Current Tolerance 18mA≤ IL≤ 45mA, Forward Only • Forward Only •••IL = 26.5mA, RLIM = 38.3kΩ Forward and Reverse (Note 27, Figure 10) 0.92I L IL 1.08IL mA Tip Open State TIPX Leakage Current S = Closed (Figure 11) - - -200 µA •••••• Tip Open State RINGX Current R 1 = 0Ω , VBH = -48V, RLIM = 38.3kΩ 22.6 26.8 31 mA

•••••R 1 = 2.5kΩ , VBH = -48V (Figure 11) 15.5 17.1 18.2 mA Tip Open State RINGX Voltage 5mA < IR1 < 26mA (Figure 11) - 42.8 - V •••••• Tip Voltage (Ground Start) Active State, (S Open) R1 = 150Ω (Figure 11) -5.3 -4.8 -4.3 V NA NA NA •• NA Tip Voltage (Ground Start) Active State, (S Closed) Tip Lead to
•-48V Through 7kΩ , Ring Lead to Ground Through 150Ω (Figure 11) -5.3 -4.8 -4.3 V NA NA NA NA Open Circuit State Loop Current (Active) RL = 0Ω -20 0 20 µA •••••• LOOP CURRENT DETECTOR Programmable Threshold I LTh = (500/ RD )≥ 5mA, 0.9I LTh ILTh 1.1ILTh mA Forward Only • Forward Only •••Forward and Reverse I LTh = 8.5mA R D = 58.8kΩ GROUND KEY DETECTOR Ground Key Detector Threshold Tip/Ring Current Difference Tip Open 5 8 11 mA NA NA Active (Note 29, R1 = 2.5kΩ , Figure 12) 12.5 20 27.5 mA LINE VOLTAGE MEASUREMENT RING TRIP DETECTOR (DT, DR) Ring Trip Comparator Current Source Res = 2MΩ -2- µA Input Common-Mode Range Source Res = 2M Ω -- ±200 V •••••• to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1 HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

FIGURE 12. GROUND KEY DETECT

POWER DISSIPATION (V BH = -48V, VBL = -24V) Open Circuit State C1, C2, C3 = 0, 0, 0 - 25 - mW Forward Only • Forward Only ••• On-Hook, Active C1, C2, C3 = 0, 1, 0 Forward and Reverse I L = 0mA, Longitudinal Current = 0mA - 52 - mW Forward Only • Forward Only ••• POWER SUPPLY CURRENTS (V BH = -48V, VBL = -24V) VCC Current, ICC Open Circuit State - 2.25 3.0 mA Forward Only • Forward Only ••• VBH Current, IBH - 0.3 0.45 mA Forward Only • Forward Only ••• VBL Current, IBL - 0.022 0.035 mA Forward Only • Forward Only ••• VCC Current, ICC Forward and Reverse Active State IL = 0mA, Longitudinal Current = 0mA - 2.7 3.6 mA Forward Only • Forward Only ••• VBH Current, IBH Forward and Reverse - 0.8 1.06 mA Forward Only • Forward Only ••• VBL Current, IBL Forward and Reverse - - 0.01 mA Forward Only • Forward Only ••• POWER SUPPLY REJECTION RATIOS VCC to 2 or 4 Wire Port Forward and Reverse Active State RL = 600Ω 50Hz < f < 3400Hz, VIN =100mV - 40 - dB Forward Only • Forward Only ••• VBH to 2 or 4 Wire Port Forward and Reverse - 40 - dB Forward Only • Forward Only ••• VBL to 2 or 4 Wire Port Forward and Reverse - 40 - dB Forward Only • Forward Only ••• TEMPERATURE GUARD Junction Threshold Temperature - 175 - oC• ••••• to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1 HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Overload Level (Two-Wire Port, Off Hook) -The overload level is specified at the 2-wire port (VTR ) with the signal source at the 4-wire receive port (ERX ). RL = 600Ω , IDCMET ≥ 18mA. Increase the amplitude of ERX until 1% THD is measured at VTR . Reference Figure 1. 3. Overload Level (Two-Wire Port, On Hook) -The overload level is specified at the 2-wire port (VTR ) with the signal source at the 4-wire receive port (ERX ). RL =∞ , IDCMET = 0mA. Increase the amplitude of ERX until 1% THD is measured at VTR . Reference Figure 1. 4. Longitudinal Impedance -The longitudinal impedance is computed using the following equations, where TIP and RING voltages are referenced to ground. L ZT,LZR ,VT,VR ,AR and AT are deﬁned in Figure 2. (TIP) L ZT = VT/AT (RING) LZR = VR /AR where: EL = 1VRMS (0Hz to 100Hz) 5. Longitudinal Current Limit (On-Hook Active) -On-Hook longitudinal current limit is determined by increasing the (60Hz) amplitude of E L (Figure 3A) until the 2-wire longitudinal current is greater than 28mARMS /Wire. Under this condition,SHD pin remains low (no false detection) and the 2-wire to 4-wire longitudinal balance is veriﬁed to be greater than 45dB (LB 2-4= 20log VTX/EL). 6. Longitudinal Current Limit (Off-Hook Active) -Off-Hook longitudinal current limit is determined by increasing the (60Hz) amplitude of E L (Figure 3B) until the 2-wire longitudinal current is greater than 28mARMS /Wire. Under this condition,SHD pin remains high (no false detection) and the 2-wire to 4-wire longitudinal balance is veriﬁed to be greater than 45dB (LB 2-4= 20log VTX/EL). 7. Longitudinal to Metallic Balance -The longitudinal to metallic balance is computed using the following equation: BLME = 20 log (EL/VTR ), where: EL and VTR are deﬁned in Figure 4. 8. Metallic to Longitudinal FCC Part 68, Para 68.310 -The metallic to longitudinal balance is deﬁned in this spec. 9. Longitudinal to Four-Wire Balance -The longitudinal to 4-wire balance is computed using the following equation: BLFE = 20 log (EL/VTX ), EL and VTX are deﬁned in Figure 4. 10. Metallic to Longitudinal Balance -The metallic to longitudinal balance is computed using the following equation: BMLE = 20 log (ETR /VL), ERX = 0 where: ETR, VL and ERX are deﬁned in Figure 5. 11. Four-Wire to Longitudinal Balance -The 4-wire to longitudinal balance is computed using the following equation: BFLE = 20 log (ERX /VL), ETR = source is removed. where: ERX, VL and ETR are deﬁned in Figure 5. 12. Two-Wire Return Loss -The 2-wire return loss is computed using the following equation: r = -20 log (2V M /VS) where: ZD = The desired impedance; e.g., the characteristic impedance of the line, nominally 600Ω. (Reference Figure 6). 13. Overload Level (4-Wire Port Off-Hook) -The overload level is speciﬁed at the 4-wire transmit port (VTX ) with the signal source (EG ) at the 2-wire port, ZL = 20kΩ, R L = 600Ω (Reference Figure 7). Increase the amplitude of EG until 1% THD is measured at VTX . Note the PTG pin is open, and the gain from the 2-wire port to the 4-wire port is equal to 1. 14. Overload Level (4-Wire Port On-Hook) -The overload level is speciﬁed at the 4-wire transmit port (VTX ) with the signal source (EG ) at the 2-wire port, ZL = 20kΩ, R L = ∞ (Reference Figure 7). Increase the amplitude of EG until 1% THD is measured at VTX . Note the PTG pin is open, and the gain from the 2-wire port to the 4-wire port is equal to 1. 15. Output Offset Voltage -The output offset voltage is speciﬁed with the following conditions: E G =0 ,RL = 600Ω ,ZL = ∞ and is measured at VTX . EG ,R L, VTX and ZL are deﬁned in Figure 7. 16. Two-Wire to Four-Wire Frequency Response -The 2-wire to 4-wire frequency response is measured with respect to E G = 0dBm at 1.0kHz, ERX = 0V (VRX input floating), RL = 600Ω . The frequency response is computed using the following equation: F2-4= 20 log (VTX /VTR ), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTX , VTR ,R L and EG are deﬁned in Figure 8. 17. Four-Wire to Two-Wire Frequency Response -The 4-wire to 2- wire frequency response is measured with respect to ERX = 0dBm at 1.0kHz, EG source removed from circuit, RL = 600Ω . The frequency response is computed using the following equation: F4-2= 20 log (VTR /ERX ), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTR ,R L and ERX are deﬁned in Figure 8. 18. Four-Wire to Four-Wire Frequency Response -The 4-wire to 4-wire frequency response is measured with respect to E RX = 0dBm at 1.0kHz, EG source removed from circuit, R L = 600Ω . The frequency response is computed using the following equation: F4-4= 20 log (VTX /ERX ), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTX ,R L and ERX are deﬁned in Figure 8. 19. Two-Wire to Four-Wire Insertion Loss (PTG = Open) -The 2-wire to 4-wire insertion loss is measured with respect to E G = 0dBm at 1.0kHz input signal, ERX = 0 (VRX input floating), R L = 600Ω and is computed using the following equation: L2-4 = 20 log (VTX /VTR ) where: VTX , VTR ,R L and EG are deﬁned in Figure 8. (Note: The fuse resistors, RF, impact the insertion loss. The speciﬁed insertion loss is for RF1 = RF2 = 0). 20. Two-Wire to Four-Wire Insertion Loss (PTG = AGND) -The 2-wire to 4-wire insertion loss is measured with respect to EG = 0dBm at 1.0kHz input signal, ERX = 0 (VRX input floating), RL = 600Ω and is computed using the following equation: L2-4 = 20 log (VTX /VTR ) where: VTX , VTR ,R L and EG are deﬁned in Figure 8. (Note: The fuse resistors, RF, impact the insertion loss. The speciﬁed insertion loss is for RF1 = RF2 = 0). 21. Four-Wire to Two-Wire Insertion Loss -The 4-wire to 2-wire insertion loss is measured based upon ERX = 0dBm, 1.0kHz input signal, EG source removed from circuit, RL = 600Ω and is computed using the following equation: L4-2 = 20 log (VTR /ERX ) where: VTR ,RL and ERX are deﬁned in Figure 8. 22. Two-Wire to Four-Wire Gain Tracking -The 2-wire to 4-wire gain tracking is referenced to measurements taken for E G = -10dBm, 1.0kHz signal, ERX = 0 (VRX output ﬂoating), R L = 600Ω and is computed using the following equation. G 2-4=2 0• log (VTX /VTR ) vary amplitude -40dBm to +3dBm, or -55dBm to -40dBm and compare to -10dBm reading. VTX ,R L and VTR are deﬁned in Figure 8. HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

protection resistors (RP), the required (peak) off hook voltage for speech (Vsp(off)) and the required (peak) off hook voltage for the pulse metering (Vpm(off)), if applicable. The off hook overhead voltage is deﬁned in Equation 2 and calculated using Equation 3. where: VOH(off) at Load = Off hook overhead voltage at load VOH (Rsense) = Required overhead for the DC voltage drop across sense resistors (2RS x Iloop(max)) Vsp(off) = Required (peak) off hook AC voltage for speech Vpm(off)= Required (peak) off hook AC voltage for pulse metering where: 80 = 2Rs + 2RINT (reference Figure 17) Zpm = Pulse metering load impedance (typically 200Ω ). 2.0V = Additional off hook overhead voltage requirement R SAT Resistance Calculation The RSAT resistance of the DC feed curve is used to determine the value of the RDC_RAC resistor (Equation 6). The value of this resistor has an effect on both the on hook and off hook overheads. In most applications the off hook condition will dominate the overhead requirements. Therefore, we’ll start by calculating the R SAT value for the off hook conditions and then verify that the on hook conditions are also satisﬁed. When considering the Off hook condition, R SAT is equal to VOH(off) at Load divided by Iloop(min) (Equation 4). For the given system requirements (recommended application circuit in back of data sheet): Iloop (min) = 20mA, Iloop (max) = 30mA, V sp(off)= 3.2VPEAK , Vspm(off)= 0VPEAK , VOH(off) at Load = 8.34V the value of RSAT(off) is equal to 417Ω as calculated in Equation 4. Before using this RSAT value, to calculate the RDC_RAC resistor, we need to verify that the on hook requirements will also be met. The on hook overhead voltage calculated with the off hook R SAT (RSAT(off)), is given in Equation 5 and equals 3.0V. The on hook overhead calculated with Equation 1 equals 2.85V for the given system requirements (recommended application circuit in back of data sheet): Switch Hook Detect threshold = 12mA, ISH- = (0.6)12mA = 7.2mA, V sp(on)= 0.775VRMS Thus, the on hook overhead requirements of 2.85V will be met if we use the R SAT(off) value. If the on hook overhead requirement is not met, then we need to use the RSAT(on)value to determine the RDC_RAC resistor value. The external saturation guard resistor RDC_RAC is equal to 50 times R SAT. In the example above RSAT would equal 417Ω and RDC_RAC would then equal to 20.85kΩ (closest standard value is 21kΩ ). The Switch Hook Detect threshold current is set by resistor R D and is calculated using Equation 7. For the above example RD is calculated to be 41.6kΩ (500/12mA). The next closest standard value is 41.2kΩ. The true value of ISH-, for the selected value of RD is given by Equation 8: For the example above, ISH- equals 7.28mA (500 x 0.6/ 41.2K). Verify that the value of ISH- is above the suspected line leakage of the application. The UniSLIC family will provide a constant on hook voltage level for leakage currents up to this value of line leakage. (EQ. 2)V OH off() at Load V OH Rsense() V sp off() V pm off()++= (EQ. 3) V OH(off) at Load 80 I LOOP max()× V sp off() 1 2R P 2R S+ ZL ×+= pm off() 1 2R P 2R S+ Zpm × 2.0V+ VBH VSAT VOH(off) 2.5V TIP TO RING VOLTAGE LOOP CURRENT ILOOP(min) VOH(off) AT LOAD ILOOP(min) R SAT R SAT DC FEED CURVE R SAT(off)= V OH(off) at Load ILOOP(min) VOH(on) AT LOAD ISH-(min) R SAT VBH VSAT VOH(on) 2.5V ISH-(min) LOOP CURRENT DC FEED CURVE TIP TO RING VOLTAGE R SAT on() 2.85V R SAT V OH on() ISH-() R SAT off()()= (EQ. 5) V OH on() 7.2mA 417 Ω×= V OH on() 3.0V= RDC_RAC = 50 x RSAT (EQ. 6) R D = 500 ISHD ISH- =500 R D HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

The ROH resistor, which is used to set the offhook overhead voltage, is calculated using Equations 9 and 10. I OH is deﬁned as the difference between the I LOOP(min) and ISH-. Substituting Equation 8 for ISH- into Equation 9 and solving for ROH deﬁnes ROH in terms of ILOOP(min) and RD. Equation 10 can be used to determine the actual ISH- value resulting from the RD resistor selected. The value of RD should be the next standard value that islow er than that calculated. This will insure meeting the ILOOP(min) requirement. ROH for the above example equals 39.1kΩ. The current limit is set by a single resistor and is calculated using Equation 11. The maximum loop resistance is calculated using Equation 12. The resistance of the protection resistors (2R P) is subtracted out to obtain the maximum loop length to meet the required off hook overhead voltage. If R LOOP(MAX) meets the loop length requirements you are done. If the loop length needs to be longer, then consider adjusting one of the following: 1) the SHD threshold, 2) minimum loop current requirement or 3) the on and off hook signal levels. SLIC in the Active Mode Figure 17 shows a simpliﬁed AC transmission model. Circuit analysis yields the following design equations: Substitute Equation 14 into Equation 15 Substitute Equation 16 into Equation 17 Substitute Equation 18 into Equation 19 Substituting -V TR /ZL into Equation 20 for IM and rearranging to solve for VTR results in Equation 21 where: VRX = The input voltage at the VRX pin. VA = An internal node voltage that is a function of the loop current detector and the impedance matching networks. IX = Internal current in the SLIC that is the difference between the input receive current and the feedback current. IM = The AC metallic current. R P = A protection resistor (typical 30Ω ). ZT = An external resistor/network for matching the line impedance. VTX ´= The tip to ring voltage at the output pins of the SLIC. VTR = The tip to ring voltage including the voltage across the protection resistors. ZL = The line impedance. ZTR = The input impedance of the SLIC including the protection resistors. (AC) 4-Wire to 2-Wire Gain The 4-wire to 2-wire gain is equal to VTR /VRX . From Equation 21 and the relationship ZT = 200(ZTR -2RP). Notice that the phase of the 4-wire to 2-wire signal is 180o out of phase with the input signal. VBH VSAT VOH(off) 2.5V OFF HOOK TIP TO RING VOLTAGE LOOP CURRENT ILOOP(min) DC FEED CURVE ISH- IOH OVER HEAD R OH 500 IOH R OH = R D 500 R LIM = 1000 ILOOP(max) VBH VSAT VOH(off) 2.5V TIP TO RING VOLTAGE LOOP CURRENT ILOOP(min) DC FEED CURVE R LOOP(MAX) R LOOP(max) = V BH V SAT 2V V OH off()++[]– ILOOP(min) V A = IM 2R S V A IM V RX V A Node Equation (EQ. 15) IX V RX IM ZTR 2R P–() IX 500k - VTX ′+I X 500k = 0 Loop Equation (EQ. 17) V TX ′ 2V RX IM ZTR 2R P–()–= (EQ. 18) V TR -IM 2R P +V TX ′= 0 Loop Equation (EQ. 19) V TR IM ZTR 2V RX–= (EQ. 20) V TR 1 ZTR ZL  2– V RX= (EQ. 21) G 4-2 = V TR V RX ZL ZL +Z TR ZL ZL ZT + (EQ. 22) HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Substituting Equation 24 into Equation 23 and simplifying. from EG to VTR as shown in Equation 27. TR ) and the protection resistors (RP). phase with the input signal. The 4-wire to 4-wire gain is equal to VTX /VRX , EG = 0. simplifying results in Equation 31. impedance to any known line impedance (ZTR ). FIGURE 17. SIMPLIFIED AC TRANSMISSION CIRCUIT

EXAMPLE: Calculate ZT to make ZTR = 600Ω in series with 2.16µF. R P = 30Ω . ZT = 114kΩ in series with 0.0108µF. Note: Some impedance models, with a series capacitor, will cause the op-amp feedback to behave as an open circuit DC. A resistor with a value of about 10 times the reactance of the Z T capacitor (2.16µF/200 = 10.8nF) at the low frequency of interest (200Hz for example) can be placed in parallel with the capacitor in order to solve the problem (736kΩ for a 10.8nF capacitor). Calculating Tip and Ring Voltages The on hook tip to ground voltage is calculated using Equation 34. The minus 1.0 volt results from the SLIC self programming. ISH- is the maximum loop current for a constant on hook overhead voltage (ISH- = I SHD (0.6)) and the value of RSAT(off) is calculated in Equation 4. On hook Tip Voltage The off hook tip to ground voltage is calculated using Equation 35. ILOOP(min) is the minimum loop current allowed by the design and the value of RSAT(off)is calculated in Equation 4. Off hook Tip Voltage The on hook ring to ground voltage is calculated using Equation 36. The 1.5 volt results from the SLIC self programming. ISH- is the maximum loop current for a constant on hook overhead voltage (ISH- = I SHD (0.6)) and the value of RSAT(off) is calculated in Equation 4. On hook Ring Voltage The calculation of the ring voltage with respect to ground in the off hook condition is dependent upon whether the SLIC is in current limit or not. The off hookring to ground voltage (in current limit) is calculated using Equation 37. I LIM is the programmed loop current limit and RL is the load resistance across tip and ring. The minus 0.2V is a correction factor for the 60kΩ slope in Figure 15. Off hook Ring Voltage in Current Limit The off hookring to ground voltage (not in current limit) is calculated using Equation 38. The 1.5V results from the SLIC self programming. I LOOP(min) is the minimum loop current allowed by the design and the value of RSAT(off)is calculated in Equation 4. Off hook Ring Voltage not in Current Limit Layout Considerations Systems with Dual Supplies (VBH and VBL ) If the VBL supply isnot derived from the VBH supply, it is recommended that an additional diode be placed in series with the V BH supply. The orientation of this diode is anode on pin 8 of the device and cathode to the external supply. This external diode will inhibit large currents and potential damage to the SLIC, in the event the V BH supply is shorted to GND. If VBL is derived from VBH then this diode is not required. Floating the PTG Pin The PTG pin is a high impedance pin (500kΩ ) that is used to program the 2-wire to 4-wire gain to either 0dB or -6dB. If 0dB is required, it is necessary to ﬂoat the PTG pin. The PC board interconnect should be as short as possible to minimize stray capacitance on this pin. Stray capacitance on this pin forms a low pass ﬁlter and will cause the 2-wire to 4-wire gain to roll off at the higher frequencies. If a 2-wire to 4-wire gain of -6dB is required, the PTG pin should be grounded as close to the device as possible. SPM Pin For optimum performance, the PC board interconnect the SPM pin should be as short as possible. If pulses metering is not being used, then this pin should be grounded as close to the device pin as possible. RLIM Pin The current limiting resistor RLIM needs to be as close to the RLIM pin as possible. Layout of the 2-Wire Impedance Matching Resistor ZT Proper connection to the ZT pin is to have the external ZT network as close to the device pin as possible. The ZT pin is a high impedance pin that is used to set the proper feedback for matching the impedance of the 2-wire side. This will eliminate circuit board capacitance on this pin to maintain the 2-wire return loss across frequency. ZT 200 600 1 = (EQ. 33) V TIP onhook() 1.0V– ISH-()– R SAToff += (EQ. 34) V TIP offhook() 1V– ILOOP min()() R SAT off() ILOOP MAX() R P×– V RING onhook() V BH 1.5V ISH() R SAT off() ++= (EQ. 36) V RING CL() V TIP offhook() ILOOP MAX() R L– 0.2V–= (EQ. 37) V RING NCL() V BH 1.5V I LOOP min()() R SAT off() ++= (EQ. 38) ILOOP MIN() R P×– HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

SHD and GKD outputs are at a TTL high level. for the delay in the opening of the relay. activate an internal latch prohibiting the ringing of the line. TABLE 1. DETECTOR STATES On hook or Off hook status of the line. On hook or Off hook status of the line.

8 X X X Thermal Shutdown LOW LOW

The GKD_LVM output is disabled (TTL high level) during the ringing state. Reference the Section titled “Ringing the Phone” for more information. Forward Active State (C3 = 0, C2 = 1, C1 = 0) In this state, the SLIC is fully functional. The tip voltage is more positive than the ring voltage. The tip and ring output voltages are an unbalanced DC feed, reference Figure 13. Both SHD and GKD supervisory functions are active. Reference the section titled “DC Feed Curve” for more information. Test Active State (C3 = 0, C2 = 1, C1 = 1) Proper operation of the Test Active State requires the previous state be the Forward Active state to determine the on hook or off hook status of the line. In this state, the SLIC can perform two different tests. If the subscriber ison hook when the state is entered, a loopback test is performed by switching an internal 600Ω resistor between tip and ring. The current flows through the internal 600Ω is unidirectional via blocking diodes. (Cannot be used in reverse.) When the loopback current flows, the SHD output will go low and remain there until the state is exited. This is intended to be a short test since the ability to detect subscriber off hook is lost during loopback testing. Reference the section titled “Loopback Tests” for more information. If the subscriber isoff hook when the state is entered, a Line Voltage Measurement test is performed. The output of the GKD_ LVM pin is a pulse train. The pulse width of the active low portion of the signal is proportional to the voltage across the tip and ring pins. If the loop length is such that the SLIC is operating in constant current, the tip to ring voltage can be used to determine the length of the line under test. The longer the line, the larger the tip to ring voltage and the wider the pulse. This relationship can determine the length of the line for setting gains in the system. Reference the section titled “Operation of LineVoltageMeasurement” for more information. Tip Open State (C3 = 1, C2 = 0, C1 = 0) In this state, the tip output is in a high impedance state (>250kΩ) and the ring output is capable of full operation, i.e. has full longitudinal current capability. The Tip Open/Ground Start state is used to interface to a PBX incoming 2-wire trunk line. When a ground is applied through a resistor to the ring lead, this current is detected and presented as a TTL logic low on the SHD and GKD_ LVM output pins. Reserved (C3 = 1, C2 = 0, C1 = 1) This state is undeﬁned and reserved for future use. Reverse Active State (C3 = 1, C2 = 1, C1 = 0) In this state, the SLIC is fully functional. The ring voltage is more positive than the tip voltage. The tip and ring output voltages are an unbalanced DC feed, reference Figure 13. The polarity reversal time is determined by the RC time constant of the RSYNC_REV resistor and the CRT_REV_ LVM capacitor.Capacitor CRT_REV_ LVM performs three different functions: Ring trip filtering, polarity reversal time and line voltage measurement. It is recommended that programming of the reversal time be accomplished by changing the value ofRSYNC_REV resistor (see Figure 18). The value of RSYNC_REV resistor is limited between 34.8K (10ms) and 73.2k (21ms).Equation 39 gives the formula for programming the reversal time. Both SHD and GKD supervisory functions are active. Reference the section titled “Polarity Reversal” for more information. Test Reversal Active State (C3 = 1, C2 = 1, C1 = 1) Proper operation of the Test Reversal Active State requires the previous state be the Reverse Active state to determine the on hook or off hook status of the line. If the subscriber ison hook when the state is entered, the SLIC’s tip and ring voltages are the same as the Reverse Active state. The SHD output will go low when the subscriber goes off hook and theGKD_LVM output is disabled (TTL level high). (Note: operation is the same as the Reverse Active state with the GKD_LVM output disabled.) If the subscriber isoff hook when the state is entered, a Line Voltage Measurement test is performed. The output of the GKD_ LVM pin is a pulse train. The pulse width of the active low portion of the signal is proportional to the voltage across the tip and ring pins. If the loop length is such that the SLIC is operating in constant current mode, the tip to ring voltage can be used to determine the length of the line under test. The longer the line, the larger the tip to ring voltage and the wider the pulse. This relationship can determine the length of the line for setting gains in the system. Reference the section titled “Operation of LineVoltageMeasurement” for more information. Thermal Shutdown The UniSLIC14’s thermal shutdown protection is invoked if a fault condition causes the junction temperature of the die to exceed about 175 oC. Once the thermal limit is exceeded, both detector outputs go low (SHD and GKD_ LVM) and one of two things can happen. For marginal faults where loop current is ﬂowing during the time of the over-temperature condition, foldback loop current limiting reduces the loop current by reducing the tip to ring voltage. An equilibrium condition will exist that maintains the junction temperature at about 175 oC until the fault condition is removed. For short circuit faults (tip or ring to ground, or to a supply, etc.) that result in an over-temperature condition, the foldback current limiting will try to maintain an equilibrium at about 175 oC. If the junction temperature keeps rising, the device will thermally shutdown and disconnect tip and ring until the junction temperature falls to approximately 150 oC. RSYNC REV– 3.47kΩ ReversalTime ms()×= (EQ. 39) HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

the low battery supply (VBL). FIGURE 26. BATTERY SELECTION (DUAL SUPPLY SYSTEMS)LOOP CURRENT (mA)

(28 LEAD PLCC) TOP VIEW HC55150 (28 LEAD PLCC) TOP VIEW Pinouts - 32 Lead PLCC Packages HC55120 (32 LEAD PLCC) TOP VIEW HC55121 (32 LEAD PLCC) TOP VIEW Pinouts - 28 Lead PLCC Packages (Continued) DR SHD CDC DT RRLY PTG VTX SPM VRX ZT CH RSYNC_REV ILIM ROH RD AGND GKD_ LVM VCC 1234 12 13 14 15 16 17 18 262728 BGND TIP VBH VBL RING CRT_REV_ RDC_RAC LVM DR SHD CDC DT RRLY PTG VTX SPM VRX ZT CH RSYNC_REV ILIM ROH RD AGND LVM VCC 1234 12 13 14 15 16 17 18 262728 BGND TIP VBH VBL RING CRT_REV_ RDC_RAC LVM DR SHD CDC DT RRLY PTG VTX VRX ZT CH RSYNC ILIM ROH RD AGNDGKD VCC 1234 14 15 16 17 18 19 20 303132 BGND TIP VBH VBL RING CRT RDC_RAC NC TRLY2 TRLY1 DR SHD CDC DT RRLY PTG VTX VRX ZT CH RSYNC_REV ILIM ROH RD AGNDGKD VCC 1234 14 15 16 17 18 19 20 303132 BGND TIP VBH VBL RING CRT_REV RDC_RAC NC TRLY2 TRLY1 HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

(32 LEAD PLCC) TOP VIEW HC55140 (32 LEAD PLCC) TOP VIEW HC55142 (32 LEAD PLCC) TOP VIEW HC55150 (32 LEAD PLCC) TOP VIEW Pinouts - 32 Lead PLCC Packages DR SHD CDC DT RRLY PTG VTX VRX ZT CH RSYNC ILIM ROH RD AGND NC V CC 1234 14 15 16 17 18 19 20 303132 BGND TIP VBH VBL RING CRT RDC_RAC NC TRLY2 TRLY1 DR SHD CDC DT RRLY PTG VTX VRX ZT CH RSYNC_REV ILIM ROH RD AGNDGKD_ LVM VCC 1234 14 15 16 17 18 19 20 303132 BGND TIP VBH VBL RING CRT_REV_LVM RDC_RAC NC TRLY2 TRLY1 DR SHD CDC DT RRLY PTG VTX VRX ZT CH RSYNC_REV ILIM ROH RD AGNDGKD_ LVM VCC 1234 14 15 16 17 18 19 20 303132 BGND TIP VBH VBL RING CRT_REV_ RDC_RAC SPM TRLY2 TRLY1 LVM DR SHD CDC DT RRLY PTG VTX VRX ZT CH RSYNC_REV ILIM ROH RD AGNDLVM VCC 1234 14 15 16 17 18 19 20 303132 BGND TIP VBH VBL RING CRT_REV_ RDC_RAC SPM TRLY2 TRLY1 LVM HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Pinouts - 28 Lead SOIC Packages HC55120 (28 LEAD SOIC) TOP VIEW HC55121 (28 LEAD SOIC) TOP VIEW HC55130 (28 LEAD SOIC) TOP VIEW HC55140 (28 LEAD SOIC) TOP VIEW ZT PTG RRLY CH RING BGND TIP VBH VBL RDC_RAC CDC DT DR CRT AGND NC VRX RSYNC ILIM RD SHD GKD VTX ROH VCC ZT PTG RRLY CH RING BGND TIP VBH VBL RDC_RAC CDC DT DR CRT_REV AGND SPM VRX RSYNC_REV ILIM RD SHD GKD VTX ROH VCC ZT PTG RRLY CH RING BGND TIP VBH VBL RDC_RAC CDC DT DR CRT AGND NC VRX RSYNC ILIM RD SHD NC VTX ROH VCC ZT PTG RRLY CH RING BGND TIP VBH VBL RDC_RAC CDC DT DR CRT_REV_ LVM AGND NC VRX RSYNC_REV ILIM RD SHD GKD_ LVM VTX ROH VCC HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

(28 LEAD SOIC) TOP VIEW HC55150 (28 LEAD SOIC) TOP VIEW Pinouts - 28 Lead SOIC Packages (Continued) ZT PTG RRLY CH RING BGND TIP VBH VBL RDC_RAC CDC DT DR CRT_REV_ LVM AGND SPM VRX RSYNC_REV ILIM RD SHD GKD_ LVM VTX ROH VCC ZT PTG RRLY CH RING BGND TIP VBH VBL RDC_RAC CDC DT DR CRT_REV_ LVM AGND SPM VRX RSYNC_REV ILIM RD SHD LVM VTX ROH VCC Pin Descriptions PIN PLCC PIN PLCC PIN SOIC SYMBOL DESCRIPTION 1 1 2 PTG Programmable Transmit Gain - The 2-wire to 4-wire transmission gain is 0dB if this pin is left floating and -6.02dB if tied to ground. The -6.02dB gain option is useful in systems where Pulse Metering is used. See Figure 23. 2 2 3 RRLY Ring Relay Driver Output - The relay coil may be connected to a maximum of 14V. 3 3 4 CH AC/DC Separation Capacitor - CH is required to properly process the AC current from the DC loop current. Recommended value 0.1µF. 4 4 1 ZT 2-Wire Impedance Matching Pin - Impedance matching of the 2-wire side is accomplished by placing an impedance between the ZT pin and ground. See Equation 32. 5 5 5 RING Connects via protection resistor R P to ring wire of subscriber pair. 6 6 6 BGND Battery ground. 7 7 7 TIP Connects via protection resistor R P to tip wire of subscriber pair. 888 V BH High Battery Supply (negative with respect to GND). 999 V BL Low Battery Supply (negative with respect to GND, magnitude≤ VBH ). 10 10 10 RDC_RAC Resistive Feed/Anti Clipping - Performs anti clipping function on constant current application and sets the slope of the resistive feed curve for constant voltage applications. 11 11 14 CRT_REV _LVM Ring Trip, Soft Polarity Reversal and Line Voltage Measurement - A capacitor when placed between the CRT_REV_ LVM pin and +5V performs 3 mutually exclusive functions. When the SLIC is configured in the Ringing mode it provides filtering of the ringing signal to prevent false detect. When the SLIC is transitioning between the Forward Active State and Reverse Active State it provides Soft Polarity Reversal and performs charge storage in the Line Voltage Measurement State. Recommended value 0.47µF. 12 12 11 CDC Filter Capacitor- The CDC Capacitor removes the VF signals from the battery feed control loop. 13 13 12 DT Tip side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external network to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DT is more negative than the voltage on DR. 14 14 13 DR Ring Side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external network to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DR is more positive than the voltage on DT. - 15 - C5 Activates Test Relay TRLY2. HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

16 - C4 Activates Test Relay TRLY1. 15 17 16 C3 TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the SLIC. Reference Table 1 for details. 16 18 17 C2 TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the SLIC. Reference Table 1 for details. 17 19 18 C1 TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the SLIC. Reference Table 1 for details. 18 20 19 SHD Switch Hook Detect - Active during off hook, ground key and loopback. Reference Table 1 for details. 19 21 15 GKD_ LVM Ground Key Detector and Line Voltage Measurement - Reference Table 1 for details. 20 22 20 V CC 5V Supply. 21 23 21 RD Loop Current Threshold Programming Pin - A resistor between this pin and ground will determine the trigger level for the loop current detect circuit. See Equation 7. 22 24 22 ROH Off Hook Overload Setting Resistor - Used to set combined overhead for voice and pulse metering signals. See Equation 10. 23 25 23 ILIM Current Limit Programming Pin - A resistor between this pin and ground will determine the constant current limit of the feed curve. See Equation 11. 24 26 24 RSYNC_REV Ring Synchronization Input and Reversal Time Setting. A resistor between this pin and GND determines the polarity reversal time. Synchronization of the closing of the relay at zero voltage is achieved via a ring sync pulse (5V to 0V) synchronized to the ring signal zero voltage crossing (Reference Figure 18). 25 27 28 AGND Analog ground 26 28 25 VRX Receive Input - Ground referenced 4-wire side. 27 29 26 SPM Pulse Metering Signal Input. If pulse metering is not used, then this pin should be grounded as close to the device pin as possible. 28 30 27 VTX Transmit Output - Ground referenced 4-wire side. - 31 - TRLY2 Test Relay Driver 2. - 32 - TRLY1 Test Relay Driver 1. Pin Descriptions (Continued) PIN PLCC PIN PLCC PIN SOIC SYMBOL DESCRIPTION HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

FIGURE 27. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.

FIGURE 28. UniSLIC14 PULSE METERING BASIC APPLICATION CIRCUIT TABLE 3. BASIC APPLICATION CIRCUIT COMPONENT LIST

FIGURE 29. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT TABLE 4. BASIC APPLICATION CIRCUIT COMPONENT LIST HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.

FIGURE 30. UniSLIC14 PULSE METERING BASIC APPLICATION CIRCUIT TABLE 5. BASIC APPLICATION CIRCUIT COMPONENT LIST

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certiﬁcation. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Sales Ofﬁce Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369 HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Summary

Low Power Universal SLIC Family June 2000

Description