HC5513 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • DI Monolithic High Voltage Process
  • Programmable Current Feed (20mA to 60mA)
  • Programmable Loop Current Detector Threshold and Bat- tery Feed Characteristics
  • Ground Key and Ring Trip Detection
  • Compatible with Ericsson’s PBL3764
  • Thermal Shutdown
  • On-Hook Transmission
  • Wide Battery Voltage Range (-24V to -58V)
  • Low Standby Power
  • Meets TR-NWT -000057 Transmission Requirements
  • -40 oC to 85oC Ambient Temperature Range

Applications

  • Hybrid Fiber Coax
  • Related Literature - AN9537, Operation of the HC5513/26 Evaluation Board Block Diagram

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. HC5513BIM -40 to 85 28 Ld PLCC N28.45 HC5513BIP -40 to 85 22 Ld PDIP E22.4 RINGRLY DT DR TIP RING HPT HPR VBAT VCC VEE AGND BGND VTX RSN DET RING RELAY DRIVER 4-WIRE INTERFACE VF SIGNAL PATH GROUND KEY DETECTOR LOOP CURRENT DETECTOR R DC RSG BIAS DIGITAL MULTIPLEXER RING TRIP DETECTOR 2-WIRE INTERFACE R D Data Sheet October 1998 File Number 3963.10

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

  1. θJA is measured with the component mounted on an evaluation PC board in free air.

These represent the conditions under which the part was developed and are suggested as guidelines. Specified. All pin number references in the figures refer to the 28 lead PLCC package. FIGURE 1. OVERLOAD LEVEL (TWO-WIRE PORT) FIGURE 2. LONGITUDINAL IMPEDANCE

FIGURE 6. TWO-WIRE RETURN LOSS FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT),

FIGURE 10. IDLE CHANNEL NOISE FIGURE 11. GROUND KEY DETECT

FIGURE 12. POWER SUPPLY REJECTION RATIO

including the voltage drop across the fuse resistors RF. referenced 4-wire side or the SLIC tip and ring terminals. IM = Is the AC metallic current. ZT = Is used to set the SLIC’s 2-wire impedance. VRX = Is the analog ground referenced receive signal. ZRX = Is used to set the 4-wire to 2-wire gain. EG = Is the AC open circuit voltage. impedance to any known line impedance (ZTR ). Calculate ZT to make ZTR = 600Ω in series with 2.16µF. ZT = 560kΩ in series with 2.16nF . The 2-wire to 4-wire gain is equal to VTX / VTR . The 4-wire to 2-wire gain is equal to VTR /VRX . The 4-wire to 4-wire gain is equal to VTX /VRX . FIGURE 16. SIMPLIFIED AC TRANSMISSION CIRCUIT

tip to ring DC conditions and circuits processing AC signals. fault condition has been removed. and ring against high voltage transients. when the line in exposed to a power cross. most negative potential as with junction isolated ICs. TABLE 1. LOGIC TRUTH TABLE

0000 Open Circuit No Active Detector Logic Level High

0001 Active Ground Key Detector Ground Key Status

0010 Ringing No Active Detector Logic Level High

0011 Standby Ground Key Detector Ground Key Status

0100 Open Circuit No Active Detector Logic Level High

0101 Active Loop Current Detector Loop Current Status

0110 Ringing Ring Trip Detector Ring Trip Status

0111 Standby Loop Current Detector Loop Current Status

1000 Open Circuit No Active Detector

1001 Active Ground Key Detector

1010 Ringing No Active Detector

1011 Standby Ground Key Detector

1100 Open Circuit No Active Detector

1101 Active Loop Current Detector

1110 Ringing Ring Trip Detector

1111 Standby Loop Current Detector

  1. Overload Level (Two-Wire port) -The overload level is speci- fied at the 2-wire port (VTR0 ) with the signal source at the 4-wire receive port (ERX ). IDCMET =3 0µA, increase the amplitude of ERX until 1% THD is measured at VTRO . Reference Figure 1. 3. Longitudinal Impedance -The longitudinal impedance is computed using the following equations, where TIP and RING voltages are referenced to ground. L ZT,LZR ,V T,V R ,A R and AT are defined in Figure 2. (TIP) LZT = VT/AT (RING) LZR = VR /AR Where: EL = 1VRMS (0Hz to 100Hz). 4. Longitudinal Current Limit (Off-Hook Active) -Off-Hook (Active, C1 =1 ,C2 = 0) longitudinal current limit is determined by increasing the amplitude of EL (Figure 3A) until the 2-wire longitudinal balance drops below 45dB.DET pin remains low (no false detection). 5. Longitudinal Current Limit (On-Hook Standby) -On-Hook (Active, C1 =1 ,C2 = 1) longitudinal current limit is determined by increasing the amplitude of EL (Figure 3B) until the 2-wire longi- tudinal balance drops below 45dB.DET pin remains high (no false detection). 6. Longitudinal to Metallic Balance -The longitudinal to metal- lic balance is computed using the following equation: BLME = 20 • log (EL/VTR ), where: EL and VTR are defined in Figure 4. 7. Metallic to Longitudinal FCC Part 68, Para 68.310 -The metallic to longitudinal balance is defined in this spec. 8. Longitudinal to Four-Wire Balance -The longitudinal to 4-wire balance is computed using the following equation: BLFE = 20• log (EL/VTX ),: EL and VTX are defined in Figure 4. 9. Metallic to Longitudinal Balance -The metallic to longitudinal balance is computed using the following equation: BMLE = 20 • log (ETR /VL), ERX = 0 Where: ETR ,VL and ERX are defined in Figure 5. 10. Four-Wire to Longitudinal Balance -The 4-wire to longitudinal balance is computed using the following equation: BFLE = 20• log (ERX /VL), ETR = source is removed. Where: ERX ,VL and ETR are defined in Figure 5. 11. Two-Wire Return Loss -The 2-wire return loss is computed using the following equation: r = -20• log (2VM /VS) Where: ZD = The desired impedance; e.g., the characteristic impedance of the line, nominally 600Ω. (Reference Figure 6). 12. Overload Level (4-Wire port) -The overload level is specified at the 4-wire transmit port (VTXO ) with the signal source (EG )a t the 2-wire port, IDCMET = 23mA, ZL = 20kΩ (Reference Figure 7). Increase the amplitude of EG until 1% THD is measured at VTXO . Note that the gain from the 2-wire port to the 4-wire port is equal to 1. 13. Output Offset Voltage -The output offset voltage is specified with the following conditions: EG =0 ,IDCMET = 23mA, ZL = ∞ and is measured at VTX .E G ,IDCMET ,V TX and ZL are defined in Figure 7. Note: IDCMET is established with a series 600Ω resistor between tip and ring. 14. Two-Wire to Four-Wire (Metallic to VTX ) Voltage Gain -The 2-wire to 4-wire (metallic to VTX ) voltage gain is computed using the following equation. G 2-4 =( VTX /VTR ), EG = 0dBm0, V TX ,V TR , and EG are defined in Figure 7. 15. Current Gain RSN to Metallic -The current gain RSN to Metallic is computed using the following equation: K=I M [(RDC1 +R DC2 )/(VRDC -V RSN )] K, IM ,R DC1 ,R DC2 , VRDC and VRSN are defined in Figure 8. 16. Two-Wire to Four-Wire Frequency Response -The 2-wire to 4-wire frequency response is measured with respect to E G = 0dBm at 1.0kHz, ERX =0 V ,IDCMET = 23mA. The frequency response is computed using the following equation: F2-4 =2 0 • log (VTX /VTR ), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTX , VTR , and EG are defined in Figure 9. 17. Four-Wire to Two-Wire Frequency Response -The 4-wire to 2-wire frequency response is measured with respect to E RX = 0dBm at 1.0kHz, EG =0 V ,IDCMET = 23mA. The frequency response is computed using the following equation: F4-2 =2 0 • log (VTR /ERX ), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTR and ERX are defined in Figure 9. 18. Four-Wire to Four-Wire Frequency Response -The 4-wire to 4-wire frequency response is measured with respect to E RX = 0dBm at 1.0kHz, EG =0 V ,IDCMET = 23mA. The frequency response is computed using the following equation: F4-4 =2 0 • log (VTX /ERX ), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTX and ERX are defined in Figure 9. 19. Two-Wire to Four-Wire Insertion Loss -The 2-wire to 4-wire insertion loss is measured with respect to EG = 0dBm at 1.0kHz input signal, ERX =0 ,IDCMET = 23mA and is computed using the following equation: L2-4 = 20• log (VTX /VTR ) where: VTX ,V TR , and EG are defined in Figure 9. (Note: The fuse resistors, RF, impact the insertion loss. The specified insertion loss is for RF = 0). 20. Four-Wire to Two-Wire Insertion Loss -The 4-wire to 2-wire insertion loss is measured based upon ERX = 0dBm, 1.0kHz input signal, EG =0 ,IDCMET = 23mA and is computed using the following equation: L4-2 = 20• log (VTR /ERX ) Where: VTR and ERX are defined in Figure 9. 21. Two-Wire to Four-Wire Gain Tracking -The 2-wire to 4-wire gain tracking is referenced to measurements taken for E G = -10dBm, 1.0kHz signal, ERX =0 ,IDCMET = 23mA and is computed using the following equation. G 2-4=2 0• log (VTX /VTR ) vary amplitude -40dBm to +3dBm, or -55dBm to -40dBm and compare to -10dBm reading. VTX and VTR are defined in Figure 9. 22. Four-Wire to Two-Wire Gain Tracking -The 4-wire to 2-wire gain tracking is referenced to measurements taken for E RX = -10dBm, 1.0kHz signal, EG =0 ,IDCMET = 23mA and is computed using the following equation: G 4-2 =2 0 • log (VTR /ERX ) vary amplitude -40dBm to +3dBm, or -55dBm to -40dBm and compare to -10dBm reading. VTR and ERX are defined in Figure 9. The level is specified at the 4-wire receive port and referenced to a 600Ω impedance level. HC5513

22 2 RD Loop current programming resistor. Resistor R D sets the trigger level for the loop current detect circuit. A filter ca- pacitor CD is also connected between this pin and VEE . 23 3 DT Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. 25 4 DR Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. 26 TIP SENSE Internally connected to output of tip power amplifier. 27 5 TIPX Output of tip power amplifier. 28 6 RINGX Output of ring power amplifier. 3, 10 17, 24 N/C No internal connection. Pin Descriptions (Continued) PLCC PDIP SYMBOL DESCRIPTION Pinouts HC5513 (PLCC) TOP VIEW HC5513 (PDIP) TOP VIEW R DC AGND RSN N/C VEE BGND RING SENSE RINGX TIPX TIP SENSE VCC N/C N/C DT RD HPT DR VTX HPR 1234 12 13 14 15 16 17 18 262728 V BAT R SG RINGRLY DET N/C RD DT DR TIPX RINGX BGND RINGRLY VCC VBAT R SG VTX RSN AGND R DC VEE DET HPT HPR HC5513

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

21 HPT

27 TIPX

28 RINGX

2 BGND

4 VCC

5 RINGRLY

6 VBAT

7 RSG

U2 Combination CODEC/Filter e.g.

  1. It is recommended that the anodes of D3 and D4 be shorted to ground through a battery referenced surgector (SGT27S10).
  2. To meet the specified 25dB 2-wire return loss at 200Hz, CHP needs to be 20nF, 20%, 100V.

FIGURE 21. APPLICATION CIRCUIT