DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 20
Technical content
Features
- DI Monolithic High Voltage Process
- Programmable Current Feed (20mA to 60mA)
- Programmable Loop Current Detector Threshold and Battery Feed Characteristics
- Ground Key and Ring Trip Detection
- Compatible with Ericsson’s PBL3764
- Thermal Shutdown
- On-Hook Transmission
- Wide Battery Voltage Range (-24V to -58V)
- Low Standby Power
- Meets TR-NWT-000057 Transmission Requirements
- - 4 0 oC to 85oC Ambient Temperature Range
Applications
- Digital Loop Carrier Systems • Pair Gain
- Fiber-In-The-Loop ONUs • POTS
- Wireless Local Loop • PABX
- Hybrid Fiber Coax
- Related Literature - AN9537, Operation of the HC5513/26 Evaluation Board Block Diagram Part Number Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. DWG. # HC5513BIP -40 to 85 22 Ld PDIP E22.4 RINGRLY DT DR TIP RING HPT HPR VBAT VCC VEE AGND BGND VTX RSN DET RING RELAY DRIVER 4-WIRE INTERFACE VF SIGNAL PATH GROUND KEY DETECTOR LOOP CURRENT DETECTOR RDC RSG BIAS DIGITAL MULTIPLEXER RING TRIP DETECTOR 2-WIRE INTERFACE RD OBSOLETE PRODUCT RECOMMENDED REPLACEMENT HC5515
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
- JA is measured with the component mounted on an evaluation PC board in free air.
These represent the conditions under which the part was developed and are suggested as guidelines. FIGURE 1. OVERLOAD LEVEL (TWO-WIRE PORT) FIGURE 2. LONGITUDINAL I MPEDANCE
FIGURE 6. TWO-WIRE RETURN LOSS FIGURE 7. O VERLOAD LEVEL (4-WIRE TRANSMIT PORT),
FIGURE 10. IDLE CHANNEL NOISE FIGURE 11. GROUND KEY DETECT
FIGURE 12. POWER SUPPLY REJECTION RATIO
FN3963 Rev.12.00 Page 10 of 20 August 2003 where: VTR = Is the AC metallic voltage between tip and ring, including the voltage drop across the fuse resistors RF . VTX = Is the AC metallic voltage. Either at the ground referenced 4-wire side or the SLIC tip and ring terminals. IM = Is the AC metallic current. RF = Is a fuse resistor. ZT = Is used to set the SLIC’s 2-wire impedance. VRX = Is the analog ground referenced receive signal. ZRX = Is used to set the 4-wire to 2-wire gain. EG = Is the AC open circuit voltage. ZL = Is the line impedance. (AC) 2-Wire Impedance The AC 2-wire impedance (ZTR) is the impedance looking into the SLIC, including the fuse resistors, and is calculated as follows: Let V RX = 0. Then from Equation 10 ZTR is defined as: Substituting in Equation 9 for VTR Substituting in Equation 12 for VTX Therefore Equation 16 can now be used to match the SLIC’s impedance to any known line impedance (Z TR). Example: Calculate ZT to make ZTR = 600 in series with 2.16F. RF = 20: ZT = 560k in series with 2.16nF. (AC) 2-Wire to 4-Wire Gain The 2-wire to 4-wire gain is equal to VTX/ VTR. From Equations 9 and 10 with VRX = 0: (AC) 4-Wire to 2-Wire Gain The 4-wire to 2-wire gain is equal to VTR/VRX. From Equations 9, 10 and 11 with EG = 0: For applications where the 2-wire impedance (ZTR, Equation 15) is chosen to equal the line impedance (ZL), the expression for A4-2 simplifies to: (AC) 4-Wire to 4-Wire Gain The 4-wire to 4-wire gain is equal to VTX/VRX. From Equations 9, 10 and 11 with EG = 0: VTX ZT IM ZTR VTR IM ZTR VTX IM 2RF IM IM ZTR ZT ZT 1000 Z TR 2RF–= (EQ. 16) ZT 1000 600 1 j 2.16 10 6– = A24– VTX VTR ZT 1000 A42– VTR VRX ZT ZRX ZL ZT A42– ZT ZRX 2---= (EQ. 19) A44– VTX VRX ZT ZRX ZL 2RF+ ZT
- Overload Level (Two-Wire port) - The overload level is specified
THD is measured at VTRO. Reference Figure 1.
- Longitudinal Impedance - The longitudinal impedance is com-
Where: EL = 1VRMS (0Hz to 100Hz).
- Longitudinal Current Limit (Off-Hook Active) - Off-Hook
- Longitudinal Current Limit (On-Hook Standby) - On-Hook
- Longitudinal to Metallic Balance - The longitudinal to metallic
- Metallic to Longitudinal FCC Part 68, Para 68.310 - The metal-
lic to longitudinal balance is defined in this spec.
- Longitudinal to Four-Wire Balance - The longitudinal to 4-wire
BLFE = 20 log (EL/VTX),: EL and VTX are defined in Figure 4.
- Metallic to Longitudinal Balance - The metallic to longitudinal
Where: ETR, VL and ERX are defined in Figure 5.
- Four-Wire to Longitudinal Balance - The 4-wire to longitudinal
BFLE = 20 log (ERX/VL), ETR = source is removed. Where: ERX, VL and ETR are defined in Figure 5.
- Two-Wire Return Loss - The 2-wire return loss is computed
impedance of the line, nominally 600(Reference Figure 6).
- Overload Level (4-Wire port) - The overload level is specified at
2-wire port, I DCMET = 23mA, Z L = 20k (Reference Figure 7). Increase the amplitude of EG until 1% THD is measured at VTXO.
- Output Offset Voltage - The output offset voltage is specified
Figure 7. Note: IDCMET is established with a series 600 resistor TABLE 1. LOGIC TRUTH TABLE
FN3963 Rev.12.00 Page 17 of 20 August 2003 Pin Descriptions PDIP SYMBOL DESCRIPTION 7 BGND Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground. Internally separate from AGND but it is recommended that it is connected to the same potential as AGND. 8V CC 5V power supply. 9 RINGRLY Ring relay driver output. 10 V BAT Battery supply voltage, -24V to -56V. 11 R SG Saturation guard programming resistor pin. 12 E1 TTL compatible logic input. The logic state of E1 in co njunction with the logic state of C1 determines which detector is gated to the DET output. 13 E0 TTL compatible logic input. Enables the DET output when set to logic level zero and disables DET output when set to a logic level one. 14 DET Detector output. TTL compatible logic output. A zero logi c level indicates that the selected detector was triggered (see Truth Table for selection of Ground Key detector, Loop Current detector or the Ring Trip detector). The DET output is an open collector with an internal pull-up of approximately 15k to VCC. 15 C2 TTL compatible logic input. The l ogic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing or Standby) of the SLIC. 16 C1 TTL compatible logic input. The l ogic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing or Standby) of the SLIC. 17 R DC DC feed current programming resistor pin. Constant current feed is programmed by resistors RDC1 and RDC2 connected in series from this pin to the receive summing node (RSN). The resistor junction point is decoupled to AGND to isolate the AC signal components. 18 AGND Analog ground. 19 RSN Receive Summing Node. The AC and DC current flowing into th is pin establishes the metallic loop current that flows between tip and ring. The magnitude of the metallic loop current is 1000 times greater than the current into the RSN pin. The constant current programming resistors and the networks for program receive gain and 2-wire impedance all connect to this pin. 20 V EE -5V power supply. 21 V TX Transmit audio output. This output is equivalent to the TIP to RING metallic voltage. The network for programming the 2-wire input impedance connects between this pin and RSN. 22 HPR RING side of AC/DC separation capacitor C HP. CHP is required to properly separate the ring AC current from the DC loop current. The other end of CHP is connected to HPT. 1 HPT TIP side of AC/DC separation capacitor C HP. CHP is required to properly separate the tip AC current from the DC loop current. The other end of CHP is connected to HPR. 2 RD Loop current programming resistor. Resistor R D sets the trigger level for the loop current detect circuit. A filter capacitor CD is also connected between this pin and VEE. 3 DT Input to ring trip comparator. Ring trip detection is accomp lished by connecting an external network to a comparator in the SLIC with inputs DT and DR. 4 DR Input to ring trip comparator. Ring trip detection is accomp lished by connecting an external network to a comparator in the SLIC with inputs DT and DR. TIPSENSE Internally connected to output of tip power amplifier. 5 TIPX Output of tip power amplifier. 6 RINGX Output of ring power amplifier. N/C No internal connection.
FN3963 Rev.12.00 Page 18 of 20 August 2003 Pinout HC5513 (PDIP) TOP VIEW RD DT DR TIPX RINGX BGND RINGRLY VCC VBAT RSG VTX RSN AGND RDC VEE DET HPT HPR
1 HPT
5 TIPX
6 RINGX
7 BGND
8 VCC
9 RINGRLY
10 VBAT
11 RSG
U2 Combination CODEC/Filter e.g.
- It is recommended that the anodes of D 3 and D4 be shorted to ground through a battery referenced surgector (SGT27S10).
- To meet the specified 25dB 2-wire return loss at 200Hz, C HP needs to be 20nF, 20%, 100V.
FIGURE 21. APPLICATION CIRCUIT
FN3963 Rev.12.00 Page 20 of 20 August 2003 HC5513 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2003. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. e B and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E22.4 (JEDEC MS-010-AA ISSUE C)
22 LEAD DUAL-IN-LINE PLASTIC PACKAGE
A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.065 1.15 1.65 8 C 0.009 0.015 0.229 0.381 - D 1.065 1.120 27.06 28.44 5 D1 0.005 - 0.13 - 5 E 0.390 0.425 9.91 10.79 6 E1 0.330 0.390 8.39 9.90 5 e 0.100 BSC 2.54 BSC - eA 0.400 BSC 10.16 BSC 6 eB - 0.500 - 12.70 7 L 0.115 0.160 2.93 4.06 4 N2 2 2 2 9 Rev. 0 12/93