HC55120CBZ

HC55120_06 INTERSIL | Alldatasheet

Document overview

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PDF pages: 36

Technical content

Features

Ultra Low Active Power (OHT) < 60mW
Single/Dual Battery Operation
Automatic Silent Battery Selection
Power Management/Shutdown
Battery Tracking Anti Clipping
Single 5V Supply with 3V Compatible Logic
Zero Crossing Ring Control - Zero Voltage On/Zero Current Off
Tip/Ring Disconnect
Pulse Metering Capability
4 Wire Loopback
Programmable Current Feed
Programmable Resistive Feed
Programmable Loop Detect Threshold
Programmable On-Hook and Off-Hook Overheads
Programmable Overhead for Pulse Metering
Programmable Polarity Reversal Time
Selectable Transmit Gain 0dB/-6dB
2 Wire Impedance Set by Single Network
Loop and Ground Key Detectors
On-Hook Transmission
Common Pinout
Pb-Free Plus Anneal Available (RoHS Compliant)
HC55121 - Polarity Reversal
HC55130 - -63dB Longitudinal Balance
HC55140 - Polarity Reversal - Ground Start - Line Voltage Measurement - 2 Wire Loopback - -63dB Longitudinal Balance
HC55142 - Polarity Reversal - Ground Start - Line Voltage Measurement -2 . 2 V RMS Pulse Metering - 2 Wire Loopback
HC55150 - Polarity Reversal - Line Voltage Measurement -2 . 2 V RMS Pulse Metering - 2 Wire Loopback Related Literature
AN9871, User’s Guide for UniSLIC14 Eval Board
AN9903, UniSLIC14 and TI TCM38C17 RRLY DT DR TIP RING VBH VCC RING AND TEST RELAY DRIVERS RING TRIP DETECTOR VBL BGND BATTERY SELECTION AND BIAS NETWORK ZERO CURRENT 2-WIRE INTERFACE CROSSING TRLY1 TRLY2 VTX VRX GKD_LVM ROH RD CDC RDC_RAC ZT CH LOOP CURRENT DETECTOR PTG ILIM STATE DECODER AND DETECTOR LOGIC GKD/LOOP LENGTH DETECTOR RSYNC_REV SHD 4-WIRE INTERFACE VF SIGNAL PATH LINE FEED CONTROL CRT_REV_LVMPOLARITY REVERSAL PULSE METERING SPM SIGNAL PATH AGND Block Diagram Data Sheet June 1, 2006

2 FN4659.13 June 1, 2006

Ordering Information

NUMBER* MAX LOOP CURRENT (mA) POLARITY REVERSAL GND START GND KEY LINE VOLTAGE MEASUREMENT PULSE METERING

2 TEST

2 WIRE

(°C) PKG. DWG. # HC55120CB 30 • 53dB 0 to 70 M28.3 SOIC HC55120CBZ Pb-free (Note) 30 • 53dB 0 to 70 M28.3 SOIC HC55120CM 30 • 53dB 0 to 70 N28.45 PLCC HC55120CMZ Pb-free (Note) 30 • 53dB 0 to 70 N28.45 PLCC HC55121IB 30 •• • • 53dB -40 to 85 M28.3 SOIC HC55121IBZ Pb-free (Note) 30 •• • • 53dB -40 to 85 M28.3 SOIC HC55121IM 30 •• • • 53dB -40 to 85 N28.45 PLCC HC55121IMZ Pb-free (Note) 30 •• • • 53dB -40 to 85 N28.45 PLCC HC55130IB 45 63dB -40 to 85 M28.3 SOIC HC55130IB96 (Tape and Reel) 45 63dB -40 to 85 M28.3 SOIC HC55130IBZ Pb-free (Note) 45 63dB -40 to 85 M28.3 SOIC HC55130IBZ96 (Tape and Reel) Pb-free (Note) 45 63dB -40 to 85 M28.3 SOIC HC55130IM 45 63dB -40 to 85 N28.45 PLCC HC55130IMZ Pb-free (Note) 45 63dB -40 to 85 N28.45 PLCC HC55140IB 45

• • • • 63dB -40 to 85 M28.3 SOIC HC55140IBZ Pb-free (Note) 45 •• • • • 63dB -40 to 85 M28.3 SOIC HC55140IM 45 •• • • • 63dB -40 to 85 N28.45 PLCC HC55140IMZ Pb-free (Note) 45 •• • • • 63dB -40 to 85 N28.45 PLCC HC55142IB 45 •• • • • • 63dB -40 to 85 M28.3 SOIC HC55142IBZ Pb-free (Note) 45 •• • • • • 63dB -40 to 85 M28.3 SOIC HC55142IM 45 •• • • • • 63dB -40 to 85 N28.45 PLCC HC55142IM96 (Tape and Reel) 45 •• • • • • 63dB -40 to 85 N28.45 PLCC HC55142IMZ Pb-free (Note) 45 •• • • • • 63dB -40 to 85 N28.45 PLCC HC55142IMZ96 (Tape and Reel) Pb-free (Note)
• • • • • 63dB -40 to 85 N28.45 PLCC HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

3 FN4659.13 June 1, 2006 HC55143IM 45 •• • • • • • 63dB -40 to 85 N32.45x55 PLCC HC55143IMZ Pb-free (Note) 45 •• • • • • • 63dB -40 to 85 N32.45x55 PLCC HC55150CB 45 •• • • 55dB 0 to 70 M28.3 SOIC HC55150CBZ Pb-free (Note) 45 •• • • 55dB 0 to 70 M28.3 SOIC HC55150CM 45 •• • • 55dB 0 to 70 N28.45 PLCC HC55150CMZ Pb-free (Note) 45 •• • • 55dB 0 to 70 N28.45 PLCC HC5514XEVAL1 Evaluation board † Available by placing SLIC in Test mode. *Part marking is the same as the part number on all parts. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Ordering Information (Continued) PART NUMBER* MAX LOOP CURRENT (mA) POLARITY REVERSAL GND START GND KEY LINE VOLTAGE MEASUREMENT PULSE METERING (°C) PKG. DWG. # Device Operating Modes C3 C2 C1 DESCRIPTION HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1 0 0 0 Open Circuit 4-Wire Loopback 0 1 1 Test Forward Active

2 Wire Loopback and

• • • 1 0 0 Tip Open Ground Start •• 1 1 0 Reverse Active •• • • 1 1 1 Test Reverse Active Line Voltage Measurement
•• HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

4 FN4659.13 June 1, 2006 Absolute Maximum Ratings TA = 25°C Thermal Information Temperature, Humidity Power Supply (-40°C ≤ T A ≤ 85°C) Relay Driver Digital Inputs, Outputs (C1, C2, C3, C4, C5, SHD, GKD_LVM) Tipx and Ringx Terminals (-40°C ≤ T A ≤ 85°C) Thermal Resistance (Typical, Note 1) θJA Continuous Power Dissipation at 85°C (PLCC, SOIC - Lead Tips Only) Derate above 70°C Tip and Ring Terminals Tipx or Ringx, Pulse < 250ns, TREP > 10s 20A CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Typical Operating Conditions These represent the conditions under which the device was developed and are suggested as guidelines. PARAMETER CONDITIONS MIN TYP MAX UNITS Ambient Temperature HC55120, HC55150/1 0 - 70 °C HC55121, HC55130/1, HC55140/1, HC55142/3 -40 - 85 °C VBH with Respect to GND -58 - -8 V VBL with Respect to GND VBH -0 V VCC with Respect to GND 4.75 - 5.25 V HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

6 FN4659.13 June 1, 2006 OFF-HOOK LONGITUDINAL BALANCE MIN MIN MIN MIN MIN MIN Longitudinal to Metallic (Note 7) Forward and Reverse IEEE 455 - 1985, RLR, RLT = 368Ω Normal Polarity: Forward Only Forward Only 0.2kHz < f < 1.0kHz, 0°C to 70°C - - - dB 53 NA NA NA NA 55 1.0kHz < f < 3.4kHz, 0°C to 70°C - - - dB 53 NA NA NA NA 55 0.2kHz < f < 1.0kHz, -40°C to 85°C - - - dB NA 53 63 63 63 NA 1.0kHz < f < 3.4kHz, -40°C to 85°C - - - dB NA 53 58 58 58 NA Reverse Polarity 0.2kHz < f < 3.4kHz, (Figure 4) - - - dB NA 53 NA 58 58 55 MIN MIN MIN MIN MIN MIN Longitudinal to Metallic (Note 7) Forward and Reverse R LR, RLT = 300Ω, Normal Polarity: Forward Only Forward Only 0.2kHz < f < 1.0kHz, 0°C to 70°C - - - dB 53 NA NA NA NA 55 1.0kHz < f < 3.4kHz, 0°C to 70°C - - - dB 53 NA NA NA NA 55 0.2kHz < f < 1.0kHz, -40°C to 85°C - - - dB NA 53 63 63 63 NA 1.0kHz < f < 3.4kHz, -40°C to 85°C - - - dB NA 53 58 58 58 NA Reverse Polarity 0.2kHz < f < 3.4kHz, (Figure 4) - - - dB NA 53 NA 58 58 55 MIN MIN MIN MIN MIN MIN Longitudinal to 4-Wire (Note 9) (Forward and Reverse) Normal Polarity: Forward Only Forward Only 0.2kHz < f < 1.0kHz, 0°C to 70°C - - - dB 53 NA NA NA NA 61 1.0kHz < f < 3.4kHz, 0°C to 70°C - - - dB 53 NA NA NA NA 61 0.2kHz < f < 1.0kHz, -40°C to 85°C - - - dB NA 53 63 63 63 NA 1.0kHz < f < 3.4kHz, -40°C to 85°C - - - dB NA 53 58 58 58 NA Reverse Polarity 0.2kHz < f < 3.4kHz, (Figure 4) - - dB NA 53 NA 58 58 61 Metallic to Longitudinal (Note 10) Forward and Reverse FCC Part 68, Para 68.310 (Note 8) 0.2kHz < f < 3.4kHz, (Figure 5) 40 50 - dB Forward Only

Forward Only ••• 4-Wire to Longitudinal (Note 11) Forward and Reverse 0.2kHz < f < 3.4kHz, (Figure 5) 40 - - dB Forward Only
Forward Only ••• applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1 HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

•••PTG = Open (Note 19, Figure 8) -0.2 - 0.2 dB Forward Only Forward OnlyPTG = GND (Note 20, Figure 8) -6.22 -6.02 -5.82 dB 4-Wire to 2-Wire Forward and Reverse 0dBm, 1kHz (Note 21, Figure 8) -0.2 - 0.2 dB Forward Only • Forward Only ••• GAIN TRACKING (Ref = -10dBm, at 1.0kHz) 2-Wire to 4-Wire Forward and Reverse -40dBm to +3dBm (Note 22, Figure 8) -0.1 - 0.1 dB Forward Only • Forward Only •••-55dBm to -40dBm (Note 22, Figure 8) -0.2 - 0.2 dB 4-Wire to 2-Wire Forward and Reverse -40dBm to +3dBm (Note 23, Figure 8) -0.1 - 0.1 dB Forward Only • Forward Only •••-55dBm to -40dBm (Note 23, Figure 8) -0.2 - 0.2 dB NOISE Idle Channel Noise at 2-Wire C-Message Weighting - 10.5 13 dBrnC Forward Only • Forward Only •••Forward and Reverse Psophometric Weighting (Note 24, Note 30, Figure 9) - -79.5 -77 dBmp Idle Channel Noise at 4-Wire C-Message Weighting - 10.5 13 dBrnC Forward Only • Forward Only •••Forward and Reverse Psophometrical Weighting (Note 25, Note 30, Figure 9) - -79.5 -77 dBmp HARMONIC DISTORTION 2-Wire to 4-Wire Forward and Reverse 0dBm, 0.3kHz to 3.4kHz (Note 26, Figure 7) - -67 -50 dB Forward Only • Forward Only ••• 4-Wire to 2-Wire Forward and Reverse 0dBm, 0.3kHz to 3.4kHz (Note 27, Figure 8) - -67 -50 dB Forward Only
Forward Only •••

FIGURE 10. CONSTANT LOOP CURRENT TOLERANCE FIGURE 11. TIPX VOLTAGE

10 FN4659.13 June 1, 2006 BATTERY FEED CHARACTERISTICS Constant Loop Current Tolerance 18mA ≤ IL ≤ 45mA, Forward Only • Forward Only •••IL = 26.5mA, RLIM = 38.3kΩ Forward and Reverse (Note 27, Figure 10) 0.92I L IL 1.08IL mA Tip Open State TIPX Leakage Current S = Closed (Figure 11) - - -200 µA •••••• Tip Open State RINGX Current R 1 = 0Ω, VBH = -48V, RLIM = 38.3kΩ 22.6 26.8 31 mA

•••••R1 = 2.5kΩ, VBH = -48V (Figure 11) 15.5 17.1 18.2 mA Tip Open State RINGX Voltage 5mA < I R1 < 26mA (Figure 11) - 42.8 - V •••••• Tip Voltage (Ground Start) Active State, (S Open) R 1 = 150Ω (Figure 11) -5.3 -4.8 -4.3 V NA NA NA •• NA Tip Voltage (Ground Start) Active State, (S Closed) Tip Lead to
•-48V Through 7kΩ, Ring Lead to Ground Through 150Ω (Figure 11) -5.3 -4.8 -4.3 V NA NA NA NA Open Circuit State Loop Current (Active) R L = 0Ω -20 0 20 µA •••••• LOOP CURRENT DETECTOR Programmable Threshold I LTh = (500/ RD) ≥ 5mA, 0.9I LTh ILTh 1.1ILTh mA Forward Only • Forward Only •••Forward and Reverse I LTh = 8.5mA RD = 58.8kΩ GROUND KEY DETECTOR Ground Key Detector Threshold Tip/Ring Current Difference Tip Open 5 8 11 mA NA NA Active (Note 29, R1 = 2.5kΩ, Figure 12) 12.5 20 27.5 mA LINE VOLTAGE MEASUREMENT RING TRIP DETECTOR (DT, DR) Ring Trip Comparator Current Source Res = 2M Ω -2- µA Input Common-Mode Range Source Res = 2M Ω -- ±200 V •••••• applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1 HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

FIGURE 12. GROUND KEY DETECT

12 FN4659.13 June 1, 2006 POWER DISSIPATION (VBH = -48V, VBL = -24V) Open Circuit State C1, C2, C3 = 0, 0, 0 - 25 - mW Forward Only • Forward Only ••• On-Hook, Active C1, C2, C3 = 0, 1, 0 Forward and Reverse I L = 0mA, Longitudinal Current = 0mA -5 2- m W F o r w a r d Only • Forward Only ••• POWER SUPPLY CURRENTS (VBH = -48V, VBL = -24V) VCC Current, ICC Open Circuit State - 2.25 3.0 mA Forward Only • Forward Only ••• VBH Current, IBH - 0.3 0.45 mA Forward Only • Forward Only ••• VBL Current, IBL - 0.022 0.035 mA Forward Only • Forward Only ••• VCC Current, ICC Forward and Reverse Active State IL = 0mA, Longitudinal Current = 0mA - 2.7 3.6 mA Forward Only • Forward Only ••• VBH Current, IBH Forward and Reverse - 0.8 1.06 mA Forward Only • Forward Only ••• VBL Current, IBL Forward and Reverse - - 0.01 mA Forward Only • Forward Only ••• POWER SUPPLY REJECTION RATIOS VCC to 2 or 4 Wire Port Forward and Reverse Active State RL = 600Ω 50Hz < f < 3400Hz, VIN =100mV - 40 - dB Forward Only • Forward Only ••• VBH to 2 or 4 Wire Port Forward and Reverse - 40 - dB Forward Only • Forward Only ••• VBL to 2 or 4 Wire Port Forward and Reverse - 40 - dB Forward Only • Forward Only ••• TEMPERATURE GUARD Junction Threshold Temperature - 175 - °C • ••••• applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1 HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

16 FN4659.13 June 1, 2006 Off Hook Overhead Voltage The off hook overhead voltage VOH(off) at Load is also independent of the VBH battery voltage and remains constant over temperature. The required off hook overhead voltage is the sum of the AC and DC voltage drops across the internal sense resistors (R S), the protection resistors (RP), the required (peak) off hook voltage for speech (Vsp(off)) and the required (peak) off hook voltage for the pulse metering (Vpm(off)), if applicable. The off hook overhead voltage is defined in Equation 2 and calculated using Equation 3. where: VOH(off) at Load = Off hook overhead voltage at load VOH(Rsense) = Required overhead for the DC voltage drop across sense resistors (2RS x Iloop(max)) Vsp(off) = Required (peak) off hook AC voltage for speech Vpm(off) = Required (peak) off hook AC voltage for pulse metering where: 80 = 2Rs + 2RINT (reference Figure 17) Zpm = Pulse metering load impedance (typically 200Ω). 2.0V = Additional off hook overhead voltage requirement RSAT Resistance Calculation The RSAT resistance of the DC feed curve is used to determine the value of the RDC_RAC resistor (Equation 6). The value of this resistor has an effect on both the on hook and off hook overheads. In most applications the off hook condition will dominate the overhead requirements. Therefore, we’ll start by calculating the R SAT value for the off hook conditions and then verify that the on hook conditions are also satisfied. When considering the Off hook condition, R SAT is equal to VOH(off) at Load divided by Iloop(min) (Equation 4). For the given system requirements (recommended application circuit in back of data sheet): Iloop (min) = 20mA, Iloop (max) = 30mA, V sp(off) = 3.2VPEAK, Vspm(off) = 0VPEAK, VOH(off) at Load = 8.34V the value of RSAT(off) is equal to 417Ω as calculated in Equation 4. Before using this RSAT value, to calculate the RDC_RAC resistor, we need to verify that the on hook requirements will also be met. The on hook overhead voltage calculated with the off hook R SAT (RSAT(off)), is given in Equation 5 and equals 3.0V. The on hook overhead calculated with Equation 1 equals 2.85V for the given system requirements (recommended application circuit in back of data sheet): Switch Hook Detect threshold = 12mA, ISH- = (0.6)12mA = 7.2mA, V sp(on) = 0.775VRMS Thus, the on hook overhead requirements of 2.85V will be met if we use the RSAT(off) value. If the on hook overhead requirement is not met, then we need to use the RSAT(on) value to determine the RDC_RAC resistor value. The external saturation guard resistor RDC_RAC is equal to 50 times R SAT. In the example above RSAT would equal 417Ω and RDC_RAC would then equal to 20.85kΩ (closest standard value is 21kΩ). The Switch Hook Detect threshold current is set by resistor RD and is calculated using Equation 7. For the above VBH VSAT VOH(off) 2.5V OFF HOOK TIP TO RING VOLTAGE LOOP CURRENT ILOOP(min) DC FEED CURVE OVER HEAD (EQ. 2)VOH off() at Load VOH Rsense() Vsp off() Vpm off()++= (EQ. 3) VOH(off) at Load 80 I LOOP max()× Vsp off() 1 2RP 2RS+ ZL ⎛⎞×+= + Vpm off() 1 2RP 2RS+ Zpm ⎛⎞× 2.0V+ VBH VSAT VOH(off) 2.5V TIP TO RING VOLTAGE LOOP CURRENT ILOOP(min) VOH(off) AT LOAD ILOOP(min) RSAT RSAT DC FEED CURVE RSAT(off) = VOH(off) at Load ILOOP(min) VOH(on) AT LOAD ISH-(min) RSAT VBH VSAT VOH(on) 2.5V ISH-(min) LOOP CURRENT DC FEED CURVE TIP TO RING VOLTAGE RSAT on() 2.85V RSAT VOH on() ISH-() RSAT off()()= (EQ. 5) VOH on() 7.2mA 417 Ω×= VOH on() 3.0V= RDC_RAC = 50 x RSAT (EQ. 6) HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

17 FN4659.13 June 1, 2006 example RD is calculated to be 41.6kΩ (500/12mA). The next closest standard value is 41.2kΩ. The true value of ISH-, for the selected value of RD is given by Equation 8: For the example above, ISH- equals 7.28mA (500 x 0.6/ 41.2K). Verify that the value of ISH- is above the suspected line leakage of the application. The UniSLIC family will provide a constant on hook voltage level for leakage currents up to this value of line leakage. The R OH resistor, which is used to set the offhook overhead voltage, is calculated using Equations 9 and 10. I OH is defined as the difference between the I LOOP(min) and ISH-. Substituting Equation 8 for ISH- into Equation 9 and solving for ROH defines ROH in terms of ILOOP(min) and RD. Equation 10 can be used to determine the actual ISH- value resulting from the RD resistor selected. The value of RD should be the next standard value that is lower than that calculated. This will insure meeting the ILOOP(min) requirement. ROH for the above example equals 39.1kΩ. The current limit is set by a single resistor and is calculated using Equation 11. The maximum loop resistance is calculated using Equation 12. The resistance of the protection resistors (2R P) is subtracted out to obtain the maximum loop length to meet the required off hook overhead voltage. If R LOOP(MAX) meets the loop length requirements you are done. If the loop length needs to be longer, then consider adjusting one of the following: 1) the SHD threshold, 2) minimum loop current requirement or 3) the on and off hook signal levels. SLIC in the Active Mode Figure 17 shows a simplified AC transmission model. Circuit analysis yields the following design equations: Substitute Equation 14 into Equation 15 Substitute Equation 16 into Equation 17 Substitute Equation 18 into Equation 19 Substituting -V TR/ZL into Equation 20 for IM and rearranging to solve for VTR results in Equation 21 where: VRX = The input voltage at the VRX pin. VA = An internal node voltage that is a function of the loop current detector and the impedance matching networks. IX = Internal current in the SLIC that is the difference between the input receive current and the feedback current. IM = The AC metallic current. RP = A protection resistor (typical 30Ω). ZT = An external resistor/network for matching the line impedance. VTX´= The tip to ring voltage at the output pins of the SLIC. RD = 500 ISHD ISH- = 500 RD VBH VSAT VOH(off) 2.5V OFF HOOK TIP TO RING VOLTAGE LOOP CURRENT ILOOP(min) DC FEED CURVE ISH- IOH OVER HEAD ROH 500 IOH ROH = RD500 RLIM = 1000 ILOOP(max) VBH VSAT VOH(off) 2.5V TIP TO RING VOLTAGE LOOP CURRENT ILOOP(min) DC FEED CURVE RLOOP(MAX) RLOOP(max) = VBH VSAT 2V V OH off()++[]– ILOOP(min) VA = IM 2RS VA IM VRX VA Node Equation (EQ. 15) IX VRX IM ZTR 2RP–() IX500k - VTX ′ + IX500k = 0 Loop Equation (EQ. 17) VTX ′ 2VRX IM ZTR 2RP–()–= (EQ. 18) VTR-IM2RP + VTX ′ = 0 Loop Equation (EQ. 19) VTR IMZTR 2VRX–= (EQ. 20) VTR 1 ZTR ZL ⎛⎞ 2– V RX= (EQ. 21) HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

The 4-wire to 2-wire gain is equal to VTR/VRX. From Equation 21 and the relationship ZT = 200(ZTR-2RP). of phase with the input signal. Substituting Equation 24 into Equation 23 and simplifying. from EG to VTR as shown in Equation 27. TR) and the protection resistors (RP). phase with the input signal. The 4-wire to 4-wire gain is equal to VTX/VRX, EG = 0. FIGURE 17. SIMPLIFIED AC TRANSMISSION CIRCUIT

19 FN4659.13 June 1, 2006 Substituting Equation 21 for VTR in Equation 30 and simplifying results in Equation 31. (AC) 2-Wire Impedance The AC 2-wire impedance (ZTR) is the impedance looking into the SLIC, including the fuse resistors. The formula to calculate the proper Z T for matching the 2-wire impedance is shown in Equation 32. Equation 32 can now be used to match the SLIC’s impedance to any known line impedance (ZTR). EXAMPLE: Calculate ZT to make ZTR = 600Ω in series with 2.16µF. RP = 30Ω. ZT = 108kΩ in series with 0.0108µF. Note: Some impedance models, with a series capacitor, will cause the op-amp feedback to behave as an open circuit DC. A resistor with a value of about 10 times the reactance of the Z T capacitor (2.16µF/200 = 10.8nF) at the low frequency of interest (200Hz for example) can be placed in parallel with the capacitor in order to solve the problem (736kΩ for a 10.8nF capacitor). Calculating Tip and Ring Voltages The on hook tip to ground voltage is calculated using Equation 34. The minus 1.0 volt results from the SLIC self programming. ISH- is the maximum loop current for a constant on hook overhead voltage (ISH- = I SHD(0.6)) and the value of RSAT(off) is calculated in Equation 4. On hook Tip Voltage The off hook tip to ground voltage is calculated using Equation 35. ILOOP(min) is the minimum loop current allowed by the design and the value of RSAT(off) is calculated in Equation 4. Off hook Tip Voltage The on hook ring to ground voltage is calculated using Equation 36. The 1.5 volt results from the SLIC self programming. ISH- is the maximum loop current for a constant on hook overhead voltage (ISH- = I SHD(0.6)) and the value of RSAT(off) is calculated in Equation 4. On hook Ring Voltage The calculation of the ring voltage with respect to ground in the off hook condition is dependent upon whether the SLIC is in current limit or not. The off hook ring to ground voltage (in current limit) is calculated using Equation 37. I LIM is the programmed loop current limit and RL is the load resistance across tip and ring. The minus 0.2V is a correction factor for the 60kΩ slope in Figure 15. Off hook Ring Voltage in Current Limit The off hook ring to ground voltage (not in current limit) is calculated using Equation 38. The 1.5V results from the SLIC self programming. ILOOP(min) is the minimum loop current allowed by the design and the value of RSAT(off) is calculated in Equation 4. Off hook Ring Voltage not in Current Limit Layout Considerations Systems with Dual Supplies (VBH and VBL) If the VBL supply is not derived from the VBH supply, it is recommended that an additional diode be placed in series with the V BH supply. The orientation of this diode is anode on pin 8 of the device and cathode to the external supply. This external diode will inhibit large currents and potential damage to the SLIC, in the event the V BH supply is shorted to GND. If VBL is derived from VBH then this diode is not required. Suggested (not required) supply sequence VBH - VBL- VCC. Floating the PTG Pin The PTG pin is a high impedance pin (500kΩ) that is used to program the 2-wire to 4-wire gain to either 0dB or -6dB. If 0dB is required, it is necessary to float the PTG pin. The PC board interconnect should be as short as possible to minimize stray capacitance on this pin. Stray capacitance on this pin forms a low pass filter and will cause the 2-wire to 4-wire gain to roll off at the higher frequencies. If a 2-wire to 4-wire gain of -6dB is required, the PTG pin should be grounded as close to the device as possible. G44– VTX VRX ZL+ 2R P ⎛⎞== (EQ. 31) ZT 200 Z TR 2RP–()•= (EQ. 32) ZT 200 600 1 ⎛⎞= (EQ. 33) V TIP onhook() 1.0V– ISH-()– RSAToff ⎛⎞+= (EQ. 34) VTIP offhook() 1V– ILOOP min()() RSAT off() ILOOP MAX() RP×– VRING onhook() VBH 1.5V ISH() RSAT off() ⎛⎞++= (EQ. 36) VRING CL() VTIP offhook() ILOOP MAX() RL– 0.2V–= (EQ. 37) VRING NCL() VBH 1.5V I LOOP min()() RSAT off() ⎛⎞++= (EQ. 38) ILOOP MIN() RP×– HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

network as close to the device pin as possible. to maintain the 2-wire return loss across frequency. and SHD and GKD outputs are at a TTL high level. approximately the same as its input and 180o out of phase. the current into the RSYNC_REV pin. TABLE 1. DETECTOR STATES On hook or Off hook status of the line. On hook or Off hook status of the line.

8 X X X Thermal Shutdown LOW LOW

21 FN4659.13 June 1, 2006 low at zero voltage crossing of the ring signal. This pulse should have a rise and fall time <400µs and a minimum pulse width of 2ms. Zero ring current detection is performed automatically inside the SLIC. This feature de-energizes the ring relay slightly before zero current occurs to partially compensate for the delay in the opening of the relay. The SHD output will go low when the subscriber goes off hook. Once SHD is activated, an internal latch will prohibit the re-ringing of the line until the ringing code is removed and then reapplied. The state prior to ringing the phone, can not be the Reverse Active State. In the reverse active state the polarity of the voltage on the CRT_REV_LVM capacitor, will make it appear as if the subscriber is off hook. This subsequently will activate an internal latch prohibiting the ringing of the line. The GKD_LVM output is disabled (TTL high level) during the ringing state. Reference the Section titled “Ringing the Phone” for more information. Forward Active State (C3 = 0, C2 = 1, C1 = 0) In this state, the SLIC is fully functional. The tip voltage is more positive than the ring voltage. The tip and ring output voltages are an unbalanced DC feed, reference Figure 13. Both SHD and GKD supervisory functions are active. Reference the section titled “DC Feed Curve” for more information. Test Active State (C3 = 0, C2 = 1, C1 = 1) Proper operation of the Test Active State requires the previous state be the Forward Active state to determine the on hook or off hook status of the line. In this state, the SLIC can perform two different tests. If the subscriber is on hook when the state is entered, a loopback test is performed by switching an internal 600Ω resistor between tip and ring. The current flows through the internal 600Ω is unidirectional via blocking diodes. (Cannot be used in reverse.) When the loopback current flows, the SHD output will go low and remain there until the state is exited. This is intended to be a short test since the ability to detect subscriber off hook is lost during loopback testing. Reference the section titled “Loopback Tests” for more information. If the subscriber is off hook when the state is entered, a Line Voltage Measurement test is performed. The output of the GKD _LVM pin is a pulse train. The pulse width of the active low portion of the signal is proportional to the voltage across the tip and ring pins. If the loop length is such that the SLIC is operating in constant current, the tip to ring voltage can be used to determine the length of the line under test. The longer the line, the larger the tip to ring voltage and the wider the pulse. This relationship can determine the length of the line for setting gains in the system. Reference the section titled “Operation of L ine Voltage Measurement” for more information. Tip Open State (C3 = 1, C2 = 0, C1 = 0) In this state, the tip output is in a high impedance state (>250kΩ) and the ring output is capable of full operation, i.e. has full longitudinal current capability. The Tip Open/Ground Start state is used to interface to a PBX incoming 2-wire trunk line. When a ground is applied through a resistor to the ring lead, this current is detected and presented as a TTL logic low on the SHD and GKD_LVM output pins. Reserved (C3 = 1, C2 = 0, C1 = 1) This state is undefined and reserved for future use. Reverse Active State (C3 = 1, C2 = 1, C1 = 0) In this state, the SLIC is fully functional. The ring voltage is more positive than the tip voltage. The tip and ring output voltages are an unbalanced DC feed, reference Figure 13. The polarity reversal time is determined by the RC time constant of the RSYNC_REV resistor and the CRT_REV_LVM capacitor. Capacitor CRT_REV_LVM performs three different functions: Ring trip filtering, polarity reversal time and line voltage measurement. It is recommended that programming of the reversal time be accomplished by changing the value of RSYNC_REV resistor (see Figure 18). The value of RSYNC_REV resistor is limited between 34.8K (10ms) and 73.2k (21ms). Equation 39 gives the formula for programming the reversal time. Both SHD and GKD supervisory functions are active. Reference the section titled “Polarity Reversal” for more information. Test Reversal Active State (C3 = 1, C2 = 1, C1 = 1) Proper operation of the Test Reversal Active State requires the previous state be the Reverse Active state to determine the on hook or off hook status of the line. If the subscriber is on hook when the state is entered, the SLIC’s tip and ring voltages are the same as the Reverse Active state. The SHD output will go low when the subscriber goes off hook and the GKD_LVM output is disabled (TTL level high). (Note: operation is the same as the Reverse Active state with the GKD_LVM output disabled.) If the subscriber is off hook when the state is entered, a Line Voltage Measurement test is performed. The output of the GKD_LVM pin is a pulse train. The pulse width of the active low portion of the signal is proportional to the voltage across the tip and ring pins. If the loop length is such that the SLIC is operating in constant current mode, the tip to ring voltage can be used to determine the length of the line under test. The longer the line, the larger the tip to ring voltage and the wider the pulse. This relationship can determine the length of the line for setting gains in the system. Reference the section titled “Operation of L ine Voltage Measurement” for more information. RSYNC REV– 3.47k Ω ReversalTime ms()×= (EQ. 39) HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

until the junction temperature falls to approximately 150°C. low when an off hook condition is detected. positive than DT by approximately 4V. place an external snubber diode across the ring relay. voltage and opening the ring relay at zero current. time is not desired, R1 equal to 50kΩ is suggested. instant the logic code for ringing is applied. FIGURE 18. REDUCING IMPULSE NOISE USING THE

27 FN4659.13 June 1, 2006 HC55130 (28 LEAD PLCC) TOP VIEW HC55140 (28 LEAD PLCC) TOP VIEW HC55142 (28 LEAD PLCC) TOP VIEW HC55150 (28 LEAD PLCC) TOP VIEW Pinouts - 28 Lead PLCC Packages (Continued) DR SHD CDC DT RRLY PTG VTX NC VRX ZT CH RSYNC ILIM ROH RD AGND NC V CC 1234 12 13 14 15 16 17 18 262728 BGND TIP VBH VBL RING CRT RDC_RAC DR SHD CDC DT RRLY PTG VTX NC VRX ZT CH RSYNC_REV ILIM ROH RD AGND GKD _LVM VCC 1234 12 13 14 15 16 17 18 262728 BGND TIP VBH VBL RING CRT_REV_ RDC_RAC LVM DR SHD CDC DT RRLY PTG VTX SPM VRX ZT CH RSYNC_REV ILIM ROH RD AGND GKD_LVM VCC 1234 12 13 14 15 16 17 18 262728 BGND TIP VBH VBL RING CRT_REV_ RDC_RAC LVM DR SHD CDC DT RRLY PTG VTX SPM VRX ZT CH RSYNC_REV ILIM ROH RD AGND LVM VCC 1234 12 13 14 15 16 17 18 262728 BGND TIP VBH VBL RING CRT_REV_ RDC_RAC LVM HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

28 FN4659.13 June 1, 2006 Pinouts - 32 Lead PLCC Packages HC55143 (32 LEAD PLCC) TOP VIEW DR SHD CDC DT RRLY PTG VTX VRX ZT CH RSYNC_REV ILIM ROH RD AGND GKD _LVM VCC 1234 14 15 16 17 18 19 20 303132 BGND TIP VBH VBL RING CRT_REV_ RDC_RAC SPM TRLY2 TRLY1 LVM Pinouts - 28 Lead SOIC Packages HC55120 (28 LEAD SOIC) TOP VIEW HC55121 (28 LEAD SOIC) TOP VIEW ZT PTG RRLY CH RING BGND TIP VBH VBL RDC_RAC CDC DT DR CRT AGND NC VRX RSYNC ILIM RD SHD GKD VTX ROH VCC ZT PTG RRLY CH RING BGND TIP VBH VBL RDC_RAC CDC DT DR CRT_REV AGND SPM VRX RSYNC_REV ILIM RD SHD GKD VTX ROH VCC HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

29 FN4659.13 June 1, 2006 HC55130 (28 LEAD SOIC) TOP VIEW HC55140 (28 LEAD SOIC) TOP VIEW HC55142 (28 LEAD SOIC) TOP VIEW HC55150 (28 LEAD SOIC) TOP VIEW Pinouts - 28 Lead SOIC Packages (Continued) ZT PTG RRLY CH RING BGND TIP VBH VBL RDC_RAC CDC DT DR CRT AGND NC VRX RSYNC ILIM RD SHD NC VTX ROH VCC ZT PTG RRLY CH RING BGND TIP VBH VBL RDC_RAC CDC DT DR CRT_REV_LVM AGND NC VRX RSYNC_REV ILIM RD SHD GKD_LVM VTX ROH VCC ZT PTG RRLY CH RING BGND TIP VBH VBL RDC_RAC CDC DT DR CRT_REV_LVM AGND SPM VRX RSYNC_REV ILIM RD SHD GKD_LVM VTX ROH VCC ZT PTG RRLY CH RING BGND TIP VBH VBL RDC_RAC CDC DT DR CRT_REV_LVM AGND SPM VRX RSYNC_REV ILIM RD SHD LVM VTX ROH VCC Pin Descriptions PIN PLCC PIN PLCC PIN SOIC SYMBOL DESCRIPTION 1 1 2 PTG Programmable Transmit Gain - The 2-wire to 4-wire transmission gain is 0dB if this pin is left floating and -6.02dB if tied to ground. The -6.02dB gain option is useful in systems where Pulse Metering is used. See Figure 23. 2 2 3 RRLY Ring Relay Driver Output - The relay coil may be connected to a maximum of 14V. 3 3 4 CH AC/DC Separation Capacitor - CH is required to properly process the AC current from the DC loop current. Recommended value 0.1µF. 4 4 1 ZT 2-Wire Impedance Matching Pin - Impedance matching of the 2-wire side is accomplished by placing an impedance between the ZT pin and ground. See Equation 32. 5 5 5 RING Connects via protection resistor R P to ring wire of subscriber pair. 6 6 6 BGND Battery ground. 7 7 7 TIP Connects via protection resistor R P to tip wire of subscriber pair. HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

30 FN4659.13 June 1, 2006 888 V BH High Battery Supply (negative with respect to GND). 999 V BL Low Battery Supply (negative with respect to GND, magnitude ≤ VBH). 10 10 10 RDC_RAC Resistive Feed/Anti Clippi ng - Performs anti clipping function on constant current application and sets the slope of the resistive feed curve for constant voltage applications. 11 11 14 CRT_REV _LVM Ring Trip, Soft Polarity Reversal and Line Voltage Measurement - A capacitor when placed between the CRT_REV_LVM pin and +5V performs 3 mutually exclusive functions. When the SLIC is configured in the Ringing mode it provides filtering of the ringing signal to prevent false detect. When the SLIC is transitioning between the Forward Active State and Reverse Active State it provides Soft Polarity Reversal and performs charge storage in the Line Voltage Measurement State. Recommended value 0.47µF. 12 12 11 CDC Filter Capacitor - The CDC Capacitor removes the VF signals from the battery feed control loop. 13 13 12 DT Tip side of Ring Trip Detector - Ring trip det ection is accomplished by connecting an external network to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DT is more negative than the voltage on DR. 14 14 13 DR Ring Side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external network to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DR is more positive than the voltage on DT. - 15 - C5 Activates Test Relay TRLY2. TTL Compatible Logic Input. C5 input high, test relay TRLT2 Low(ON). C5 input floating, test relay TRLY2 High(OFF). This is due to an internal 100kΩ pull down resistor. - 16 - C4 Activates Test Relay TRLY1. TTL Compatible Logic Input. C4 input high, test relay TRLT1 Low(ON). C4 input floating, test relay TRLY1 High(OFF). This is due to an internal 100kΩ pull down resistor. 15 17 16 C3 TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the SLIC. Reference Table 1 for details. 16 18 17 C2 TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the SLIC. Reference Table 1 for details. 17 19 18 C1 TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the SLIC. Reference Table 1 for details. 18 20 19 SHD Switch Hook Detect - Active during off hook , ground key and loopback. Reference Table 1 for details. 19 21 15 GKD_LVM Ground Key Detector and Line Voltage Measurement - Reference Table 1 for details. 20 22 20 V CC 5V Supply. 21 23 21 RD Loop Current Threshold Programming Pin - A resistor between this pin and ground will determine the trigger level for the loop current detect circuit. See Equation 7. 22 24 22 ROH Off Hook Overload Setting Resistor - Used to set combined overhead for voice and pulse metering signals. See Equation 10. 23 25 23 ILIM Current Limit Programming Pin - A resistor between this pin and ground will determine the constant current limit of the feed curve. See Equation 11. 24 26 24 RSYNC_REV Ring Synchronization Input and Reversal Time Setting. A resistor between this pin and GND determines the polarity reversal time. Synchronization of the closing of the relay at zero voltage is achieved via a ring sync pulse (5V to 0V) synchronized to the ring signal zero voltage crossing (Reference Figure 18). 25 27 28 AGND Analog ground 26 28 25 VRX Receive Input - Ground referenced 4-wire side. 27 29 26 SPM Pulse Metering Signal Input. If pulse metering is not used, then this pin should be grounded as close to the device pin as possible. Input impedance to ground = 125kΩ. 28 30 27 VTX Transmit Output - Ground referenced 4-wire side. - 31 - TRLY2 Test Relay Driver 2. Open Collector Trans istor. Internal Clamp between it’s output and ground elimnates the need to place an external snubber diode across Test Relay Driver. TRLY2 may be connected to maximum of 14V. - 32 - TRLY1 Test Relay Driver 1. Open Collector Trans istor. Internal Clamp between it’s output and ground elimnates the need to place an external snubber diode across Test Relay Driver. TRLY1 may be connected to maximum of 14V. Pin Descriptions (Continued) PIN PLCC PIN PLCC PIN SOIC SYMBOL DESCRIPTION HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150

FIGURE 27. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST Limit = 31mA, Synthesize Device Impedance = 540Ω (600 - 60), with 30Ω protection resistors, impedance across Tip and Ring terminals = 600Ω. and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.

FIGURE 28. UniSLIC14 PULSE METERING BASIC APPLICATION CIRCUIT TABLE 3. BASIC APPLICATION CIRCUIT COMPONENT LIST

FIGURE 29. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT TABLE 4. BASIC APPLICATION CIRCUIT COMPONENT LIST Limit = 31mA, Synthesize Device Impedance = 540Ω (600 - 60), with 30Ω protection resistors, impedance across Tip and Ring terminals = 600Ω. and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.

34 FN4659.13 June 1, 2006 HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Small Outline Plastic Packages (SOIC) α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. In- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional . If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M M28.3 (JEDEC MS-013-AE ISSUE C)

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 e 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N2 8 2 8 7 α 0o 8o 0o 8o - Rev. 0 12/93

35 FN4659.13 June 1, 2006 HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14) R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10) C -C- D2/E2 CL N28.45 (JEDEC MS-018AB ISSUE A)

28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.485 0.495 12.32 12.57 - D1 0.450 0.456 11.43 11.58 3 D2 0.191 0.219 4.86 5.56 4, 5 E 0.485 0.495 12.32 12.57 - E1 0.450 0.456 11.43 11.58 3 E2 0.191 0.219 4.86 5.56 4, 5 N2 8 2 8 6 Rev. 2 11/97

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4659.13 June 1, 2006 HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Plastic Leaded Chip Carrier Packages (PLCC) A SEATING PLANE 0.015 (0.38) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14) R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 PIN (1) CL D 0.020 (0.51) MAX

3 PLCS

0.026 (0.66) 0.032 (0.81) 0.050 (1.27) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10) C -C- D2/E2 CL NE ND IDENTIFIER (0.12) M DS- B SAS 0.042 (1.07) 0.048 (1.22) 0.005 N32.45x55 (JEDEC MS-016AE ISSUE A)

32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

A 0.125 0.140 3.18 3.55 - A1 0.060 0.095 1.53 2.41 - D 0.485 0.495 12.32 12.57 - D1 0.447 0.453 11.36 11.50 3 D2 0.188 0.223 4.78 5.66 4, 5 E 0.585 0.595 14.86 15.11 - E1 0.547 0.553 13.90 14.04 3 E2 0.238 0.273 6.05 6.93 4, 5 N2 8 2 8 6 ND 7 7 7 NE 9 9 7 Rev. 0 7/98 NOTES: 1. Controlling dimension: INCH . Converted millimeter dimen- sions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Al- lowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are mea- sured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 7. ND denotes the number of leads on the two shorts sides of the package, one of which contains pin #1. NE denotes the num- ber of leads on the two long sides of the package. -C-

Summary

Low Power Universal SLIC Family June 1, 2006

Description