HC5503PRI INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 8

Technical content

Features

  • Wide Operating Battery Range (-40V to -58V)
  • Single Additional +5V Supply
  • 30mA Short Loop Current Limit
  • Ring Relay Driver
  • Switch Hook and Ring Trip Detect
  • Low On-Hook Power Consumption
  • On-Hook Transmission
  • ITU-T Longitudinal Balance Performance
  • Loop Power Denial Function
  • Thermal Protection
  • Supports Tip, Ring or Balanced Ringing Schemes
  • Low Profile SO Surface Mount Packaging
  • Pb-Free Available (RoHS Compliant)

Applications

  • Central Office, PBX, Call Centers
  • Related Literature - AN571, Using Ring Sync with HC-5502A and HC-5504 SLICs Block Diagram

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. # HC5503PRIB -40 to +85 24 Ld SOIC M24.3 HC5503PRIBZ (Note) -40 to +85 24 Ld SOIC Pb-Free M24.3 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. RD RFS TIP TF RING RF VBAT VCC BGND DGND TX RX SHD RS RC PD RING RELAY DRIVER 4-WIRE INTERFACE VF SIGNAL PATH LOOP CURRENT DETECTOR BIAS LOGIC INTERFACE RING TRIP DETECTOR 2-WIRE INTERFACE AGND THERMAL LIMIT OUT +IN -IN Data Sheet November 2, 2004

2 FN6101.0 Absolute Maximum Ratings Thermal Information Maximum Continuous Supply Voltages Operating Conditions Thermal Resistance (Typical, Note 2 θJA (°C/W) (SOIC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Absolute maximum ratings are limiting values, applied indivi dually, beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Unless Otherwise Specified, VB- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP = 50Ω, RS = 100Ω, Typical Parameters. TA = 25°C. Min-Max Parameters are Over Operating Temperature Range PARAMETER CONDITIONS MIN TYP MAX UNITS On Hook Power Dissipation I LONG = 0 (Notes 3,4) - 113 - mW Off Hook Power Dissipation R L = 600Ω, ILONG = 0 (Notes 3, 4) - 750 - mW On Hook IB+R L = ∞, ILONG = 0 - 1.4 - mA Off Hook IB+R L = 600Ω, ILONG = 0 - 2.8 - mA On Hook IB-R L = ∞, ILONG = 0 - 2.2 - mA Off Hook IB-R L = 600Ω, ILONG = 0 - 31 - mA Off Hook Loop Current R L = 1800Ω (ILOOP = 0) 18 - - mA Off Hook Loop Current R L = 200Ω, ILONG = 0 (Note 3) 25 30 35 mA Fault Currents TIP to Ground -2 7- m A RING to Ground -5 5- m A TIP to RING -3 0- m A TIP and RING to Ground -6 9- m A Ring Relay Drive VOL IOL = 62mA - 0.2 0.5 V Ring Relay Driver Off Leakage V RD = 12V, RC = 1 = HIGH, TA = 25°C - - 100 µA DC Ring Trip Threshold 6.5 10 13.5 mA Switch Hook Detection Threshold 5.0 7.5 10 mA Loop Current During Power Denial R L = 200Ω -3 . 2-m A Dial Pulse Distortion (Note 4) 0 - 0.5 ms Receive Input Impedance (Note 4) - 110 - k Ω Transmit Output Impedance (Note 4) - 10 20 Ω HC5503PRI

3 FN6101.0 2-Wire Return Loss (Referenced to 600 Ω + 2.16µF), RP = RS = 150Ω (Note 4)SRL LO - 15.5 - dB ERL -2 4-d B SRL HI -3 1-d B Longitudinal Balance 1V RMS 200Hz - 3400Hz, (Note 4) IEEE Method -40°C ≤ TA ≤ 85°C, RP = RS = 150Ω 2-Wire Off Hook (Note 4) 53 58 - dB 2-Wire On Hook (Note 4) 53 58 - dB 4-Wire Off Hook 50 58 - dB Insertion Loss At 1kHz, 0dBm Input Level, Referenced 600 Ω, RP =R S = 150Ω 2-Wire to 4-Wire, 4-Wire to 2-Wire - ±0.05 ±0.2 dB Frequency Response 200 - 3400Hz Referenced to Absolute Loss at 1kHz and 0dBm Signal Level, RP = RS = 150Ω (Note 4) - ±0.02 ±0.05 dB Idle Channel Noise R P = RS = 150Ω (Note 4) 2-Wire to 4-Wire, 4-Wire to 2-Wire -15 d B r n C -- 8 9 - 8 5 d B m 0 p Absolute Delay R P = RS = 150Ω (Note 4) 2-Wire to 4-Wire, 4-Wire to 2-Wire --2 µs Trans Hybrid Loss Balance Network Set Up for 600 Ω Termination at 1kHz, RP = RS = 150Ω (Note 4) 30 40 - dB Overload Level V B+ = +5V, RP = RS = 150Ω (Note 4) 2-Wire to 4-Wire, 4-Wire to 2-Wire 1.5 - - V PEAK Level Linearity 2-Wire to 4-Wire, 4-Wire to 2-Wire (Note 4) At 1kHz, (Note 4) Referenced to 0dBm Level, RP = RS = 150Ω +3 to -40dBm - - ±0.05 dB -40 to -50dBm - - ±0.1 dB -50 to -55dBm - - ±0.3 dB Power Supply Rejection Ratio R P = RS = 150Ω (Note 4) 30 - 60Hz, RL = 600ΩVB+ to 2-Wire 15 - - dB VB+ to Transmit 15 - - dB VB- to 2-Wire 15 - - dB VB- to Transmit 15 - - dB VB+ to 2-Wire 200 - 16kHz, R L = 600Ω, RP = RS = 150Ω 30 - - dB VB+ to Transmit 30 - - dB VB- to 2-Wire 30 - - dB VB- to Transmit 30 - - dB Logic Input Current (RS, RC, PD)0 V ≤ VIN ≤ 5V - - ±100 µA Logic Inputs Logic ‘0’ VIL -- 0 . 8 V Logic ‘1’ VIH 2.0 - 5.5 V Logic Outputs Logic ‘0’ VOL ILOAD 800µA, VB+ = 5V - 0.1 0.5 V Logic ‘1’ VOH ILOAD 40µA, VB+ = 5V 2.7 - 5.0 V Electrical Specifications Unless Otherwise Specified, VB- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP = 50Ω, RS = 100Ω, Typical Parameters. TA = 25°C. Min-Max Parameters are Over Operating Temperature Range (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS HC5503PRI

4 FN6101.0 UNCOMMITTED OP AMP SPECIFICATIONS Input Offset Voltage - ±5- m V Input Offset Current - ±10 - nA Input Bias Current -2 0-n A Differential Input Resistance (Note 4) - 1 - M Ω Output Voltage Swing R L = 10K, VB+ = 5V - ±3- V PEAK Output Resistance A VCL = 1 (Note 4) - 10 - Ω Small Signal GBW (Note 4) - 1 - MHz NOTES: 3. I LONG = Longitudinal Current. 4. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. Electrical Specifications Unless Otherwise Specified, VB- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP = 50Ω, RS = 100Ω, Typical Parameters. TA = 25°C. Min-Max Parameters are Over Operating Temperature Range (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS Pin Descriptions

24 PIN

DIP/SOIC SYMBOL DESCRIPTION 1 TIP An analog input connected to the TIP (more positive) side of the subscriber loop through a sense resistor (RS) and a ring relay contact. Functions with the Ring terminal to receive voice signals from the telephone and for loop monitoring purposes. 2 RING An analog input connected to the RING (more negative) side of the subscriber loop through a sense resistor (RS) and a ring relay contact. Functions with the Tip terminal to receive voice signals from the telephone and for loop monitoring purposes. 3 RFS Senses ring side of loop for ground key and ring trip detecti on. During ringing, the ring signal is inserted into the line at this node and RF is isolated from RFS via a relay. 4V B+ Positive Voltage Source - Most positive supply. V B+ is typically. 5C 1 Capacitor #1 - An external capacitor to be connected between this terminal and analog ground. Required for proper operation of the loop current limiting function, and for filtering VB-. Typical value is 0.3µF, 30V. 6 DG Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and outputs on the SLIC microcircuit. 7 RS Ring Synchronization Input - A TTL - compatible clock inpu t. The clock should be arranged such that a positive pulse transition occurs on the zero crossing of the ring voltage source, as it appears at the RFS terminal. For Tip side injected systems, the RS pulse should occur on the negative going zero crossing and for Ring injected systems, on the positive going zero crossing. This ensures that the ring relay activates and deactivates when the instantaneous ring voltage is near zero. If synchronization is not required, the pin should be tied to 5V. 8R D Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized. 9 TF Tip Feed - A low impedance analog output connected to the TIP terminal through a sense resistor (R S). Functions with the RF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. 10 RF Ring Feed - A low impedance analog output connected to the RING terminal through a sense resistor (RS). Functions with the TF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. 11 V B- Negative Voltage Source - Most negative supply. V B- is typically -48V with an operational range of -42V to -58V. Frequently referred to as “battery”. 12 BG Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground terminal. 13 SHD Switch Hook Detection - A low active LS TTL - compatible logic output. This output is enabled for loop currents exceeding the switch hook threshold. 14 NC Used during production te st. Leave disconnected. HC5503PRI

5 FN6101.0 Functional Diagram 15 PD Power Denial - A low active TTL - Compatible logic input. When enabled, the ring feed voltage collapses to the tip feed voltage (~4V). The DC feed is disabled, but the AC transmission is maintained. The switch hook detect (SHD) is not necessarily valid, and the relay driver (RD) output is disabled. 16 RC Ring Command - A low active TTL - Compatible logic input. When enabled, the relay driver (RD) output goes low on the next high level of the ring sync (RS) input, as long as the SLIC is not in the power denial state (PD = 0) or the subscriber is not already off- hook (SHD = 0). 17 NC Leave disconnected. 18 OUT The analog output of the spare operational amplifier. 19 -IN The inverting analog input of the spare operational amplifier. 20 +IN The non-inverting analog input of the spare operational amplifier. 21 RX Receive Input, Four Wire Side - A high impedance analog input which is internally biased. Capacitive coupling to this input is required. AC signals appearing at this input differentially drive the Tip feed and Ring feed terminals. 22 C 2 Capacitor #2 - An external capacitor to be connected between this terminal and analog ground. This capacitor is required for the proper operation of ring trip detection. Recommended value 0.82µF ±10% 10V non-polarized. 23 AG Analog Ground - To be connected to zero potential and serv es as a reference for the transmit output (TX) and receive input (RX) terminals. 24 TX Transmit Output, Four Wire Side - A low impedance anal og output proportional to the loop current. Transhybrid balancing must be performed beyond this output to completely implement two to four wire conversion. This output is unbalanced and referenced to analog ground. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is essential. NC No internal connection. NOTE: All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first. Pin Descriptions (Continued) DIP/SOIC SYMBOL DESCRIPTION DIFF AMP OP AMP LOOP MONITORING RING CONTROL 2-WIRE LOOP SECONDARY PROTECTION LINE DRIVERS TIP RING VB- VB- PDPOWER DENIAL RP RING RS RF BG TF TIP RD RC RS RING SYNC RING COMMAND RING TRIP SHD TX TRANSMIT OUTPUT OUT +IN -IN RX RECEIVE INPUT SLIC MICROCIRCUIT 1/2 RING RELAY VB- RING VOLTAGE RFS 1/2 RING RELAY RS SWITCH HOOK DETECTION BATTERY FEED LOOP CURRENT LIMITER RP RS: 100 Ω; 1/2W to 2W depending on surge requirements RP:5 0 Ω; 1/2W to 2W depending on surge requirements HC5503PRI

6 FN6101.0 SLIC FUNCTIONAL SCHEMATIC SOIC PIN NUMBERS SHOWN VB2 VB1 VB2 VB3 VB4 VB5 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 VBAT IB9 IB10 IB11 VB+ VB+ A-100 TRANSV’L I/V AMP IB6 R11 VB+ R10 R22 R23 R16 R15 VBAT VBAT R12 VBAT VB+ A-200 LONG’L I/V AMP IB7 R20 VBAT VB+ A-400 TIP FEED AMP IB4 RING FEED SENSE VBAT VBAT VB4 IB8 RING TRIP DETECTOR SWITCH HOOK VB1 IB6 R18 DETECTOR VB+ QD28QD27 VBAT - + GND SHORTS CURRENT LIMITING IB1 VB3 THERMAL LIMITING VB5 STTL AND LOGIC INTERFACE RFC SH GK VB5- IB2 LOAD CURRENT LIMITING R14 R13 VBAT VBAT/2 REFERENCE R21 VBAT A-300 RING FEED AMP IB5 RING RF TIP TF RX C2 VBAT BAT ANA DIG VB+GND GND GND 21 22 11 12 23 6 4 + - OUT 20 19 18 A-500 OP AMP VBAT IB3 VB+ VB+5V IB10 VBAT PD RC SHD NC NC TXC1 RS RD 87245 R17 VB2 VB+ R19 VBAT QD3 QD36 VOLTAGE AND CURRENT BIAS NETWORK HC5503PRI

7 FN6101.0 Surge Protection The SLIC device, in conjunction with an external protection bridge, will withstand high voltage lightning surges and power line crosses. The voltage withstand capability of pins ‘Tip’, ‘Ring’ and ‘RFs’ is ±450V with respect to ground, as shown in Table 1. This device is intended for use with an appropriate secondary protection circuit scheme. The SLIC will withstand longitudinal currents up to a maximum or 30mA RMS, 15mARMS per leg, without any performance degradation. LOGIC GATE SCHEMATIC A B C C B A TTL TO STTL TTL TO STTL TTL TO STTL TO R21 SHDRDPDRCRS TTL TO STTL DELAY LOGIC BIAS RELAY DRIVER SH GK 11 14 SCHOTTKY LOGIC TABLE 1. PARAMETER TEST CONDITION PERFORMANCE (MAX) UNITS Longitudinal Surge 10 µs Rise/ 1000µs Fall ±450 (Plastic) V PEAK Metallic Surge 10 µs Rise/ 1000µs Fall ±450 (Plastic) V PEAK T/GND R/GND 10µs Rise/ 1000µs Fall ±450 (Plastic) V PEAK 50/60Hz Current T/GND R/GND

11 Cycles

315 (Plastic) V RMS HC5503PRI

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6101.0 HC5503PRI Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H µ 0.25(0.010) BM M α M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.020 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 e 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N2 4 2 4 7 α 0o 8o 0o 8o - Rev. 0 12/93