HC5503 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 17
Technical content
Features
- Wide Operating Battery Range (-21V to -44V)
- Single Additional +5V Supply
- 25mA Short Loop Current Limit
- Ring Relay Driver
- Switch Hook and Ring Trip Detect
- Low On-Hook Power Consumption
- On-Hook Transmission
- ITU-T Longitudinal Balance Performance
- Loop Power Denial Function
- Thermal Protection
- Supports Tip, Ring or Balanced Ringing Schemes
- Low Profile Surface Mount Packaging
- Pin Compatible with Industry Standard HC5504B SLIC
- Pb-free Available
Applications
- Analog Subscriber Line Interfaces in Analog Key Systems and Digital ISDN PABX Systems
- Related Literature - AN571, Using Ring Sync with HC-5502A and HC-5504 SLICs
Ordering Information
TEMP. RANGE (°C) PACKAGE PKG. DWG. # HC5503CB 0 to 75 24 Ld SOIC M24.3 HC5503CBZ (Note) 0 to 75 24 Ld SOIC (Pb-free) M24.3 HC5503CBZ96 (Note) 0 to 75 24 Ld SOIC (Pb-free) M24.3 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPLACEMENT PART HC5503PRC
FN4344 Rev 5.00 Page 2 of 17 June 2004 Block Diagram RD RFS TIP TF RING RF VBAT VCC BGND DGND TX RX SHD RS RC PD RING RELAY DRIVER 4-WIRE INTERFACE VF SIGNAL PATH LOOP CURRENT DETECTOR BIAS LOGIC INTERFACE RING TRIP DETECTOR 2-WIRE INTERFACE AGND THERMAL LIMIT
FN4344 Rev 5.00 Page 3 of 17 June 2004 Absolute Maximum Ratings (Note 1) Thermal Information Maximum Continuous Supply Voltages Operating Conditions Operating Temperature Range Thermal Resistance (Typical, Note 2) JA (°C/W) (SOIC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Absolute maximum ratings are limiting values, applied individual ly, beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Unless Otherwise Specified, VBAT = -24V, VCC = 5V, AG = BG = DG = 0V, Typical Parameters TA = 25°C. Min-Max Parameters are Over Operating Temperature Range. PARAMETER CONDITIONS MIN TYP MAX UNITS On Hook Power Dissipation I LONG = 0 (Note 3), VCC = 5V - 80 100 mW Off Hook Power Dissipation R L = 600, ILONG = 0 (Note 4), VCC = 5V - 180 200 mW Off Hook IVCC RL = 600, ILONG = 0 (Note 3), TA = 0°C - - 6.0 mA Off Hook IVCC RL = 600, ILONG = 0 (Note 3), TA = 25°C - - 4.0 mA Off Hook IBAT RL = 600, ILONG = 0 (Notes 3, 4) - 19 23 mA Off Hook Loop Current R L = 400, ILONG = 0 (Note 3) - 22.9 - mA Off Hook Loop Current R L = 400, VBAT = -21.6V, ILONG = 0 (Note 3), TA = 25°C 17.5 - - mA Off Hook Loop Current R L = 200, ILONG = 0 (Note 3) - 25 30 mA Fault Currents TIP to Ground (Note 4) - 27.5 - mA RING to Ground -7 0- m A TIP to RING (Note 4) - 30 - mA TIP and RING to Ground - 140 - mA Ring Relay Drive VOL IOL = 62mA - 0.2 0.5 V Ring Relay Driver Off Leakage V RD = 12V, RC = 1 = HIGH, TA = 25°C - - 25 A Ring Trip Detection Period R L = 600(Note 5) - 2 3 Ring Cycles Switch Hook Detection Threshold 5 - 10.5 mA Loop Current During Power Denial R L = 200 - 2- m A
FN4344 Rev 5.00 Page 4 of 17 June 2004 Dial Pulse Distortion (Note 4) 0 - 0.5 ms Receive Input Impedance (Note 5) - 90 - k Transmit Output Impedance (Note 5) - 10 20 2-Wire Return Loss Referenced to 600 +2.16F (Note 4) SRL LO - 15.5 - dB ERL -2 4- d B SRL HI -3 1- d B Longitudinal Balance 1V RMS 200Hz - 3400Hz, (Note 4) IEEE Method 0°C TA 75°C2-Wire Off Hook 53 58 - dB 2-Wire On Hook 53 58 - dB 4-Wire Off Hook at 1kHz 50 58 - dB Insertion Loss 0dBm Input Level, Referenced 600 2-Wire to 4-Wire at 3.4kHz VTR to VO VO is the Output of the Transhybrid Amplifier - 0.05 0.2 dB 4-Wire to 2-Wire at 300Hz -3.8 -4.0 -4.2 dB Frequency Response 200 - 3400Hz Referenced to Absolute Loss at 1kHz and 0dBm Signal Level (Note 4) - 0.02 0.05 dB Idle Channel Noise, 2-Wire to 4-Wire -15 d B r n C - -89 -85 dBm0p Idle Channel Noise, 4-Wire to 2-Wire (Note 4) - 1 5 dBrnC - -89 -85 dBm0p Absolute Delay (Note 5) 2-Wire to 4-Wire, 4-Wire to 2-Wire - - 2 s Trans Hybrid Loss Balance Network Set Up for 600 Termination at 1kHz 30 40 - dB Overload Level V CC = +5V 2-Wire to 4-Wire (On-hook) 2.5 - - V PEAK 4-Wire to 2-Wire (Off-hook, RL = 600 3.1 - - V PEAK Level Linearity At 1kHz, (Note 4) Referenced to 0dBm Level 2-Wire to 4-Wire, 4-Wire to 2-Wire +3 to -40dBm - - 0.05 dB -40 to -50dBm - - 0.1 dB -50 to -55dBm - - 0.3 dB Electrical Specifications Unless Otherwise Specified, VBAT = -24V, VCC = 5V, AG = BG = DG = 0V, Typical Parameters TA = 25°C. Min-Max Parameters are Over Operating Temperature Range. (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS
FN4344 Rev 5.00 Page 5 of 17 June 2004 Power Supply Rejection Ratio (Note 4), 30 - 60Hz, RL = 200VCC to 2-Wire 35 - - dB VCC to Transmit 35 - - dB VBAT to 2-Wire 20 - - dB VBAT to Transmit 20 - - dB VCC to 2-Wire 200 - 16kHz, R L = 200 35 - - dB VCC to Transmit 35 - - dB VBAT to 2-Wire 35 - - dB VBAT to Transmit 35 - - dB Logic Input Current (RS, RC, PD)0 V VIN 2.4V - - 20 A Logic Inputs Logic ‘0’ VIL -- 0 . 8 V Logic ‘1’ VIH 2.0 - 5.5 V SHD Output I LOAD 800A, VCC = 5V Logic ‘0’ VOL -0 . 1 0 . 4 V Logic ‘1’ VOH ILOAD 40A, VCC = 5V 2.7 - 5.0 V NOTES: 3. I LONG = Longitudinal Current. 4. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. 5. Guaranteed by design, not tested. Electrical Specifications Unless Otherwise Specified, VBAT = -24V, VCC = 5V, AG = BG = DG = 0V, Typical Parameters TA = 25°C. Min-Max Parameters are Over Operating Temperature Range. (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS
load for the 2-wire to 4-wire transmission. output and to provide sufficient overhead for receive signals. current) to flow around the loop. then AC coupled to the earpiece of the telephone set. The HC5503 is optimized for operation with a -24V battery. NOTE: Grounded for AC analysis. FIGURE 1. IMPEDANCE MATCHING CIRCUITRY
Where: VTX = -4RSIL = -600IL. divided by the AC current IL as shown in Equation 2. dividing both sides by IL results in Equation 3. RINTERNAL, reference Figure 2. voltage at VTX times the feedback factor (Equation 5). the Tip feed + Ring feed amplifiers). back factor to match a 900 load is 1/2 (300/600). (10k). R3 should be greater then 90k. FIGURE 2. FEEDBACK EQUIVALENT CIRCUITHC5503
FN4344 Rev 5.00 Page 8 of 17 June 2004 The 2-wire to 4-wire gain is defined as the output voltage V TX divided by the tip to ring voltage (V TR). Where: VTX =- 4 RSIL = -600IL and VTR = (RL)IL = 600IL. The 2-wire to 4-wire gain is ther efore equal to -1.0, as shown in Equation 9. 4-Wire to 2-Wire Gain The 4-wire to 2-wire gain is defined as the output voltage VTR divided by the input voltage, VIN. To determine the 4-wire to 2- wire gain we need to define VTR in terms of VIN. The voltage at VTR is the loop current times the load impedance ZL. For optimum 2-wire return loss, the input impedance of the SLIC (ZO) must equal the load impedance (ZL) of the line. All Equations going further assume ZL= ZO. The loop current IL is the total voltage across the loop divided by the total resistance of the loop. The total voltage across the loop is the sum of the tip feed voltage (VTF) and the ring feed voltage (VRF) where VTF = -VRF . The total resistance is the sum of the sense resistors RB1 and RB2 and the load ZL (ZL +2RS). The total loop current is defined in Equation 11. From Equation 10: Substituting Equation 12 into Equation 11 and solving for VTR: Using Superposition, the voltage at the receive input RX is given as: Where R1 is the effective impedance that is formed by the parallel combination of RINTERNAL (90k), R3 (150k), R1 (10k) and is equal to 8.49k. R2 is the effective impedance that’s formed by the parallel combination of RINTERNAL (90k), R3 (150k), R2 (24.9k) and is equal to 17.25k. VRX for the recommended values of R1 and R2 is given in Equations 15 and 16. For impedance matching to a load other than 600, recalculate the parallel impedances R 1, R2 and substitute into Equation 15. The 4-wire to 2-wire gain is recalculated by using the Equations below. Substituting Equation 16 into Equation 13: From Equation 10: From Equation 1: Substituting Equation 18 into Equation 19: Substituting Equation 20 into Equation 17: Assuming R S = 150 and rearranging terms: The 4-wire to 2-wire gain (Given that: R1 =1 0 k, R2 = 24.9k and R3 = 150kfor a 600 load is: A24– VTX VTR 600– IL 600IL VTR IL ZL IL ZO== (EQ. 10) IL VTF VRF– 2V TF IL VTR ZO VTR 2V TF ZO= (EQ. 13) VRX VTF R1 VTX R2 VIN+== (EQ. 14) VRX VTF 8.49k VTX 17.25k VIN+== (EQ. 15) VRX VTF 0.25 VTX 0.633 VIN+== (EQ. 16) VTR ZO= (EQ. 17) IL VTR ZO VTX 4RS IL–= (EQ. 19) VTX 4RS VTR ZO VTR 2RS VTR ZO ZO 1 300 VTR 1.266ZO V IN= (EQ. 22) A42– VTR VIN 1.266ZO
FN4344 Rev 5.00 Page 12 of 17 June 2004 Pin Descriptions
24 PIN
1 TIP An analog input connected to the TIP (more positive) side of the subscriber loop. Functions with the Ring terminal to receive voice signals from the telephone and for loop monitoring purposes. 2 RING An analog input connected to the RING (more negative) side of the subscriber loop. Functions with the Tip terminal to receive voice signals from the telephone and for loop monitoring purposes. 3 RFS Senses ring side of loop for ring trip detection. During ri nging, the ring signal is inserted into the line at this node and RF is isolated from RFS via a relay. 4V CC Positive Voltage Source - Most positive supply. VCC is typically 5V. 5C 1 Capacitor #1 - An external capacitor to be connected between this terminal and analog ground. Required for proper operation of the loop current limiting function, and for filtering VBAT. Typical value is 0.3F, 16V. 6 DG Digital Ground - To be connected to zero potential and serv es as a reference for all digital inputs and outputs on the SLIC microcircuit. 7 RS Ring Synchronization Input - A TTL - compatible clock in put. The clock should be arranged such that a positive pulse transition occurs on the zero crossing of the ring voltage source, as it appears at the RFS terminal. For Tip side injected systems, the RS pulse should occur on the negative going zero crossing and for Ring injected systems, on the positive going zero crossing. This ensures that the ring relay activates and deactivates when the instantaneous ring voltage is near zero. If synchronization is not required, the pin should be tied to 5V. 8R D Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized. 9 TF Tip Feed - A low impedance analog output connected to the TIP terminal through a 150 feed resistor. Functions with the RF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. 10 RF Ring Feed - A low impedance analog output connec ted to the RING terminal through a 150 feed resistor. Functions with the TF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. 11 V BAT Negative Voltage Source - Most negative supply. VBAT is typically -24V. Frequently referred to as “battery”. 12 BG Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground terminal. 13 SHD Switch Hook Detection - A low active LS TTL - compatible logic output. This output is enabled for loop currents exceeding 10.5mA and disabled for loop currents less than 5mA. 15 PD Power Denial - A low active TTL - Compatible logic input. When enabled, the switch hook detect (SHD) is not necessarily valid, and the relay driver (RD) output is disabled. 16 RC Ring Command - A low active TTL - Compatible logic input. When enabled, the relay driver (RD) output goes low on the next high level of the ring sync (RS) input, as long as the SLIC is not in the power denial state (PD = 0) or the subscriber is not already off-hook (SHD = 0). 21 R X Receive Input, Four Wire Side - A high impedance analog input which is internally biased. Capacitive coupling to this input is required. AC signals appearing at this input deferentially drive the Tip feed and Ring feed terminals, which in turn drive tip and ring through 150 of feed resistance on each side of the line. 22 C 2 Capacitor #2 - An external capacitor to be connected between this terminal and analog ground. This capacitor prevents false ring trip detection from occurring when longitudinal currents are induced onto the subscriber loop from nearby power lines and other noise sources. Recommended value is 1.0F, 20V. This capacitor should be nonpolarized. 23 AG Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX) and receive input (RX) terminals. 24 TX Transmit Output, Four Wire Side - A low impedance analog ou tput which represents the differential voltage across Tip and Ring. Transhybrid balancing must be performed beyond this output to completely implement two to four wire conversion. This output is unbalanced and referenced to analog ground. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is essential. 14 NC Used during production testing. For proper o peration of the SLIC, this pin should float. 17, 18, 19, NC No internal connection. NOTE: All grounds (AG, BG, and DG) must be applied before V CC or VBAT. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first.
FN4344 Rev 5.00 Page 13 of 17 June 2004 Functional Block Diagram Pinout HC5503 (SOIC) TOP VIEW TIP RING DG RS TF RF BG TX N/C N/C AG N/C VCC RX N/C RC PD N/C SHD RD RFS VBAT DIFF AMP LOOP MONITORING RING CONTROL 2-WIRE LOOP SECONDARY PROTECTION LINE DRIVERS TIP RING VBAT VBAT PDPOWER DENIAL RING 150 RF BG TF TIP RD RC RS RING SYNC RING COMMAND RING TRIP SHD TX TRANSMIT OUTPUT RX RECEIVE INPUT SLIC MICROCIRCUIT 1/2 RING RELAY VBAT RING VOLTAGE RFS 1/2 RING RELAY 150 SWITCH HOOK DETECTION BATTERY FEED LOOP CURRENT LIMITER FIGURE 7.
FIGURE 8. FUNCTIONAL SCHEMATIC
High voltage surge conditions are as specified in Table 1. FIGURE 9. LOGIC NETWORK
11 Cycles
- Secondary protection diode bridge recommended is a 2A, 200V type.
- All grounds (AG, BG, and DG) must be applied before VCC or VBAT. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
- Application shows Ring Injected Ringing, Bal anced or Tip injected configuration may be used.
FIGURE 10. -24V APPLICATION CIRCUIT RB1 = RB2 = 150 (1% absolute value). Z1 = 250V to 350V transient protection. PTC used as ring generator ballast.
FN4344 Rev 5.00 Page 17 of 17 June 2004 HC5503 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1999-2004. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H µ 0.25(0.010) BM M M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.020 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 e 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N2 4 2 4 7 0o 8o 0o 8o - Rev. 0 12/93