HC4511

CD54HC4511 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 17

Technical content

/C0067/C0068/C0053/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0084/C0052/C0053/C0049/C0049 /C0066/C0067/C0068/C0262/C0084/C0079/C0262/C0055 /C0083/C0069/C0071/C0077/C0069/C0078/C0084 /C0076/C0065/C0084/C0067/C0072/C0047/C0068/C0069/C0067/C0079/C0068/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082/C0083 SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00682-V to 6-V VCC Operation (’HC4511) /C00684.5-V to 5.5-V VCC Operation (CD74HCT4511) /C0068High-Output Sourcing Capability − 7.5 mA at 4.5 V (CD74HCT4511) − 10 mA at 6 V (’HC4511) /C0068Input Latches for BCD Code Storage /C0068Lamp Test and Blanking Capability /C0068Balanced Propagation Delays and Transition Times /C0068Significant Power Reduction Compared to LSTTL Logic ICs /C0068’HC4511 − High Noise Immunity, N IL or NIH = 30% of VCC at VCC = 5 V /C0068CD74HCT4511 − Direct LSTTL Input Logic Compatibility, VIL = 0.8 V Maximum, VIH = 2 V Minimum − CMOS Input Compatibility, II ≤ 1 µA at VOL , VOH description/ordering information The CD54HC4511, CD74HC4511, and CD74HCT4511 are BCD-to-7 segment latch/decoder/drivers with four address inputs (D0−D 3), an active-low blanking (BL) input, lamp-test (LT) input, and a latch-enable (LE) input that, when high, enables the latches to store the BCD inputs. When LE is low, the latches are disabled, making the outputs transparent to the BCD inputs. These devices have standard-size output transistors, but are capable of sourcing (at standard VOH levels) up to 7.5 mA at 4.5 V. The HC types can supply up to 10 mA at 6 V.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − E Tube of 25 CD74HC4511E CD74HC4511E PDIP − E Tube of 25 CD74HCT4511E CD74HCT4511E Tube of 40 CD74HC4511M −55°C to 125°C SOIC − M Reel of 2500 CD74HC4511M96 HC4511M −55°C to 125°C SOIC − M Reel of 250 CD74HC4511MT HC4511M TSSOP − PW Reel of 2000 CD74HC4511PWR HJ4511TSSOP − PW Reel of 250 CD74HC4511PWT HJ4511 CDIP − F Tube of 25 CD54HC4511F3A CD54HC4511F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright  2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D 1 D 2 LT BL LE D 3 D 0 GND VCC f g a b c d e BCD Inputs BCD Inputs 7-Segment Outputs CD54HC4511 ...F PACKAGE CD74HC4511 . . . E, M, OR PW PACKAGE CD74HCT4511 ...E PACKAGE (TOP VIEW) 01 2 3 456789 DISPLAY a b c d e fg /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0067/C0068/C0053/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0084/C0052/C0053/C0049/C0049 /C0066/C0067/C0068/C0262/C0084/C0079/C0262/C0055 /C0083/C0069/C0071/C0077/C0069/C0078/C0084 /C0076/C0065/C0084/C0067/C0072/C0047/C0068/C0069/C0067/C0079/C0068/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082/C0083 SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

LE BL LT D 3 D 2 D 1 D 0 a b c d e f g DISPLAY X X L X X X X H H H H H H H 8 X LHX XXXL L L L L L L Blank L HHL LLLH HHHHHL 0 L HHL LLHL H HLLLL 1 L HHL LHLH HLHHLH 2 L HHL LHHH HHHL LH 3 L HHL HLLL HHL LHH 4 L HHL HLHH LHHLHH 5 L HHL HHL L LHHHHH 6 L HHL HHHH H HLLLL 7 L HHH LLLH HHHHHH 8 L HHH LLH H HHL LHH 9 L HHH LHLL L L L L L L Blank L HHH LHHL L L L L L L Blank L HHH HLLL L L L L L L Blank L HHH HLHL L L L L L L Blank L HHH HHL L L L L L L L Blank L HHH HHHL L L L L L L Blank X = Don’t care † Depends on BCD code previously applied when LE = L NOTE: Display is blank for all illegal input codes (BCD > HLLH). function diagram D 0 D 1 D 2 D 3 LE BL LT 3 VSS = 8 VDD = 16 a b c d e f g Latch Decoder Driver 7-Segment OutputsBCD Inputs

/C0067/C0068/C0053/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0084/C0052/C0053/C0049/C0049 /C0066/C0067/C0068/C0262/C0084/C0079/C0262/C0055 /C0083/C0069/C0071/C0077/C0069/C0078/C0084 /C0076/C0065/C0084/C0067/C0072/C0047/C0068/C0069/C0067/C0079/C0068/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082/C0083 SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram 15 f BL 4 13 a b c e g 3LT D 3 D 2 D 1 D 0 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE D D D D Q Q Q Q Q Q Q Q Latch Latch Latch Latch LE LE 10 d

/C0067/C0068/C0053/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0084/C0052/C0053/C0049/C0049 /C0066/C0067/C0068/C0262/C0084/C0079/C0262/C0055 /C0083/C0069/C0071/C0077/C0069/C0078/C0084 /C0076/C0065/C0084/C0067/C0072/C0047/C0068/C0069/C0067/C0079/C0068/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082/C0083 SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Lead temperature (during soldering): Unit inserted into a PC board (minimum thickness 1/16 in, 1.59 mm), † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions for ’HC4511 (see Note 3) TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C UNIT MIN MAX MIN MAX MIN MAX UNIT VCC Supply voltage 2 6 2 6 2 6 V VCC = 2 V 1.5 1.5 1.5 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 3.15 VVIH High-level input voltage VCC = 6 V 4.2 4.2 4.2 V VCC = 2 V 0.5 0.5 0.5 VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 1.35 VVIL Low-level input voltage VCC = 6 V 1.8 1.8 1.8 V VI Input voltage 0 VCC 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC 0 VCC V VCC = 2 V 1000 1000 1000 tt Input transition (rise and fall) time VCC = 4.5 V 500 500 500 nstt Input transition (rise and fall) time VCC = 6 V 400 400 400 ns NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

/C0067/C0068/C0053/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0084/C0052/C0053/C0049/C0049 /C0066/C0067/C0068/C0262/C0084/C0079/C0262/C0055 /C0083/C0069/C0071/C0077/C0069/C0078/C0084 /C0076/C0065/C0084/C0067/C0072/C0047/C0068/C0069/C0067/C0079/C0068/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082/C0083 SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions for CD74HCT4511 (see Note 4) TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C UNIT MIN MAX MIN MAX MIN MAX UNIT VIH High-level input voltage 2 2 2 V VIL Low-level input voltage 0.8 0.8 0.8 V VI Input voltage VCC VCC VCC V VO Output voltage VCC VCC VCC V tt Input transition (rise and fall) time 500 500 500 ns NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ’HC4511 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C UNITPARAMETER TEST CONDITIONS VCC MIN MAX MIN MAX MIN MAX UNIT 2 V 1.9 1.9 1.9 IOH = −20 µA 4.5 V 4.4 4.4 4.4 VOH VI = VIH or VIL IOH = −20 µA 6 V 5.9 5.9 5.9 VVOH VI = VIH or VIL V IOH = −10 mA 6 V 5.48 5.2 5.34 2 V 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.1 0.1 0.1 VOL VI = VIH or VIL IOL = 20 µA 6 V 0.1 0.1 0.1 VVOL VI = VIH or VIL IOL = 4 mA 4.5 V 0.26 0.4 0.33 V IOL = 5.2 mA 6 V 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±1 ±1 µA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA C i 10 10 10 pF

/C0067/C0068/C0053/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0084/C0052/C0053/C0049/C0049 /C0066/C0067/C0068/C0262/C0084/C0079/C0262/C0055 /C0083/C0069/C0071/C0077/C0069/C0078/C0084 /C0076/C0065/C0084/C0067/C0072/C0047/C0068/C0069/C0067/C0079/C0068/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082/C0083 SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT VOH VI = VIH or VIL IOH = −20 µA 4.5 V 4.4 4.4 4.4 VVOH VI = VIH or VIL IOH = −4 mA 4.5 V 3.98 3.7 3.84 V VOL VI = VIH or VIL IOL = 20 µA 4.5 V 0.1 0.1 0.1 VVOL VI = VIH or VIL IOL = 4 mA 4.5 V 0.26 0.4 0.33 V II VI = VCC to GND 5.5 V ±0.1 ±1 ±1 µA ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA ∆ICC † One input at VCC − 2.1 V, Other inputs at 0 or VCC 4.5 V to 5.5 V 100 360 490 450 µA C i 10 10 10 pF † Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. HCT INPUT LOADING TABLE INPUT UNIT LOADS ‡ LT, LE 1.5 BL, Dn 0.3 ‡ Unit load is ∆ICC limit specified in electrical characteristics table, e.g., 360 µA maximum at 25°C. ’HC4511 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C UNITVCC MIN MAX MIN MAX MIN MAX UNIT

2 V 80 120 100

tw Pulse duration, LE low 4.5 V 16 24 20 nstw Pulse duration, LE low

6 V 14 20 17

2 V 60 90 75

tsu Setup time, BCD inputs before LE↑ 4.5 V 12 18 15 nstsu Setup time, BCD inputs before LE↑

6 V 10 15 13

2 V 3 3 3

th Hold time, BCD inputs before LE↑ 4.5 V 3 3 3 nsth Hold time, BCD inputs before LE↑

6 V 3 3 3

/C0067/C0068/C0053/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0084/C0052/C0053/C0049/C0049 /C0066/C0067/C0068/C0262/C0084/C0079/C0262/C0055 /C0083/C0069/C0071/C0077/C0069/C0078/C0084 /C0076/C0065/C0084/C0067/C0072/C0047/C0068/C0069/C0067/C0079/C0068/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082/C0083 SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ’HC4511 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE VCC TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C UNITPARAMETER (INPUT) (OUTPUT) CAPACITANCE VCC MIN TYP MAX MIN MAX MIN MAX UNIT

2 V 300 450 375

C L = 50 pF 4.5 V 60 90 75 D n Output C L = 50 pF

6 V 51 77 64

C L = 15 pF 5 V 25

2 V 270 405 340

C L = 50 pF 4.5 V 54 81 68 LE Output C L = 50 pF

6 V 46 69 58

C L = 15 pF 5 V 23 nstpd 2 V 220 330 275 ns BL Output C L = 50 pF 4.5 V 44 66 55 BL Output C L = 50 pF

6 V 37 56 47

C L = 15 pF 5 V 18

2 V 160 240 200

C L = 50 pF 4.5 V 32 48 40 LT Output C L = 50 pF

6 V 27 41 34

C L = 15 pF 5 V 13

2 V 75 110 95

tt Any C L = 50 pF 4.5 V 15 22 19 nstt Any C L = 50 pF

6 V 13 19 16

/C0067/C0068/C0053/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0052/C0053/C0049/C0049/C0044 /C0067/C0068/C0055/C0052/C0072/C0067/C0084/C0052/C0053/C0049/C0049 /C0066/C0067/C0068/C0262/C0084/C0079/C0262/C0055 /C0083/C0069/C0071/C0077/C0069/C0078/C0084 /C0076/C0065/C0084/C0067/C0072/C0047/C0068/C0069/C0067/C0079/C0068/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082/C0083 SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range VCC = 4.5 V (unless otherwise noted) (see Figure 2) TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C UNIT MIN MAX MIN MAX MIN MAX UNIT tw Pulse duration, LE low 16 24 20 ns tsu Setup time, BCD inputs before LE↑ 16 24 20 ns th Hold time, BCD inputs before LE↑ 5 5 5 ns CD74HCT4511 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE VCC TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C UNITPARAMETER (INPUT) (OUTPUT) CAPACITANCE VCC MIN TYP MAX MIN MAX MIN MAX UNIT D n Output C L = 50 pF 4.5 V 60 90 75 D n Output C L = 15 pF 5 V 25 LE Output C L = 50 pF 4.5 V 54 81 68 tpd LE Output C L = 15 pF 5 V 23 nstpd BL Output C L = 50 pF 4.5 V 44 66 55 ns BL Output C L = 15 pF 5 V 18 LT Output C L = 50 pF 4.5 V 33 50 41 LT Output C L = 15 pF 5 V 13 tt Any C L = 50 pF 4.5 V 15 22 19 ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TYP UNIT C pd† Power dissipation capacitance ’HC4511 114 pFC pd† Power dissipation capacitance CD74HCT4511 110 pF † C pd is used to determine the dynamic power consumption, per package. PD = Cpd VCC 2 fi + ∑ C L VCC 2 fo where: fi = input frequency fo = output frequency C L = output load capacitance VCC = supply voltage

NOTES: A. C L includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NOTES: A. C L includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-8773301EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC4511F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74HC4511E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC4511EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC4511M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4511E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT4511EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2006, Texas Instruments Incorporated