CD74HC4060 TI | Alldatasheet

Document overview

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Technical content

Features

  • Onboard Oscillator
  • Common Reset
  • Negative Edge Clocking
  • Typical f MAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC
  • Fanout (Over Temperature Range)
  • Wide Operating Temperature Range . . . -55 oC to 125oC
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il≤ 1µA at VOL , VOH Pinout CD74HC4060, CD74HCT4060 (PDIP, SOIC) TOP VIEW Q12 Q13 Q14 GND V CC MR φI φO φO Q10 February 1998 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 File Number 1654.1 CD74HC4060, CD74HCT4060 High Speed CMOS Logic 14-Stage Binary Counter with Oscillator [ /Title (CD74 HC406 CD74 HCT40 60) /Sub- ject (High Speed CMOS

Description

The Harris CD74HC4060 and CD74HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition ofφI (and φO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times. In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels. Functional Diagram

Ordering Information

PART NUMBER TEMP. RANGE ( oC) PACKAGE PKG. NO. CD74HC4060E -55 to 125 16 Ld PDIP E16.3 CD74HCT4060E -55 to 125 16 Ld PDIP E16.3 CD74HC4060M -55 to 125 16 Ld SOIC M16.15 CD74HCT4060M -55 to 125 16 Ld SOIC M16.15 NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. φI Q12 Q14 φO φO MR Q13 Q10 14-STAGE RIPPLE COUNTER AND OSCILLATOR GND = 8 VCC = 16 CD74HC4060, CD74HCT4060

FIGURE 1. LOGIC BLOCK DIAGRAM

Absolute Maximum Ratings Thermal Information DC Input Diode Current, IIK DC Output Diode Current, IOK DC Drain Current, per Output, IO Operating Conditions Supply Voltage Range, VCC DC Input or Output Voltage, V Input Rise and Fall Time Thermal Resistance (Typical, Note 3) θ JA (oC/W) (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oCT O1 2 5oC UNITSVI(V) I O (mA) MIN TYP MAX MIN MAX MIN MAX HC TYPES High Level Input Voltage V Low Level Input Voltage High Level Output Voltage Q Outputs CMOS Loads V OH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V High Level Output Voltage Q Outputs TTL Loads - - --- - - - - V Low Level Output Voltage Q Outputs CMOS Loads V OL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V Low Level Output Voltage Q Outputs TTL Loads - - --- - - - - V High-Level Output Voltage φO Output (Pin 10) CMOS Loads V OH VCC or GND CD74HC4060, CD74HCT4060

VoltageφO Output (Pin 10) TTL Loads Note 6 V OH VCC or GND Low-Level Output VoltageφO Output (Pin 10) CMOS Loads V OL VCC or GND Low-Level Output Voltage φO Output (Pin 10) TTL Loads V OL VCC or GND High-Level Output VoltageφO Output (Pin 9) TTL Loads V Low-Level Output VoltageφO Output (Pin 9) TTL Loads V Input Leakage Current II VCC or GND Quiescent Device Current ICC VCC or GND 0 6 - - 8 - 80 - 160 µA HCT TYPES High Level Input Voltage VIH - - 4.5 to 5.5 2-- 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 High Level Output Voltage Q Outputs CMOS Loads V OH VIH or VIL Note 5 High Level Output Voltage Q Outputs TTL Loads Low Level Output Voltage Q Outputs CMOS Loads V OL VIH or VIL Note 5 Low Level Output Voltage Q Outputs TTL Loads High-Level Output Voltage φO Output (Pin 10) CMOS Loads V OH VCC or GND High-Level Output VoltageφO Output (Pin 10) TTL Loads Note 6 V OH VCC or GND Low-Level Output VoltageφO Output (Pin 10) CMOS Loads V OL VCC or GND PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oCT O1 2 5oC UNITSVI(V) I O (mA) MIN TYP MAX MIN MAX MIN MAX CD74HC4060, CD74HCT4060

VoltageφO Output (Pin 10) TTL Loads V OL VCC or GND High-Level Output VoltageφO Output (Pin 9) TTL Loads V Low-Level Output VoltageφO Output (Pin 9) TTL Loads V OL VIH or VIL Note 5 Input Leakage Current II Any Voltage Between VCC and GND Quiescent Device Current ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load ΔI CC (Note 4) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTES: 5. For pin 11 VIH = 3.15V, VIL = 0.9V. 6. Limits not valid when pin 12 (instead of pin 11) is used as control input. PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oCT O1 2 5oC UNITSVI(V) I O (mA) MIN TYP MAX MIN MAX MIN MAX HCT Input Loading Table INPUT UNIT LOADS MR 0.35 NOTE: Unit Load isΔICC limit specified in DC Electrical Specifica- tions Table, e.g. 360µA max at 25oC. Prerequisite for Switching Specifications PARAMETER SYMBOL V CC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX HC TYPES Maximum Input Pulse Frequency t MAX 2 6 - - 5 - - 4 - - MHz 4.5 30 - - 25 - - 20 - - MHz 6 35 - - 29 - - 23 - - MHz Input Pulse Width t W 2 80 - - 100 - - 120 - - ns 61 4 - -1 7- -2 0- - n s Reset Removal Time t REM 2 100 - - 125 - - 150 - - ns 61 7 - -2 1- -2 6- - n s CD74HC4060, CD74HCT4060

Reset Pulse Width t W 2 80 - - 100 - - 120 - - ns 61 4 - -1 7- -2 0- - n s HCT TYPES Maximum Input, Pulse Frequency tMAX 4.5 30 - - 25 - - 20 - - MHz Input Pulse Width t W 4.5 16 - - 20 - - 24 - - ns Reset Removal Time t REM 4.5 26 - - 33 - - 39 - - ns Reset Pulse Width t W 4.5 25 - - 31 - - 38 - - ns Prerequisite for Switching Specifications (Continued) PARAMETER SYMBOL V CC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX Switching SpecificationsInput tr, tf= 6ns PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX HC TYPES Propagation Delay t PLH , tPHL C L = 50pF 2 - - 300 - 375 - 450 ns φI to Q4 4.5 - - 60 - 75 - 90 ns C L = 15pF 5 - 25 - - - - - ns C L = 50pF 6 - - 51 - 64 - 78 ns Q n to Qn+1 tPLH , tPHL C L = 50pF 2 - - 80 - 100 - 120 ns 4.5 - - 16 - 20 - 24 ns C L = 15pF 5 - 6 - - - - - ns C L = 50pF 6 - - 14 - 17 - 20 ns MR to Qn tPHL C L = 50pF 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns C L = 15pF 5 - 14 - - - - - ns C L = 50pF 6 - - 30 - 37 - 45 ns Output Transition Time t THL , tTLH C L = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Input Capacitance C I (TBD) Propagation Dissipation Capacitance HCT TYPES Propagation Delay tPLH , tPHL C L = 50pF 2 - - - - - - - -ns φI to Q4 4.5 - - 66 - 83 - 100 ns CD74HC4060, CD74HCT4060

  1. CPD is used to determine the dynamic power consumption, per package.
  2. At very high frequencies f = 1/2.2 RXC X no longer gives an

FIGURE 2. FREQUENCY OF ON-BOARD OSCILLATOR AS A

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