MM74HC4060 FAIRCHILD | Alldatasheet

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Features

■ Typical propagation delay: 16 ns ■ Wide operating voltage range: 2–6V ■ Low input current: 1 µA maximum ■ Low quiescent current: 80 µA maximum (74 Series) ■ Output drive capability: 10 LS-TTL loads Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View Order Number Package Number Package Description MM74HC4060M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74HC4060SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC4060MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC4060N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2 MM74HC4060 Logic Diagram

3 www.fairchildsemi.com MM74HC4060 Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating: plastic “N” package: −12 mW/ °C from 65°C to 85°C. Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH , and VOL ) occur for HC at 4.5V. Thus the 4.5V values should be used when rent (IIN, ICC , and IOZ ) occur for CMOS at the higher voltage and so the 6.0V values should be used. Supply Voltage (VCC ) −0.5 to +7.0V DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT ) −0.5 to VCC +0.5V Clamp Diode Current (ICD ) ±20 mA DC Output Current, per pin (IOUT ) ±25 mA DC V CC or GND Current, per pin (ICC ) ±50 mA Storage Temperature Range (TSTG ) −65°C to +150°C Power Dissipation (PD ) (Note 3) 600 mW S.O. Package only 500 mW Lead Temperature (T (Soldering 10 seconds) 260 °C Min Max Units Supply Voltage (VCC )2 6 V DC Input or Output Voltage (VIN, VOUT )0 V CC V Operating Temperature Range (TA) −40 +85 °C Input Rise or Fall Times (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Symbol Parameter Conditions VCC TA = 25°CT A = −40 to 85°CT A = −55 to 125°C Units Typ Guaranteed Limits VIH Minimum HIGH 2.0V 1.5 1.5 1.5 V Level Voltage 4.5V 3.15 3.15 3.15 V (Not Applicable to Pins 9 & 10) 6.0V 4.2 4.2 4.2 V V IL Maximum LOW Level 2.0V 0.5 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 1.35 V (Not Applicable to Pins 9 & 10) 6.0V 1.8 1.8 1.8 V V OH Minimum HIGH Level V IN = VIH or VIL Except Pins VIN = VIH or VIL Pins V IN = VIH or VIL 3.98 3.84 3.7 V 9 & 10 |I OUT | = 0.4 mA 5.48 5.34 5.2 V |IOUT | = 0.52 mA VOL Maximum LOW Level V IN = VIH or VIL Output Voltage |I OUT | ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V Except Pins VIN = VIH or VIL Pins V IN = VIH or VIL 0.26 0.33 0.4 V 9 & 10 |I OUT | = 0.4 mA 0.26 0.33 0.4 V |IOUT | = 0.52 mA IIN Maximum Input Current V IN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent V IN = VCC or GND Supply Current I OUT = 0 µA6 . 0 V 8 . 0 8 0 1 6 0 µA

www.fairchildsemi.com 4 MM74HC4060 VCC = 5V, TA = 25°C, CL = 15 pF , tr = tf = 6 ns VCC = 2.0V to 6.0V, CL = 50 pF , tr = tf = 6 ns (unless otherwise specified) Note 5: Typical Propagation delay time to any output can be calculated using: tP = 17+12(N–1) ns; where N is the number of the output, QW , at VCC = 5V. Note 6: C PD determines the no load dynamic power consumption, PD = C PD V CC 2 f+ICC V CC , and the no load dynamic current consumption, IS = C PD VCC f+ ICC . Symbol Parameter Conditions Typ Guaranteed Units Limit fMAX Maximum Clock Frequency 30 MHz tPHL , tPLH Maximum Propagation (Note 5) 40 20 ns Delay to Q4 tPHL , tPLH Maximum Propagation 16 40 ns Delay to any Q tREM Minimum Reset 10 20 ns Removal Time t W Minimum Pulse Width 10 16 ns Symbol Parameter Conditions VCC TA = 25°CT A = −40 to 85°CT A = −55 to 125°C Units Typ Guaranteed Limits fMAX Maximum Operating 2.0V 6 5 4 MHz Frequency 4.5V 30 24 20 MHz 6.0V 35 28 24 MHz tPHL , tPLH Maximum Propagation 2.0V 120 380 475 171 ns Delay Clock to Q4 4.5V 42 76 95 114 ns 6.0V 35 65 81 97 ns tPHL Maximum Propagation 2.0V 72 240 302 358 ns Delay Reset to any Q 4.5V 24 48 60 72 ns 6.0V 20 41 51 61 ns tPHL , tPLH Maximum Propagation 2.0V 125 156 188 ns Delay Between Stages 4.5V 25 31 38 ns Q n to Qn+1 6.0V 21 26 31 ns tREM Minimum Reset 2.0V 100 125 150 ns Removal Time 4.5V 20 25 30 ns 6.0V 17 21 25 ns tW Minimum Pulse Width 2.0V 80 100 120 ns 4.5V 16 20 24 ns 6.0V 14 17 20 ns tr, tf Maximum Input Rise and 2.0V 1000 1000 1000 ns Fall Time 4.5V 500 500 500 ns 6.0V 400 400 400 ns tTHL , tTLH Maximum Output Rise 2.0V 30 75 95 110 ns and Fall Time 4.5V 10 15 19 22 ns 6.0V 9 13 16 19 ns C PD Power Dissipation (per package) 55 pF Capacitance (Note 6) C IN Maximum Input 5 10 10 10 pF Capacitance

5 www.fairchildsemi.com MM74HC4060 Timing Diagram

www.fairchildsemi.com 6 MM74HC4060 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

7 www.fairchildsemi.com MM74HC4060 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74HC4060 14 Stage Binary Counter LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E