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Technical content

Features

  • Output Drive Capability: 10 LSTTL Loads
  • Outputs Directly Interface to CMOS, NMOS, and TTL
  • Operating V oltage Range: 2.0 to 6.0 V
  • Low Input Current: 1 /C0109A
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance With JEDEC Standard No. 7A Requirements
  • Chip Complexity: 390 FETs or 97.5 Equivalent Gates
  • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
  • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant LOGIC DIAGRAM Q47 Q55 Q64 Q76 Q814 Q913 Q1015 Q121 Q132 Q143 Osc In 11 Reset 12 Pin 16 = VCC Pin 8 = GND Osc Out 1 Osc Out 2 910 www.onsemi.com See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

SOIC−16 D SUFFIX CASE 751B TSSOP−16 DT SUFFIX CASE 948F HC4060AG AWLYWW HC40 60A ALYW/C0071 /C0071 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or /C0071= Pb−Free Package (Note: Microdot may be in either location) FUNCTION TABLE Clock Reset Output State X L L H No Change Advance to Next State All Outputs Are Low SOIC−16 TSSOP−16 PIN ASSIGNMENT 16−Lead Package (Top View) 1516 14 13 12 11 10 21 34567 VCC Q10 Q8 Q9 Reset Osc In Osc Out 1 Osc Out 2 Q12 Q13 Q14 Q6 Q5 Q7 Q4 GND

www.onsemi.com MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, SOIC Package† 500 450 mW Tstg Storage Temperature Range – 65 to + 150 /C0095C TL Lead Temperature, 1 mm from Case for 10 Seconds SOIC or TSSOP Package 260 /C0095C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/ /C0095C from 65/C0095 to 125/C0095C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.5* 6.0 V Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature Range, All Package Types –55 +125 /C0095C tr, tf Input Rise/Fall Time V CC = 2.0 V (Figure 1) V CC = 4.5 V VCC = 6.0 V 1000 500 400 ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. *The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested at 2.0 V by driving Pin 11 with an external clock source. DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition VCC V Guaranteed Limit Unit−55 to 25°C ≤85°C ≤125°C VIH Minimum High−Level Input Voltage Vout = 0.1V or VCC −0.1V |Iout| ≤ 20/C0109A 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low−Level Input Voltage Vout = 0.1V or VCC − 0.1V |Iout| ≤ 20/C0109A 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 V VOH Minimum High−Level Output Voltage (Q4−Q10, Q12−Q14) Vin = VIH or VIL |Iout| ≤ 20/C0109A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V Vin =VIH or VIL |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 VOL Maximum Low−Level Output Voltage (Q4−Q10, Q12−Q14) Vin = VIH or VIL |Iout| ≤ 20/C0109A 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V Vin = VIH or VIL |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance cir- cuit. For proper operation, V in and Vout should be constrained to the range GND /C0118 (Vin or Vout) /C0118 VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.

www.onsemi.com DC CHARACTERISTICS (Voltages Referenced to GND) (continued) Symbol Unit Guaranteed LimitVCC VConditionParameterSymbol Unit≤125°C≤85°C−55 to 25°C VCC VConditionParameter VOH Minimum High−Level Output Voltage (Osc Out 1, Osc Out 2) Vin = VCC or GND |Iout| ≤ 20/C0109A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V Vin =VCC or GND |I out| ≤ 0.7mA |Iout| ≤ 1.0mA |Iout| ≤ 1.3mA 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 VOL Maximum Low−Level Output Voltage (Osc Out 1, Osc Out 2) Vin = VCC or GND |Iout| ≤ 20/C0109A 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V Vin =VCC or GND |I out| ≤ 0.7mA |Iout| ≤ 1.0mA |Iout| ≤ 1.3mA 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 /C0109A ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0/C0109A 6.0 4 40 160 /C0109A AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symbol Parameter VCC V Guaranteed Limit Unit−55 to 25°C ≤85°C ≤125°C fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 3.0 4.5 6.0 6.0 9.0 8.0 MHz tPLH, tPHL Maximum Propagation Delay, Osc In to Q4* (Figures 1 and 4) 2.0 3.0 4.5 6.0 300 180 375 200 450 250 ns tPLH, tPHL Maximum Propagation Delay, Osc In to Q14* (Figures 1 and 4) 2.0 3.0 4.5 6.0 500 350 250 200 750 450 275 220 1000 600 300 250 ns tPHL Maximum Propagation Delay, Reset to Any Q (Figures 2 and 4) 2.0 3.0 4.5 6.0 195 245 100 300 125 ns tPLH, tPHL Maximum Propagation Delay, Qn to Qn+1 (Figures 3 and 4) 2.0 3.0 4.5 6.0 125 ns AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) − continued Symbol Parameter VCC V Guaranteed Limit Unit−55 to 25°C ≤85°C ≤125°C tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 3.0 4.5 6.0 110 ns Cin Maximum Input Capacitance 10 10 10 pF * For T A = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations: CPD Power Dissipation Capacitance (Per Package)* Typical @ 25°C, VCC = 5.0 V pF35 * Used to determine the no−load dynamic power consumption: P D = CPD VCC2f + ICC VCC.

www.onsemi.com TIMING REQUIREMENTS (Input tr = tf = 6 ns) Symbol Parameter VCC V Guaranteed Limit Unit−55 to 25°C ≤85°C ≤125°C trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 3.0 4.5 6.0 100 125 100 150 120 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 3.0 4.5 6.0 110 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 3.0 4.5 6.0 110 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns Device Package Shipping† MC74HC4060ADG SOIC−16 (Pb−Free)

48 Units / Rail

MC74HC4060ADR2G SOIC−16 (Pb−Free)

2500 Units / Reel

NLV74HC4060ADR2G* SOIC−16 (Pb−Free) MC74HC4060ADTG TSSOP−16 (Pb−Free)

96 Units / Rail

MC74HC4060ADTR2G TSSOP−16 (Pb−Free) NLVHC4060ADTR2G* TSSOP−16 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.

TABLE 1. CRYSTAL OSCILLATOR AMPLIFIER SPECIFICATIONS (TA = 25°C; Input = Pin 11, Output = Pin 10)

5.0 Expected Minimum

4.0 Expected Minimum

3.3 Expected Minimum

3.1 Expected Minimum

Figure 8. Equivalent Crystal Networks Value are supplied by crystal manufacturer (parallel resonant crystal). Figure 9. Series Equivalent Crystal Load Figure 10. Parasitic Capacitances of the Amplifier the load. Ca and Rf typically have minimal effect below 2MHz. Values are listed in Table 1.

www.onsemi.com DESIGN PROCEDURES The following procedure applies for oscillators operating below 2MHz where Z is a resistor R1. Above 2MHz, additional impedance elements should be considered: Cout and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from 180°C. Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation. Ze /C0043 /C0042jXCo(Rs /C0041jXLs /C0042jXCs) /C0042jXCo /C0041Rs /C0041jXLs /C0042jXCs /C0043Re /C0041jXe Reactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency. The maximum Rs for the crystal should be used in the equation. Step 2: Determine β, the attenuation, of the feedback network. For a closed-loop gain of 2,Aνβ = 2,β = 2/Aν where Aν is the gain of the HC4060A amplifier. Step 3: Determine the manufacturer’s loading capacitance. For example: A manufacturer may specify an external load capacitance of 32pF at the required frequency. Step 4: Determine the required Q of the system, and calculate Rload, For example, a manufacturer specifies a crystal Q of 100,000. In-circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then Rload = (2πfoLS/Q) − Rs where Ls and Rs are crystal parameters. Step 5: Simultaneously solve, using a computer, /C0098/C0043XC /C0064XC2 R /C0064Re /C0041XC2 (Xe /C0042XC) ( Eq 1 (with feedback phase shift = 180°) Xe /C0043XC2 /C0041XC /C0041ReXC2 R /C0043XCload ( Eq 2 (where the loading capacitor is an external load, not including Co) Rload /C0043 RXCoXC2 [(XC /C0041XC2)(XC /C0041XCo) /C0042XC(XC /C0041XCo /C0041XC2)] X2C2(XC /C0041XCo)2 /C0041R2(XC /C0041XCo /C0041XC2)2 ( Eq 3 Here R = Rout + R1. Rout is amp output resistance, R1 is Z. The C corresponding to XC is given by C = C1 + Cin. Alternately, pick a value for R1 (i.e, let R1 = RS). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact that Q = 2πfoLs/(Rs + Rload) to find in-circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure. CHOOSING R1 Power is dissipated in the effective series resistance of the crystal. The drive level specified by the crystal manufacturer is the maximum stress that a crystal can withstand without damage or excessive shift in frequency. R1 limits the drive level. To verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a function of voltage at Osc Out 2 (Pin 9). The frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal will decrease in frequency or become unstable with an increase in supply voltage. The operating supply voltage must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the oscillator start-up time is proportional to the value of R1. SELECTING Rf The feedback resistor, Rf, typically ranges up to 20M/C0087. Rf determines the gain and bandwidth of the amplifier. Proper bandwidth insures oscillation at the correct frequency plus roll-off to minimize gain at undesirable frequencies, such as the first overtone. Rf must be large enough so as to not affect the phase of the feedback network in an appreciable manner. ACKNOWLEDGEMENTS AND RECOMMENDED REFERENCES The following publications were used in preparing this data sheet and are hereby acknowledged and recommended for reading: Technical Note TN-24, Statek Corp. Technical Note TN-7, Statek Corp. D. Babin, “Designing Crystal Oscillators”, Machine Design, March 7, 1985. D. Babin, “Guidelines for Crystal Oscillator Design”, Machine Design, April 25, 1985. ALSO RECOMMENDED FOR READING: E. Hafner, “The Piezoelectric Crystal Unit-Definitions and Method of Measurement”, Proc. IEEE, V ol. 57, No. 2, Feb., 1969. D. Kemper, L. Rosine, “Quartz Crystals for Frequency Control”, Electro-Technology, June, 1969. P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic Design, May, 1966.

Figure 11. Timing Diagram

www.onsemi.com PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE B ÇÇÇ ÇÇÇ DIM MIN MAX MIN MAX INCHESMILLIMETERS A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. /C0095/C0095/C0095/C0095 SECTION N−N SEATING PLANE IDENT. PIN 1 1 8 16 9 DETAIL E J B C D A K H G ÉÉÉ ÉÉÉ DETAIL E F M L 2X L/2 −U− SU0.15 (0.006) T SU0.15 (0.006) T SUM0.10 (0.004) V ST 0.10 (0.004) −T− −V− −W− 0.25 (0.010) 16X REFK N N 7.06 16X 0.36 16X 1.26 0.65 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 16 9 SEATING PLANE F JM R X 45/C0095 G

8 PLP−B−

−A− M0.25 (0.010) B S −T− D K C 16 PL SBM0.25 (0.010) A ST DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 6.40 16X 0.58 16X 1.12 1.27 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries i n the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . A listing of ON Semiconductor’s product/patent ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the right s of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 MC74HC4060A/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative