M74HC4060RM13TR STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 16

Technical content

Datasheet sections

  • 1 Pin description
  • 2 Functional description
  • 3 Maximum ratings
  • 4 Electrical characteristics
  • 5 Waveforms
  • 6 Package information
  • 7 Revision history

Features

 High speed: fmax = 65 MHz (typ.) at VCC = 6 V  Low power dissipation: ICC = 4 A (max.) at TA = 25 °C  High noise immunity: VNIH = VNIL = 28% VCC (min.)  Symmetrical output impedance: |IOH| = IOL = 4 mA (min.)  Balanced propagation delays: TPLH  TPHL  Wide operating voltage range: VCC (opr.) = 2 V to 6 V  Pin and function compatible with 74 series 4060

Applications

 Automotive  Industrial  Computer  Consumer

Description

The M74HC4060 device is a high speed CMOS 14-stage binary counter/oscillator fabricated with silicon gate C2MOS technology. The oscillator configuration allows design of either RC or crystal oscillator circuits. A high level on the CLEAR accomplishes the reset function, i.e. all counter outputs are made low and the oscillator is disabled. A negative transition on the clock input increments the counter. Ten kinds of divided output are provided; 4 to 10 and 12 to 14 stage inclusive. The maximum division available at Q12 is 1/16384 of the oscillator frequency. The  I input and the CLEAR input are equipped with protection circuits against static discharge and transient excess voltage. 766233',3 62 Table 1. Device summary

  1. Qualification and characterization according to AEC Q1 00 and Q003 or equivalent, advanced screening according to AEC

Q001 and Q002 or equivalent.

1 Pin description

Figure 1. Pin connection and IEC logic symbols Figure 2. Input and output equivalent circuit Table 2. Pin description

12 CLEAR Master reset

8 GND Ground (0 V)

16 V CC Positive supply voltage

2 Functional description

Figure 3. Logic diagram

  1. This logic diagram has not be used to estimate propagation delays.

Table 3. Truth table

3 Maximum ratings

Table 4. Absolute maximum ratings(1)

  1. Absolute maximum ratings are those values bey ond which damage to the device may occur. Functional

operation under these conditions is not implied. Table 5. Recommended operating conditions

4 Electrical characteristics

Table 6. DC specifications

Table 7. AC electrical characteristics (CL = 50 pF, input tr = tf = 6 ns)

Figure 4. Test circuit

  1. C L = 50 pF or equivalent (includes jig and probe capacitance)

RT = ZOUT of pulse generator (typically 50 ). Table 8. Capacitive characteristics

  1. C PD is defined as the value of the IC's internal equivalent capacitance which is calculated from the

be obtained by the following equation. ICC(opr.) = CPD x VCC x fIN + ICC.

5 Waveforms

Figure 5. Waveform 1: propagation delay times, minimum pulse width (I) Figure 6. Waveform 2: propagation delay times, minimum pulse width (CLEAR)

Figure 9. Typical clock drive circuits

6 Package information

specifications, grade definitions and product status are available at: www.st.com. Figure 10. Plastic DIP-16 package outline Table 9. Plastic DIP-16 (0.25) package mechanical data

Figure 11. SO-16 package outline Table 10. SO-16 package mechanical data

Figure 12. TSSOP-16 package outline Table 11. TSSOP-16 mechanical data

7 Revision history

Table 12. Document revision history 1-Feb-2008 1 Initial release. Added Applications on page 1. range, updated package, added marking). Redrawn Figure 1, Figure 3, Figure 5 to Figure 9. Minor corrections throughout document.