HC4052A

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Document overview

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• PDF pages: 17

Technical content

Features

• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (VCC − VEE) = 2.0 to 12.0 V
• Digital (Control) Power Supply Range (VCC − GND) = 2.0 to 6.0 V
• Improved Linearity and Lower ON Resistance Than Metal−Gate Counterparts
• Low Noise
• In Compliance with the Requirements of JEDEC Standard No. 7A
• Chip Complexity: HC4051A − 184 FETs or 46 Equivalent Gates HC4052A − 168 FETs or 42 Equivalent Gates HC4053A − 156 FETs or 39 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR−Free and are RoHS Compliant This document contains information on some products that are still under development. ON Semiconductor reserves the right to change or discontinue these products without notice. www.onsemi.com MARKING DIAGRAMS SOIC−16 TSSOP−16 HC405xAG AWLYWW HC40 5xA ALYW/C0071 /C0071 SOIC−16 WIDE HC405xA AWLYWWG See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.

ORDERING INFORMATION

x = 1, 2 or 3 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or /C0071= Pb−Free Package (Note: Microdot may be in either location) SOIC−16 D SUFFIX CASE 751B TSSOP−16 DT SUFFIX CASE 948F SOIC−16 WIDE DW SUFFIX CASE 751G 4051 ALYW/C0071 /C0071 QFN16 QFN16 MN SUFFIX CASE 485AW

MC74HC4051A, MC74HC4052A, MC74HC4053A www.onsemi.com LOGIC DIAGRAM MC74HC4051A Single−Pole, 8−Position Plus Common Off X0 13 X1 14 X2 15 X3 12 X4 1 X5 5 X6 2 X7 4 A 11 B 10 C 9 ENABLE 6 MULTIPLEXER/ DEMULTIPLEXER ANALOG INPUTS/ CHANNEL INPUTS PIN 16 = VCC PIN 7 = VEE PIN 8 = GND COMMON OUTPUT/ INPUT 1516 14 13 12 11 10 21 34567 VCC X2 X1 X0 X3 A B C X4 X6 X X7 X5 Enable V EE GND Pinout: MC74HC4051A (Top View) OUTPUTS SELECT L L L L H H H H X L L H H L L H H X L H L H L H L H X FUNCTION TABLE − MC74HC4051A Control Inputs ON ChannelsEnable Select CBA NONE L L L L L L L L H X = Don’t Care LOGIC DIAGRAM MC74HC4052A Double−Pole, 4−Position Plus Common Off X0 12 X1 14 X2 15 X3 11 Y0 1 Y1 5 Y2 2 Y3 4 A 10 B 9 ENABLE 6 X SWITCH Y SWITCH X13 ANALOG INPUTS/OUTPUTS CHANNEL‐SELECT INPUTS PIN 16 = VCC PIN 7 = VEE PIN 8 = GND COMMON OUTPUTS/INPUTS L L H H X L H L H X FUNCTION TABLE − MC74HC4052A Control Inputs ON ChannelsEnable Select BA L L L L H X = Don’t Care Pinout: MC74HC4052A (Top View) 1516 14 13 12 11 10 21 34567 VCC X2 X1 X X0 X3 A B Y0 Y2 Y Y3 Y1 Enable V EE GND NONE

MC74HC4051A, MC74HC4052A, MC74HC4053A www.onsemi.com LOGIC DIAGRAM MC74HC4053A Triple Single−Pole, Double−Position Plus Common Off X0 12 X1 13 A 11 B 10 C 9 ENABLE 6 X SWITCH Y SWITCH X14 ANALOG INPUTS/OUTPUTS CHANNEL‐SELECT INPUTS PIN 16 = VCC PIN 7 = VEE PIN 8 = GND COMMON OUTPUTS/INPUTS L L L L H H H H X L L H H L L H H X L H L H L H L H X FUNCTION TABLE − MC74HC4053A Control Inputs ON ChannelsEnable Select CBA L L L L L L L L H X = Don’t Care Pinout: MC74HC4053A (Top View) 1516 14 13 12 11 10 21 34567 VCC Y X X1 X0 A B C Y1 Y0 Z1 Z Z0 Enable V EE GND NONE Y0 2 Y1 1 Y15 Z0 5 Z1 3 Z4Z SWITCH NOTE: This device allows independent control of each switch. Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch and Input C controls the Z−Switch MAXIMUM RATINGS Symbol Parameter Value Unit VCC Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) –0.5 to +7.0 –0.5 to +14.0 V VEE Negative DC Supply Voltage (Referenced to GND) –7.0 to +5.0 V VIS Analog Input Voltage VEE − 0.5 to VCC + 0.5 V Vin Digital Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V I DC Current, Into or Out of Any Pin ±25 mA PD Power Dissipation in Still Air, SOIC Package† 500 450 mW Tstg Storage Temperature Range –65 to +150 /C0095C TL Lead Temperature, 1 mm from Case for 10 Seconds SOIC or TSSOP Package 260 /C0095C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/ /C0095C from 65/C0095 to 125/C0095C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance cir- cuit. For proper operation, V in and Vout should be constrained to the range GND /C0118 (Vin or Vout) /C0118 VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.

MC74HC4051A, MC74HC4052A, MC74HC4053A www.onsemi.com RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) 2.0 2.0 6.0 12.0 V VEE Negative DC Supply Voltage, Output (Referenced to GND) −6.0 GND V VIS Analog Input Voltage VEE VCC V Vin Digital Input Voltage (Referenced to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch 1.2 V TA Operating Temperature Range, All Package Types –55 +125 /C0095C tr, tf Input Rise/Fall Time V CC = 2.0 V (Channel Select or Enable Inputs) V CC = 3.0 V VCC = 4.5 V VCC = 6.0 V 1000 600 500 400 ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. *For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted Symbol Parameter Condition VCC V Guaranteed Limit Unit−55 to 25°C ≤85°C ≤125°C VIH Minimum High−Level Input Voltage, Channel−Select or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low−Level Input Voltage, Channel−Select or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V Iin Maximum Input Leakage Current, Channel−Select or Enable Inputs Vin = VCC or GND, VEE = − 6.0 V ICC Maximum Quiescent Supply Current (per Package) Channel Select, Enable and V IS = VCC or GND; V EE = GND VIO = 0 V V EE = − 6.0 6.0 6.0 /C0109A

MC74HC4051A, MC74HC4052A, MC74HC4053A www.onsemi.com DC CHARACTERISTICS — Analog Section Symbol Parameter Condition VCC VEE Guaranteed Limit Unit−55 to 25°C ≤85°C ≤125°C Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 − 4.5 − 6.0 190 120 100 240 150 125 280 170 140 /C0087 Vin = VIL or VIH; VIS = VCC or VEE (Endpoints); IS ≤ 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 − 4.5 − 6.0 150 100 190 125 100 230 140 115 /C0068Ron Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA 4.5 4.5 6.0 0.0 − 4.5 − 6.0 /C0087 Ioff Maximum Off−Channel Leakage Current, Any One Channel Vin = VIL or VIH; VIO = VCC − VEE; Switch Off (Figure 3) /C0109A Maximum Off−ChannelHC4051A Leakage Current, HC4052A Common Channel HC4053A Vin = VIL or VIH; VIO = VCC − VEE; Switch Off (Figure 4) 6.0 6.0 6.0 − 6.0 − 6.0 − 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Ion Maximum On−ChannelHC4051A Leakage Current, HC4052A Channel−to−Channel HC4053A Vin = VIL or VIH; Switch−to−Switch = VCC − VEE; (Figure 5) 6.0 6.0 6.0 − 6.0 − 6.0 − 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 /C0109A AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symbol Parameter VCC V Guaranteed Limit Unit−55 to 25°C ≤85°C ≤125°C tPLH, tPHL Maximum Propagation Delay, Channel−Select to Analog Output (Figure 9) 2.0 3.0 4.5 6.0 270 320 110 350 125 ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) 2.0 3.0 4.5 6.0 ns tPLZ, tPHZ Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 3.0 4.5 6.0 160 200 220 110 ns tPZL, tPZH Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 3.0 4.5 6.0 245 115 315 145 345 155 ns Cin Maximum Input Capacitance, Channel−Select or Enable Inputs 10 10 10 pF CI/O Maximum Capacitance Analog I/O 35 35 35 pF (All Switches Off) Common O/I: HC4051A HC4052A HC4053A 130 130 130 Feed−through 1.0 1.0 1.0 CPD Power Dissipation Capacitance (Figure 13)* HC4051A HC4052A HC4053A Typical @ 25°C, VCC = 5.0 V, VEE = 0 V pF45 * Used to determine the no−load dynamic power consumption: P D = CPD VCC2f + ICC VCC.

MC74HC4051A, MC74HC4052A, MC74HC4053A www.onsemi.com ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) Symbol Parameter Condition VCC V VEE V Limit* Unit25°C BW Maximum On−Channel Bandwidth or Minimum Frequency Response (Figure 6) fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain 0dBm at VOS; Increase fin Frequency Until dB Meter Reads −3dB; RL = 50/C0087, CL = 10pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 ‘51 ‘52 ‘53 MHz 120 120 120 − Off−Channel Feed−through Isolation (Figure 7) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600/C0087, CL = 50pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −50 −50 −50 dB fin = 1.0MHz, RL = 50/C0087, CL = 10pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −40 −40 −40 − Feedthrough Noise. Channel−Select Input to Common I/O (Figure 8) Vin ≤ 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND R L = 600/C0087, CL = 50pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 105 135 mVPP RL = 10k/C0087, CL = 10pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 145 190 − Crosstalk Between Any Two Switches (Figure 12) (Test does not apply to HC4051A) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600/C0087, CL = 50pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −50 −50 −50 dB fin = 1.0MHz, RL = 50/C0087, CL = 10pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −60 −60 −60 THD Total Harmonic Distortion (Figure 14) fin = 1kHz, RL = 10k/C0087, CL = 50pF THD = THDmeasured − THDsource VIS = 4.0VPP sine wave VIS = 8.0VPP sine wave VIS = 11.0VPP sine wave 2.25 4.50 6.00 −2.25 −4.50 −6.00 0.10 0.08 0.05 *Limits not tested. Determined by design and verified by qualification. Figure 1a. Typical On Resistance, VCC − VEE = 2.0 V Figure 1b. Typical On Resistance, V CC − VEE = 3.0 V 250 200 150 100 V IS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Ron , ON RESISTANCE (OHMS) 100 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Ron , ON RESISTANCE (OHMS) 25°C -/C820255°C 125°C 25°C -/C820255°C 125°C 2.00 300 180 160 140 120 0 2.5 2.75 3.0

MC74HC4051A, MC74HC4052A, MC74HC4053A www.onsemi.com Device Package Shipping† MC74HC4051ADG SOIC−16 (Pb−Free)

48 Units / Rail

MC74HC4051ADR2G 2500 Units / Tape & Reel NLV74HC4051ADR2G* 2500 Units / Tape & Reel MC74HC4051ADWG SOIC−16 WIDE (Pb−Free) MC74HC4051ADWR2G 1000 Units / Tape & Reel NLVHC4051ADWR2G* 1000 Units / Tape & Reel MC74HC4051ADTG TSSOP−16 (Pb−Free)

96 Units / Rail

MC74HC4051ADTR2G 2500 Units / Tape & Reel NLVHC4051ADTR2G* 2500 Units / Tape & Reel NLVHC4051AMNTWG* (In Development) QFN16 (Pb−Free)

3000 Units / Tape & Reel

SOIC−16 (Pb−Free) MC74HC4052ADR2G 2500 Units / Tape & Reel NLV74HC4052ADR2G* 2500 Units / Tape & Reel MC74HC4052ADWG SOIC−16 WIDE (Pb−Free) MC74HC4052ADWR2G 1000 Units / Tape & Reel MC74HC4052ADTG TSSOP−16 (Pb−Free) MC74HC4052ADTR2G 2500 Units / Tape & Reel NLV74HC4052ADTR2G* 2500 Units / Tape & Reel NLVHC4052ADTR2G* 2500 Units / Tape & Reel NLVHC4052AMNTWG* (In Development) QFN16 (Pb−Free) SOIC−16 (Pb−Free) MC74HC4053ADR2G 2500 Units / Tape & Reel NLV74HC4053ADR2G* 2500 Units / Tape & Reel MC74HC4053ADWG SOIC−16 WIDE (Pb−Free) NLV74HC4053ADWRG* 1000 Units / Tape & Reel MC74HC4053ADWR2G 1000 Units / Tape & Reel NLV74HC4053ADWR2G* 1000 Units / Tape & Reel MC74HC4053ADTG TSSOP−16 (Pb−Free) MC74HC4053ADTR2G 2500 Units / Tape & Reel NLVHC4053ADTR2G* 2500 Units / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.

MC74HC4051A, MC74HC4052A, MC74HC4053A www.onsemi.com PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE B ÇÇÇ ÇÇÇ DIM MIN MAX MIN MAX INCHESMILLIMETERS A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. /C0095/C0095/C0095/C0095 SECTION N−N SEATING PLANE IDENT. PIN 1 1 8 16 9 DETAIL E J B C D A K H G ÉÉÉ ÉÉÉ DETAIL E F M L 2X L/2 −U− SU0.15 (0.006) T SU0.15 (0.006) T SUM0.10 (0.004) V ST 0.10 (0.004) −T− −V− −W− 0.25 (0.010) 16X REFK N N 7.06 16X 0.36 16X 1.26 0.65 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HC4051A, MC74HC4052A, MC74HC4053A www.onsemi.com PACKAGE DIMENSIONS SOIC−16 WB CASE 751G−03 ISSUE D D 14X B16X SEATING PLANE SAM0.25 B ST 16 9 h X 45/C0095 MBM0.25 H8X E B A e T A L C /C0113 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM MIN MAX MILLIMETERS A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0 7 /C0095/C0095 11.00 16X 0.58 16X 1.62 1.27 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HC4051A, MC74HC4052A, MC74HC4053A www.onsemi.com PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 16 9 SEATING PLANE F JM R X 45/C0095 G

8 PLP−B−

−A− M0.25 (0.010) B S −T− D K C 16 PL SBM0.25 (0.010) A ST DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 6.40 16X 0.58 16X 1.12 1.27 DIMENSIONS: MILLIMETERS PITCH

MC74HC4051A, MC74HC4052A, MC74HC4053A www.onsemi.com PACKAGE DIMENSIONS QFN16, 2.5x3.5, 0.5P CASE 485AW ISSUE O ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ DIM MIN MAX MILLIMETERS A A1 0.00 0.05 b 0.20 0.30 D 2.50 BSC D2 0.85 1.15 E 3.50 BSC e 0.50 BSC K 0.20 --- NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

0.20 REF

b L PIN ONE D E B A C0.15 C0.15 e 16X 16X 0.10 C 0.05 C A B NOTE 3 A 16X K (A3) SEATING PLANE C0.08 C0.10 0.80 1.00 L 0.35 0.45 1.85 2.15 DETAIL A L ALTERNATE TERMINAL CONSTRUCTIONS L ÇÇÇ ÇÇÇÉÉÉ DETAIL B MOLD CMPDEXPOSED Cu ALTERNATE CONSTRUCTIONSDETAIL B *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 2.80 3.80 1.10 0.50 0.60 16X 0.30 16X DIMENSIONS: MILLIMETERS REFERENCE TOP VIEW SIDE VIEW NOTE 4 C

0.15 C A B

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