HC4052

74VHC4051 FAIRCHILD | Alldatasheet

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Technical content

Features

■ Wide analog input voltage range: ±6V ■ Low “on” resistance: 50 typ. (VCC –VEE = 4.5V) 30 typ. (VCC –VEE = 9V) ■ Logic level translation to enable 5V logic with ±5V ana- log signals ■ Low quiescent current: 80 µA maximum ■ Matched switch characteristic ■ Pin and function compatible with the 74HC4051/ 4052/ 4053 Ordering Code: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Order Number Package Number Package Description 74VHC4051M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 74VHC4051WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74VHC4051MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC4051N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74VHC4052M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 74VHC4052WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74VHC4052MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC4052N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74VHC4053M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 74VHC4053WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74VHC4053MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC4053N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2 74VHC4051 • 74VHC4052 • 74VHC4053 Connection Diagrams Top View Top View Top View Truth Tables 4051 4052 4053 Input “ON” I N H CBA C h a n n e l H XXX N o n e L LLL Y 0 LL L H Y 1 LL H L Y 2 LL H H Y 3 LH L L Y 4 LH L H Y 5 LH H L Y 6 L HHH Y 7 Inputs “ON” Channels INH B A X Y HX XN o n e N o n e LL L 0 X 0 Y LL H 1 X 1 Y LH L 2 X 2 Y LH H 3 X 3 Y Input “ON” Channels I N HCBA C B A H X X X None None None L L L L CX BX AX LL L H C X B X A Y L L H L CX BY AX LL H H C X B Y A Y L H L L CY BX AX LH L HC Y B X A Y L H H L CY BY AX L HHH C Y B Y A Y

3 www.fairchildsemi.com 74VHC4051 • 74VHC4052 • 74VHC4053 Logic Diagrams 74VHC4051 74VHC4052 74VHC4053

www.fairchildsemi.com 4 74VHC4051 • 74VHC4052 • 74VHC4053 Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions Note 1: Absolute Maximum Ratings are those values beyond which dam- age to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/ °C from 65°C to 85°C. Supply Voltage (VCC ) −0.5 to +7.5V Supply Voltage (VEE ) +0.5 to −7.5V Control Input Voltage (VIN) −1.5 to VCC +1.5V Switch I/O Voltage (VIO)V EE −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK ) ±20 mA Output Current, per pin (IOUT ) ±25 mA VCC or GND Current, per pin (ICC ) ±50 mA Storage Temperature Range (TSTG ) −65°C to +150°C Power Dissipation (PD ) (Note 3) 600 mW S.O. Package only 500 mW Lead Temperature (TL) (Soldering 10 seconds) 260 °C Min Max Units Supply Voltage (VCC )2 6 V Supply Voltage (VEE )0 −6V DC Input or Output Voltage 0 V CC V (VIN, VOUT ) Operating Temperature Range (TA) −40 +85 °C Input Rise or Fall Times (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns

5 www.fairchildsemi.com 74VHC4051 • 74VHC4052 • 74VHC4053 Note 4: For a power supply of 5V ±10% the worst case on resistances (RON ) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing for CMOS at the higher voltage and so the 5.5V values should be used. Note 5: At supply voltages (VCC –VEE ) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital only when using these supply voltages. Note 6: Adjust 0 dB for f = 1 kHz (Null R1/RON Attenuation). Symbol Parameter Conditions VEE VCC TA = 25°CT A = −40 to 85°C Units Typ Guaranteed Limits VIH Minimum HIGH Level 2.0V 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 V 6.0V 4.2 4.2 V VIL Maximum LOW Level 2.0V 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 V 6.0V 1.8 1.8 V R ON Maximum “ON” Resistance V INH = VIL, IS = 2.0 mA GND 4.5V 40 160 200 Ω (Note 5) V IS = VCC to VEE −4.5V 4.5V 30 120 150 Ω (Figure 1) −6.0V 6.0V 20 100 125 Ω VINH = VIL, IS = 2.0 mA GND 2.0V 100 230 280 Ω VIS = VCC or VEE GND 4.5V 40 110 140 Ω (Figure 1) −4.5V 4.5V 20 90 120 Ω −6.0V 6.0V 15 80 100 Ω R ON Maximum “ON” Resistance V INH = VIL GND 4.5V 10 20 25 Ω Matching V IS = VCC to GND −4.5V 4.5V 5 10 15 Ω −6.0V 6.0V 5 10 12 Ω IN Maximum Control V IN = VCC or GND ±.05 ±0.5 µA Input Current V CC = 2 − 6V ICC Maximum Quiescent V IN = VCC or GND GND 6.0V 4 40 µA Supply Current I OUT = 0 µA −6.0V 6.0V 8 80 µA IIZ Maximum Switch “OFF” V OS = VCC or VEE GND 6.0V ±60 ±300 nA Leakage Current V IS = VEE or VCC −6.0V 6.0V ±100 ±500 nA (Switch Input) V INH = VIH (Figure 2) IIZ Maximum Switch “ON” V IS = VCC to VEE GND 6.0V ±0.1 ±1.0 µA Leakage Current VHC4051 V INH = VIL −6.0V 6.0V ±0.2 ±2.0 µA (Figure 3) V IS = VCC to VEE GND 6.0V ±0.050 ±0.5 µA VHC4052 V INH = VIL −6.0V 6.0V ±0.1 ±1.0 µA (Figure 3) V IS = VCC to VEE GND 6.0V ±0.05 ±0.5 µA VHC4053 V INH = VIL −6.0V 6.0V ±0.5 ±0.5 µA (Figure 3) IIZ Maximum Switch V OS = VCC or VEE GND 6.0V ±0.1 ±1.0 µA “OFF” Leakage VHC4051 V IS = VEE or VCC −6.0V 6.0V ±0.2 ±2.0 µA Current (Common Pin) V INH = VIH VOS = VCC or VEE GND 6.0V ±0.05 ±0.5 µA VHC4052 V IS = VEE or VCC −6.0V 6.0V ±0.1 ±1.0 µA VINH = VIH VOS = VCC or VEE GND 6.0V ±0.05 ±0.5 µA VHC4053 V IS = VEE or VCC −6.0V 6.0V ±0.05 ±0.5 µA VINH = VIH

www.fairchildsemi.com 6 74VHC4051 • 74VHC4052 • 74VHC4053 VCC = 2.0V − 6.0V, VEE = 0V − 6V, CL = 50 pF (unless otherwise specified) Symbol Parameter Conditions VEE VCC TA =25°CT A =−40 to 85°C Units Typ Guaranteed Limits tPHL , tPLH Maximum Propagation Delay Switch In to Out GND 3.3V 25 35 40 ns GND 4.5V 5 12 15 ns −4.5V 4.5V 4 8 12 ns −6.0V 6.0V 3 7 11 ns tPZL , tPZH Maximum Switch Turn “ON” Delay R L = 1 kΩ GND 3.3V 92 200 250 ns GND 4.5V 69 87 ns −4.5V 4.5V 16 46 58 ns −6.0V 6.0V 15 41 51 ns tPHZ , tPLZ Maximum Switch Turn “OFF” Delay GND 3.3V 65 170 210 ns GND 4.5V 28 58 73 ns −4.5V 4.5V 18 37 46 ns −6.0V 6.0V 16 32 41 ns fMAX Minimum Switch GND 4.5V 30 MHz Frequency Response −4.5V 4.5V 35 MHz 20 log (VI/VO ) = 3 dB Control to Switch R L = 600Ω ,V IS = 4 VPP 0V 4.5V 1080 mV Feedthrough Noise f = 1 MHz, V IS = 8 VPP −4.5V 4.5V 250 mV C L = 50 pF Crosstalk between R L = 600Ω ,V IS = 4 VPP 0V 4.5 −52 dB any Two Switches f = 1 MHz V IS = 8 VPP −4.5V 4.5V −50 dB Switch OFF Signal R L = 600Ω ,V IS = 4 VPP 0V 4.5V −42 dB Feedthrough f = 1 MHz, V IS = 8 VPP −4.5V 4.5V −44 dB Isolation V CTL = VIL THD Sinewave Harmonic R L = 10 kΩ ,V IS = 4 VPP 0V 4.5V 0.013 % Distortion C L = 50 pF, V IS = 8 VPP −4.5V 4.5V 0.008 % f = 1 kHz C IN Maximum Control 5 10 10 pF Input Capacitance C IN Maximum Switch Input 15 pF Input Capacitance 4051 Common 90

4052 Common 45

4053 Common 30

C IN Maximum Feedthrough 5 pF Capacitance

FIGURE 8. Crosstalk Between Any Two Switches 1.2V (calculated from the ON resistance).

9 www.fairchildsemi.com 74VHC4051 • 74VHC4052 • 74VHC4053 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Package Number M16B

www.fairchildsemi.com 10 74VHC4051 • 74VHC4052 • 74VHC4053 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHC4051 • 74VHC4052 • 74VHC4053 8-Channel Analog Multiplexer • Dual 4-Channel Analog Multiplexer • Triple 2-Channel Analog Multiplexer LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E