SL74HC4046 SLS | Alldatasheet
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Technical content
High-Performance Silicon-Gate CMOS The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC4046 phase -locked loop contains three phase comparators, a voltage -controlled oscillator (VCO) and unity gain op - amp DEM OUT. The comparators have two common signal inputs, COMPIN, and SIGIN. Input SIG IN and COMP IN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self -bias circuit adjusts small voltage signals in the linear region of the amplifier. Ph ase comparator 1 (an exclusive OR gate) provides a digital error signal PC1 OUT and maintains 90 degrees phase shift at the center frequency between SIG IN and COMP IN signals (both at 50% duty cycle). Phase comparator 2 (with leading-edge sensing logic) pr ovides digital error signals PC2 OUT and PCPOUT and maintains a 0 degree phase shift between SIG IN and COMPIN signals (duty cycle is immaterial). The linear VCO produces an output signal VCOOUT whose frequency is determined by the voltage of input VCOIN signal and the capacitor and resistors connected to pins C1A, C1B, R1 and R2. The unity gain op-amp output DEM OUT with an external resistor is used where the VCO IN signal is needed but no loading can be tolerated. The inhibit input, when high, disables th e VCO and all on -amps to minimize standby power consumption. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronizati on and conditioning, voltage -to-frequency conversion and motor speed control.
- Low Power Consumption Characteristic of CMOS Device
- Operating Speeds Similary to LS/ALSTTL
- Wide Operating Voltage Range: 3.0 to 6.0 V
- Low Input Current: 1.0 µA Maximum (except SI GIN and COMPIN)
- Low Quiescent Current: 80 µA Maximum (VCO disabled)
- High Noise Immunity Characteristic of CMOS Devices
- Diode Protection on all Inputs Pin No. Symbol Name and Function
1 PCPOUT Phase Comparator Pulse Output
2 PC1OUT Phase Comparator 1 Output
3 COMPIN Comparator Input
4 VCOOUT VCO Output
5 INH Inhibit Input
6 C1A Capacitor C1 Connection A
7 C1B Capacitor C1 Connection B
8 GND Ground (0 V) VSS
9 VCOIN VCO Input
10 DEMOUT Demodulator Output
11 R1 Resistor R1 Connection
12 R2 Resistor R2 Connection
13 PC2OUT Phase Comparator 2 Output
14 SIGIN Signal Input
15 PC3OUT Phase Comparator 3 Output
16 VCC Positive Supply Voltage
ORDERING INFORMATION
TA = -55° to 125° C for all packages PIN ASSIGNMENT
MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ 750 500 mW Tstg Storage Temperature -65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260 °C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) VCO only 3.0 6.0 V VCC DC Supply Voltage (Referenced to GND) NON-VCO 2.0 6.0 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types -55 +125 °C tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high -impedance circuit. For proper operation, V IN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.
[Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter Test Condit ions V 25 °C to -55°C ≤85 ≤125 Unit VIH Minimum High-Level Input Voltage DC Coupled SIGIN , COMPIN VOUT= 0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage DC Coupled SIGIN , COMPIN VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V VOH Minimum High-Level Output Voltage PCPOUT, PCnOUT VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V VIN= VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 VOL Maximum Low-Level Output Voltage Qa-Qh PCPOUT, PCnOUT VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V VIN= VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 IIN Maximum Input Leakage Current SIGIN , COMPIN VIN=VCC or GND 2.0 3.0 4.5 6.0 ±3.0 ±7.0 ±18.0 ±30.0 ±4.0 ±9.0 ±23.0 ±38.0 ±5.0 ±11.0 ±27.0 ±45.0 µA IOZ Maximum Three-State Leakage Current PC2OUT Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GND ICC Maximum Quiescent Supply Current (per Package) (VCO disabled) Pins 3,5 and 14 at VCC Pin 9 at GND; Input Leacage at Pin 3 and 14 to be excluded VIN=VCC or GND IOUT=0µA 6.0 4.0 40 160 µA
[Phase Comparator Section] AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT (Figure 1) 2.0 4.5 6.0 175 220 265 ns tPLH, tPHL Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT (Figure 1) 2.0 4.5 6.0 340 425 510 102 ns tPLH, tPHL Maximum Propagation Delay , SIGIN/COMPIN to PC3OUT (Figure 1) 2.0 4.5 6.0 270 340 405 ns tPLZ, tPHZ Maximum Propagation Delay , SIGIN/COMPIN Output Disable Time to PC2OUT (Figures 2 and 3) 2.0 4.5 6.0 200 250 300 ns tPZL, tPZH Maximum Propagation Delay , SIGIN/COMPIN Output Enable Time to PC2OUT (Figures 2 and 3) 2.0 4.5 6.0 230 290 345 ns tTLH, tTHL Maximum Output Transition Time (Figure 1) 2.0 4.5 6.0 110 ns [VCO Section] DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter Test Conditions V 25 °C to-55°C ≤85°C ≤125°C Unit VIH Minimum High-Level Input Voltage INH VOUT= 0.1 V or VCC-0.1 V IOUT≤ 20 µA 3.0 4.5 6.0 2.1 3.15 4.2 2.1 3.15 4.2 2.1 3.15 4.2 V VIL Maximum Low -Level Input Voltage INH VOUT=0.1 V or VCC- 0.1 V IOUT ≤ 20 µA 3.0 4.5 6.0 0.90 1.35 1.8 0.90 1.35 1.8 0.90 1.35 1.8 V VOH Minimum High-Level Output Voltage VCOOUT VIN=VIH or VIL IOUT ≤ 20 µA 3.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V VIN= VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 VOL Maximum Low-Level Output Voltage VCOOUT VIN=VIH or VIL IOUT ≤ 20 µA 3.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V VIN= VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4
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[VCO Section] DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) - continued VCC Guaranteed Limit Symbol Parameter Test Conditions V 25 °C to -55°C ≤85°C ≤125°C Unit IIN Maximum Input Leakage Current INH, VCOIN VIN =Vcc or GND 6.0 0.1 1.0 1.0 µA Min Max Min Max Min Max VVCOIN Operating Voltage Range at VCOIN over the range specified for R1; For linearity see Fig.13A, Parallel value of R1 and R2 should be >2.7 kΩ INH= VIL 3.0 4.5 6.0 0.1 0.1 0.1 1.0 2.5 4.0 0.1 0.1 0.1 1.0 2.5 4.0 0.1 0.1 0.1 1.0 2.5 4.0 V R1 Resistor Range 3.0 4.5 6.0 3.0 3.0 3.0 300 300 300 3.0 3.0 3.0 300 300 300 3.0 3.0 3.0 300 300 300 kΩ R2 3.0 4.5 6.0 3.0 3.0 3.0 300 300 300 3.0 3.0 3.0 300 300 300 3.0 3.0 3.0 300 300 300 C1 Capacitor Range 3.0 4.5 6.0 No Li- mit pF [VCO Section] AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit Min Max Min Max Min Max Δf/T Frequency Stability with Temperature Changes (Figures 11A,B,C) 3.0 4.5 6.0 %/K fo VCO Center Frequency (Duty Factor = 50%) (Figures 12A,B,C) 3.0 4.5 6.0 MHz ΔfVCO VCO Frequency Linearity 3.0 4.5 6.0 See Figures 13A,B % ∂VCO Duty Factor at VCOOUT 3.0 4.5 6.0 Typical 50% %
minimizing standby power consumption. CMOS output with an equivalent LS -TTL fan out of 10. (counters) to enable frequency synthesis. Figure 5. Logic Diagram for VCO