HC-55564883 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Para- graph 1.2.1.Requires Few External Parts
  • All Digital
  • Requires Few External Parts
  • Low Power Drain
  • Time Constants Determined by Clock Frequency; No Cali- bration or Drift Problems: Automatic Offset Adjustment
  • Half Duplex Operation Under Digital Control
  • Filter Reset Under Digital Control
  • Automatic Overload Recovery
  • Automatic “Quiet” Pattern Generation
  • AGC Control Signal Available

Applications

  • Voice Transmission Over Data Channels (Modems)
  • Voice/Data Multiplexing (Pair Gain)
  • Voice Encryption/Scrambling
  • V o i c e m a i l
  • Audio Manipulations: Delay Lines, Time Compression, Echo Generation/Suppression, Special Effects, etc.
  • Pagers/Satellites
  • Data Acquisition Systems
  • Voice I/O for Digital Systems and Speech Synthesis Requiring Small Size, Low Weight, and Ease of Repro- grammability Pinouts

Ordering Information

HC1-55564/883 -55 oC to +125oC 14 Lead CerDIP HC4-55564/883 -55 oC to +125oC 20 Lead Ceramic LCC HC-55564/883 (CERDIP) TOP VIEW HC-55564/883 (CLCC) TOP VIEW VDD ANALOG GND AOUT AGC AIN NC NC DIG OUT FZ DIG IN APT ENC/DEC CLOCK DIG GND 91 0 1 1 1 2 22 011 9 NC VDD ANALOG GND DIGITAL FZ AOUT NC AGC NC AIN DIGITAL IN NC APT NC ENCODE /DECODE CLOCK NC DIGITAL NC NC OUTGND October 1999 FN3738.1 OBSOLETE PRODUCT NO RECOMMENDED REPLACEMENT contact our Technical Support Center at CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1-888-INTERSIL or www.intersil.com/tsc

PIN NO.

14 LEAD

PIN NO.

20 LEAD

12 V DD Positive Supply Voltage. Voltage range is +3.2V to +6.0V. 2 3 Analog GND Analog Ground connection to D/A ladders and comparator. 34 A OUT Audio Out recovered from 10-bit DAC. May be used as side tone at the transmitter. Presents approximately 75kΩ source with DC offset of V DD/2. Within ±2dB of Audio Input. Should be externally AC coupled. 46 A G C Automatic Gain Control output. A logic low level will appear at this output when the recovered signal ex- cursion reaches one-half of full scale value. In each half cycle full scale is V DD/2. The mark-space ratio is proportional to the average signal level. 58 A IN Audio Input to comparator. Should be externally AC coupled. Presents approximately 200k Ω in series with VDD/2. 6, 7 1, 5, 7, 9, 10, 11, 15, NC No internal connection is made to these pins. 81 2 D i g i t a l GND Logic ground. 0V reference for all logic inputs and outputs. 9 13 Clock Sampling rate clock. In the decode mode, must be synchronized with the digital input data such that the data is valid at the positive clock transition. In the encode mode, the digital data is clocked out on the negative going clock transition. The clock rate equals the data rate. 10 14 Encode / Decode A single CVSD can provide half-duplex operation. The encode or decode function is selected by the logic level applied to this input. A low level selects the encode mode, a high level the decode mode. 11 16 APT Alternate Plain Text input. Activating this input caused a digital quieting pattern to be transmitted, however; internally the CVSD is still functional and a signal is still available at the AOUT port. Active low. 12 18 Digital In Input for the received digital NRZ data. 13 19 FZ Force Zero input. Activating this input resets the internal logic and forces the digital output and the recov- ered audio output into the “quieting” condition. An alternating 1-0 pattern appears at the digital output at 1/2 the clock rate. When this is decoded by a receive CVSD, a 10mVP-P inaudible signal appears at audio output. Active low. 14 20 Digital Out Output for transmitted digital NRZ data. NOTE: 1. No active input should be left in a “floating condition”. 3-BIT SHIFT STEP SIZE SYLLABIC FILTER 4ms REGISTER LOGIC DIGITAL MODULATOR SIGNAL ESTIMATE FILTER 1ms 10-BIT DAC APT (14) DIGITAL OUT F/F RESET ZOUT D T RESET 10-BIT DAC (3) AOUT (SIDE TONE) (4) AGC OUT Q FORCE ZERO (9) DIGITAL GND (10) ENC/DEC (11) (13) CLOCK (8)(12) DIGITAL (1) VDD 3V TO 6V ZIN ANALOG GND (2) (5) AIN VDD COMPARATOR IN RESET HC-55564/883

device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: V SUPPLY = +5V, fclk = 16kHz, Operating Temperature = -55 oC ≤ TA ≤ +125oC, Unless Otherwise Specified. AGC Threshold (Note 9) V ATH Encode Mode 1 +25 oC 0.45 0.65 F.S. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Table 2 Intentionally Left Blank. TABLE 3. ELECTRICL PERFORMANCE CHARACTERISTICS Devices Characterized at: V DD = +5.0V, TA = +25oC, Operating Temperature, fclk = 16kHz Clock Sampling Rate. ENC/DDC = ENC = Encode Mode, Unless Otherwise Specified.

Clamping Threshold V CTH 10, 12 +25 oC 0.70 0.90 F.S.

  1. There is one NRZ (Non-Return Zero) data bit per clock period. Data is clocked out on the negative clock edge. Data is clocked into the CVSD

on the positive going edge (see Figure 2). Clock may be run at less than 9kbps.

  1. Logic inputs are CMOS compatible at supply voltage and are diode protected. Digital data input is NRZ at clock rate.
  2. Logic outputs are CMOS compatible at supply voltage and will withstand short-circuits to V DD or ground; however, the short circuit duty cycle

sitions. Each output will drive one LS TTL loads.

  1. Recommended voice input range for best voice performance. Should be externally AC coupled.
  2. May be used for side-tone in encode mode. Should be externally AC coupled.
  3. Presents series impedance with audio signal. Zero signal reference is approximately V

DD/2. Varies with audio input level by ±2dB.

  1. The minimum audio output voltage change that can be produced by the internal DAC.
  2. The “quieting” pattern or idle-channel audio output steps at 1/2 the bit rate, changing state on negative clock transitions.
  3. A logic “0” will appear at the AGC output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e. at VDD/2
  4. The recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarter s of full-scale val-

ue, and will unclamp when it falls below this value (positive or negative).

  1. No load condition measured from audio in to audio out.
  2. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These param eters are charac-

terized upon initial design release and upon design changes which would affect these characteristics.

  1. The minimum audio input voltage above which encoding is guaranteed to take place.

TABLE 4. ELECTRICAL TEST REQUIREMENTS

  1. PDA applies to Subgroup 1 only.

TABLE 3. ELECTRICL PERFORMANCE CHARACTERISTICS (Continued) DD = +5.0V, TA = +25oC, Operating Temperature, fclk = 16kHz Clock Sampling Rate.

DIE DIMENSIONS: 82 x 147 x 20 ± 1 mils METALLIZATION: Type: AlSi Thickness: 10kÅ ± 1kÅ GLASSIVATION: Type: Silane, 3% Phosphorous Thickness: 13kÅ ± 2.6kÅ WORST CASE CURRENT DENSITY: 2.0 x 105A/cm2 TRANSISTOR COUNT: 1896 PROCESS: CMOS; SAJI Metallization Mask Layout HC-55564/883 AOUT ANALOG VDD DIGITAL FZ DIGITAL IN APT ENC/DEC CLOCK AIN AGC OUTGND DIGITAL GND HC-55564/883