HC20000

HC20000 HONEYWELL | Alldatasheet

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4551872 HONEYWELL/SS ELEK, MIL O3E 00236 OD =—_

FEATURES . + Performance Optimized Series of 1.2-Micron CMOS + Proven VLSI Design System (VDS) Toolkit™ pi Gate Arrays + Boundary and Internal Scan *TTL and CMOS I/O Interfaces + VHSIC Built-In Self Test (BIST) Testability Protocols * Over 110 Library Macrocells Designed for Optimized System Performance + MIL-M-38510 Qualification Pending * Standard Megacell Capability * MIL-STD 883C Class B and Modified Class S Screening * High Density Advanced Packages + Available in Military and Commercial Versions Honeywell's CMOS gate arrays offer the designer ans ae Re eyes peptone 4 ® so ee complete ASIC design capability coupled with state-of- gees Ce es Rp aces. the-art CMOS 1.2-micron manufacturing capability. ne einer ees eg Depending on the system design, three compatible array mgs cn ay Be Ses families are available: HC, HCT and HCS. BS eee ee oe oe ae Nee Ee ee ae a po eas ARRAY TYPES poe one Hea boos Cc | Application Commercial Tactical Strategic ey ae bie iy Hy zi a ‘ We ee Military Military Military ees Eh a ele iM ay WS — ee Ee aN Radiation Tactical |Full Strategic | aR! Asmermnreri remmrmer 4 cad ae Environment ea | ROR ge 8 oni a ars CMOS-IIl kh, AEN Process CMOS-I| | ichogm | RICMOS™ ee xX GRO ss fps Array Sizes 20K 15K 10K* euteee, Neaneastaee ae LON % “Consult Honeywell foravalabilty. BS Re | eae al > i cee 7 lel Sis This data sheet addresses the design and manufacturing ae ey li [baled es capability of Honeywell's HC high-performance CMOS La PoE gate array. i Honeywell 1150 E. Cheyenne Mtn. Bivd., Colorado Springs, Colorado 80906 (719) 540-3807 Telex #452433

DESCRIPTION

The high-performance HC20000 gate array offers metal CMOS process. The Array is based upon a improved system performance, testability and space unique ten-transistor physical cell that allows architecture reduction benefits to advanced military avionics and specific memory elements to be built on-array for commercial CPU designers. The HC20000 is manu- improved system performance. factured using a production level 1.2-micron, two-level HC ARRAY PHYSICAL ATTRIBUTES Device HC20000 Total Gates (6T) 20,097 Equivalent 2-Input NAND Gates * 17,382 Total Pins 284 Total /O 238 Input Only 98 Power & Ground 40 Test/Clock 6 * Usable gates at 85% utilization, includes ~2K test gates HC FEATURES/BENEFITS Features Benefits : + 17K Equivalent Usable Gates + Flexible System Partitioning * 238 I/O Pins + Fewer l/O Boundary Crossings « TTLand CMOS Interfaces * Optimized System Performance * High Level of Logic Integration + Reduced Board Space Required + Performance Programmable Macrocells + Increased System Reliability « Soft Macrocell Function Capability + Low-risk, Low-cost Implementation of DoD Standard Communications and Testability Protocols + Macrocell Library Compatibility + Upward Migration Path for Systems with HCT and HCS CMOS Gate Arrays Requiring Strategic Radiation Hardness + Proven VLSI Design System (VDS) Toolkit™ * Minimized Design Risk + Faster Deployment of Military Systems « Support for Present and Emerging DoD Standards « User Selectable Built-In Test Options + Simplified Design Debug and System Test » Reduced Manufacturing Test Time and Cost * Advanced Packaging with Logic Densities of * Reduced Board Space Required 20,000 Gates/Inch? of Board Space + MIL-M-38510 Qualification Pending « Reduced Program-Specific Qualification Costs + Dedicated Quick-Turn Prototype Facility * Quicker Deployment of Military Systems. ee Honeywell 2

capability, illustrated in Figure 1. The following table block. PATTERN GENERATION } } TEST PROGRAM. FIGURE 1. HONEYWELL'S DESIGN AND MANUFACTURING CAPABILITIES

ee EE | . San Sate RSet Det VLSI DESIGN SYSTEM (VDS)™ VDS™ is a design methodology and CAD system that — providing maximum flexibility and efficiency in the front- helps assure first pass design success resulting in faster end design process. deployment of a military system. Honeywell's design methodology consists of the VDS Toolkit™, a physical All phases of the design cycle are supported by design service, and a test generation service. The VDS —_ Honeywell from schematic capture through test vector Toolkit™ is a comprehensive, technology-independent generation. The VDS Toolkit™ is currently available on ASIC design package that equips the ASIC designer with Mentor workstations and can be ported to other design VDS Software™ and a macrocell library. The toolkit is platforms. accessed via a user-friendly, graphical human interface, HONEYWELL HONEYWELL MENTOR™ vDS VDS™ DESIGN DESCRIPTION APPLICATION TOOLKIT™ SERVICES _ Schematic Entry NETED/SYMED Schematic Capture EXPAND Error Checking VERIFY™ - fanout exceeds drive capability . = unconnected macro inputs/outputs - external signal not connected through I/O buffer Design Statistics VERIFY™ . - cell inventory and utilization - VO inventory and utilization - total number of nets and pins Propagation Delay Calculation DELAY™ + intrinsic delay of each path within each macrocell - additional delay of fanout and interconnect capacitance - at user-defined power supply voltage and junction temperature - pre/post route options Functional Simulation QUICKSIM SIM VF MODELS: LASAR-6 Fault Analysis LASAR-6 Static Timing Analysis DAMSEL™ Test Program Generation MIGHT™ - produces ANDO compatible functional and/or scan test vectors - accepts output files from Mentor, DAISY, and LASAR-6 simulators Automatic Test Vector Generation RIGEL™ Automatic Placement XPL. - Netlists received by magnetic media or dial-up field transfer Automatic Routing MERLYN-G Automatic Performance Biasing PERFBIAS™ we Honeywell 4

EE EE EE | SILICON UNDERLAYERS ee A gate array is a semicustom device assembled on a The HC anrray's I/O buffers have the following matrix of X columns by Y rows of physical cells. The — characteristics: physical cell in the HC Array Family consists of ten uncommitted transistors. This array of uncommitted * Built-in configurable test logic transistors, along with the WO ring, are called * Dedicated I/O and input only functions underlayers and are common to all personali- * 8mA TTL output drive zations of the gate array. The I/O ring consists of YO » CMOS or TTL input and output configurable interface buffers, a clock distribution network, and power busses. + ESD input protection greater than 2000 volts . The macrocell library contains the data needed to connect the transistors of one or more physical cells to Each /O buffer can be independently used as an input form a logic function. only, output only, or I/O function. The output buffer has a high impedance state. The input and output portions of the 1/O buffer act independently. CMOS/TTL INPUT INTERFACE CHARACTERISTICS Interface Logic HI Logic LO Switchpoint TH TV.

5 Honeywell

HC20000 HONEYWELL/SS ELEK. MIL 03 ya | 4yS51872 oodde41 & r » 4551872 HONEYWELL/SS ELEK, MIL O3E 00241 D THHQ-\\1-09 _ PERFORMANCE PROGRAMMABLE MACROCELL LIBRARY Honeywell provides an accurately modeled and highly - performance programmable NAND, NOR and inverter flexible macrocell library that has been optimized for —_ macrocells to optimize critical path performance. maximum synchronous system performance. The library contains approximately 110 hard-wired data path - static and dynamic register bits are constructed using elements ranging from inverters to flip-flops, adders and CMOS transmission gates and optional serial-scan shifters. testability to allow the tradeoff of minimum register area (dynamic) with minimum register power (static) during the The CMOS 1.2-micron macrocell library has been designprocess. characterized at the device level through extensive SPICE modeling. The resulting SPICE K-factors are - architecture specific soft RAM macrocells can be stored in a technology table and used in circuit simulation constructed to provide improved system performance by and the simulation results compared to actualtest arrays. _ eliminating I/O delays required during accessing off-array Each macrocell has been evaluated over the entire = memory. military temperature range, voltage and process spectra to ensure accuracy and guaranteed worst case delays. The table below provides performance data for selected LSI functions designed with the CMOS macrocell library. The CMOS 1.2-micron macrocell library provides these The Macrocell Performance Guide shows the area, benefits in new system designs: intrinsic delay, and additional metal loading delays for macrocells in the HC library. - a common library of over 110 cells including bit-width programmable register, counter and multiplexer macrocells to maximize array efficiency, and minimize dynamic power. LSI FUNCTION PERFORMANCE Typical Case (1) Worst Case (2) Cell Function (ns) (ns) Count 32-bit Fast Adder with FullCaryLookAhead | 44 | 445 32-bit x 32-bit Word Register File Read 8 1,300 (1 Read /1 Write) Write 16 16-word x 1-bit RAM (1 Read/1 Write) 108 (1) Vag = 5.0V, Tj = +25°C, Process = Nominal (2) Vdd = 4.5V, 7 = +150°C, Process = Worst case Honeywell 6

. a HONEYWELL/SS ELEK, MIL 03 ve 4S514?2 gogde4e 7 r HC20000 = 4551872 HONEYWELL/SS ELEK. MIL O3E 00242 D --4Aa-N-09 — MACROCELL PERFORMANCE GUIDE (Tj = 25° C; Vag = 5.0V; Tin = Ins; Process = Nominal) (Typical) * . Cell Cell Base |Load Factor | Base j|Load Factor | Input Cell Description Name Size Rising Rising Falling Falling Cap. (wxh) (ns) (ns/pF) (ns) (ns/pF) (pF) Inverters/Buffers Inverter INVO 1x1 1 183 527 188 566 192 Power Inverter INV1 1x1 1 .208 360 081 235 365 Double Power Inverter INV2 1x2 2 206 176 .078 142 668 Balanced Drive Inverter INV3 1x1 1 207 371 116 369 334 Non-inverting Buffer BUF1 4x1 1 469 518 571 406 127 Delay Macro BUF4 | 2x1 2 | 1.886 1.024 1.858 113 127 AND, OR, NAND, & NOR 2-NAND ND2 1x1 1 276 983 186 850 128 3-NAND ND3 1x1 1 342 97 301 1.070 113 4-NAND ND4 1x2 2 477 911 494 1.32 123 6-NAND ND6 2x2 4 1.195 520 4.118 431 126 2-AND AND2 4x1 1 533 1.105 539 640 123 5-AND ANDS | 2x1 2 | 1.245 1.173 681 734 123 Power 2-NAND ND2H 1x2 2 289 388 214 356 364 Power 3-NAND ND3H 1x2 2 A19 493 386 548 .283 2-NOR NOR2 | 1x1 1 512 1.337 194 446 194 3-NOR NOR3 | 3x1 3 | 1.041 542 839 409 154 6-NOR NOR6 | 2x2 4 | 1.362 599 1,010 650 126 Power 2-NOR NORH 1x2 2 440 673 158 252 379 2-0R OR2 1x1 1 420 104 732 743 128 AND/OR, OR/AND Gates 1-2 AND/OR/Invert AOH 1x1 1 463 1.638 218 745 112 2-2 AND/OR/Invert AOl2 3x1 3 1.139 527 983 391 128 3-3 AND/OR/Invert AOI3. 3x1 3 1.042 1.010 1.028 645 127 Power 1-2 AND/OR/Invert AOIH 1x2 2 485 946 211 407 267 1-2 OR/AND/Invert OAI1 1x1 1 450 1.509 -306 939 129 2-2-1 OR/AND/Invert OAI3 2xt 2 840 1.714 603 1.106 131 Power 1-2 OR/AND/invert OIAH 1x2 2- 471 754 .273 432 268 3-3-3 AND/OR AO3 2x2 4 850 977 779 1.089 114 1-2-3-4 AND/OR AO4 2x3 6 930 .997 986 1.190 115 1-3 OR/AND OA1 2x2 4 639 903 -766 1.037 .203 Exclusive OR/NOR Gates . Exclusive-OR EXOR 3x1 3 913 535 704 438 225 Exclusive-NOR EXNR 3x1 3 575 541 667 461 247 4-Bit Exclusive-OR EXO4 2x3 6 1.730 532 1.748 1.938 202 8-Bit Exclusive-OR EXxO8 6x3 18 2.238 541 2.114 445 263 10-Bit Exclusive-NOR EXNO 4x5 20 2.612 537 2.323 439 185 2-2 AND/Exclusive-OR AXO2 2x2 4 1.217 571 1.138 495 143 Priority/Decode 2 to 4 Decode w/ Enable DEC2 10 | 1.469 588 1.173 Aad 188 3 to 8 Decode w/ Enable DEC3 18 | 1.852 525 1.690 401 324 8-Bit Priority Selector SEL8 15 1.070 1.398 861 630 233 4-Bit Priority Encoder ENC4 4 500 1.438 514 755, 248

7 Honeywell

HC20uuy ONEYWELL/SS ELEK. maL 03 Dell ussia72 coooe43 9 yuu 4551872 HONEYWELL/SS ELEK. MIL O3E 00243) =D 7~yYQ-yy-0q9 — MACROCELL PERFORMANCE GUIDE (continued) (Tj = 25° C; Vag = 5.0V; Tin = ins; Process = Nominal) (Typical) Base Load Factor Base | Load Factor | Input Cell Description Rising Rising Falling Falling Cap. (ns) (nsipF) (ns) (ns/pF) (pF) Multiplexers 2 to 1 Multiplexer MxC2/| 2x1 4 1.072 547 1.091 496 119 MXE2 | 2x1 2 to 1 Multiplexer with MXC3/} 3x2 9 1.362 1.042 1.335 1.053 138 Complement Enable MXE3 | 3x1 4to 1 Multiplexer with MXC4/| 2x2 8 1.300 969 1.474 869 196 Enable MCE4 | 2x2 8 to 1 Multiplexer with MXC8/} 2x3 16 1.622 1.092 1.886 1.160 122 Enable MXE8 | 2x5 Flip-Flops (F/F) Dynamic F/F DFC1/ | 2x2 6 1.456 985 1.497 799 126 DFE1 2x1 Dynamic F/F w/Clk. DFC2/ | 3x4 15 1.364 889 1.293 -764 124 En. & Sync. Set/Clr. DFE2 3x1 Dynamic F/F w/Clk. DFC3/ | 2x4 10 1.734 1.055 1.663 892 176 En. DFE3 2x1 Dynamic F/F w/ 2-1 DFC4/ | 2x4 10 1.850 1.061 1.791 844 167 MUX Data Input DFE4 2x1 En. and 2-1 DFE5S 3X1 MUX Data In. Static F/F w/ Clk DFC6/ | 2x3 10 2.680 5A 2.273 466 257 En. & Syne. Clr. DFE6 2x2 Single F/F SFF2 | 2x4 8 1.37 488 1.26 550 .130 Quad D Latch QDL 2x4 8 .796 477 .959 563 302 SCAN Flip-Flop (F/F) SCAN Reg Cont! w/reset DSC6/ 5x3 633 .0835 511 .0656 420 SCAN F/F Ele. w/reset DSE6 5X1 1.264 944 1.241 651 150 SCAN Reg. Cont'l w/set DSC8/ | 5x3 590 078 605 .072 312 SCAN F/F Ele. w/set DSE8 | 5X1 1.265 944 1.242 652 -150 Miscellaneous 4-Bit Up/Dn Counter w/ CNT4 | 5x7 35 2.03 509 2.46 889 -190 Parallel Load 4-Bit Shifter SFC1/ | 3x4 24 1.240 528 1.187 455 .258 SFE1 3x4 4-Bit Adder ADD4 | 6x8 48 1.889 794 1.621 805 263 4-Bit Partial Adder ADDS | 3x3 9 1.808 1.07 1.845 878 257 Single-Bit Adder ADD1 2x3 6 1.713 .766 1.586 688 .215 4-Bit Comparator CMP1 | 3x5 15 1.819 540 1.774 429 2441 4-Bit Magnitude Comp. CMP4 | 4x7 28 2.081 1.163 2.050 794 198 4-Bit Incrementer INC4 | 4x6 24 1.530 566 1.686 519 .255 4-Bit Decrementer DCR4 | 4x5 20 1.828 565 1.559 458 236 Rd/Wr RAM MME1 | 18x2 Honeywell 8

HONEYWELL/SS ELEK. MIL 03 vel 4551472 go00c44 oO T HC20000 . 4551872 HONEYWELL/SS ELEK, MIL O3E 00244 D T-HQ-ss-0qG 7 MACROCELL PERFORMANCE GUIDE (continued) (Tj = 25°C; Vag = 5.0V; Tin = ins; Process = Nominal) (Typical) : ne | S| com | ie [Re [rine | Ene = Cell Description Name | Size Rising Rising Falling Falling Cap. (wxh) (ns) (ns/pF) (ns) (ns/pF) (pF) HC I/O Cells* Clock Driver (Low Drive) CLKA 2.760 .0096 2.77 O11 4.0 2-Stage CMOS Input (CTL) | CIN2 .990 499 942 581 3.0 2-Stage TTL Input (CTL) CIN3 571 425 1.480 660 3.0 Unused Input w/SCAN tooo — —_— — — _ Unused Input only w/SCAN | !003 3.515 985 3.01 1.068 3.0 CMOS Inv. Input w/SCAN 1103 813 400 881 475 3.0 w/Input SCAN Reg. 2-Stage CMOS Input Only 1203 4,050 .967 3.743 1.005 3.0 w/ SCAN w/ SCAN Unused /O Boo4 4.25 914 3.845 986 .069 w/ SCAN CMOS Low Drive Output Bo14 961 0953 1.181 1120 4.0 w/ SCAN CMOS Output B021 3.44 042 3.14 .057 4.0 w/ SCAN CMOS High Drive Output Bo24 3.44 0423 3.140 .0567 4.0 w/ SCAN 5V TTL Output Buffer Bo41 3.61 085 3.24 .038 4.0 w/ SCAN w/ SCAN CMOS Invert Input B104 813 .400 881 475 4.0 w/ SCAN 2-Stage CMOS Input B203 1.55 75 1.43 775 3.0 w/ SCAN 2-Stage CMOS Input B204 1.44 -700 1.350 .720 3.20 w/ SCAN 2-Stage CMOS 1/0 B224 2.44 371 2.245 388 4.0 w/SCAN 2-Stage TTL Input B303 982 69 2.00 89 3.0 w/SCAN 2-Stage TTL Input B304 926 647 1.880 823 3.20 w/SCAN 2-Stage TTL Input/ CMOS High Drive Out B324 2.183 344 2.51 4.39 4.0 wiSCAN 2-Stage TTL /O B344 2.296 383 2.62 464 4.0 w/ SCAN 2.030 118 2.020 118 667 SCAN Control Circuitry cco2 BIST Control Circuitry CCo3 2.61 117 2.73 118 667 CMOS High Drive Output cot2 2.887 043 5.470 .039 4.0 For Test-Data-Out TTL Output For COT4 2.843 071 5.023 .033 4.0 Test-Data-Out * All TTL outputs have 8mA drive capability. **For use with BIST (Built-In Self-Test)

9 Honeywell

HC2000u HONEYWELL/SS ELEK. MIL 03 DEf§ 4551872 goone4s e

4551872 HONEYWELL/SS ELEK, MIL O3E 00245 D T-4H&-11-09 —

Each macrocell has its own intrinsic base delay and load = Macrocells using a control hat and elements (e.g., DFC1, factor. Macrocell performance is influenced by = DFE1) require an additional load per element. temperature, voltage, and process variations. _ Intrinsic base delay is also a factor of the input edge rate. In the following equation for calculating the propagation delay, Tpa, the input edge rate for the intrinsic base delay When calculating the propagation delay of amacrocellor _is 1 ns. logic path, temperature, voltage, process, input capacitance of the next macrocell, and capacitive loading Best case/worst case delay values can be obtained from due to metal interconnect must be considered. Honeywell's CMOS Design Manual. Tpd =[Tp + (LF x Cj) + (EF x (No-1))] where, Th = Intrinsic base delay at 25° C, 5V, nominal process, ns LF = Load factor for macrocell, ns/pF METAL LOAD vs. FANOUT Cj =Total capacitive load = Cin + Cmetal: PF EF = Element factor for control that macrocell, ns/element Ne = Number of elements attached to the control hat Example 1. 12 Assume a 2-input NAND gate, ND2, 25°C, 5V, 1.0 nominal process, fanout = 2 identical 2-input NAND gates. ec From Macrocell Performance Guide, Cjp = 0.128 pF. 8 0.8 From Metal Load vs. Fanout, interconnect s capacitance = 0.375 pF HM 06 Tpa(Rising)=[ Th + (LF xCj)] 0.4 0.2 Example 2. 0 2 4 6 8 10 12 Assume a 2:1 multiplexer with 4 elements (MXC2/MXE2), Fanout 25°C, 5V, nominal process, fanout = 4 2-input NAND gates. 0.657 EF =0.05 C(metal) = (0.238) x (Fanout) (Nominal) From Macrocell Performance Guide, Cjn= 0.119 pF. From Metal Load vs. Fanout, interconnect capacitance = 0.592 pF (worst case) Tpa(Falling)= [Tp + (LF x Cj) + (EF x (Ne-1 ” = 2.033 ns —_—— Honeywell 40

HONEYWELL/SS ELEK. MIL 03 vel 451472 OOOOe4b 4 I HC20000

4551872 HONEYWELL/SS ELEK, MIL O3E 00246 0 T-4a-\\)-09 —

Power dissipation of a CMOS circuit is difficult to calculate be made by summing array power (PI), output buffer because it is extremely dependent upon such conditions — power(PE) and clock power (PC) as follows: as switching frequency, load capacitance, supply voltage, x input rise or fall time and temperature. PT =(PI+D PEn +PC) Typically, power consumption of a CMOS gate array is wherex is the number of output buffers. comprised of array power and I/O power. The array is dominated by AC power (CV? f), which is controlled by | Maximum power dissipation should not exceed a level at the logic function (how heavily loaded each gate is and which the junction temperature (Tj) will exceed 150°C. how fast they switch). Within the array, power is Tj=PTx TRja+Ta where TRia is thermal resistivity of the dissipated by two components: the clock and the rest of | package from junction to ambient and Ta is ambient the array. The \\/O buffers are dominated by DC power _ temperature for the condition of device cooled by free (I*V), although AC power is an important consideration. air. Afirst-order approximation of power dissipation can Array Power PL =GxP xf088x Vdd 225 x 0.23 x 10° in milliWatt, where G = equivalent gates (number of physical cells used x 1.5). P = fraction of gates which switch, on the average, each clock cycle (0<P<1). f =clock frequency in MHz. Vdd = array supply voltage. Itis expected that .1 < P <.4is normal system operation for a majority of the array designs. Output Buffer Power (Single Buffer) Case 1: Output buffer drives a transmission line with only one pulse present at a time. CRITERIA: 2Tg < (minimum time between data changes) Tg = one-way delay on transmission line, inns. Tg=Lx Vp L= length of line, in inches Vp =.100ns/in 50 ohm coax =.185 ns/in PC board, 50 ohm, glass-epoxy These numbers are approximations. Use actual values if available. Positive clock edge (assuming a 1Ons clock rate). 1 10 20 30 40 50 60 70 80 90 100 EXAMPLE | DATA —>| min je— For clocked data, the minimum is the time clock period. ~ 11 - Honeywell

HC20000 HONEYWELL/SS ELEK. MIL 03 DE) yssia72 ooooay7 &

4551872 HONEYWELL/SS ELEK, MIL O3E 002470 D —7-HQ-1\\-09 ——

POWER DISSIPATION (cont'd) PE = Tx Vddx? x (Cj + Cy) in milliWatt, where: T = numberof positive logic transitions per nanosecond, on the average. Forthe example above, this is 3/100 = 0.03. C= lumped load capacitance, in pF, made up of array input pin capacitance and PC board via capacitance. Cy= transmission line capacitance, in pF, made up of PC board foil capacitance and coax capacitance, 50 ohm. Vddx = output buffer power supply. . Case 2: Output buffer drives a transmission with two or more pulses present at a time. CRITERIA: 2Tg > (minimum time between data changes) PE(max) = Vddx2 (Tx Cy+1— min{ Tp, Ty} x 103 ) in milliwatt, 2Zgo 0 To+T where: Zo = path characteristic impedance, in ohms { }= minimum of values in brackets To = average time signal is at logic LO Ty = average time signal is at logic HI Forthe example above, min{To,T4} = 4 = 0.4 To+T; 10 Note that the expression for this case is indicated as a maximum. Although it is theoretically possible to dissipate the maximum power, it is realistically not probable. Power dissipation for long lines that may contain more than one pulse on the line at one time is a complex function of duty cycle, line length and frequency. Clock Power PC = (30 + Cg + 0.26 XL +5.24 x B) x £988 x Vdd 225 x 10 in milliWatt, where: f = Clock frequency, in MHz. Vdd = = Array supply voltage. Co = Total clock bus capacitance composed of metal and macro clock pin capacitances, in pF. . ,B = Total number of clocked macros, e.g., DFC1. L = Total number of elements in stacked flip-flop macros, e.g., DFE1. Constants used in PC formula are derived from actual test results. ns Honeywell 12

HONEYWELL/SS ELEK, MIL 03 DEM 4sS1472 o000e48 8 ii HC20000

4551872 HONEYWELL/SS ELEK, MIL O3E 00248 D “T= Ha-1)-0g _

Design-for-Test and Maintainabllity Today's designs often carry demanding component and single stuck-at type faults. These tests are applied and system-level test and maintenance requirements. gatheredusing SSD. Honeywell provides support for a full range of Design-For- Test (DFT) techniques, intended to reduce design Boundary Scan Design debug time, board and module costs, and field system The boundary scan method is also fully supported down time. Built-in Self-Test reduces test costs and —_ utilizing scan-compatible input, output, and I/O buffer improves system maintainability. Boundary Scan macrocells. Figures 3 and 4 illustrate the scan circuitry simplifies testing of board interconnects and provides associated with each input and each output buffer, excellent fault isolation. Serial Scan generates high- fault-coverage test patterns which simplify system and software checkout. Honeywell also offers automatic test > Program generation in the form of MIGHT™, and an DSCB8) - automatic, deterministic test pattern generation system with RIGEL™, mM MIGHT™ [_oses_] ra The MIGHT™ system provides automatic test program Hose |] generation for Honeywell gate arrays. Test programs are n_| automatically generated and formatted, simplifying a {tt process that requires weeks of manual development U_oses_ and expensive debug time on the tester. The shell and Ci Menu approach allows rapid integration of new L{ oses | technologies, expands to any language driven ATE, and m7 —| achieves a new standard in test quality control. Hoses] mT] RIGEL™ [mn L{_oses_| RIGEL™ is an automatic, deterministic single stuck-at a) fault test pattern generation system. it is based on an C{ ses | enhanced D-algorithm. Fundamental to its use is the mT] circuit implementation of Honeywell Scan Design (HSD), Hoses | a scan structured approach to design for test. The mm _] RIGEL™ test generation tools provide a greater than 98 (Unt percent fault coverage of permanent single stuck-at Hoses FF faults. tt L{ oses | | BUILT-IN SCAN CIRCUITRY m1 Loses ] The HC gate array supports synchronous scan design m_| and boundary scan design testability methods. Loses _ Serial Scan Design a Designs which provide easy application of stimulus and L{ ses | easy measurement of responses are necessary to make I circuits thoroughly testable. Honeywell's primary L{ oses | technique that supports this is called Synchronous Scan mM] Design (SSD). SSD specifies that registers in the circuit (Or have an ability to also be reconfigured into a serial shift Hoses F register (Figure 2). The serial chain is able to be loaded [uit with test input and unloaded with test responses from L{ oses | the component edge. Honeywell's RIGEL™ automatic test generation tool can be used to build a test that is FIGURE 2. 16-BIT D-REGISTER IN SERIAL capable of detecting greater than 98% of all permanent SCAN PATH : 13° Honeywell

4551872 HONEYWELL/SS ELEK, MIL O3E 00249 D T-WQ-}|-09 ——

FIGURE 3. INPUT SCAN REGISTER FIGURE 4. OUTPUT SCAN REGISTER output scan ring around the periphery of the array. Also | Element Test and Maintenance Bus (ETM-bus). FIGURE 5. VHSIC TESTABILITY ARCHITECTURE

HONEYWELL/SS ELEK, MIL 03 a | 4551872 o000250 & I HC20000 . 4551872 HONEYWELL/SS ELEK. MIL 03E 00250 D T-y Q.1)-09— ADVANCED PACKAGING busses for increased fault tolerance. A microprocessor The HC array is available in advanced single and multi- and memory interface increases the capabilities of the | array packages to reduce board and module space, TIU as a TM-bus master or as the test interface on an quickly debug brassboard and prototype systems, and application module. ‘The Joint Test Action Group (JTAG-) improve system reliability through reduction of array bus and the Element Test and Maintenance (ETM-) bus _ junction temperatures. ports provide standard test and maintenance control at the chip level. Honeywell's TIU supports multiple Leaded chip carriers (LDCC) and pin grid array (PGA) JTAG/ETM ports to handle large boards with up to 128 _— packages, available in open or proprietary tooling, are JTAG- or ETM-bus compatible components. supported over the military temperature range for a variety of military and commercial applications. The ETM-bus is a multidrop, synchronous bus that transfers bit-serial test and maintenance instructions and Honeywell's advanced +MICROPAK-II™ — multi-array data between a master device and up to 32 slave module provides packaging techniques for assembly of elements on other chips in a module. The slave element —_ multiple HC series CMOS arrays and cache memory die is the on-chip TMC, a function block that controls the test into a single hermetically sealed ceramic module. and maintenance features such as chip initialization, © MICROPAK-II™ multi-array modules dramatically improve serial scan, debug, and built-in self-test. Figure 5 — systems’ reliability, and reduce system volume and cost. illustrates how the TIU and TMC are used in a testable Consult Honeywell for more details. VHSIC system to assure low cost field maintenance and quick design debug. The HC20000 is available in a 256 LDCC and a 284 PGA package. If more specific packaging information is User configurable built-in self-test methodologies can _ needed, please contact your Honeywell representative. also be implemented using the scan macrocells in the HC macrocell library.

15 Honeywell

HC20000 HONEYWELL/SS ELEK. MIL O03 Deg 4551872 OOO0eS1 6 i

4551872 HONEYWELL/SS ELEK, MIL 03E 00251 D 7-4-4109 —

284 PIN GRID ARRAY THERMAL CHARACTERISTICS

[2000 #:000-— 100 am AI +.012 20 SOSOGOOOGHOGOOGOOOOG!* O©QQOQOQQHOGQOHOQOOOHGDOOOD © ©QOOQOOOQOQOOOHOOQHOOOO = © QOQQOOHOOQGHOHOQOOGOOQOOO 2 16 OGOOOO OO 9OOQOOHOGOOOOOD) ~ OOQOO@ Q0000| ©2000 f ea | ©0000 10 OG©OO eal =| ©0000 4 OGQ0O a ©0000) F OGGO® ee =| ©0000 83008 | Femme l| So000| so 35 @O00 a @OOOO} PLATED E Package Only Besseese | oescosce Le f Packege +.002 o 200 400 600 800 1000 Forced Air Velocity (LFM) _| Leo s20 Hoat sink: 7 Fins, Omnidirectional (Dia. = 1.5%, Ht. = 0.77)

256 LEADED CHIP CARRIER

1.940 [= 1.480 2.010 080 +008 4 can (—] (Se Jos ee ' + = a Honeywell 16

4551872 HONEYWELL/SS ELEK, MIL O3E 00252 L3) T-4Q-\\)-0 —

advanced military or commercial standards. modified Class S flows available. specific qualification data is available, at an additional —_ or to customer-specific qualification flows. charge, upon request from Honeywell. FIGURE 6. MIL-STD-883C CLASS B PRODUCT FLOW FIGURE 7. MODIFIED MIL-STD-883C CLASS S PRODUCT FLOW

| HC206 HONEYWELL/SS ELEK, MIL 03 pel 4ssLa72 OO00e253 1 I uu

4551872 HONEYWELL/SS ELEK, MIL O3E 00253 D T-4Q1-09 —

Parameter D ‘ipti Ratings Units Vi Input Voltage | 03 | Vda +0.3 Vv lo DC Output Current [ -10 | 10 | ma Ta Operating Ambient Temperature | -s5 | +125 | °C Ts Storage Temperature | 5 | +150 | °C Note: Stresses above those listed under “Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating and functional operation of the device at these or any condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS [om [cmos Recognized as Low Signal Vit Low Level Input Voltage 15 Vv Over Recommended Vad &Ta Recognized as High Signal Vy i Vv Over Recommended ih High Level Input Voltage Vad & Ts [Low Level inputcurent [sof [so [| wa | Min =08¥" (3) | 3-State Output Off = loz @) Leakage Current Low HA | Vout =Vss 1... (3) | 3-State Output Off Vi eV ozn ©) Leakage High HA ‘out = Vdd fos (3) | Output Short Circuit Current jv [os | se [os | mm | Vout =Vss i input Capacitance Cout(4) | Output Capacitance Tf 40 | | 40 | pr _| BioirectionaL (1) Power supply voltage Vag = 5.0V 10%. (2) Ambient temperature range Tais-55°C to +125°C. ; ; (3) Currententering a pins defined as positive. Current leaving a pin is defined as negative. For specifying current on input or output pins, the most negative value is the minimum and the most positive value is the maximum. (4) Values for Cj, and Coy do not include package capacitance. . (5) For lpg testing, not more than one output should be shorted ata time, nor for more than one second. “Includes pull-down device SS Honeywell 18