SN74HC165-Q1 TI | Alldatasheet
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/C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0054/C0053/C0262/C0081/C0049 /C0056/C0262/C0066/C0073/C0084 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076/C0262/C0076/C0079/C0065/C0068 /C0083/C0072/C0073/C0070/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082 SCLS518 − AUGUST 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Qualification in Accordance With AEC-Q100 † /C0068Qualified for Automotive Applications /C0068Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval /C0068ESD Protection Exceeds 1500 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) /C0068Wide Operating Voltage Range of 2 V to 6 V /C0068Outputs Can Drive Up To 10 LSTTL Loads /C0068Low Power Consumption, 80-µA Max ICC /C0068Typical tpd = 13 ns /C0068±4-mA Output Drive at 5 V /C0068Low Input Current of 1 µA Max /C0068Complementary Outputs /C0068Direct Overriding Load (Data) Inputs /C0068Gated Clock Inputs /C0068Parallel-to-Serial Data Conversion † Contact factory for details. Q100 qualification data available on request. description/ordering information The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shift the data toward a serial (QH ) output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SN74HC165 also features a clock-inhibit (CLK INH) function and a complementary serial (QH ) output. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
ORDERING INFORMATION
TA PACKAGE ‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 125°C SOIC − D Tape and reel SN74HC165QDRQ1 HC165Q1 −40°C to 125°C TSSOP − PW Tape and reel SN74HC165QPWRQ1 HC165Q1 ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D OR PW PACKAGE (TOP VIEW) SH/LD CLK E F G H Q H GND VCC CLK INH D C B A SER Q H Copyright 2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0054/C0053/C0262/C0081/C0049 /C0056/C0262/C0066/C0073/C0084 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076/C0262/C0076/C0079/C0065/C0068 /C0083/C0072/C0073/C0070/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082 SCLS518 − AUGUST 2003
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
H L ↑ Shift† H ↑ L Shift† † Shift = content of each internal register shifts toward serial output QH . Data at SER is shifted into the first register. logic diagram (positive logic) S R S R S R S R S R S R S R S R SH/LD CLK INH CLK SER Q H Q H 11 12 13 14 3 4 5 6 AB CD EFG H
/C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0054/C0053/C0262/C0081/C0049 /C0056/C0262/C0066/C0073/C0084 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076/C0262/C0076/C0079/C0065/C0068 /C0083/C0072/C0073/C0070/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082 SCLS518 − AUGUST 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 typical shift, load, and inhibit sequence Load E Q H H G C F Data Inputs D SH/LD SER CLK INH CLK B A Q H L L H L H L H H H H L H L H L H L H L L H L H L H Inhibit Serial Shift
/C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0054/C0053/C0262/C0081/C0049 /C0056/C0262/C0066/C0073/C0084 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076/C0262/C0076/C0079/C0065/C0068 /C0083/C0072/C0073/C0070/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082 SCLS518 − AUGUST 2003
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN NOM MAX UNIT VCC Supply voltage 2 5 6 V VCC = 2 V 1.5 VIH High-level input voltage VCC = 4.5 V 3.15 VVIH High-level input voltage VCC = 6 V 4.2 V VCC = 2 V 0.5 VIL Low-level input voltage VCC = 4.5 V 1.35 VVIL Low-level input voltage VCC = 6 V 1.8 V VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 2 V 1000 ∆t/∆v‡ Input transition rise/fall time VCC = 4.5 V 500 ns∆t/∆v‡ Input transition rise/fall time VCC = 6 V 400 ns TA Operating free-air temperature −40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
/C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0054/C0053/C0262/C0081/C0049 /C0056/C0262/C0066/C0073/C0084 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076/C0262/C0076/C0079/C0065/C0068 /C0083/C0072/C0073/C0070/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082 SCLS518 − AUGUST 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C MIN MAX UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX UNIT 2 V 1.9 1.998 1.9 IOH = −20 µA 4.5 V 4.4 4.499 4.4 VOH VI = VIH or VIL IOH = −20 µA 6 V 5.9 5.999 5.9 VVOH VI = VIH or VIL IOH = −4 mA 4.5 V 3.98 4.3 3.7 V IOH = −5.2 mA 6 V 5.48 5.8 5.2 2 V 0.002 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 VOL VI = VIH or VIL IOL = 20 µA 6 V 0.001 0.1 0.1 VVOL VI = VIH or VIL IOL = 4 mA 4.5 V 0.17 0.26 0.4 V IOL = 5.2 mA 6 V 0.15 0.26 0.4 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 8 160 µA C i 2 V to 6 V 3 10 10 pF
/C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0054/C0053/C0262/C0081/C0049 /C0056/C0262/C0066/C0073/C0084 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076/C0262/C0076/C0079/C0065/C0068 /C0083/C0072/C0073/C0070/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082 SCLS518 − AUGUST 2003
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timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC TA = 25°C MIN MAX UNITVCC MIN MAX MIN MAX UNIT 2 V 6 4.2 fclock Clock frequency 4.5 V 31 21 MHzfclock Clock frequency
6 V 36 25
2 V 80 120
SH/LD low 4.5 V 16 24 tw Pulse duration SH/LD low
6 V 14 20
nstw Pulse duration 2 V 80 120 ns CLK high or low 4.5 V 16 24CLK high or low SH/LD high before CLK↑ 4.5 V 16 24SH/LD high before CLK↑
2 V 40 60
SER before CLK↑ 4.5 V 8 12SER before CLK↑
6 V 7 10
2 V 100 150
tsu Setup time CLK INH low before CLK ↑ 4.5 V 20 30 nstsu Setup time CLK INH low before CLK↑
6 V 17 25
CLK INH high before CLK↑ 4.5 V 8 12CLK INH high before CLK↑ Data before SH/LD↓ 4.5 V 20 30Data before SH/LD↓
6 V 17 26
2 V 5 5
SER data after CLK↑ 4.5 V 5 5 th Hold time SER data after CLK↑
6 V 5 5
PAR data after SH/LD↓ 4.5 V 5 5PAR data after SH/LD↓
/C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0054/C0053/C0262/C0081/C0049 /C0056/C0262/C0066/C0073/C0084 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076/C0262/C0076/C0079/C0065/C0068 /C0083/C0072/C0073/C0070/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082 SCLS518 − AUGUST 2003 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM TO VCC TA = 25°C MIN MAX UNITPARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX MIN MAX UNIT 2 V 6 13 4.2 fmax 4.5 V 31 50 21 MHzfmax
6 V 36 62 25
2 V 80 150 225
SH/LD Q H or QH 4.5 V 20 30 45SH/LD Q H or QH
6 V 16 26 38
2 V 75 150 225
tpd CLK Q H or QH 4.5 V 15 30 45 nstpd CLK Q H or QH
6 V 13 26 38
H Q H or QH 4.5 V 15 30 45H Q H or QH
2 V 38 75 110
tt Any 4.5 V 8 15 22 nstt Any
6 V 6 13 19
operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance No load 75 pF
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NOTES: A. C L includes probe and test-fixture capacitance. characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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