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Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
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Technical content

Features

  • Output Drive Capability: 10 LSTTL Loads
  • Outputs Directly Interface to CMOS, NMOS, and TTL
  • Operating V oltage Range: 2.0 to 6.0 V
  • Low Input Current: 1 /C0109A
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance with the Requirements Defined by JEDEC Standard No. 7 A
  • Chip Complexity: 286 FETs or 71.5 Equivalent Gates
  • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
  • These Devices are Pb−Free, Halogen Free and are RoHS Compliant See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

SOIC−16 D SUFFIX CASE 751B TSSOP−16 DT SUFFIX CASE 948F PDIP−16 N SUFFIX CASE 648 MC74HC165AN AWLYYWWG HC165AG AWLYWW HC 165A ALYW/C0071 /C0071 A = Assembly Lo- cation L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or /C0071= Pb−Free Package (Note: Microdot may be in either location) 165A ALYW/C0071 /C0071 QFN16 MN SUFFIX CASE 485AW1 www.onsemi.com

www.onsemi.com MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 50 mA PD Power Dissipation in Still Air Plastic DIP† 750 500 450 mW Tstg Storage Temperature – 65 to + 150 /C0095C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) 260 /C0095C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating — Plastic DIP: – 10 mW/ /C0095C from 65/C0095 to 125/C0095C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND)

0 VCC V

TA Operating Temperature, All Package Types – 55 + 125 /C0095C tr, tf Input Rise and Fall Time V CC = 2.0 V (Figure 1) V CC = 3.0 V VCC = 4.5 V VCC = 6.0 V 1000 600 500 400 ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditions VCC V Guaranteed Limit Unit– 55 to 25/C0095C /C0118 85/C0095C /C0118 125/C0095C VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| /C0118 20 /C0109A 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| /C0118 20 /C0109A 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.80 0.5 0.9 1.35 1.80 0.5 0.9 1.35 1.80 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| /C0118 20 /C0109A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V Vin = VIH or VIL |Iout| /C0118 2.4 mA |Iout| /C0118 4.0 mA |Iout| /C0118 5.2 mA 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance cir- cuit. For proper operation, V in and Vout should be constrained to the range GND /C0118 (Vin or Vout) /C0118 VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.

www.onsemi.com DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Unit Guaranteed LimitVCC VTest ConditionsParameterSymbol Unit/C0118 125/C0095C/C0118 85/C0095C– 55 to 25/C0095C VCC VTest ConditionsParameter VOL Maximum Low−Level Output Voltage Vin = VIH or VIL |Iout| /C0118 20 /C0109A 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V Vin = VIH or VIL |Iout| /C0118 2.4 mA |Iout| /C0118 4.0 mA |Iout| /C0118 5.2 mA 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 /C0109A ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 /C0109A 6.0 4 40 160 /C0109A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symbol Parameter VCC V Guaranteed Limit Unit– 55 to 25/C0095C /C0118 85/C0095C /C0118 125/C0095C fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 8) 2.0 3.0 4.5 6.0 4.8 MHz tPLH, tPHL Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH (Figures 1 and 8) 2.0 3.0 4.5 6.0 150 190 225 ns tPLH, tPHL Maximum Propagation Delay, Serial Shift/Parallel Load to QH or QH (Figures 2 and 8) 2.0 3.0 4.5 6.0 175 220 265 ns tPLH, tPHL Maximum Propagation Delay, Input H to QH or QH (Figures 3 and 8) 2.0 3.0 4.5 6.0 150 190 225 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 8) 2.0 3.0 4.5 6.0 110 ns Cin Maximum Input Capacitance − 10 10 10 pF CPD Power Dissipation Capacitance (Per Package)* Typical @ 25°C, VCC = 5.0 V pF40 * Used to determine the no−load dynamic power consumption: P D = CPD VCC2f + ICC VCC.

www.onsemi.com TIMING REQUIREMENTS (Input tr = tf = 6 ns) ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎ ÎÎÎ ÎÎÎ VCC V ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit ÎÎÎ ÎÎÎ ÎÎÎ Unit ÎÎÎÎÎ ÎÎÎÎÎ – 55 to 25/C0095C ÎÎÎÎ ÎÎÎÎ /C0118 85/C0095C ÎÎÎ ÎÎÎ /C0118 125/C0095C ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load (Figure 4) ÎÎÎ ÎÎÎ ÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 110 ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Minimum Setup Time, Input SA to Clock (or Clock Inhibit) (Figure 5) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 110 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit) (Figure 6) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 110 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Minimum Setup Time, Clock to Clock Inhibit (Figure 7) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 110 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ th ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs (Figure 4) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ th ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Minimum Hold Time, Clock (or Clock Inhibit) to Input SA (Figure 5) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ th ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load (Figure 6) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ trec ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Minimum Recovery Time, Clock to Clock Inhibit (Figure 7) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 110 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tw ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Minimum Pulse Width, Clock (or Clock Inhibit) (Figure 1) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 100 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tw ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Minimum Pulse width, Serial Shift/Parallel Load (Figure 2) ÎÎÎ ÎÎÎ ÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 100 ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Maximum Input Rise and Fall Times (Figure 1) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 1000 800 500 400 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1000 800 500 400 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1000 800 500 400 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns

www.onsemi.com PIN DESCRIPTIONS INPUTS Parallel Data inputs. Data on these inputs are asynchronously entered in parallel into the internal flip−flops when the Serial Shift/Parallel Load input is low. SA (Pin 10) Serial Data input. When the Serial Shift/Parallel Load input is high, data on this pin is serially entered into the first stage of the shift register with the rising edge of the Clock. CONTROL INPUTS Serial Shift/Parallel Load (Pin 1) Data−entry control input. When a high level is applied to this pin, data at the Serial Data input (SA) are shifted into the register with the rising edge of the Clock. When a low level is applied to this pin, data at the Parallel Data inputs are asynchronously loaded into each of the eight internal stages. Clock, Clock Inhibit (Pins 2, 15) Clock inputs. These two clock inputs function identically. Either may be used as an active−high clock inhibit. However, to avoid double clocking, the inhibit input should go high only while the clock input is high. The shift register is completely static, allowing Clock rates down to DC in a continuous or intermittent mode. OUTPUTS QH, QH (Pins 9, 7) Complementary Shift Register outputs. These pins are the noninverted and inverted outputs of the eighth stage of the shift register. Device Package Shipping† MC74HC165ANG PDIP−16 (Pb−Free)

500 Units / Rail

MC74HC165ADG SOIC−16 (Pb−Free)

48 Units / Rail

MC74HC165ADR2G SOIC−16 (Pb−Free)

2500 Units / Reel

NLV74HC165ADR2G* SOIC−16 (Pb−Free) MC74HC165ADTR2G TSSOP−16 (Pb−Free) NLV74HC165ADTR2G* TSSOP−16 (Pb−Free) (Pb−Free)

3000 Units / Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.

www.onsemi.com AB C FG H 11 12 13 4 5 6 9 QH 7 QH SERIAL SHIFT/ PARALLEL LOAD 1 SERIAL DATA INPUT SA CLOCK 2 CLOCK INHIBIT EXPANDED LOGIC DIAGRAM CLOCK CLOCK INHIBIT SA SERIAL SHIFT/ PARALLEL LOAD A B C D E F G H QH QH H L H L H L H H HH LL L H H L L H H L L H H L PARALLEL LOAD PARALLEL DATA INPUTS TIMING DIAGRAM DQ A CC DQ B CC DQ C CC DQ F CC DQ G CC DQ H CC CLOCK INHIBIT MODE SERIAL-SHIFT MODE

www.onsemi.com PACKAGE DIMENSIONS PDIP−16 CASE 648−08 ISSUE U 16 9 b2NOTE 8 D A TOP VIEW B b L A C SEATING PLANE

0.010 CASIDE VIEW M

e NOTE 3 M B M eB E END VIEW END VIEW WITH LEADS CONSTRAINED DIM MIN MAX INCHES A −−−− 0.210 A1 0.015 −−−− b 0.014 0.022 C 0.008 0.014 D 0.735 0.775 D1 0.005 −−−− e 0.100 BSC E 0.300 0.325 M −−−− 10 −−− 5.33 0.38 −−− 0.35 0.56 0.20 0.36 18.67 19.69 0.13 −−−

2.54 BSC

7.62 8.26 −−− 10 MIN MAX MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY . 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). E1 0.240 0.280 6.10 7.11 0.060 TYP 1.52 TYP c A2 0.115 0.195 2.92 4.95 L 0.115 0.150 2.92 3.81 H NOTE 5 NOTE 6 M e/2

www.onsemi.com PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 16 9 SEATING PLANE F JM R X 45/C0095 G

8 PLP−B−

−A− M0.25 (0.010) B S −T− D K C 16 PL SBM0.25 (0.010) A ST DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 6.40 16X 0.58 16X 1.12 1.27 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT

www.onsemi.com PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE B ÇÇÇ ÇÇÇ DIM MIN MAX MIN MAX INCHESMILLIMETERS A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. /C0095/C0095/C0095/C0095 SECTION N−N SEATING PLANE IDENT. PIN 1 1 8 16 9 DETAIL E J B C D A K H G ÉÉÉ ÉÉÉ DETAIL E F M L 2X L/2 −U− SU0.15 (0.006) T SU0.15 (0.006) T SUM0.10 (0.004) V ST 0.10 (0.004) −T− −V− −W− 0.25 (0.010) 16X REFK N N 7.06 16X 0.36 16X 1.26 0.65 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT

www.onsemi.com PACKAGE DIMENSIONS QFN16, 2.5x3.5, 0.5P CASE 485AW ISSUE O ÉÉÉ ÉÉÉ ÉÉÉ DIM MIN MAX MILLIMETERS A A1 0.00 0.05 b 0.20 0.30 D 2.50 BSC D2 0.85 1.15 E 3.50 BSC e 0.50 BSC K 0.20 --- NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

0.20 REF

b L PIN ONE D E B A C0.15 C0.15 e 16X 16X 0.10 C 0.05 C A B NOTE 3 A 16X K (A3) SEATING PLANE C0.08 C0.10 0.80 1.00 L 0.35 0.45 1.85 2.15 DETAIL A L ALTERNATE TERMINAL CONSTRUCTIONS L ÇÇÇÉÉÉ ÉÉÉ DETAIL B MOLD CMPDEXPOSED Cu ALTERNATE CONSTRUCTIONSDETAIL B *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 2.80 3.80 1.10 0.50 0.60 16X 0.30 16X DIMENSIONS: MILLIMETERS REFERENCE TOP VIEW SIDE VIEW NOTE 4 C

0.15 C A B

L1 --- 0.15 2.10 PITCH PACKAGE OUTLINE PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 MC74HC165AD LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.