SL74HC161 SLS | Alldatasheet
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High-Performance Silicon-Gate CMOS The SL74HC161 is identical in pinout to the LS/ALS161. The device inputs are compatibl e with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC161 is programmable 4 -bit synchronous counter that feature parallel Load, asynchronous Reset, a Carry Output for cascading and count -enable controls. The SL74HC161 is binary counter with asynchronous Reset.
- Outputs Directly Interface to CMOS, NMOS, and TTL
- Operating Voltage Range: 2.0 to 6.0 V
- Low Input Current: 1.0 µA
- High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC161N Plastic SL74HC161D SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN 16 =VCC PIN 8 = GND FUNCTION TABLE Inputs Outputs Reset Load Enable P Enable T Clock Q0 Q1 Q2 Q3 Function L X X X X L L L L Reset to “0” H L X X P0 P1 P2 P3 Preset Data H H X L No change No count H H L X No change No count H H H H Count up Count H X X X No change No count X=don’t care P0,P1,P2,P3 = logic level of Data inputs Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3 PIN ASSIGNMENT
MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ 750 500 mW Tstg Storage Temperature -65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260 °C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types -55 +125 °C tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avo id applications of any voltage higher than maximum rated voltages to this high -impedance circuit. For proper operation, V IN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter Test Conditions V 25 °C to -55°C ≤85 ≤125 Unit VIH Minimum High-Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 4.0 40 160 µA
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit fmax Maximum Clock Frequency (Figures 1,6) 2.0 4.5 6.0 MHz tPLH Maximum Propagation Delay Clock to Q 2.0 4.5 6.0 120 160 200 ns tPHL (Figures 1,6) 2.0 4.5 6.0 145 185 320 ns tPHL Maximum Propagation Delay Reset to Q (Figures 2 and 6) 2.0 4.5 6.0 145 185 220 ns tPLH Maximum Propagation Delay Enable T to Ripple Carry Out 2.0 4.5 6.0 110 150 190 ns tPHL (Figures 3,6) 2.0 4.5 6.0 135 175 210 ns tPLH Maximum Propagation Delay Clock to Ripple 2.0 4.5 6.0 120 160 200 ns tPHL Carry Out (Figures 1,6) 2.0 4.5 6.0 145 185 220 ns tPHL Maximum Propagation Delay Reset to Ripple Carry Out (Figures 2,6) 2.0 4.5 6.0 155 190 230 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 6) 2.0 4.5 6.0 110 ns CIN Maximum Input Capacitance - 10 10 10 pF Power Dissipation Capacitance (Per Gate) Typical @25°C,VCC=5.0 V CPD Used to determine the no -load dynamic power consu mption: PD=CPDVCC 2f+ICCVCC 30 pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit tSU Minimum Setup Time, Preset Data Inputs to Clock (Figure 4) 2.0 4.5 6.0 ns tSU Minimum Setup Time, Load to Clock (Figure 4) 2.0 4.5 6.0 ns tSU Minimum Setup Time, Enable T or Enable P to Clock (Figure 5) 2.0 4.5 6.0 110 ns th Minimum Hold Time, Clock to Load or Preset Data Inputs (Figure 4) 2.0 4.5 6.0 ns th Minimum Hold Time, Clock to Enable T or Enable P (Figure 5) 2.0 4.5 6.0 ns trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 4.5 6.0 110 ns trec Minimum Recovery Time, Load Inactive to Clock (Figure 4) 2.0 4.5 6.0 110 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 4.5 6.0 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 4.5 6.0 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns
VCC=Pin 16 GND=Pin 8 The flip-flops shown in the circuit diagrams are Toggle -Enable flip-flops. A Toggle -Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip -flop. The logic level at the Pn input is then clocked to the Q output of the flip -flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip - flop low. Figure 7.Expanded logic diagram
- Count to thirteen, four teen, fifteen, zero, one, and two.
Figure 8. Timing Diagram