HC154

CD54HC154_08 TI | Alldatasheet

Document overview

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Technical content

Features

• Two Enable Inputs to Facilitate Demultiplexing and Cascading Functions
• Fanout (Over Temperature Range)
• Wide Operating Temperature Range . . . -55 oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types - 2V to 6V Operation - High Noise Immunity: N IL= 30%, NIH = 30%of VCC at VCC = 5V
• HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il≤ 1µA at VOL , VOH

Description

The ’HC154 and ’HCT154 are 4- to 16-line decoders/demultiplexers with two enable inputs, E1 and E2. A High on either enable input forces the output into the High state. The demultiplexing function is performed by using the four input lines, A0 to A3, to select the output lines Y0 to Y15, and using one enable as the data input while holding the other enable low. Pinout CD54HC154, CD54HCT154 (CERDIP) CD74HC154, CD74HCT154 (PDIP, SOIC) TOP VIEW

Ordering Information

TEMP. RANGE (oC) PACKAGE CD54HC154F3A -55 to 125 24 Ld CERDIP CD54HCT154F3A -55 to 125 24 Ld CERDIP CD74HC154E -55 to 125 24 Ld PDIP CD74HC154EN -55 to 125 24 Ld PDIP CD74HC154M -55 to 125 24 Ld SOIC CD74HC154M96 -55 to 125 24 Ld SOIC CD74HCT154E -55 to 125 24 Ld PDIP CD74HCT154EN -55 to 125 24 Ld PDIP CD74HCT154M -55 to 125 24 Ld SOIC CD74HCT154M96 -55 to 125 24 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. Y10 GND VCC Y15 Y13 Y12 Y11 Y14 September 1997 - Revised June 2004 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, Texas Instruments Incorporated CD54HC154, CD74HC154, CD54HCT154, CD74HCT154 High-Speed CMOS Logic 4- to 16-Line Decoder/Demultiplexer [ /Title (CD74 H C154 C D74 H CT15 /Sub- ject (High Speed C MOS Logic 4-to-16 Line D ecod er/Dem

E1 E2 A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 L L L L L L LHHHHHHHHHHHHHHH L L L L LHHLHHHHHHHHHHHHHH L L L LHLHHLHHHHHHHHHHHHH L L L LHHHHHLHHHHHHHHHHHH L L LHL LHHHHLHHHHHHHHHHH L L LHLHHHHHHLHHHHHHHHHH L L LHHLHHHHHHLHHHHHHHHH L L LHHHHHHHHHHLHHHHHHHH L LHL L LHHHHHHHHLHHHHHHH L LHL LHHHHHHHHHHLHHHHHH L LHLHLHHHHHHHHHHLHHHHH L LHLHHHHHHHHHHHHHLHHHH L LHHL LHHHHHHHHHHHHLHHH L LHHLHHHHHHHHHHHHHHLHH L LHHHLHHHHHHHHHHHHHHLH L LHHHHHHHHHHHHHHHHHHHL LHXXXXHHHHHHHHHHHHHHHH HLXXXXHHHHHHHHHHHHHHHH HHXXXXHHHHHHHHHHHHHHHH H = High Voltage Level, L = Low Voltage Level, X = Don’t Care Y10 GND = 12 VCC = 24 Y11 Y12 Y13 Y14 Y15 CD54HC154, CD74HC154, CD54HCT154, CD74HCT154

Absolute Maximum Ratings Thermal Information DC Input Diode Current, IIK DC Output Diode Current, IOK DC Output Source or Sink Current per Output Pin, IO Operating Conditions Supply Voltage Range, VCC DC Input or Output Voltage, V Input Rise and Fall Time Thermal Resistance (Typical) θ JA (oC/W) oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3. 2. The package thermal impedance is calculated in accordance with JESD 51-7. PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSVI(V) I O (mA) MIN TYP MAX MIN MAX MIN MAX HC TYPES High Level Input Voltage V Low Level Input Voltage High Level Output Voltage CMOS Loads V OH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V High Level Output Voltage TTL Loads - - --- - - - - V Low Level Output Voltage CMOS Loads V OL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V Low Level Output Voltage TTL Loads - - --- - - - - V Input Leakage Current I I VCC or GND Quiescent Device Current ICC VCC or GND 0 6 - - 8 - 80 - 160 µA CD54HC154, CD74HC154, CD54HCT154, CD74HCT154

VIH - - 4.5 to 5.5 2-- 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 High Level Output Voltage CMOS Loads V High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads V Low Level Output Voltage TTL Loads Input Leakage Current I I VCC and GND Quiescent Device Current ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load CC (Note 3) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSVI(V) I O (mA) MIN TYP MAX MIN MAX MIN MAX HCT Input Loading Table INPUT UNIT LOADS A0 - A3 1.4 E1,E2 1.3 NOTE: Unit Load is∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Switching SpecificationsInput tr, tf = 6ns PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25oC -40oC TO 85oC -55 oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX HC TYPES Propagation Delay (Figure 1) tPLH, tPHL C L = 50pF 2 - - 175 - 220 - 265 ns Address to Output 4.5 - - 35 - 44 - 53 ns C L =15pF 5 - 14 - - - - - ns C L = 50pF 6 - - 30 - 37 - 45 ns CD54HC154, CD74HC154, CD54HCT154, CD74HCT154

E1 to Output t PLH, tPHL C L = 50pF 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns C L =15pF 5 - 14 - - - - - ns C L = 50pF 6 - - 30 - 37 - 45 ns E2 to Output t PLH, tPHL C L = 50pF 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns C L =15pF 5 - 14 - - - - - ns C L = 50pF 6 - - 30 - 37 - 45 ns Output Transition Time (Figure 1) tTLH , tTHL C L = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Input Capacitance C IN - - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 4, 5) HCT TYPES Propagation Delay (Figure 2) tPLH , tPHL Address to Output C L = 50pF 4.5 - - 35 - 44 - 53 ns C L =15pF 5 - 14 - - - - ns E1 to Output t PLH , tPHL C L = 50pF 4.5 - - 34 - 43 - 51 ns C L =15pF 5 - 14 - - - - - ns E2 to Output t PLH , tPHL C L = 50pF 4.5 - 34 - 43 - 51 ns C L =15pF 5 - 14 - - - - - ns Output Transition Time t TLH , tTHL C L = 50pF 4.5 - - 15 - 19 - 22 ns Input Capacitance C IN - - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 4, 5) C PD - 5 84 - - - - - pF NOTES: 4. CPD is used to determine the dynamic power consumption, per gate. 5. PD = VCC 2 fi(CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. Switching SpecificationsInput tr, tf = 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25oC -40oC TO 85oC -55 oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX CD54HC154, CD74HC154, CD54HCT154, CD74HCT154

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-8670101JA ACTIVE CDIP J 24 1 TBD A42 SNPB N / A for Pkg Type 5962-8682201JA ACTIVE CDIP J 24 1 TBD A42 SNPB N / A for Pkg Type CD54HC154F3A ACTIVE CDIP J 24 1 TBD A42 SNPB N / A for Pkg Type CD54HCT154F3A ACTIVE CDIP J 24 1 TBD A42 SNPB N / A for Pkg Type CD74HC154E ACTIVE PDIP N 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC154EE4 ACTIVE PDIP N 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC154EN ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC154ENE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC154M ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC154M96 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC154M96E4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC154M96G4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC154ME4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC154MG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT154E ACTIVE PDIP N 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT154EE4 ACTIVE PDIP N 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT154EN ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT154ENE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT154M ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT154M96 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT154M96E4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT154M96G4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT154ME4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT154MG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Addendum-Page 1

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC154M96 SOIC DW 24 2000 346.0 346.0 41.0 CD74HCT154M96 SOIC DW 24 2000 346.0 346.0 41.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 2

MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 N (R–PDIP–T24) PLASTIC DUAL–IN–LINE 0.020 (0,51) MIN 0.021 (0,53) 0.015 (0,38) 0.100 (2,54) 0.070 (1,78) MAX 1.222 (31,04) MAX 0.125 (3,18) MIN 0’–15’ 0.010 (0,25) NOM 0.425 (10,80) MAX Seating Plane 0.200 (5,08) MAX 0.360 (9,14) MAX 0.010 (0,25) 4040051–3/D 09/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS–010

MPDI004 – OCTOBER 1994 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NT (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 4040050/B 04/95

24 PINS SHOWN

1.425 (36,20) 1.385 0.295 (7,49) (8,00) 0.315 (35,18) 28PINS ** A MIN A MAX B MAX B MIN 0.250 (6,35) 0.280 (7,11) 0.200 (5,08) MAX DIM 24 1.230 (31,24) (32,04) 1.260 0.310 (7,87) (7,37) 0.290 B 0.125 (3,18) MIN Seating Plane 0.010 (0,25) NOM A 0.070 (1,78) MAX 0.015 (0,38) 0.021 (0,53) 0.020 (0,51) MIN 0.100 (2,54) M0.010 (0,25) 0°–15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.

MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE A C 0.018 (0,46) MIN Seating Plane 0.010 (0.25) MAX Lens Protrusion (Lens Optional) WIDENARRWIDE NARRWIDE 0.125 (3,18) MIN 4040084/C 10/97 0.012 (0,30) 0.008 (0,20) B 0.090 (2,29) 0.060 (1,53) 0.045 (1,14) 0.065 (1,65) 0.022 (0,56) 0.014 (0,36) NARR NARR WIDE ”A” DIM ”B” ”C” PINS ** MAX MIN MIN MAX MAX 0.175 (4,45) 0.140 (3,56) 0.100 (2,54) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin). D. This package can be hermetically sealed with a ceramic lid using glass frit. E. Index point is provided on cap for terminal identification.

MPDI008 – OCTOBER 1994 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

24 PIN SHOWN

0.560 (14,22) 0.520 (13,21) 0.610 (15,49) 0.590 (14,99) 524840 0.125 (3,18) MIN 2.390 (60,71) (62,23)(53,09) (51,82) 2.040 2.090 2.450 2.650 (67,31) (65,79) 2.590 0.010 (0,25) NOM 4040053/B 04/95 A 0.060 (1,52) TYP 322824 1.230 (31,24) (32,26) (36,83) (35,81) 1.410 1.4501.270 PINS ** DIM 0.015 (0,38) 0.021 (0,53) A MIN A MAX 1.650 (41,91) (40,89) 1.610 0.020 (0,51) MIN 0.200 (5,08) MAX 0.100 (2,54) M0.010 (0,25) 0°–15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-011 D. Falls within JEDEC MS-015 (32 pin only)

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