HC132A

MC74HC132A_V01 ONSEMI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

Features

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating V oltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 /C0109A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements as Defined by JEDEC Standard No. 7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

Figure 1. Pin Assignment dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or /C0071= Pb−Free Package TSSOP−14 DT SUFFIX CASE 948G SOIC−14 D SUFFIX CASE 751A HC132AG AWLYWW HC 132A ALYW/C0071 /C0071 (Note: Microdot may be in either location)

www.onsemi.com Figure 2. Logic Diagram Device Package Shipping† MC74HC132ADG SOIC−14 (Pb−Free)

55 Units / Rail

MC74HC132ADR2G SOIC−14 (Pb−Free) 2500 / Tape & Reel MC74HC132ADTG TSSOP−14 (Pb−Free)

96 Units / Rail

MC74HC132ADTR2G TSSOP−14 (Pb−Free) 2500 / Tape & Reel NLV74HC132ADG* SOIC−14 (Pb−Free) NLV74HC132ADR2G* SOIC−14 (Pb−Free) 2500 / Tape & Reel NLV74HC132ADTG* TSSOP−14 (Pb−Free) NLV74HC132ADTR2G* TSSOP−14 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable

www.onsemi.com MAXIMUM RATINGS Symbol Parameter Value Unit VCC Positive DC Supply Voltage /C00420.5 to +7.0 V VIN Digital Input Voltage /C00420.5 to VCC+0.5 V VOUT DC Output Voltage /C00420.5 to VCC+0.5 V IIK Input Diode Current /C003620 mA IOK Output Diode Current /C003620 mA IOUT DC Output Current, per Pin /C003625 mA ICC DC Supply Current, VCC and GND Pins /C003675 mA IGND DC Ground Current per Ground Pin /C003675 mA TSTG Storage Temperature Range −65 to +150 /C0095C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 /C0095C TJ Junction Temperature Under Bias +150 /C0095C /C0113JA Thermal Resistance 14 −SOIC 14−TSSOP 125 170 /C0095C/W PD Power Dissipation in Still Air at 85/C0095C SOIC TSSOP 500 450 mW MSL Moisture Sensitivity Level 1 FR Flammability Rating Oxygen Index: 30% − 35% UL 94 V0 @ 0.125 in VESD ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) /C01172000 /C0117100 /C0117500 V ILatch−Up Latch−Up Performance Above V CC and Below GND at 85/C0095C (Note 4) /C0036300 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22 −A114−A. 2. Tested to EIA/JESD22 −A115−A. 3. Tested to JESD22 −C101−A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit ÎÎÎÎÎ ÎÎÎÎÎ VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage (Referenced to GND) ÎÎÎÎ ÎÎÎÎ 2.0 ÎÎÎÎ ÎÎÎÎ 6.0 ÎÎÎ ÎÎÎ V ÎÎÎÎÎ ÎÎÎÎÎ VIN, VOUT ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Voltage, Output Voltage (Referenced to GND) ÎÎÎÎ ÎÎÎÎ 0 ÎÎÎÎ ÎÎÎÎ VCC ÎÎÎ ÎÎÎ V ÎÎÎÎÎ ÎÎÎÎÎ TA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Operating Temperature, All Package Types ÎÎÎÎ ÎÎÎÎ /C004255 ÎÎÎÎ ÎÎÎÎ /C0041125 ÎÎÎ ÎÎÎ /C0095C ÎÎÎÎÎ ÎÎÎÎÎ tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Rise and Fall Time (Figure 3) ÎÎÎÎ ÎÎÎÎ − ÎÎÎÎ ÎÎÎÎ No Limit (Note 5) ÎÎÎ ÎÎÎ ns 5. When V IN /C0088 0.5 VCC, ICC >> quiescent current. 6. Unused inputs may not be left open. All inputs must be tied to a high −logic voltage level or a low−logic input voltage level. DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter Test Conditions V /C004255/C0095C to 25/C0095C /C011885/C0095C /C0118125/C0095C Unit ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VT+max ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Maximum Positive−Going Input Threshold Voltage (Figure 5) ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOUT = 0.1 V |IOUT| /C0118 20 /C0109A ÎÎÎ ÎÎÎ ÎÎÎ 2.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 1.5 3.15 4.2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1.5 3.15 4.2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1.5 3.15 4.2 ÎÎ ÎÎ ÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VT+min ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Minimum Positive−Going Input Threshold Voltage (Figure 5) ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOUT = 0.1 V |IOUT| /C0118 20 /C0109A ÎÎÎ ÎÎÎ ÎÎÎ 2.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 1.0 2.3 3.0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.95 2.25 2.95 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.95 2.25 2.95 ÎÎ ÎÎ ÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VT–max ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Maximum Negative−Going Input Threshold Voltage (Figure 5) ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOUT = VCC – 0.1 V |IOUT| /C0118 20 /C0109A ÎÎÎ ÎÎÎ ÎÎÎ 2.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 0.9 2.0 2.6 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.95 2.05 2.65 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.95 2.05 2.65 ÎÎ ÎÎ ÎÎ V

www.onsemi.com DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed LimitVCC Symbol Unit/C0118125/C0095C/C011885/C0095C/C004255/C0095C to 25/C0095CVTest ConditionsParameter ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VT–min ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Minimum Negative−Going Input Threshold Voltage (Figure 5) ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOUT = VCC – 0.1 V |IOUT| /C0118 20 /C0109A ÎÎÎ ÎÎÎ ÎÎÎ 2.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 0.3 0.9 1.2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.3 0.9 1.2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.3 0.9 1.2 ÎÎ ÎÎ ÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VHmax (Note 7) ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Maximum Hysteresis Voltage (Figure 5) ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOUT = 0.1 V or VCC – 0.1 V |IOUT| /C0118 20 /C0109A ÎÎÎ ÎÎÎ ÎÎÎ 2.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 1.2 2.25 3.0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1.2 2.25 3.0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1.2 2.25 3.0 ÎÎ ÎÎ ÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VHmin (Note 7) ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Minimum Hysteresis Voltage (Figure 5) ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VOUT = 0.1 V or VCC – 0.1 V |IOUT| /C0118 20 /C0109A ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 0.2 0.4 0.5 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.2 0.4 0.5 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.2 0.4 0.5 ÎÎ ÎÎ ÎÎ ÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VOH ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Minimum High−Level Output Voltage ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VIN /C0118 VT−min or VT+max |IOUT| /C0118 20 /C0109A ÎÎÎ ÎÎÎ ÎÎÎ 2.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 1.9 4.4 5.9 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1.9 4.4 5.9 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1.9 4.4 5.9 ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VIN /C0118 −VT−min or VT+max |IOUT| /C0118 4.0 mA |IOUT| /C0118 5.2 mA ÎÎÎ ÎÎÎ ÎÎÎ 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 3.98 5.48 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 3.84 5.34 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 3.7 5.2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VOL ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Maximum Low−Level Output Voltage ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VIN ≥ VT+max |IOUT| /C0118 20 /C0109A ÎÎÎ ÎÎÎ ÎÎÎ 2.0 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 0.1 0.1 0.1 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.1 0.1 0.1 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.1 0.1 0.1 ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VIN ≥ VT+max |I OUT| /C0118 4.0 mA |IOUT| /C0118 5.2 mA ÎÎÎ ÎÎÎ ÎÎÎ 4.5 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 0.26 0.26 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.33 0.33 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.4 0.4 ÎÎÎÎ ÎÎÎÎ IIN ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Maximum Input Leakage Current ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VIN = VCC or GND ÎÎÎ ÎÎÎ 6.0 ÎÎÎÎÎ ÎÎÎÎÎ /C00360.1 ÎÎÎÎ ÎÎÎÎ /C00361.0 ÎÎÎÎ ÎÎÎÎ /C00361.0 ÎÎ ÎÎ /C0109A ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ICC ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Maximum Quiescent Supply Current (per Package) ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ VIN = VCC or GND IOUT = 0 /C0109A ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 6.0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 1.0 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ /C0109A 7. V Hmin /C0117 (VT+min) /C0042 (VT−max); VHmax = (VT+max) /C0041 (VT−min).

SOIC−14 NB CASE 751A−03 ISSUE L DATE 03 FEB 2016SCALE 1:1 GENERIC MARKING DIAGRAM* XXXXXXXXXG AWLYWW XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week G = Pb −Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ /C0071”, may or may not be present. STYLES ON PAGE 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. H 14 8 M0.25 B M C h X 45 SEATING PLANE A M /C0095 SAM0.25 B SC b13X B A E D e DETAIL A L DETAIL A DIM MIN MAX MIN MAX INCHESMILLIMETERS D 8.55 8.75 0.337 0.344 E 3.80 4.00 0.150 0.157 A 1.35 1.75 0.054 0.068 b 0.35 0.49 0.014 0.019 L 0.40 1.25 0.016 0.049 e 1.27 BSC 0.050 BSC A3 0.19 0.25 0.008 0.010 A1 0.10 0.25 0.004 0.010 M 0 7 0 7 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 6.50 14X 0.58 14X 1.18 1.27 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 0.10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98ASB42565BDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2SOIC−14 NB © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 7: PIN 1. ANODE/CATHODE 2. COMMON ANODE 3. COMMON CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. ANODE/CATHODE 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. COMMON CATHODE 12. COMMON ANODE 13. ANODE/CATHODE 14. ANODE/CATHODE STYLE 5: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 6: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 1: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 3: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 4: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 8: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE STYLE 2: CANCELLED ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98ASB42565BDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2SOIC−14 NB © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

TSSOP−14 WB CASE 948G ISSUE C DATE 17 FEB 2016 SCALE 2:1 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ /C0071”, may or may not be present. DIM MIN MAX MIN MAX INCHESMILLIMETERS A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. /C0095/C0095/C0095/C0095 SU0.15 (0.006) T 2X L/2 SUM0.10 (0.004) V ST L −U− SEATING PLANE 0.10 (0.004) −T− ÇÇÇ ÇÇÇ SECTION N−N DETAIL E J J1 K ÉÉÉ ÉÉÉ DETAIL E F M −W− 0.25 (0.010) 814 PIN 1 IDENT. HG A D C B SU0.15 (0.006) T −V− 14X REFK N N GENERIC MARKING DIAGRAM* XXXX XXXX ALYW/C0071 /C0071 A = Assembly Location L = Wafer Lot Y = Year W = Work Week /C0071 = Pb−Free Package 7.06 14X 0.36 14X 1.26 0.65 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT (Note: Microdot may be in either location) MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98ASH70246ADOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1TSSOP−14 WB © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

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