SN54AHCT08_V01 TI | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 39
Technical content
SNx4AHCT08 Quadruple 2-Input Positive-AND Gates
1 Features
- Inputs are TTL-voltage compatible
- Latch-up performance exceeds 250 mA per JESD 17
- ESD protection exceeds JESD 22: – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
- On products compliant to MIL-PRF-38535, All parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
2 Applications
- Servers
- Network switches
- PCs and notebooks
- Electronic points-of-sale
3 Description
The SNx4AHCT08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean function Y A B or Y A B/c61 /c180 /c61 /c43 in positive logic. Package Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SNx4AHCT08 D (SOIC, 14) 8.65 mm × 3.91 mm DB (SSOP, 14) 6.20 mm × 5.30 mm NS (SOP, 14) 12.60 mm × 5.30 mm PW (TSSOP, 14) 5.00 mm × 4.40 mm RGY (VQFN, 14) 3.50 mm × 3.50 mm J (CDIP, 14) 19.56 mm × 6.67 mm W (CFP, 14) 9.21 mm × 5.97 mm DGV (TVSOP, 14) 3.60 mm × 4.40 mm N (PDIP, 14) 19.30 mm × 6.35 mm FK (LCCC, 20) 8.89 mm × 8.89 mm BQA (WQFN, 14) 3.00 mm × 2.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. A B Y Simplified Schematic SN54AHCT08, SN74AHCT08 SCLS237O – OCTOBER 1995 – REVISED MAY 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
10.1 Receiving Notification of Documentation Updates..12
11 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision N (September 2015) to Revision O (May 2023) Page Changes from Revision M (July 2014) to Revision N (September 2015) Page Changes from Revision L (October 1995) to Revision M (July 2014) Page
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and SN54AHCT08, SN74AHCT08 SCLS237O – OCTOBER 1995 – REVISED MAY 2023 www.ti.com
2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: SN54AHCT08 SN74AHCT08
5 Pin Configuration and Functions
Figure 5-1. SN54AHCT08 J or W Package, 14-Pin CDIP or CFP SN74AHCT08 D, DB, DGV, N, NS, or PW Package, 14-Pin SOIC, SSOP, TVSOP, PDIP, SO, or TSSOP (Top View) 1 14 7 8 1 1 V GND CC Figure 5-2. SN7AHCT08 RGY or BQA Package, 14- Pin VQFN or WQFN (Top View) 3 2 1 20 19 9 10 11 12 13 NC NC NC NC 1B 1A NC 3Y 3A V 4B GNDNC CC NC − No internal connection Figure 5-3. SN54HACT08 FK Package, 20-Pin LCCC (Top View) Table 5-1. Pin Functions PIN TYPE (1) DESCRIPTION NAME SN74AHCT08 SN54AHCT08 D, DB, DGV, N, NS, PW RGY, BQA J, W FK 1A 1 1 1 2 I 1A Input 1B 2 2 2 3 I 1B Input 1Y 3 3 3 4 O 1Y Output 2A 4 4 4 6 I 2A Input 2B 5 5 5 8 I 2B Input 2Y 6 6 6 9 O 2Y Output 3Y 8 8 8 12 O 3Y Output 3A 9 9 9 13 I 3A Input 3B 10 10 10 14 I 3B Input 4Y 11 11 11 16 O 4Y Output 4A 12 12 12 18 I 4A Input 4B 13 13 13 19 I 4B Input GND 7 7 7 10 — Ground Pin www.ti.com SN54AHCT08, SN74AHCT08 SCLS237O – OCTOBER 1995 – REVISED MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN54AHCT08 SN74AHCT08
Table 5-1. Pin Functions (continued) PIN TYPE (1) DESCRIPTION NAME SN74AHCT08 SN54AHCT08 D, DB, DGV, N, NS, PW RGY, BQA J, W FK NC — — — — No Connection VCC 14 14 14 20 — Power Pin (1) I = input, O = output SN54AHCT08, SN74AHCT08 SCLS237O – OCTOBER 1995 – REVISED MAY 2023 www.ti.com
4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: SN54AHCT08 SN74AHCT08
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI Input voltage range(2) –0.5 7 V VO Output voltage range(2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA Continuous current through VCC or GND ±50 mA Tstg Storage temperature range –65 150 °C TJ Junction temperature 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1) SN54AHCT08 SN74AHCT08 UNIT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC V IOH High-level output current –8 –8 mA IOL Low-level output current 8 8 mA Δt/Δv Input transition rise or fall rate 20 20 ns/V TA Operating free-air temperature –55 125 –40 125 °C (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI Application Report, Implications of Slow or Floating CMOS Inputs, (SCBA004). www.ti.com SN54AHCT08, SN74AHCT08 SCLS237O – OCTOBER 1995 – REVISED MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: SN54AHCT08 SN74AHCT08
6.4 Thermal Information
THERMAL METRIC(1) SN74AHCT08 UNITD (SOIC) DB (SSOP) DGV (TVSOP) N (PDIP) BQA (WQFN)
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, (SPRA953).
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54AHCT08 SN74AHCT08 UNIT MIN TYP MAX MIN MAX MIN MAX VOH IOH = –50 µA 4.5 V 4.4 4.5 4.4 4.4 V IOH = –8 mA 3.94 3.8 3.8 VOL IOL = 50 µA 4.5 V 0.1 0.1 0.1 V IOL = 8 mA 0.36 0.44 0.44 II VI = 5.5 V or GND 0 V to ICC VI = VCC or GND, IO = 0 5.5 V 2 20 20 µA ΔICC (2) One input at 3.4 V, Other inputs at VCC or GND 5.5 V 1.35 1.5 1.5 mA Ci VI = VCC or GND 5 V 4 10 10 pF (1) On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. (2) This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. 6.6 Switching Characteristics, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C SN54AHCT08 SN74AHCT08 UNIT MIN TYP MAX MIN MAX MIN MAX tPLH A or B Y CL = 15 pF ns tPLH A or B Y CL = 50 pF 5.5 7.9 1 9 1 9 ns tPHL 5.5 7.9 1 9 1 9 (1) On products compliant to MIL-PRF-38535, this parameter is not production tested. SN54AHCT08, SN74AHCT08 SCLS237O – OCTOBER 1995 – REVISED MAY 2023 www.ti.com
6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: SN54AHCT08 SN74AHCT08
6.7 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C(1) PARAMETER SN74AHCT08 UNIT MIN TYP MAX VOL(P) Quiet output, maximum dynamic VOL 0.4 0.8 V VOL(V) Quiet output, minimum dynamic VOL –0.4 –0.8 V VOH(V) Quiet output, minimum dynamic VOH 4.4 V VIH(D) High-level dynamic input voltage 2 V VIL(D) Low-level dynamic input voltage 0.8 V (1) Characteristics are for surface-mount packages only.
6.8 Operating Characteristics
VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load, f = 1 MHz 18 pF
6.9 Typical Characteristics
Temperature (qC) TPD (ns) -100 -50 0 50 100 150 0.5 1.5 2.5 3.5 4.5 D001 TPD in ns Figure 6-1. TPD vs Temperature www.ti.com SN54AHCT08, SN74AHCT08 SCLS237O – OCTOBER 1995 – REVISED MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN54AHCT08 SN74AHCT08
7 Parameter Measurement Information
50% VCC 3 V 3 V 0 V 0 V th tsu VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Data Input tPLH tPHL tPHL tPLH VOH VOH VOL VOL 3 V 0 V 50% VCC50% VCC Input Out-of-Phase Output In-Phase Output Timing Input 50% VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Control Output Waveform 1 S1 at VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ ≈ VCC 0 V 50% VCC VOL + 0.3 V 50% VCC ≈ 0 V 3 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC TEST S1 3 V 0 V tw VOLTAGE WAVEFORMS PULSE DURATION Input NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output i s low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the fol lowing characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, t r ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transi tion per measurement. E. All parameters and waveforms are not applicable to all dev ices. From Output Under Test CL (see Note A) LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC RL = 1 kΩ GND From Output Under Test CL (see Note A) Test Point LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS Open VOH − 0.3 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V1.5 V 1.5 V Figure 7-1. Load Circuit and Voltage Waveforms SN54AHCT08, SN74AHCT08 SCLS237O – OCTOBER 1995 – REVISED MAY 2023 www.ti.com
8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: SN54AHCT08 SN74AHCT08
8 Detailed Description
8.1 Overview
The SNx4AHCT08 devices are quadruple 2-input positive-AND gates with low drive that will produce slow rise and fall times. This slow transition reduces ringing on the output signal. The device has TTL inputs that allow up translation from 3.3 V to 5 V. The inputs are high impedance when VCC = 0 V.
8.2 Functional Block Diagram
A B Y
8.3 Feature Description
- Slow rise and fall time on outputs allow for low-noise outputs
- TTL inputs allow up translation from 3.3 V to 5 V
8.4 Device Functional Modes
Table 8-1 is the function table for the SNx4AHCT08. Table 8-1. Function Table (Each Gate) INPUTS OUTPUT YA B H H H L X L X L L www.ti.com SN54AHCT08, SN74AHCT08 SCLS237O – OCTOBER 1995 – REVISED MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN54AHCT08 SN74AHCT08
9 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
9.1 Application Information
The SNx4AHCT08 devices are low-drive CMOS devices that can be used for a multitude of bus-interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The TTL inputs can except voltages down to 3.3 V and translate up to 5 V.
9.2 Typical Application
0.1 F µ
5 V Regulated
3.3-V Bus Driver Figure 9-1. Typical Application Diagram
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads, so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
- Recommended input conditions
- Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
- Specified High and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
- Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC 2. Recommend output conditions
- Load currents should not exceed 25 mA per output and 50 mA total for the part
- Outputs should not be pulled above VCC SN54AHCT08, SN74AHCT08 SCLS237O – OCTOBER 1995 – REVISED MAY 2023 www.ti.com
10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: SN54AHCT08 SN74AHCT08
9.2.3 Application Curves
Figure 9-2. Switching Characteristics Comparison
9.3 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each V CC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple V CC pins, 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results.
9.4 Layout
9.4.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 9-3 are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V CC; whichever makes more sense or is more convenient. It is generally acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the IOs, so they cannot float when disabled.
9.4.2 Layout Example
Figure 9-3. Layout Diagram www.ti.com SN54AHCT08, SN74AHCT08 SCLS237O – OCTOBER 1995 – REVISED MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN54AHCT08 SN74AHCT08
10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. SN54AHCT08, SN74AHCT08 SCLS237O – OCTOBER 1995 – REVISED MAY 2023 www.ti.com
12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: SN54AHCT08 SN74AHCT08
www.ti.com 12-May-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 5962-9682101Q2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962- 9682101Q2A SNJ54AHCT 08FK Samples 5962-9682101QCA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9682101QC A SNJ54AHCT08J Samples 5962-9682101QDA ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9682101QD A SNJ54AHCT08W Samples 5962-9682101VDA ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9682101VD A SNV54AHCT08W Samples SN74AHCT08BQAR ACTIVE WQFN BQA 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT08 Samples SN74AHCT08DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB08 Samples SN74AHCT08DGVR ACTIVE TVSOP DGV 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB08 Samples SN74AHCT08DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT08 Samples SN74AHCT08DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT08 Samples SN74AHCT08N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 SN74AHCT08N Samples SN74AHCT08NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT08 Samples SN74AHCT08PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 HB08 Samples SN74AHCT08PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB08 Samples SN74AHCT08RGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 HB08 Samples SNJ54AHCT08FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962- 9682101Q2A SNJ54AHCT 08FK Samples Addendum-Page 1
www.ti.com 12-May-2023 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SNJ54AHCT08J ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9682101QC A SNJ54AHCT08J Samples SNJ54AHCT08W ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9682101QD A SNJ54AHCT08W Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
www.ti.com 12-May-2023 OTHER QUALIFIED VERSIONS OF SN54AHCT08, SN54AHCT08-SP, SN74AHCT08 :
- Catalog : SN74AHCT08 , SN54AHCT08
- Enhanced Product : SN74AHCT08-EP , SN74AHCT08-EP
- Military : SN54AHCT08
- Space : SN54AHCT08-SP NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Enhanced Product - Supports Defense, Aerospace and Medical Applications
- Military - QML certified for Military and Defense Applications
- Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3
PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHCT08BQAR WQFN BQA 14 3000 210.0 185.0 35.0 SN74AHCT08DBR SSOP DB 14 2000 356.0 356.0 35.0 SN74AHCT08DGVR TVSOP DGV 14 2000 356.0 356.0 35.0 SN74AHCT08DR SOIC D 14 2500 340.5 336.1 32.0 SN74AHCT08DR SOIC D 14 2500 356.0 356.0 35.0 SN74AHCT08NSR SO NS 14 2000 356.0 356.0 35.0 SN74AHCT08PWR TSSOP PW 14 2000 364.0 364.0 27.0 SN74AHCT08PWR TSSOP PW 14 2000 356.0 356.0 35.0 SN74AHCT08PWRG4 TSSOP PW 14 2000 356.0 356.0 35.0 SN74AHCT08RGYR VQFN RGY 14 3000 356.0 356.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2023 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) 5962-9682101Q2A FK LCCC 20 1 506.98 12.06 2030 NA 5962-9682101QDA W CFP 14 1 506.98 26.16 6220 NA 5962-9682101VDA W CFP 14 1 506.98 26.16 6220 NA SN74AHCT08N N PDIP 14 25 506 13.97 11230 4.32 SN74AHCT08N N PDIP 14 25 506 13.97 11230 4.32 SNJ54AHCT08FK FK LCCC 20 1 506.98 12.06 2030 NA SNJ54AHCT08W W CFP 14 1 506.98 26.16 6220 NA Pack Materials-Page 3
www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightBQA 14 PLASTIC QUAD FLATPACK - NO LEAD2.5 x 3, 0.5 mm pitch 4227145/A
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4224636/A 11/2018 www.ti.com WQFN - 0.8 mm max height PLASTIC QUAD FLAT PACK-NO LEAD BQA0014A A 0.08 C
0.1 C A B
0.05 C B SYMM SYMM 2.6 2.4 3.1 2.9PIN 1 INDEX AREA 0.8 0.7 0.05 0.00 SEATING PLANE C 1.1 0.9 1.6 1.4 2X 0.5 8X 0.5 14X 0.3 0.2 14X 0.5 0.3 (0.2) TYP 7 8 141 PIN 1 ID (OPTIONAL)
NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4224636/A 11/2018 www.ti.com WQFN - 0.8 mm max heightBQA0014A PLASTIC QUAD FLAT PACK-NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X (1) (1.5)2X (0.5) 8X (0.5) (2) 2X (0.5) 14X (0.25) 14X (0.6) (2.3) (2.8) (Ø0.2) VIA TYP (R0.05) TYP 7 8
0.07 MAX
0.07 MIN
(PREFERRED) SOLDER MASK DEFINED
NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4224636/A 11/2018 www.ti.com WQFN - 0.8 mm max heightBQA0014A PLASTIC QUAD FLAT PACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 88% PRINTED COVERAGE BY AREA SCALE: 20X SYMM SYMM (0.95) (1.38) 8X (0.5) (2) 2X (0.5) 14X (0.25) 14X (0.6) (2.3) (2.8) (R0.05) TYP 7 8
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194
www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. LCCC - 2.03 mm max heightFK 20 LEADLESS CERAMIC CHIP CARRIER8.89 x 8.89, 1.27 mm pitch 4229370\\/A\\
www.ti.com PACKAGE OUTLINE C 14X .008-.014 [0.2-0.36]TYP -150 AT GAGE PLANE -.314 .308 -7.97 7.83 [ ] 14X -.026 .014 -1.65 1.15 [ ] .2 MAX TYP [5.08] .13 MIN TYP [3.3] TYP-.060 .015 -1.52 0.38 [ ] 4X .005 MIN [0.13] 12X .100 [2.54] .015 GAGE PLANE [0.38] A -.785 .754 -19.9419.15 [ ] B -.283 .245 -7.19 6.22 [ ] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. 7 8 PIN 1 ID (OPTIONAL) SCALE 0.900 SEATING PLANE .010 [0.25] C A B
www.ti.com EXAMPLE BOARD LAYOUT ALL AROUND [0.05] MAX .002 .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING METAL (.063) [1.6] (R.002 ) TYP [0.05] 14X ( .039) [1] ( .063) [1.6] 12X (.100 ) [2.54] (.300 ) TYP [7.62] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X SEE DETAIL A SEE DETAIL B SYMM SYMM 7 8 DETAIL A SCALE: 15X SOLDER MASK OPENING METAL DETAIL B 13X, SCALE: 15X
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01
28 PINS SHOWN
8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150
IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated