H8020S

H838024_10 RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1.1 Overview
• 1.2 Internal Block Diagram
• 1.3 Pin Arrangement and Functions
• 1.3.1 Pin Arrangement
• 1.3.2 Pin Functions
• 2.1 Overview
• 2.1.1 Features
• 2.1.2 Address Space
• 2.1.3 Register Configuration
• 2.2.1 General Registers
• 2.2.2 Control Registers
• 2.2.3 Initial Register Values
• 2.3 Data Formats
• 2.3.1 Data Formats in General Registers
• 2.3.2 Memory Data Formats
• 2.4.1 Addressing Modes
• 2.4.2 Effective Address Calculation
• 2.5 Instruction Set
• 2.5.1 Data Transfer Instructions
• 2.5.2 Arithmetic Operations
• 2.5.3 Logic Operations
• 2.5.4 Shift Operations
• 2.5.5 Bit Manipulations
• 2.5.6 Branching Instructions
• 2.5.7 System Control Instructions
• 2.5.8 Block Data Transfer Instruction
• 2.6 Basic Operational Timing
• 2.6.1 Access to On-Chip Memory (RAM, ROM)
• 2.6.2 Access to On-Chip Peripheral Modules
• 2.7 CPU States
• 2.7.1 Overview
• 2.7.2 Program Execution State

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1 st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry.

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part . 4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, an d “Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. “Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. “High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. “Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Fur ther, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renes as Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority- owned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

H8/38024, H8/38024S, H8/38024R, H8/38124 Group Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series Rev.8.00 2010.03 H8/38024 Group H8/38024 H8/38024R Group H8/38024R H8/38023 H8/38022 H8/38124 Group H8/38124 H8/38021 H8/38123 H8/38020 H8/38122 H8/38024S Group H8/38024S H8/38121 H8/38022S H8/38120 H8/38021S H8/38020S H8/38000S

Rev. 8.00 Mar. 09, 2010 Page ii of xx REJ09B0042-0800 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Notes regarding these materials

Rev. 8.00 Mar. 09, 2010 Page iii of xx REJ09B0042-0800 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. ⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. ⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. ⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. ⎯ When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ⎯ The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products.

Rev. 8.00 Mar. 09, 2010 Page iv of xx REJ09B0042-0800 Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules

• CPU and System-Control Modules
• On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix
• Product Codes, Package Dimensions, etc. 10. Main Revisions for This Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual.

Rev. 8.00 Mar. 09, 2010 Page v of xx REJ09B0042-0800 Preface The H8/38024 Group is a single-chip microcomputer built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. The H8/38024 Group incorporates peripheral functions including ROM, RAM, timer, serial communications interface (SCI), 10-bit PWM, A/D converter, LCD controller/driver, and I/O ports. It is a microcomputer allowing the implementation of a sophisticated control system. Versions are available with types of internal ROM: flash memory (F-ZTAT™ *1) and PROM (ZTAT™ *2). This makes it possible to design application products with a great deal of specification fluidity, and allows for rapid and flexible response to contingencies arising between the initial stages of production and full-scale production. Below is a table listing the product specifications for each group. Notes: 1. F-ZTAT is a trademark of Renesas Technology Corp. 2. ZTAT is a trademark of Renesas Technology Corp.

Rev. 8.00 Mar. 09, 2010 Page vi of xx REJ09B0042-0800 Specifications H8/38024 Group H8/38024R Group H8/38024S Group H8/38124 Group Item ZTAT Mask Flash Flash Mask Flash Mask Memory ROM 32 Kbytes 8 Kbytes to

32 Kbytes

32 Kbytes 32 Kbytes 8 Kbytes to

16 Kbytes/

8 Kbytes

1 Kbyte

1 Kbyte 1 Kbyte 512 bytes

1 Kbyte 512 bytes

4.5 to 5.5 V 16 MHz 16 MHz — — — 20 MHz 20 MHz 2.7 to 5.5 V 10 MHz 10 MHz — — — 20 MHz 20 MHz 1.8 to 5.5 V 4 MHz 4 MHz — — — — — 2.7 to 3.6 V — — 10 MHz 10 MHz 10 MHz — — Operating voltage and operating frequency I/O ports Input only 9 9 9 9 9 9 9 Output only 6 6 6 6 6 6 6 I/O 51 51 51 51 51 50 50 Timers Clock (timer A) 1 1 1 1 1 1 1 Reload (timer C) 1 1 1 1 1 1 1 Compare (timer F) 1 1 1 1 1 1 1 Capture (timer G) 1 1 1 1 1 1 1 AEC 1 1 1 1 1 1 1 WDT 1 1 1 1 1 WDT (discrete) 1 1 SCI UART/Synchronous 1 1 1 1 1 1 1 A-D (resolution × input channels) 10 × 8 10 × 8 10 × 8 10 × 8 10 × 8 10 × 8 10 × 8 LCD seg 32 32 32 32 32 32 32 com 4 4 4 4 4 4 4 External interrupt (internal wakeup) POR (power-on reset) — — — — — 1 1 LVD (low-voltage detection circuit) — — — — — 1 1 Package FP-80A FP-80A FP-80A FP-80A FP-80A FP-80A FP-80A FP-80B FP-80B FP-80B FP-80B TFP-80C TFP-80C TFP-80C TFP-80C TFP-80C TFP-80C TFP-80C TLP85V TLP85V TLP85V Chip Chip Chip Chip Operating temperature Standard specifications: –20 to 75 °C, WTR: –40 to 85°C Please use R version.

Rev. 8.00 Mar. 09, 2010 Page vii of xx REJ09B0042-0800 Target Readers: This manual is designed for use by people who design application systems using the H8/38024 Group, H8/38024S Group, H8/38024R Group, and H8/38124 Group. To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. Purpose: This manual provides the information of the hardware functions and electrical characteristics of the H8/38024 Group, H8/38024S Group, H8/38024R Group, and H8/38124 Group. The H8/300L Series Software Manual contains detailed information of executable instructions. Please read the Software Manual together with this manual. How to Use the Book:

• To understand general functions → Read the manual from the beginning. The manual explains the CPU, system control functions, peripheral functions and electrical characteristics in that order.
• To understanding CPU functions → Refer to the separate H8/300L Series Software Manual. Explanatory Note: Bit sequence: upper bit at left, and lower bit at right List of Related Documents: The latest documents are available on our Web site. Please make sure that you have the latest version. (http://www.renesas.com/)
• User Manual for H8/38024 Group, H8/38024S Group, H8/38024R Group, and H8/38124 Group Name of Document Document No. H8/38024 Group, H8/38024S Group, H8/38024R Group, H8/38124 Group Hardware Manual This manual H8/300L Series Software Manual REJ09B0214
• User's Manual for Development Tools Name of Document Document No. H8S, H8/300 Series, C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual REJ10B2039 H8S, H8/300 Series Simulator/Debugger User’s Manual REJ10B0211 High-Performance Embedded Workshop User’s Manual REJ10J2037

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• Application Note Name of Document Document No. H8S, H8/300 Series C/C++ Compiler Package Application Note REJ05B0464 Notes: The following limitations apply to H8/38024, H8/38024R, and H8/38124 programming and debugging when the on-chip emulator is used. 1. Pin 95 is not available because it is used exclusively by the on-chip emulator. 2. Pins 33, 34, and 35 are unavailable for use. In order to use these pins additional hardware must be mounted on the user board. 3. The address range H'7000 to H'7FFF is used by the on-chip emulator and is unavailable to the user. 4. The address range H'F780 to H'FB7F must not be accessed under any circumstances. 5. When the on-chip emulator is being used, pin 95 is I/O, pins 33 and 34 are input, and pin 35 is output. 6. When using the on-chip emulator, pins OSC1 and OSC2 should be connected to an oscillator, or an external clock should be supplied to pin OSC1, even if the on-chip oscillator of the H8/38124 Group is selected. All trademarks and registered trademarks are the property of their respective owners.

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4.5.2 Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator

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16.1 H8/38024 Group ZTAT Version and Mask ROM Version Absolute Maximum

16.3 H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT Version Absolute

16.4 H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT Version Electrical

16.7 Absolute Maximum Ratings of H8/38124 Group F-ZTAT Version and Mask ROM

16.8 Electrical Characteristics of H8/38124 Group F-ZTAT Version and Mask ROM

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Rev. 8.00 Mar. 09, 2010 Page 1 of 658 REJ09B0042-0800 Section 1 Overview

1.1 Overview

The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/38024 Group, H8/38024S Group, and H8/38124 Group comprise single-chip microcomputers equipped with a LCD (Liquid Crystal Display) controller/driver. Other on-chip peripheral functions include six timers, a two-channel 10-bit pulse width modulator (PWM), a serial communication interface, and an A/D converter. Together, these functions make the H8/38024 Group, H8/38024S Group, and H8/38124 Group ideally suited for embedded applications in systems requiring low power consumption and LCD display. Models in the H8/38024 Group, H8/38024S Group, and H8/38124 Group are the H8/38024, H8/38024S, and H8/38124 with on-chip 32-Kbyte ROM and 1-Kbyte RAM, the H8/38023, H8/38023S, and H8/38123 with on-chip 24-Kbyte ROM and 1-Kbyte RAM, the H8/38022, H8/38022S, and H8/38122 with on-chip 16-Kbyte ROM and 1-Kbyte RAM, the H8/38021, H8/38021S, and H8/38121 with 12-Kbyte ROM and 512 byte RAM, and the H8/38020, H8/38020S, and H8/38120 with 8-Kbyte ROM and 512 byte RAM. The H8/38024 is also available in a ZTAT™ * 1 version with on-chip PROM which can be programmed as required by the user. The H8/38024 is also available in F-ZTAT™ *2 versions with on-chip flash memory which can be reprogrammed on board. The H8/38124 is also available in an F-ZTAT™ version with on-chip flash memory that can be programmed on board. Table 1.1 summarizes the features of the H8/38024 Group, H8/38024S Group, and H8/38124 Group. Notes: 1. ZTAT (Zero Turn Around Time) is a trademark of Renesas Technology Corp. 2. F-ZTAT is a trademark of Renesas Technology Corp.

Rev. 8.00 Mar. 09, 2010 Page 2 of 658 REJ09B0042-0800 Table 1.1 Features Item Specification CPU High-speed H8/300L CPU

• General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers)
• Operating speed ⎯ Max. operating speed: 8 MHz (5 MHz for HD64F38024 and H8/38024S Group) ⎯ Add/subtract: 0.25 µs (operating at 8 MHz), 0.4 μs (operating at φ =

5 MHz)

⎯ Multiply/divide: 1.75 µs (operating at 8 MHz), 2.8 μs (operating at φ = ⎯ Can run on 32.768 kHz or 38.4 kHz subclock (32.768 kHz only for H8/38124 Group)

• Instruction set compatible with H8/300 CPU ⎯ Instruction length of 2 bytes or 4 bytes ⎯ Basic arithmetic operations between registers ⎯ MOV instruction for data transfer between memory and registers
• Typical instructions ⎯ Multiply (8 bits × 8 bits) ⎯ Divide (16 bits ÷ 8 bits) ⎯ Bit accumulator ⎯ Register-indirect designation of bit position Interrupts 22 interrupt sources
• 13 external interrupt sources (IRQ 4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, IRQAEC)
• 9 internal interrupt sources

Rev. 8.00 Mar. 09, 2010 Page 3 of 658 REJ09B0042-0800 Item Specification Clock pulse generators Two on-chip clock pulse generators

• System clock pulse generator: 1.0 to 16 MHz: H8/38024 Group 1.0 to 10 MHz: HD64F38024, HD64F38024R, and H8/38024S Group 2.0 to 20 MHz: H8/38124 Group
• Subclock pulse generator: 32.768 kHz, 38.4 kHz* (* does not apply to H8/38124 Group) H8/38124 Group equipped with on-chip oscillator Power-down modes Seven power-down modes
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
• Standby mode
• Watch mode
• Subsleep mode
• Subactive mode
• Active (medium-speed) mode Memory Large on-chip memory
• H8/38024, H8/38024S, and H8/38124: 32-Kbyte ROM, 1-Kbyte RAM
• H8/38023, H8/38023S, and H8/38123: 24-Kbyte ROM, 1-Kbyte RAM
• H8/38022, H8/38022S, and H8/38122: 16-Kbyte ROM, 1-Kbyte RAM
• H8/38021, H8/38021S, and H8/38121: 12-Kbyte ROM, 512 byte RAM
• H8/38020, H8/38020S, and H8/38120: 8-Kbyte ROM, 512 byte RAM I/O ports 66 pins
• 51 I/O pins (50 pins on H8/38124 Group)
• 9 input pins
• 6 output pins

Rev. 8.00 Mar. 09, 2010 Page 4 of 658 REJ09B0042-0800 Item Specification Timers Six on-chip timers

• Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the system clock (φ)* and four clock signals divided from the watch clock (φw)*
• Asynchronous event counter: 16-bit timer ⎯ Count-up timer able to count asynchronous external events independently of the MCU's internal clocks Asynchronous external events can be counted (both rising and falling edge detection possible)
• Timer C: 8-bit timer ⎯ Count-up/down timer with selection of seven internal clock signals or event input from external pin ⎯ Auto-reloading
• Timer F: 16-bit timer ⎯ Can be used as two independent 8-bit timers ⎯ Count-up timer with selection of four internal clock signals or event input from external pin ⎯ Provision for toggle output by means of compare-match function
• Timer G: 8-bit timer ⎯ Count-up timer with selection of four internal clock signals ⎯ Incorporates input capture function (built-in noise canceler)
• Watchdog timer ⎯ Reset signal generated by overflow of 8-bit counter

Rev. 8.00 Mar. 09, 2010 Page 5 of 658 REJ09B0042-0800 Item Specification Serial communication interface

• SCI3: 8-bit synchronous/asynchronous serial interface 10-bit PWM Pulse-division PWM output for reduced ripple
• Can be used as a 10-bit D/A converter by connecting to an external low- pass filter. A/D converter Successive approximations using a resistance ladder
• 8-channel analog input pins
• Conversion time: 31/ φ or 62/φ per channel LCD controller/ driver LCD controller/driver equipped with a maximum of 32 segment pins and four common pins
• Choice of four duty cycles (static, 1/2, 1/3, or 1/4)
• Segment pins can be switched to general -purpose port function in 4-bit units Power-on reset and low-voltage detect circuits (H8/38124 Group only) Power-on reset circuit
• An internal reset signal can be issued at power-on by connecting an external capacitor. Low-voltage detect circuit
• Monitors the power supply voltage and issues an internal reset signal or interrupt if the voltage goes below or above a specified range.

Rev. 8.00 Mar. 09, 2010 Page 6 of 658 REJ09B0042-0800 Item Specification Product Code Mask ROM Version ZTAT Version F-ZTAT Version Package ROM/RAM Size (Byte) Product lineup HD64338024 HD64738024 HD64F38024R HD64F38024 FP-80A FP-80B TFP-80C TLP-85V (HD64F38024R only) Die (mask ROM/F-ZTAT version only) 32K/1K HD64338023 — — FP-80A FP-80B TFP-80C Die 24K/1K HD64338022 — — FP-80A FP-80B TFP-80C Die 16K/1K HD64338021 — — FP-80A FP-80B TFP-80C Die 12K/512 HD64338020 — — FP-80A FP-80B TFP-80C Die 8K/512 HD64338024S — — FP-80A TFP-80C TLP-85V Die 32K/1K HD64338023S — — FP-80A TFP-80C TLP-85V Die 24K/1K HD64338022S — — FP-80A TFP-80C TLP-85V Die 16K/1K HD64338021S — — FP-80A TFP-80C TLP-85V Die 12K/512 HD64338020S — — FP-80A TFP-80C TLP-85V Die 8K/512 HD64338124 — HD64F38124 FP-80A TFP-80C 32K/1K HD64338123 — — FP-80A TFP-80C 24K/1K HD64338122 — HD64F38122 FP-80A TFP-80C 16K/1K HD64338121 — — FP-80A TFP-80C 12K/512 HD64338120 — — FP-80A TFP-80C 8K/512 Refer to appendix E for information on product model numbers. Note: * See section 4, Clock Pulse Generators, for the definition of φ and φw.

Rev. 8.00 Mar. 09, 2010 Page 7 of 658 REJ09B0042-0800

1.2 Internal Block Diagram

Figure 1.1(1) shows a block diagram of the H8/38024 Group and H8/38024S Group. Figure 1.1(2) shows a block diagram of the H8/38124 Group. Sub clock OSC H8/300L CPU RAM (512 bytes to 1 Kbyte) System clock OSC ROM (8 Kbytes to 32 Kbytes) Timer A Timer C Timer F Timer G Asynchronous counter (16 bits) A/D (10 bits) Serial communication interface (SCI3) 10-bit PWM1 10-bit PWM2 LCD controller Large-current (25 mA/pin) high-voltage open-drain pin (7 V) Large-current (10 mA/pin) (H8/38024S Group only) Large-current (10 mA/pin) high-voltage open-drain pin (7 V) Large-current (10 mA/pin) (H8/38024S Group only) High-voltage (7 V) input pin (Except for H8/38024S Group) Port A PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 P60/SEG9 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P67/SEG16 P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 OSC1 OSC2 P13/TMIG P14/IRQ4/ADTRG P16 P17/IRQ3/TMIF P30/UD P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 PB3/AN3/IRQ1/TMIC PB2/AN2 PB1/AN1 PB0/AN0 IRQAEC P95 P94 P93 P92 P91/PWM2 P90/PWM1 AVCC WDT VSS VSS = AVSS VCC RES TEST Port 9Port 8Port 7LCD power supplyPort B Port 6 Port 5 Port 4 Port 3 Port 1 Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. Figure 1.1(1) Block Diagram (H8/38024 Group, H8/38024R Group, and H8/38024S Group)

Rev. 8.00 Mar. 09, 2010 Page 8 of 658 REJ09B0042-0800 Sub clock OSC H8/300L CPU RAM (512 bytes to 1 Kbyte) System clock OSC ROM (8 Kbytes to 32 Kbytes) Power-on reset and low-voltage detect circuits Timer A Timer C Timer F Timer G Asynchronous counter (16 bits) A/D (10 bits) Serial communication interface (SCI3) 10-bit PWM1 10-bit PWM2 LCD controller Large-current (15 mA/pin) PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 P60/SEG9 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P67/SEG16 P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 OSC1 OSC2 P13/TMIG P14/IRQ4/ADTRG P17/IRQ3/TMIF P30/UD P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 PB3/AN3/IRQ1/TMIC PB2/AN2 PB1/AN1/extU PB0/AN0/extD IRQAEC P95 P94 P93/Vref P92 P91/PWM2 P90/PWM1 AVCC WDT CVCC VSS VSS = AVSS VCC RES TEST Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. Port 6 Port 5 Port 4 Port 3 Port 1 Port APort 9Port 8Port 7LCD power supplyPort B Figure 1.1(2) Block Diagram (H8/38124 Group)

Rev. 8.00 Mar. 09, 2010 Page 9 of 658 REJ09B0042-0800

1.3 Pin Arrangement and Functions

1.3.1 Pin Arrangement

The H8/38024 Group, H8/38024R Group, H8/38024S Group, and H8/38124 Group pin arrangements are shown in figures 1.2, 1.3, and 1.4. The bonding pad location diagram of the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 is shown in figure 1.5. The bonding pad coordinates of the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 are given in table 1.2. The bonding pad location diagram of the HCD64F38024, HCD64F38024R is shown in figure 1.6. The bonding pad coordinates of the HCD64F38024 are given in table 1.3. The bonding pad location diagram of the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S is shown in figure 1.7. The bonding pad coordinates of the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S are given in table 1.4. FP-80A, TFP-80C (Top view) 4161 0/UD P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3/IRQ1/TMIC PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 AVCC P13/TMIG P14/IRQ4/ADTRG P16 P17/IRQ3/TMIF VSS=AVSS OSC2 OSC1 TEST RES P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9 IRQAEC P95 P94 P93 P92 P91/PWM2 P90/PWM1 VSS VCC PA0/COM1 PA1/COM2 PA2/COM3 PA3/COM4 P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. Figure 1.2(1) Pin Arrangement (FP-80A, TFP-80C: Top View, H8/38024 Group, H8/38024R Group, H8/38024S Group)

Rev. 8.00 Mar. 09, 2010 Page 10 of 658 REJ09B0042-0800 FP-80A,TFP-80C (Top view) 4161 0/UD P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 PB0/AN0/extD PB1/AN1/extU PB2/AN2 PB3/AN3/IRQ1/TMIC PB4/AN4 PB5/AN5 PB6/AN6 PB 7/AN7 AVCC P13/TMIG P14/IRQ4/ADTRG CVCC P17/IRQ3/TMIF VSS=AVSS OSC2 OSC1 TEST RES P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9 IRQAEC P95 P94 P93/Vref P92 P91/PWM2 P90/PWM1 VSS VCC PA0/COM1 PA1/COM2 PA2/COM3 PA3/COM4 P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. Figure 1.2(2) Pin Arrangement (FP-80A, TFP-80C: Top View, H8/38124 Group)

Rev. 8.00 Mar. 09, 2010 Page 11 of 658 REJ09B0042-0800 FP-80B (Top view) 2/TMOFH P33 P34 P35 P36/AEVH P37/AEVL P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3/IRQ1/TMIC PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 AVCC P13/TMIG P14/IRQ4/ADTRG P16 P17/IRQ3/TMIF VSS=AVSS OSC2 OSC1 TEST RES P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 P60/SEG9 P61/SEG10 P81/SEG26 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 P63/SEG12 P62/SEG11 P31/TMOFL P30/UD IRQAEC P94 P93 P92 P91/PWM2 P90/PWM1 VSS VCC PA0/COM1 PA1/COM2 PA2/COM3 PA3/COM4 P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 P83/SEG28 P82/SEG27 Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. Figure 1.3 Pin Arrangement (FP-80B: Top View, H8/38024 Group, H8/38024R Group)

Rev. 8.00 Mar. 09, 2010 Page 12 of 658 REJ09B0042-0800 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D8 D9 D10 E1 E2 E3 E8 E9 E10 F1 F2 F3 F8 F9 F10 G1 G2 G3 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 TLP-85V (Top view) Note: Pins are shown in transparent view. Figure 1.4 Pin Arrangement (TLP-85V, H8/38024R Group, H8/38024S Group)

Rev. 8.00 Mar. 09, 2010 Page 13 of 658 REJ09B0042-0800 Y X(0, 0) 81 79 77 75 73 71 69 67 65 63 80 78 76 74 72 70 68 66 64 62 25 27 29 31 33 35 37 39 41 24 26 28 30 32 34 36 38 40 Chip size: 3.99 mm × 3.99 mm Voltage level on the back of the chip: GND Type code Figure 1.5 Bonding Pad Location Diagram of HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 (Top View)

Rev. 8.00 Mar. 09, 2010 Page 14 of 658 REJ09B0042-0800 Table 1.2 Bonding Pad Coordinates of HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 Coordinates Coordinates Pad No. Pad Name X ( μm) Y ( μm) Pad No. Pad Name X ( μm) Y ( μm)

1 AV CC –1870 1546 42 P84/SEG29 1870 –1571

2 P13/TMIG –1870 1274 43 P85/SEG30 1870 –1395

3 P14/ IRQ4/ADTRG –1870 1058 44 P86/SEG31 1870 –1251

4 P16 –1870 909 45 P87/SEG32 1870 –1111

5 P17/ IRQ3/TMIF –1870 759 46 PA3/COM4 1870 –970

6 X1 –1870 608 47 PA2/COM3 1870 –831

7 X2 –1870 475 48 PA1/COM2 1870 –691

8 AV SS –1870 304 49 PA0/COM1 1870 –550

9 V SS –1870 173 50 V3 1870 –410

10 OSC2 –1870 –10 51 V2 1870 –270

11 OSC1 –1870 –150 52 V1 1870 –131

12 TEST –1870 –290 53 V CC 1870 10

13 RES –1870 –425 54 V SS 1870 150

14 P50/ WKP0/SEG1 –1870 –560 55 P90/PWM1 1870 293

15 P51/ WKP1/SEG2 –1870 –695 56 P91/PWM2 1870 489

16 P52/ WKP2/SEG3 –1870 –831 57 P92 1870 685

17 P53/ WKP3/SEG4 –1870 –966 58 P93 1870 880

18 P54/ WKP4/SEG5 –1870 –1101 59 P94 1870 1076

19 P55/ WKP5/SEG6 –1870 –1236 60 P95 1870 1274

20 P56/ WKP6/SEG7 –1870 –1379 61 IRQAEC 1870 1546

21 P57/ WKP7/SEG8 –1870 –1561 62 P30/UD 1782 1872

22 P60/SEG9 –1780 –1872 63 P31/TMOFL 1621 1872

23 P61/SEG10 –1621 –1872 64 P32/TMOFH 1084 1872

24 P62/SEG11 –1037 –1872 65 P33 948 1872

25 P63/SEG12 –896 –1872 66 P34 810 1872

26 P64/SEG13 –765 –1872 67 P35 673 1872

27 P65/SEG14 –635 –1872 68 P 36/AEVH 536 1872

28 P66/SEG15 –502 –1872 69 P 37/AEVL 311 1872

29 P67/SEG16 –371 –1872 70 P40/SCK32 176 1872

30 P70/SEG17 –239 –1872 71 P41/RXD32 38 1872

31 P71/SEG18 –108 –1872 72 P42/TXD32 –99 1872

32 P72/SEG19 23 –1872 73 P43/ IRQ0 –234 1872

33 P73/SEG20 156 –1872 74 PB0/AN0 –482 1872

34 P74/SEG21 287 –1872 75 PB1/AN1 –614 1872

35 P75/SEG22 419 –1872 76 PB2/AN2 –745 1872

36 P76/SEG23 550 –1872 77 PB3/AN3/ IRQ1/TMIC –878 1872

37 P77/SEG24 682 –1872 78 PB4/AN4 –1008 1872

38 P80/SEG25 833 –1872 79 PB5/AN5 –1148 1872

39 P81/SEG26 1040 –1872 80 PB6/AN6 –1621 1872

40 P82/SEG27 1621 –1872 81 PB7/AN7 –1782 1872

41 P83/SEG28 1782 –1872

Note: V SS Pads (No. 8 and 9) should be connected to power supply lines. TEST Pad (No. 12) should be connected to V SS. If the pad of these aren’t connected to the power supply line, the LSI will not operate correctly. These values show the coordinates of the centers of pads. The accuracy is ±5 μm. The home-point position is the chip’s center and the center is located at half the distance between the upper and lower pads and left and right pads.

Rev. 8.00 Mar. 09, 2010 Page 15 of 658 REJ09B0042-0800 81 79 77 75 73 71 69 67 65 80 78 76 74 72 70 68 66 64 24 26 28 30 32 34 36 38 40 27 29 31 33 35 37 39 41 Y X(0, 0) Type code Chip size: 3.84 mm × 4.24 mm Voltage level on the back of the chip: GND : NC pad Figure 1.6 Bonding Pad Location Diagram of HCD64F38024, HCD64F38024R (Top View)

Rev. 8.00 Mar. 09, 2010 Page 16 of 658 REJ09B0042-0800 Table 1.3 Bonding Pad Coordinates of HCD64F38024, HCD64F38024R Coordinates Coordinates Pad No. Pad Name X ( μm) Y ( μm) Pad No. Pad Name X ( μm) Y ( μm)

1 PB7/AN7 –1802 1904 42 P83/SEG28 1802 –1898

2 AV CC –1802 1717 43 P84/SEG29 1802 –1750

3 P13/TMIG –1802 1443 44 P85/SEG30 1802 –1594

4 P14/ IRQ4/ADTRG –1802 1292 45 P86/SEG31 1802 –1454

5 P16 –1802 1157 46 P87/SEG32 1802 –1296

6 P17/ IRQ3/TMIF –1802 1022 47 PA3/COM4 1802 –1182

7 X1 –1802 887 48 PA2/COM3 1802 –1068

8 X2 –1802 753 49 PA1/COM2 1802 –954

9 AV SS –1802 638 50 PA0/COM1 1802 –840

10 V SS –1802 473 51 V3 1802 –726

11 OSC2 –1802 318 52 V2 1802 –534

12 OSC1 –1802 202 53 V1 1802 –402

13 TEST –1802 69 54 V CC 1802 –267

14 RES –1802 –63 55 V SS 1802 –126

15 P50/ WKP0/SEG1 –1802 –195 56 P90/PWM1 1802 206

16 P51/ WKP1/SEG2 –1802 –355 57 P91/PWM2 1802 457

17 P52/ WKP2/SEG3 –1802 –514 58 P92 1802 707

18 P53/ WKP3/SEG4 –1802 –674 59 P93 1802 958

19 P54/ WKP4/SEG5 –1802 –844 60 P94 1802 1209

20 P55/ WKP5/SEG6 –1802 –1008 61 P95 1802 1460

21 P56/ WKP6/SEG7 –1802 –1348 62 IRQAEC 1802 1710

22 P57/ WKP7/SEG8 –1802 –1709 63 P30/UD 1802 1904

23 P60/SEG9 –1802 –1904 64 P31/TMOFL 1686 1999

24 P61/SEG10 –1686 –1999 65 P32/TMOFH 1222 1999

25 P62/SEG11 –1198 –1999 66 P33 1077 1999

26 P63/SEG12 –1057 –1999 67 P34 932 1999

27 P64/SEG13 –916 –1999 68 P35 788 1999

28 P65/SEG14 –755 –1999 69 P 36/AEVH 643 1999

29 P66/SEG15 –625 –1999 70 P 37/AEVL 498 1999

30 P67/SEG16 –493 –1999 71 P40/SCK32 353 1999

31 P70/SEG17 –352 –1999 72 P41/RXD32 226 1999

32 P71/SEG18 –202 –1999 73 P42/TXD32 63 1999

33 P72/SEG19 –69 –1999 74 P43/ IRQ0 –82 1999

34 P73/SEG20 72 –1999 75 PB0/AN0 –229 1999

35 P74/SEG21 213 –1999 76 PB1/AN1 –404 1999

36 P75/SEG22 330 –1999 77 PB2/AN2 –577 1999

37 P76/SEG23 459 –1999 78 PB3/AN3/ IRQ1/TMIC –751 1999

38 P77/SEG24 583 –1999 79 PB4/AN4 –925 1999

39 P80/SEG25 730 –1999 80 PB5/AN5 –1099 1999

40 P81/SEG26 937 –1999 81 PB6/AN6 –1686 1999

41 P82/SEG27 1686 –1999

Note: V SS Pads (No. 9 and 10) should be connected to power supply lines. TEST Pad (No. 13) should be connected to V SS. If the pad of these aren’t connected to the power supply line, the LSI will not operate correctly. These values show the coordinates of the centers of pads. The accuracy is ±5 μm. The home-point position is the chip’s center and the center is located at half the distance between the upper and lower pads and left and right pads.

Rev. 8.00 Mar. 09, 2010 Page 17 of 658 REJ09B0042-0800 (0.0) Y X Chip size: 2.91 mm × 2.91 mm Voltage level on the back of the chip: GND Figure 1.7 Bonding Pad Location Diagram of HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S (Top View)

Rev. 8.00 Mar. 09, 2010 Page 18 of 658 REJ09B0042-0800 Table 1.4 Bonding Pad Coordinates of HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S Coordinates Coordinates Pad No. Pad Name X ( μm) Y ( μm) Pad No. Pad Name X ( μm) Y ( μm)

1 AV CC –1338 1053 41 P84/SEG29 1338 –1121

2 P13/TMIG –1338 823 42 P85/SEG30 1338 –929

3 P14/ IRQ4/ADTRG –1338 737 43 P86/SEG31 1338 –820

4 P16 –1338 649 44 P87/SEG32 1338 –721

5 P17/ IRQ3/TMIF –1338 556 45 PA3/COM4 1338 –610

6 X1 –1338 460 46 PA2/COM3 1338 –499

7 X2 –1338 363 47 PA1/COM2 1338 –388

8 V SS = AVSS –1338 229 48 PA0/COM1 1338 –277

9 OSC2 –1338 100 49 V3 1338 –189

10 OSC1 –1338 13 50 V2 1338 –91

11 TEST –1338 –74 51 V1 1338 6

12 RES –1338 –168 52 V CC 1338 156

13 P50/ WKP0/SEG1 –1338 –265 53 V SS 1338 362

14 P51/ WKP1/SEG2 –1338 –373 54 P90/PWM1 1338 528

15 P52/ WKP2/SEG3 –1338 –481 55 P91/PWM2 1338 614

16 P53/ WKP3/SEG4 –1338 –590 56 P92 1338 699

17 P54/ WKP4/SEG5 –1338 –698 57 P93 1338 785

18 P55/ WKP5/SEG6 –1338 –806 58 P94 1338 871

19 P56/ WKP6/SEG7 –1338 –892 59 P95 1338 957

20 P57/ WKP7/SEG8 –1338 –1091 60 IRQAEC 1338 1147

21 P60/SEG9 –1121 –1338 61 P30/UD 1131 1338

22 P61/SEG10 –927 –1338 62 P31/TMOFL 936 1338

23 P62/SEG11 –805 –1338 63 P32/TMOFH 831 1338

24 P63/SEG12 –703 –1338 64 P33 735 1338

25 P64/SEG13 –593 –1338 65 P34 631 1338

26 P65/SEG14 –483 –1338 66 P35 526 1338

27 P66/SEG15 –372 –1338 67 P 36/AEVH 421 1338

28 P67/SEG16 –263 –1338 68 P 37/AEVL 317 1338

29 P70/SEG17 –166 –1338 69 P40/SCK32 212 1338

30 P71/SEG18 –47 –1338 70 P41/RXD32 108 1338

31 P72/SEG19 55 –1338 71 P42/TXD32 3 1338

32 P73/SEG20 166 –1338 72 P43/ IRQ0 –101 1338

33 P74/SEG21 277 –1338 73 PB0/AN0 –249 1338

34 P75/SEG22 388 –1338 74 PB1/AN1 –362 1338

35 P76/SEG23 499 –1338 75 PB2/AN2 –476 1338

36 P77/SEG24 610 –1338 76 PB3/AN3/ IRQ1/TMIC –589 1338

37 P80/SEG25 701 –1338 77 PB4/AN4 –702 1338

38 P81/SEG26 790 –1338 78 PB5/AN5 –791 1338

39 P82/SEG27 885 –1338 79 PB6/AN6 –880 1338

40 P83/SEG28 1076 –1338 80 PB7/AN7 –1081 1338

Note: Pad No. 11 (TEST) should be connected to V SS. If it is not connected, the LSI will not operate correctly. These values show the coordinates of the centers of pads. The accuracy is ±5 µm. The home-point position is the chip’s center and the center is located at halfway between the upper and lower pads and the left and right pads.

Rev. 8.00 Mar. 09, 2010 Page 19 of 658 REJ09B0042-0800

1.3.2 Pin Functions

Table 1.5 outlines the pin functions of the H8/38024 Group. Table 1.5 Pin Functions Pin No. Type Symbol FP-80A TFP-80C FP-80B TLP-85V Pad No.*1 Pad No.*2 Pad No.*3 I/O Name and Functions Power source pins VCC 52 54 E8 53 54 52 Input Power supply: All VCC pins should be connected to the system power supply. V SS 8 (= AVSS) (= AVSS) (= AVSS) Input Ground: All VSS pins should be connected to the system power supply (0 V). AV CC 1 3 B1 1 2 1 Input Analog power supply: This is the power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. AV SS 8 (= V SS) 10 (= VSS) (= VSS) 8 9 8 Input Analog ground: This is the A/D converter ground pin. It should be connected to the system power supply (0V). V 1 Input LCD power supply: These are the power supply pins for the LCD controller/driver. CV CC*4 4 — — — — — Input Power supply: This is the internal step-down power supply pin. To ensure stability, a capacitor with a rating of about 0.1 µF should be connected between this pin and the V SS pin.

Rev. 8.00 Mar. 09, 2010 Page 20 of 658 REJ09B0042-0800 Pin No. Type Symbol FP-80A TFP-80C FP-80B TLP-85V Pad No.*1 Pad No.*2 Pad No.*3 I/O Name and Functions OSC1 10 12 F2 11 12 10 Input Clock pins OSC2 9 11 E3 10 11 9 Output These pins connect to a crystal or ceramic oscillator, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection diagram. X 1 6 8 D3 6 7 6 Input X 2 7 9 D2 7 8 7 Output These pins connect to a 32.768-kHz or 38.4-kHz*5 crystal oscillator. See section 4, Clock Pulse Generators, for a typical connection diagram. System control RES 12 14 F3 13 14 12 Input Reset: When this pin is driven low, the chip is reset TEST 11 13 E2 12 13 11 Input Test pin: This pin is reserved and cannot be used. It should be connected to VSS. Interrupt pins IRQ IRQ1 IRQ3 IRQ4 Input IRQ interrupt request 0, 1, 3, and 4: These are input pins for edge- sensitive external interrupts, with a selection of rising or falling edge IRQAEC 60 62 C10 61 62 60 Input Asynchronous event counter event signal: This is an interrupt input pin for enabling asynchronous event input. On the H8/38124 Group, this must be fixed at V CC or GND because the oscillator is selected by the input level during resets. Refer to section 4, Clock Pulse Generators, for information on the selection method.

Rev. 8.00 Mar. 09, 2010 Page 21 of 658 REJ09B0042-0800 Pin No. Type Symbol FP-80A TFP-80C FP-80B TLP-85V Pad No.*1 Pad No.*2 Pad No.*3 I/O Name and Functions Interrupt pins WKP7 to WKP0 20 to 13 22 to 15 H1, J1, H3, G1, H2, G2, F2, G3 21 to 22 to 20 to Input Wakeup interrupt request 7 to 0: These are input pins for rising or falling-edge-sensitive external interrupts. Timer pins AEVL AEVH Input Asynchronous event counter event input: This is an event input pin for input to the asynchronous event counter. TMIC 76 78 B3 77 78 76 Input Timer C event input: This is an event input pin for input to the timer C counter. UD 61 63 A9 62 63 61 Input Timer C up/down select: This pin selects up- or down-counting for the timer C counter. The counter operates as a down-counter when this pin is high, and as an up- counter when low. TMIF 5 7 D1 5 6 5 Input Timer F event input: This is an event input pin for input to the timer F counter. TMOFL 62 64 A8 63 64 62 Output Timer FL output: This is an output pin for waveforms generated by the timer FL output compare function. TMOFH 63 65 B9 64 65 63 Output Timer FH output: This is an output pin for waveforms generated by the timer FH output compare function. TMIG 2 4 C1 2 3 2 Input Timer G capture input: This is an input pin for timer G input capture.

Rev. 8.00 Mar. 09, 2010 Page 22 of 658 REJ09B0042-0800 Pin No. Type Symbol FP-80A TFP-80C FP-80B TLP-85V Pad No.*1 Pad No.*2 Pad No.*3 I/O Name and Functions 10-bit PWM pin PWM1 PWM2 E10 Output 10-bit PWM output: These are output pins for waveforms generated by the channel 1 and 2 10-bit PWMs. I/O ports P1 7 P16 P14 P13 I/O Port 1: This is a 4-bit I/O port. Input or output can be designated for each bit by means of port control register 1 (PCR1). Note that the H8/38124 Group is not equipped with a pin 16. P3 7 to P30 68 to 61 70 to 63 A6, B7 C7, A7 B8, B9 A8, A9 69 to 70 to 68 to I/O Port 3: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 3 (PCR3). If the on-chip emulator is used, pins 33, 34, and 35 are reserved for the emulator and not available to the user. P4 3 72 74 C5 73 74 72 Input Port 4 (bit 3): This is a 1- bit input port. P4 2 to P40 71 to 69 73 to 71 B6 72 to 73 to 71 to I/O Port 4 (bits 2 to 0): This is a 3-bit I/O port. Input or output can be designated for each bit by means of port control register 4 (PCR4). P5 7 to P50 20 to 13 22 to 15 H1, J1 H3, G1 H2, G2 F1, G3 21 to 22 to 20 to I/O Port 5: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 5 (PCR5). P6 7 to P60 28 to 21 30 to 23 K5, J4 H4, K4 J3, J2 K3, K2 29 to 30 to 28 to I/O Port 6: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 6 (PCR6).

Rev. 8.00 Mar. 09, 2010 Page 23 of 658 REJ09B0042-0800 Pin No. Type Symbol FP-80A TFP-80C FP-80B TLP-85V Pad No.*1 Pad No.*2 Pad No.*3 I/O Name and Functions I/O ports P7 7 to P70 36 to 29 38 to 41 J8, J7 K6, H7 H6, J7 H6, J5 J6, H5 37 to 38 to 36 to I/O Port 7: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 7 (PCR7). P8 7 to P80 44 to 37 46 to 39 H9, J9 H10, J10 K8, K9 H8, K7 45 to 46 to 44 to I/O Port 8: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 8 (PCR8). P9 5 to P90 59 to 54 61 to 56 B10, C8 D10, C9 D9, E10 60 to 61 to 59 to Output Port 9: This is a 6-bit output port. If the on-chip emulator is used, pin 95 is reserved for the emulator and not available to the user. In the case of the F-ZTAT version, pin 95 should not be left open in the user mode, and should instead be pulled up to high level. PA 3 to PA0 45 to 48 47 to 50 G10 F10 46 to 47 to 45 to I/O Port A: This is a 4-bit I/O port. Input or output can be designated for each bit by means of port control register A (PCRA). PB 7 to PB0 80 to 73 2, 1, 80 to 75 A3, A2 C3, A4 B3, B4 A5, C4 81 to 81 to 80 to Input Port B: This is an 8-bit input port. RXD32 70 72 B5 71 72 70 Input SCI3 receive data input: This is the SCI3 data input pin. Serial communi- cation (SCI) TXD32 71 73 B6 72 73 71 Output SCI3 transmit data output: This is the SCI3 data output pin. SCK 32 69 71 C6 70 71 69 I/O SCI3 clock I/O: This is the SCI3 clock I/O pin. A/D converter AN7 to AN0 80 to 73 2, 1, 80 to 75 A3, A2 C3, A4 B3, B4 A5, C4 81 to 81 to 80 to Input Analog input channels 7 to 0: These are analog data input channels to the A/D converte.

Rev. 8.00 Mar. 09, 2010 Page 24 of 658 REJ09B0042-0800 Pin No. Type Symbol FP-80A TFP-80C FP-80B TLP-85V Pad No.*1 Pad No.*2 Pad No.*3 I/O Name and Functions A/D converter ADTRG 3 5 B2 3 4 3 Input A/D converter trigger input: This is the external trigger input pin to the A/D converter. LCD controller/ driver COM 4 to COM1 45 to 48 47 to 50 G10, G8 G9, F10 46 to 47 to 45 to Output LCD common output: These are the LCD common output pins. SEG 32 to SEG1 44 to 13 46 to 15 H9, J9, H10, J10, K8, K9, H8, K7, J8, J7, K6, H7, H6, J5, J6, H5, K5, J4, H4, K4, J3, J2, K3, K2, H1, J1, H3, G1, H2, G2, F1, 45 to 46 to 44 to Output LCD segment output: These are the LCD segment output pins. NC NC — — A1, A10, D4, K2, K10 — — — — NC pin Vref 57 — — — — — Input LVD reference voltage input: This is the LVD reference voltage input pin. Low- voltage detect circuit (LVD)*4 extD 73 — — — — — Input LVD power supply drop detect voltage input: This is the LVD power supply drop detect voltage input pin. extD 74 — — — — — Input LVD power supply rise detect voltage input: This is the LVD power supply rise detect voltage input pin. Notes: 1. Pad number for HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020. 2. Pad number for HCD64F38024 and HCD64F38024R. 3. Pad number for HCD64338024 S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S. 4. H8/38124 Group only 5. Does not apply to H8/38124 Group.

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2.1 Overview

The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation.

2.1.1 Features

Features of the H8/300L CPU are listed below.

• General-register architecture Sixteen 8-bit general registers, also usable as eight 16-bit general registers
• Instruction set with 55 basic instructions, including: ⎯ Multiply and divide instructions ⎯ Powerful bit-manipulation instructions
• Eight addressing modes ⎯ Register direct ⎯ Register indirect ⎯ Register indirect with displacement ⎯ Register indirect with post-increment or pre-decrement ⎯ Absolute address ⎯ Immediate ⎯ Program-counter relative ⎯ Memory indirect
• 64-Kbyte address space
• High-speed operation ⎯ All frequently used instructions are executed in two to four states ⎯ High-speed arithmetic and logic operations ⎯ 8- or 16-bit register-register add or subtract: 0.25 µs * ⎯ 8 × 8-bit multiply: 1.75 µs * ⎯ 16 ÷ 8-bit divide: 1.75 µs * Note: * These values are at φ = 8 MHz.
• Low-power operation modes SLEEP instruction for transfer to low-power operation

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2.1.2 Address Space

The H8/300L CPU supports an address space of up to 64 Kbytes for storing program code and data. See section 2.8, Memory Map, for details of the memory map.

2.1.3 Register Configuration

Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers. 70 70 15 0 76543210 IU H U N Z V C PC R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L (SP) [Legend] SP: Stack pointer PC: Program counter CCR: Condition code register I: Interrupt mask bit U: User bit H: Half-carry flag N: Negative flag Z: Zero flag V: Overflow flag C: Carry flag CCR General registers (Rn) Control registers (CR) Figure 2.1 CPU Registers

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2.2 Register Descriptions

2.2.1 General Registers

All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing and subroutine calls. When it functions as the stack pointer, as indicated in figure 2.2, SP (R7) points to the top of the stack. Lower address side [H'0000] Upper address side [H'FFFF] Unused area Stack area SP (R7) Figure 2.2 Stack Pointer

2.2.2 Control Registers

The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). Program Counter (PC) This 16-bit register indicates the address of the next instruction the CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored (always regarded as 0).

Rev. 8.00 Mar. 09, 2010 Page 28 of 658 REJ09B0042-0800 Condition Code Register (CCR) This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For further details, see section 3.3, Interrupts. Bit 6—User Bit (U): Can be used freely by the user. instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. The H flag is used implicitly by the DAA and DAS instructions. When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. Bit 4—User Bit (U): Can be used freely by the user. Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an instruction. Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. Refer to the H8/300L Series Software Manual for the action of each instruction on the flag bits.

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2.2.3 Initial Register Values

When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer should be initialized by software, by the first instruction executed after a reset.

2.3 Data Formats

The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data.

• Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand
• All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and DIVXU (16 bits ÷ 8 bits) instructions operate on word data.
• The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit.

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2.3.1 Data Formats in General Registers

Data of all the sizes above can be stored in general registers as shown in figure 2.3.

76543210 Don't care

Data Type Register No. Data Format 1-bit data RnH 76543210Don't care 1-bit data RnL MSB LSB Don't care Byte data RnH Byte data RnL Word data Rn 4-bit BCD data RnH 4-bit BCD data RnL [Legend] RnH: RnL: MSB: LSB: Upper byte of general register Lower byte of general register Most significant bit Least significant bit MSB LSBDon't care MSB LSB 15 0 Upper digit Lower digit Don't care 70 34 Don't care Upper digit Lower digit 70 34 Figure 2.3 Register Data Formats

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2.3.2 Memory Data Formats

Figure 2.4 indicates the data formats in memory. The H8/300L CPU can access word data stored in memory (MOV.W instruction), but the word data must always begin at an even address. If word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed. The same applies to instruction codes. Data Format 76543210 AddressData Type Address n MSB LSB MSB LSB Upper 8 bits Lower 8 bits MSB LSB CCR CCR* MSB LSB MSB LSB Address n Even address Odd address Even address Odd address Even address Odd address 1-bit data Byte data Word data Byte data (CCR) on stack Word data on stack [Legend] CCR: Condition code register Note: * Ignored on return Figure 2.4 Memory Data Formats When the stack is accessed using R7 as an address register, word access should always be performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored.

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2.4 Addressing Modes

2.4.1 Addressing Modes

The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes No. Address Modes Symbol

1 Register direct Rn

2 Register indirect @Rn

3 Register indirect with displacement @(d:16, Rn)

4 Register indirect with post-increment

Register indirect with pre-decrement @Rn+ @–Rn

5 Absolute address @aa:8 or @aa:16

6 Immediate #xx:8 or #xx:16

7 Program-counter relative @(d:8, PC)

8 Memory indirect @@aa:8

Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands. Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address must be even.

Rev. 8.00 Mar. 09, 2010 Page 33 of 658 REJ09B0042-0800 Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:

• Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
• Register indirect with pre-decrement—@–Rn The @–Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. The register retains the decremented contents of the register must be even. Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is H'FF00 to H'FFFF (65280 to 65535). Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. Program-Counter Relative—@(d:8, PC): This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. The possible branching range is –126 to +128 bytes (–63 to +64 words) from the current address. The displacement should be an even number. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address.

Rev. 8.00 Mar. 09, 2010 Page 34 of 658 REJ09B0042-0800 The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area. See section 3.3, Interrupts, for details on the vector area. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See section 2.3.2, Memory Data Formats, for further information.

2.4.2 Effective Address Calculation

Table 2.2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6). Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify the operand. Register indirect (1) (BSET, BCLR, BNOT, and BTST instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position in the operand.

Rev. 8.00 Mar. 09, 2010 Page 35 of 658 REJ09B0042-0800 Table 2.2 Effective Address Calculation Addressing Mode and Instruction Format op rm 76 3 4015 No. Effective Address Calculation Method Effective Address (EA)

1 Register direct, Rn

Operand is contents of registers indicated by rm/rn Register indirect, @Rn Contents (16 bits) of register indicated by rm 015 Register indirect with displacement, @(d:16, Rn) op rm rn 87 3 4015 op rm 76 3 4015 disp op rm 76 3 4015 Register indirect with post-increment, @Rn+ op rm 76 3 4015 Register indirect with pre-decrement, @−Rn Incremented or decremented by 1 if operand is byte size, and by 2 if word size 015 disp 015 015 015 1 or 2 015 015 1 or 2 015 rm rn Contents (16 bits) of register indicated by rm Contents (16 bits) of register indicated by rm Contents (16 bits) of register indicated by rm

Rev. 8.00 Mar. 09, 2010 Page 36 of 658 REJ09B0042-0800 Addressing Mode and Instruction Format No. Effective Address Calculation Method Effective Address (EA)

5 Absolute address

@aa:8 Operand is 1- or 2-byte immediate data @aa:16 op 87 015 op 015 IMM op disp 7015 Program-counter relative @(d:8, PC) 015 PC contents 015 015 abs H'FF 87 015 015 abs op #xx:16 op 87 015 IMM Immediate #xx:8

8 Sign extension disp

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8 Memory indirect, @@aa:8

Memory contents (16 bits) 015 abs H'00 87 015 [Legend] rm, rn: op: disp: IMM: abs: Register field Operation field Displacement Immediate data Absolute address abs

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2.5 Instruction Set

The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Instruction Set Function Instructions Number Data transfer MOV, PUSH *1, POP*1 1 Arithmetic operations ADD, SUB, ADDX , SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG Logic operations AND, OR, XOR, NOT 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8 Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Branch Bcc *2, JMP, BSR, JSR, RTS 5 System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 8 Block data transfer EEPMOV 1 Total: 55 Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP. POP Rn is equivalent to MOV.W @SP+, Rn. The same applies to the machine language. 2. Bcc is a conditional branch instruction in which cc represents a condition code. The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next.

Rev. 8.00 Mar. 09, 2010 Page 39 of 658 REJ09B0042-0800 Notation Rd General register (destination) Rs General register (source) Rn General register (EAd), <EAd> Destination operand (EAs), <EAs> Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag of CCR C C (carry) flag of CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction × Multiplication ÷ Division ∧ AND logical ∨ OR logical ⊕ Exclusive OR logical → Move ~ Logical negation (logical complement) :3 3-bit length :8 8-bit length :16 16-bit length ( ), < > Contents of operand indicated by effective address

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2.5.1 Data Transfer Instructions

Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Instruction Size * Function MOV B/W (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+ addressing modes are available for word data. The @aa:8 addressing mode is available for byte data only. The @–R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. POP W @SP+ → Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. PUSH W Rn → @–SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @–SP. Note: * Size: Operand size B: Byte W: Word Certain precautions are required in data access. See section 2.9.1, Notes on Data Access, for details. Figure 2.7 lists the format of the bit manipulation instructions.

Rev. 8.00 Mar. 09, 2010 Page 41 of 658 REJ09B0042-0800 15 087 op rm rn MOV Rm→Rn 15 087 op rm rn @Rm←→Rn 15 087 op rm rn @(d:16, Rm) ←→Rn disp 15 087 op rm rn @Rm+→Rn, or Rn →@−Rm 15 087 op rn abs @aa:8←→Rn 15 087 op rn @aa:16←→Rn abs 15 087 op rn IMM #xx:8→Rn 15 087 op rn #xx:16→Rn IMM 15 087 op rn PUSH, POP [Legend] op: rm, rn: disp: abs: IMM: Operation field Register field Displacement Absolute address Immediate data @SP+ Rn, or Rn @ −SP 111 Figure 2.5 Data Transfer Instruction Codes

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2.5.2 Arithmetic Operations

Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Instruction Size * Function ADD SUB B/W Rd ± Rs → Rd, Rd + #IMM → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. ADDX SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. INC DEC B Rd ± 1 → Rd Increments or decrements a general register by 1. ADDS SUBS W Rd ± 1 → Rd, Rd ± 2 → Rd Adds or subtracts 1 or 2 to or from a general register DAA DAS B Rd decimal adjust → Rd Decimal-adjusts (adjusts to 4-bit BCD) an addition or subtraction result in a general register by referring to the CCR MULXU B Rd × Rs → Rd Performs 8-bit × 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result DIVXU B Rd ÷ Rs → Rd Performs 16-bit ÷ 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder CMP B/W Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and indicates the result in the CCR. Word data can be compared only between two general registers. NEG B 0 – Rd → Rd Obtains the two’s complement (arithmetic complement) of data in a general register Note: * Size: Operand size B: Byte W: Word

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2.5.3 Logic Operations

Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Logic Opera tion Instructions Instruction Size * Function AND B Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data OR B Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data XOR B Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data NOT B ~ Rd → Rd Obtains the one’s complement (logical complement) of general register contents Note: * Size: Operand size B: Byte

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2.5.4 Shift Operations

Table 2.7 describes the eight shift instructions. Table 2.7 Shift Instructions Instruction Size * Function SHAL SHAR B Rd shift → Rd Performs an arithmetic shift operation on general register contents SHLL SHLR B Rd shift → Rd Performs a logical shift operation on general register contents ROTL ROTR B Rd rotate → Rd Rotates general register contents ROTXL ROTXR B Rd rotate through carry → Rd Rotates general register contents through the C (carry) bit Note: * Size: Operand size B: Byte

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2.5.5 Bit Manipulations

Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Instruction Size * Function BSET B 1 → (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → (<bit-No.> of <EAd>) Clears a specified bit in a general register or memory to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>) Inverts a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ~ (<bit-No.> of <EAd>) → Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C ∧ (<bit-No.> of <EAd>) → C ANDs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. BIAND B C ∧ [~ (<bit-No.> of <EAd>)] → C ANDs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag. The bit number is specified by 3-bit immediate data. BOR B C ∨ (<bit-No.> of <EAd>) → C ORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. BIOR B C ∨ [~ (<bit-No.> of <EAd>)] → C ORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag. The bit number is specified by 3-bit immediate data. Note: * Size: Operand size B: Byte

Rev. 8.00 Mar. 09, 2010 Page 47 of 658 REJ09B0042-0800 Instruction Size * Function BXOR B C ⊕ (<bit-No.> of <EAd>) → C XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. BIXOR B C ⊕ [~(<bit-No.> of <EAd>)] → C XORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag. The bit number is specified by 3-bit immediate data. BLD B (<bit-No.> of <EAd>) → C Copies a specified bit in a general register or memory to the C flag. BILD B ~ (<bit-No.> of <EAd>) → C Copies the inverse of a specified bit in a general register or memory to the C flag. The bit number is specified by 3-bit immediate data. BST B C → (<bit-No.> of <EAd>) Copies the C flag to a specified bit in a general register or memory. BIST B ~ C → (<bit-No.> of <EAd>) Copies the inverse of the C flag to a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. Note: * Size: Operand size B: Byte Certain precautions are required in bit manipulation. See section 2.9.2, Notes on Bit Manipulation, for details. Figure 2.7 lists the format of the bit manipulation instructions.

Rev. 8.00 Mar. 09, 2010 Page 48 of 658 REJ09B0042-0800 15 087 op IMM rn Operand: Bit No.: [Legend] op: rm, rn: abs: IMM: Operation field Register field Absolute address Immediate data 15 087 op rn BSET, BCLR, BNOT, BTST register direct (Rn) immediate (#xx:3) Operand: Bit No.: register direct (Rn) register direct (Rm)rm 15 087 op 0 Operand: Bit No.: register indirect (@Rn) immediate (#xx:3) rn 0IMM 15 087 op 0 Operand: Bit No.: register indirect (@Rn) register direct (Rm) rn 0rmop 15 087 op Operand: Bit No.: absolute (@aa:8) immediate (#xx:3) abs 0000IMM op op 15 087 op Operand: Bit No.: absolute (@aa:8) register direct (Rm) abs 0000rmop 15 087 op IMM rn Operand: Bit No.: register direct (Rn) immediate (#xx:3) BAND, BOR, BXOR, BLD, BST 15 087 op 0 Operand: Bit No.: register indirect (@Rn) immediate (#xx:3) rn 0IMMop 15 087 op Operand: Bit No.: absolute (@aa:8) immediate (#xx:3) abs 0000IMMop Figure 2.7 Bit Manipulation Instruction Codes

Rev. 8.00 Mar. 09, 2010 Page 49 of 658 REJ09B0042-0800 [Legend] op: rm, rn: abs: IMM: Operation field Register field Absolute address Immediate data 15 087 op IMM rn Operand: Bit No.: register direct (Rn) immediate (#xx:3) BIAND, BIOR, BIXOR, BILD, BIST 15 087 op 0 Operand: Bit No.: register indirect (@Rn) immediate (#xx:3) rn 0IMMop 15 087 op Operand: Bit No.: absolute (@aa:8) immediate (#xx:3) abs 0000IMMop Figure 2.7 Bit Manipulation Instruction Codes (cont)

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2.5.6 Branching Instructions

Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Function Bcc — Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never BHI High C ∨ Z = 0 BLS Low or same C ∨ Z = 1 BCC (BHS) Carry clear (high or same) C = 0 BCS (BLO) Carry set (low) C = 1 BNE Not equal Z = 0 BEQ Equal Z = 1 BVC Overflow clear V = 0 BVS Overflow set V = 1 BPL Plus N = 0 BMI Minus N = 1 BGE Greater or equal N ⊕ V = 0 BLT Less than N ⊕ V = 1 BGT Greater than Z ∨ (N ⊕ V) = 0 BLE Less or equal Z ∨ (N ⊕ V) = 1 JMP — Branches unconditionally to a specified address BSR — Branches to a subroutine at a specified address JSR — Branches to a subroutine at a specified address RTS — Returns from a subroutine

Rev. 8.00 Mar. 09, 2010 Page 51 of 658 REJ09B0042-0800 [Legend] op: cc: rm: disp: abs: Operation field Condition field Register field Displacement Absolute address 15 087 op cc disp Bcc 15 087 op rm 0 JMP (@Rm)000 15 087 op JMP (@aa:16) abs 15 087 op abs JMP (@@aa:8) 15 087 op disp BSR 15 087 op rm 0 JSR (@Rm)000 15 087 op JSR (@aa:16) abs 15 087 op abs JSR (@@aa:8) 15 087 op RTS Figure 2.8 Branching Instruction Codes

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2.5.7 System Control Instructions

Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Co ntrol Instructions Instruction Size * Function RTE — Returns from an exception-handling routine SLEEP — Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details. LDC B Rs → CCR, #IMM → CCR Moves immediate data or general register contents to the condition code register STC B CCR → Rd Copies the condition code register to a specified general register ANDC B CCR ∧ #IMM → CCR Logically ANDs the condition code register with immediate data ORC B CCR ∨ #IMM → CCR Logically ORs the condition code register with immediate data XORC B CCR ⊕ #IMM → CCR Logically exclusive-ORs the condition code register with immediate data NOP — PC + 2 → PC Only increments the program counter Note: * Size: Operand size B: Byte

Rev. 8.00 Mar. 09, 2010 Page 53 of 658 REJ09B0042-0800 [Legend] op: rn: IMM: Operation field Register field Immediate data 15 087 op RTE, SLEEP, NOP 15 087 op rn LDC, STC (Rn) 15 087 op IMM ANDC, ORC, XORC, LDC (#xx:8) Figure 2.9 System Control Instruction Codes

2.5.8 Block Data Transfer Instruction

Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction Instruction Size Function EEPMOV — If R4L ≠ 0 then repeat @R5+ → @R6+ R4L – 1 → R4L until R4L = 0 else next; Block transfer instruction. Transfers the number of data bytes specified by R4L from locations starting at the address indicated by R5 to locations starting at the address indicated by R6. After the transfer, the next instruction is executed. Certain precautions are required in using the EEPMOV instruction. See section 2.9.3, Notes on Use of the EEPMOV Instruction, for details.

Rev. 8.00 Mar. 09, 2010 Page 54 of 658 REJ09B0042-0800 [Legend] op: Operation field 15 087 op op Figure 2.10 Block Data Transfer Instruction Code

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2.6 Basic Operational Timing

CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.

2.6.1 Access to On-Chip Memory (RAM, ROM)

Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.11 shows the on-chip memory access cycle. T1 state Bus cycle T2 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Read data Address Write dataInternal data bus (write access) φ or φSUB Figure 2.11 On-Chip Memory Access Cycle

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2.6.2 Access to On-Chip Peripheral Modules

On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used. Figures 2.12 and 2.13 show the on-chip peripheral module access cycle. Two-state access to on-chip peripheral modules T1 state Bus cycle T2 state φ or φSUB Internal address bus Internal read signal Internal data bus (read access) Internal write signal Read data Address Write dataInternal data bus (write access) Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)

Rev. 8.00 Mar. 09, 2010 Page 57 of 658 REJ09B0042-0800 Three-state access to on-chip peripheral modules T1 state Bus cycle Internal address bus Internal read signal Internal data bus (read access) Internal write signal Read data Address Internal data bus (write access) T2 state T3 state Write data φ or φSUB Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)

2.7 CPU States

2.7.1 Overview

There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or medium- speed) mode and subactive mode. In the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in figure 2.14. Figure 2.15 shows the state transitions.

Rev. 8.00 Mar. 09, 2010 Page 58 of 658 REJ09B0042-0800 CPU state Reset state Program execution state Program halt state Exception- handling state Active (high speed) mode Active (medium speed) mode Subactive mode Sleep (high-speed) mode Standby mode Watch mode Subsleep mode Low-power modes The CPU executes successive program instructions at high speed, synchronized by the system clock The CPU executes successive program instructions at reduced speed, synchronized by the system clock The CPU executes successive program instructions at reduced speed, synchronized by the subclock A state in which some or all of the chip functions are stopped to conserve power A transient state in which the CPU changes the processing flow due to a reset or an interrupt The CPU is initialized Note: See section 5, Power-Down Modes, for details on the modes and their transitions. Sleep (medium-speed) mode Figure 2.14 CPU Operation States

Rev. 8.00 Mar. 09, 2010 Page 59 of 658 REJ09B0042-0800 Reset state Program halt state Exception-handling state Program execution state Reset cleared SLEEP instruction executed Reset occurs Interrupt source occursReset occurs Interrupt source occurs Exception- handling complete Reset occurs Figure 2.15 State Transitions

2.7.2 Program Execution State

In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. Operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for details on these modes.

2.7.3 Program Halt State

In the program halt state there are five modes: two sleep modes (high speed and medium speed), standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on these modes.

2.7.4 Exception-Handling State

The exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the CPU changes its normal processing flow. In exception handling caused by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack. For details on interrupt handling, see section 3.3, Interrupts.

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2.8 Memory Map

2.8.1 Memory Map

The memory map of the H8/38024, H8/38024S, and H8/38124 are shown in figure 2.16(1), that of the H8/38023, H8/38023S, and H8/38123 in figure 2.16(2), that of the H8/38022, H8/38022S, and H8/38122 in figure 2.16(3), that of the H8/38021, H8/38021S, and H8/38121 in figure 2.16(4), and that of the H8/38020, H8/38020S, and H8/38120 in figure 2.16(5).

Rev. 8.00 Mar. 09, 2010 Page 61 of 658 REJ09B0042-0800 H'0000 H'0029 H'002A H'7FFF H'7000 H'F020 H'F02B H'F740 H'F74F H'FB80 H'FB7F H'FF7F H'FF80 H'FFFF Interrupt vector area User area (1 Kbyte) On-chip ROM (32768 bytes) 1024 bytes Internal I/O register (128 bytes) (Workarea for reprogramming flash memory: 1 Kbyte)*2 Internal I/O register Not used Firmware for on-chip emulator*1 H'F780 Not used Not used LCD RAM (16 bytes) H'0000 H'0029 H'002A H'7FFF H'F740 H'F74F H'FB80 H'FF7F H'FF80 H'FFFF Interrupt vector area HD64F38024, HD64F38024R, HD64F38124 (flash memory version) HD64338024 (mask ROM version) HD64338024S (mask ROM version) HD64338124 (mask ROM version) HD64738024 (PROM version) On-chip ROM (32768 bytes) 1024 bytesOn-chip RAM Internal I/O register (128 bytes) Not used Not used LCD RAM (16 bytes) On-chip RAM (2 Kbytes) Notes: 1. Not available to the user if the on-chip emulator is used. 2. Used by the programming control program when programming flash memory. Also, not available to the user if the on-chip emulator is used. Figure 2.16(1) H8/38024, H8/38024S, and H8/38124 Memory Map

Rev. 8.00 Mar. 09, 2010 Page 62 of 658 REJ09B0042-0800 H'0000 H'0029 H'002A H'5FFF H'F740 H'F74F H'FB80 H'FF7F H'FF80 H'FFFF Interrupt vector area On-chip ROM

24 Kbytes

(24576 bytes) 1024 bytesOn-chip RAM Internal I/O registers (128 bytes) Not used Not used LCD RAM (16 bytes) Figure 2.16(2) H8/38023, H8/38023S, and H8/38123 Memory Map

Rev. 8.00 Mar. 09, 2010 Page 63 of 658 REJ09B0042-0800 H'0000 H'0029 H'002A H'3FFF H'3FFF H'7FFF H'7000 H'F020 H'F02B H'F740 H'F74F H'FB80 H'FB7F H'FF7F H'FF80 H'FFFF Interrupt vector area User area (1 Kbyte) On-chip ROM 16 Kbytes (16384 bytes) 1024 bytes Internal I/O register (128 bytes) (Workarea for reprogramming flash memory: 1 Kbyte)* Internal I/O register Not used Firmware for on-chip emulator H'F780 Not used Not used Not used LCD RAM (16 bytes) H'0000 H'0029 H'002A H'F740 H'F74F H'FB80 H'FF7F H'FF80 H'FFFF Interrupt vector area Flash memory version Mask ROM version On-chip ROM

16 Kbytes

(16384 bytes) 1024 bytesOn-chip RAM Internal I/O register (128 bytes) Not used Not used LCD RAM (16 bytes) On-chip RAM (2 Kbytes) Note: * Used by the programming control program when programming flash memory. Also, not available to the user if the on-chip emulator is used. Figure 2.16(3) H8/38022, H8/38022S, and H8/38122 Memory Map

Rev. 8.00 Mar. 09, 2010 Page 64 of 658 REJ09B0042-0800 H'0000 H'0029 H'002A H'2FFF H'F740 H'F74F H'FD80 H'FF7F H'FF80 H'FFFF Interrupt vector area On-chip ROM

12 Kbytes

(12288 bytes) 512 bytesOn-chip RAM Internal I/O registers (128 bytes) Not used Not used LCD RAM (16 bytes) Figure 2.16(4) H8/38021, H8/38021S, and H8/38121 Memory Map

Rev. 8.00 Mar. 09, 2010 Page 65 of 658 REJ09B0042-0800 H'0000 H'0029 H'002A H'1FFF H'F740 H'F74F H'FD80 H'FF7F H'FF80 H'FFFF Interrupt vector area On-chip ROM (8192 bytes) 512 bytesOn-chip RAM Internal I/O registers (128 bytes) Not used Not used LCD RAM (16 bytes) Figure 2.16(5) H8/38020, H8/38020S, and H8/38120 Memory Map

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2.9 Application Notes

2.9.1 Notes on Data Access

1. Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur. Data transfer from CPU to empty area: The transferred data will be lost. This action may also cause the CPU to misoperate. Data transfer from empty area to CPU: Unpredictable data is transferred. 2. Access to Internal I/O Registers: Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the following results will occur. Word access from CPU to I/O register area: Upper byte: Will be written to I/O register. Lower byte: Transferred data will be lost. Word access from I/O register to CPU: Upper byte: Will be written to upper part of CPU register. Lower byte: Unpredictable data will be written to lower part of CPU register. Byte size instructions should therefore be used when transferring data to or from I/O registers other than the on-chip ROM and RAM areas. Figure 2.17 shows the data size and number of states in which on-chip peripheral modules can be accessed.

Rev. 8.00 Mar. 09, 2010 Page 67 of 658 REJ09B0042-0800 Interrupt vector area (42 bytes) On-chip ROM (16 bytes) Internal I/O registers (128 bytes) (1-Kbyte work area for flash memory programming) Access Word Byte ⎯⎯⎯ Not used ⎯⎯⎯ Not used ⎯⎯⎯ States 1024 bytes H'FFA8 to H'FFAF H'0000 H'0029 H'002A H'7FFF H'F740 H'F020 H'F02B H'F74F H'F780 H'FB7F H'FB80 H'FF7F H'FF80 H'FFFF Notes: These examples apply to the H8/38024. 1. On the H8/38024, H8/38124, and H8/38024S, 32 Kbytes and the address is H'7FFF; on the H8/38023, H8/38123, and H8/38023S, 24 Kbytes and the address is H'5FFF; on the H8/38022, H8/38122, and H8/38022S, 16 Kbytes and the address is H'3FFF; on the H8/38021, H8/38121, and H8/38021S, 12 Kbytes and the address is H'2FFF; on the H8/38020, H8/38120, and H8/38020S, 8 Kbytes and the address is H'1FFF. 2. On the H8/38021, H8/38121, H8/38021S, H8/38020, H8/38120, and H8/38020S, 512 bytes and the address is H'FD80. 3. Only the HD64F38024, HD64F38024R, HD64F38122, and HD64F38124 are equipped with internal I/O registers from H'F020 to H'F02B and on-chip RAM from H'F780 to H'FB7F. Attempting to access these areas on products other than the HD64F38024, HD64F38024R, HD64F38122, and HD64F38124 will result in access to an empty area. H'FF98 to H'FF9F Internal I/O registers Figure 2.17 Data Size and Number of States for Access to and from On-Chip Peripheral Modules

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2.9.2 Notes on Bit Manipulation

The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an I/O port. Order of Operation Operation

1 Read Read byte data at the designated address

2 Modify Modify a designated bit in the read data

3 Write Write the altered byte data to the designated address

1. Bit manipulation in two registers assigned to the same address Example 1: timer load register and timer counter Figure 2.18 shows an example in which two timer registers share the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. Order of Operation Operation

1 Read Timer counter data is read (one byte)

2 Modify The CPU modifies (sets or resets) the bit designated in the instruction

3 Write The altered byte data is written to the timer load register

The timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. Read Write Count clock Timer counter Timer load register Reload Internal data bus Figure 2.18 Timer Configuration Example

Rev. 8.00 Mar. 09, 2010 Page 69 of 658 REJ09B0042-0800 Example 2: BSET instruction executed designating port 3 P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P31, are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P30 to high-level output. [A: Prior to executing BSET] P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR3 0 0 1 1 1 1 1 1 PDR3 1 0 0 0 0 0 0 0 [B: BSET instruction executed] BSET #0 , @PDR3 The BSET instruction is executed designating port 3. [C: After executing BSET] P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR3 0 0 1 1 1 1 1 1 PDR3 0 1 0 0 0 0 0 1 [D: Explanation of how BSET operates] When the BSET instruction is executed, first the CPU reads port 3. Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input). P35 to P30 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value of H'80, but the value read by the CPU is H'40. Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU writes this value (H'41) to PDR3, completing execution of BSET. As a result of this operation, bit 0 in PDR3 becomes 1, and P30 outputs a high-level signal. However, bits 7 and 6 of PDR3 end up with different values.

Rev. 8.00 Mar. 09, 2010 Page 70 of 658 REJ09B0042-0800 To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. [A: Prior to executing BSET] MOV. B #80, R0L The PDR3 value (H'80) is written to a work area in memory MOV. B R0L, @RAM0 (RAM0) as well as to PDR3 MOV. B R0L, @PDR3 P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR3 0 0 1 1 1 1 1 1 PDR3 1 0 0 0 0 0 0 0 RAM0 1 0 0 0 0 0 0 0 [B: BSET instruction executed] BSET #0 , @RAM0 The BSET instruction is executed designating the PDR3 work area (RAM0). [C: After executing BSET] MOV. B @RAM0, R0L The work area (RAM0) value is written to PDR3. MOV. B R0L, @PDR3 P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR3 0 0 1 1 1 1 1 1 PDR3 1 0 0 0 0 0 0 1 RAM0 1 0 0 0 0 0 0 1

Rev. 8.00 Mar. 09, 2010 Page 71 of 658 REJ09B0042-0800 2. Bit manipulation in a register containing a write-only bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P37 and P36 are input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P30, are output pins that output low-level signals. In this example, the BCLR instruction is used to change pin P30 to an input port. It is assumed that a high-level signal will be input to this input pin. [A: Prior to executing BCLR] P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR3 0 0 1 1 1 1 1 1 PDR3 1 0 0 0 0 0 0 0 [B: BCLR instruction executed] BCLR #0 , @PCR3 The BCLR instruction is executed designating PCR3. [C: After executing BCLR] P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 Input/output Output Output Output Output Output Output Output Input Pin state Low level High level Low level Low level Low level Low level Low level High level PCR3 1 1 1 1 1 1 1 0 PDR3 1 0 0 0 0 0 0 0 [D: Explanation of how BCLR operates] When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value (H'FE) is written to PCR3 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR3 becomes 0, making P30 an input port. However, bits 7 and 6 in PCR3 change to 1, so that P37 and P36 change from input pins to output pins.

Rev. 8.00 Mar. 09, 2010 Page 72 of 658 REJ09B0042-0800 To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR3. [A: Prior to executing BCLR] MOV. B #3F, R0L The PCR3 value (H'3F) is written to a work area in memory MOV. B R0L, @RAM0 (RAM0) as well as to PCR3. MOV. B R0L, @PCR3 P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR3 0 0 1 1 1 1 1 1 PDR3 1 0 0 0 0 0 0 0 RAM0 0 0 1 1 1 1 1 1 [B: BCLR instruction executed] BCLR #0 , @RAM0 The BCLR instruction is executed designating the PCR3 work area (RAM0). [C: After executing BCLR] MOV. B @RAM0, R0L The work area (RAM0) value is written to PCR3. MOV. B R0L, @PCR3 P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR3 0 0 1 1 1 1 1 0 PDR3 1 0 0 0 0 0 0 0 RAM0 0 0 1 1 1 1 1 0 Table 2.12 lists the pairs of registers that share identical addresses. Table 2.13 lists the registers that contain write-only bits.

Rev. 8.00 Mar. 09, 2010 Page 73 of 658 REJ09B0042-0800 Table 2.12 Registers with Shared Addresses Register Name Abbreviation Address Timer counter C/Timer load register C TCC/TLC H'FFB5 Port data register 1* PDR1 H'FFD4 Port data register 3* PDR3 H'FFD6 Port data register 4* PDR4 H'FFD7 Port data register 5* PDR5 H'FFD8 Port data register 6* PDR6 H'FFD9 Port data register 7* PDR7 H'FFDA Port data register 8* PDR8 H'FFDB Port data register A* PDRA H'FFDD Note: * Port data registers have the same addresses as input pins. Table 2.13 Registers with Write-Only Bits Register Name Abbreviation Address Port control register 1 PCR1 H'FFE4 Port control register 3 PCR3 H'FFE6 Port control register 4 PCR4 H'FFE7 Port control register 5 PCR5 H'FFE8 Port control register 6 PCR6 H'FFE9 Port control register 7 PCR7 H'FFEA Port control register 8 PCR8 H'FFEB Port control register A PCRA H'FFED Timer control register F TCRF H'FFB6 PWM1 control register PWCR1 H'FFD0 PWM1 data register U PWDRU1 H'FFD1 PWM1 data register L PWDRL1 H'FFD2 PWM2 control register PWCR2 H'FFCD PWM2 data register U PWDRU2 H'FFCE PWM2 data register L PWDRL2 H'FFCF Event counter PWM data register H ECPWDRH H'FF8E Event counter PWM data register L ECPWDRL H'FF8F

Rev. 8.00 Mar. 09, 2010 Page 74 of 658 REJ09B0042-0800

2.9.3 Notes on Use of the EEPMOV Instruction

• The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. ← R6 ← R6 + R4L R5 → R5 + R4L →
• When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction. H'FFFF Not allowed ← R6 ← R6 + R4L R5 → R5 + R4L →

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 75 of 658 REJ09B0042-0800 Section 3 Exception Handling

3.1 Overview

Exception handling is performed in the H8/38024 Group, H8/38024S Group, H8/38024F-ZTAT Group, and H8/38124 Group when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1 Exception Handling Types and Priorities Priority Exception Source Time of Start of Exception Handling High Reset Exception handling starts as soon as the reset state is cleared Low Interrupt When an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed

3.2 Reset

3.2.1 Overview

A reset is the highest-priority exception. The internal state of the CPU and the registers of the on- chip peripheral modules are initialized.

3.2.2 Reset Sequence

As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state. To make sure the chip is reset properly, observe the following precautions.

• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
• Resetting during operation: Hold the RES pin low for at least 10 system clock cycles. Reset exception handling takes place as follows.
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I bit of the condition code register (CCR) set to 1.
• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after which the program starts executing from the address indicated in PC.

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 76 of 658 REJ09B0042-0800 When system power is turned on or off, the RES pin should be held low. Figure 3.1 shows the reset sequence starting from RES input. See section 14.3.1, Power-On Reset Circuit, for information on the reset sequence for the H8/38124 Group, which is equipped with an on-chip power-on reset circuit. Vector fetch φ Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) RES Internal processing Program initial instruction prefetch (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program (2) (3) (2) (1) Reset cleared Figure 3.1 Reset Sequence

3.2.3 Interrupt Immediately after Reset

After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized, PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To prevent this, immediately after reset exception handling all interrupts are masked. For this reason, the initial program instruction is always executed immediately after a reset. This instruction should initialize the stack pointer (e.g. MOV.W #xx: 16, SP).

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 77 of 658 REJ09B0042-0800

3.3 Interrupts

3.3.1 Overview

The interrupt sources include 13 external interrupts (WKP7 to WKP0, IRQ4, IRQ3, IRQ1, IRQ0, IRQAEC) and 9 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed. The interrupts have the following features:

• Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1, interrupt request flags can be set but the interrupts are not accepted.
• IRQ 4, IRQ3, IRQ1, IRQ0, and WKP7 to WKP0 can be set to either rising edge sensing or falling edge sensing, and IRQAEC can be set to either rising edge sensing, falling edge sensing, or both edge sensing.

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 78 of 658 REJ09B0042-0800 Table 3.2 Interrupt Sources and Their Priorities Interrupt Source Interrupt Vector Number Vector Address Priority RES Watchdog timer Reset 0 H'0000 to H'0001 High IRQ0 LVDI* IRQ0 Low-voltage detect interrupt*

4 H'0008 to H'0009

IRQ1 IRQ 1 5 H'000A to H'000B IRQAEC IRQAEC 6 H'000C to H'000D IRQ3 IRQ 3 7 H'000E to H'000F IRQ4 IRQ 4 8 H'0010 to H'0011 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7

9 H'0012 to H'0013

Timer A Timer A overflow 11 H'0016 to H'0017 Asynchronous event counter Asynchronous event counter overflow

12 H'0018 to H'0019

Timer C Timer C overflow or underflow 13 H'001A to H'001B Timer FL Timer FL compare match Timer FL overflow

14 H'001C to H'001D

Timer FH Timer FH compare match Timer FH overflow

15 H'001E to H'001F

Timer G Timer G input capture Timer G overflow

16 H'0020 to H'0021

18 H'0024 to H'0025

A/D A/D conversion end 19 H'0026 to H'0027 (SLEEP instruction executed) Direct transfer 20 H'0028 to H'0029 Low Notes: Vector addresses H'0002 to H'0007, H'0014 to H'0015, and H'0022 to H'0023 are reserved and cannot be used. * The low-voltage detect interrupt triggered by the LVDI is only implemented on the H8/38124 Group.

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 79 of 658 REJ09B0042-0800

3.3.2 Interrupt Control Registers

Table 3.3 lists the registers that control interrupts. Table 3.3 Interrupt Control Registers Name Abbreviation R/W Initial Value Address IRQ edge select register IEGR R/W — H'FFF2 Interrupt enable register 1 IENR1 R/W — H'FFF3 Interrupt enable register 2 IENR2 R/W — H'FFF4 Interrupt request register 1 IRR1 R/W * — H'FFF6 Interrupt request register 2 IRR2 R/W * — H'FFF7 Wakeup interrupt request register IWPR R/W * H'00 H'FFF9 Wakeup edge select register WEGR R/W H'00 H'FF90 Note: * Write is enabled only for writing of 0 to clear a flag. IRQ Edge Select Register (IEGR) Bit Initial value Read/Write IEG4 R/W IEG3 R/W IEG0 R/W W IEG1 R/W IEGR is an 8-bit read/write register used to designate whether pins IRQ4, IRQ3, IRQ1, and IRQ0 are set to rising edge sensing or falling edge sensing. For the IRQAEC pin edge sensing specifications, see section 9.7, Asynchronous Event Counter (AEC). Bits 7 to 5—Reserved Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified.

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 80 of 658 REJ09B0042-0800 Bit 4—IRQ 4 Edge Select (IEG4) Bit 4 selects the input sensing of the IRQ4 pin and ADTRG pin. Bit 4 IEG4

Description

0 Falling edge of IRQ4 and ADTRG pin input is detected (initial value)

1 Rising edge of IRQ4 and ADTRG pin input is detected

Bit 3—IRQ 3 Edge Select (IEG3) Bit 3 selects the input sensing of the IRQ3 pin and TMIF pin. Bit 3 IEG3

0 Falling edge of IRQ3 and TMIF pin input is detected (initial value)

1 Rising edge of IRQ3 and TMIF pin input is detected

Bit 2—Reserved Bit 2 is reserved: it can only be written with 0. Bit 1—IRQ

1 Edge Select (IEG1)

Bit 1 selects the input sensing of the IRQ1 pin and TMIC pin. Bit 1 IEG1

0 Falling edge of IRQ1 and TMIC pin input is detected (initial value)

1 Rising edge of IRQ1 and TMIC pin input is detected

Bit 0—IRQ 0 Edge Select (IEG0) Bit 0 selects the input sensing of pin IRQ0. Bit 0 IEG0

0 Falling edge of IRQ0 pin input is detected (initial value)

1 Rising edge of IRQ0 pin input is detected

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 81 of 658 REJ09B0042-0800 Interrupt Enable Register 1 (IENR1) Bit Initial value Read/Write IENTA R/W W IENWP R/W IEN4 R/W IEN3 R/W IEN0 R/W IENEC2 R/W IEN1 R/W IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7—Timer A Interrupt Enable (IENTA) Bit 7 enables or disables timer A overflow interrupt requests. Bit 7 IENTA

0 Disables timer A interrupt requests (initial value)

1 Enables timer A interrupt requests

Bit 6—Reserved Bit 6 is reserved: it can only be written with 0. Bit 5—Wakeup Interrupt Enable (IENWP) Bit 5 enables or disables WKP7 to WKP0 interrupt requests. Bit 5 IENWP

0 Disables WKP7 to WKP0 interrupt requests (initial value)

1 Enables WKP7 to WKP0 interrupt requests

Bits 4 and 3—IRQ 4 and IRQ3 Interrupt Enable (IEN4 and IEN3) Bits 4 and 3 enable or disable IRQ4 and IRQ3 interrupt requests. Bit n IENn

0 Disables interrupt requests from pin IRQn (initial value)

1 Enables interrupt requests from pin IRQn

(n = 4 or 3)

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 82 of 658 REJ09B0042-0800 Bit 2—IRQAEC Interrupt Enable (IENEC2) Bit 2 enables or disables IRQAEC interrupt requests. Bit 2 IENEC2

0 Disables IRQAEC interrupt requests (initial value)

1 Enables IRQAEC interrupt requests

Bits 1 and 0—IRQ 1 and IRQ0 Interrupt Enable (IEN1 and IEN0) Bits 1 and 0 enable or disable IRQ1 and IRQ0 interrupt requests. Bit n IENn (n = 1 or 0) Interrupt Enable Register 2 (IENR2) Bit Initial value Read/Write IENDT R/W IENAD R/W W IENTG R/W IENTFH R/W IENEC R/W IENTFL R/W IENTC R/W IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7—Direct Transfer Interrupt Enable (IENDT) Bit 7 enables or disables direct transfer interrupt requests. Bit 7 IENDT

0 Disables direct transfer interrupt requests (initial value)

1 Enables direct transfer interrupt requests

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 83 of 658 REJ09B0042-0800 Bit 6—A/D Converter Interrupt Enable (IENAD) Bit 6 enables or disables A/D converter interrupt requests. Bit 6 IENAD

0 Disables A/D converter interrupt requests (initial value)

1 Enables A/D converter interrupt requests

Bit 5—Reserved Bit 5 is reserved bit: it can only be written with 0. Bit 4—Timer G Interrupt Enable (IENTG) Bit 4 enables or disables timer G input capture or overflow interrupt requests. Bit 4 IENTG

0 Disables timer G interrupt requests (initial value)

1 Enables timer G interrupt requests

Bit 3—Timer FH Interrupt Enable (IENTFH) Bit 3 enables or disables timer FH compare match and overflow interrupt requests. Bit 3 IENTFH

0 Disables timer FH interrupt requests (initial value)

1 Enables timer FH interrupt requests

Bit 2—Timer FL Interrupt Enable (IENTFL) Bit 2 enables or disables timer FL compare match and overflow interrupt requests. Bit 2 IENTFL

0 Disables timer FL interrupt requests (initial value)

1 Enables timer FL interrupt requests

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 84 of 658 REJ09B0042-0800 Bit 1—Timer C Interrupt Enable (IENTC) Bit 1 enables or disables timer C overflow and underflow interrupt requests. Bit 1 IENTC

0 Disables timer C interrupt requests (initial value)

1 Enables timer C interrupt requests

Bit 0—Asynchronous Event Counter Interrupt Enable (IENEC) Bit 0 enables or disables asynchronous event counter interrupt requests. Bit 0 IENEC

0 Disables asynchronous event counter interrupt requests (initial value)

1 Enables asynchronous event counter interrupt requests

For details of SCI3 interrupt control, see section 10.2.6 Serial control register 3 (SCR3). Interrupt Request Register 1 (IRR1) Bit Initial value Read/Write IRRTA R/(W)* W IRRI4 R/(W)* IRRI3 R/(W)* IRRI0 R/(W)* IRREC2 R/(W)* IRRI1 R/(W)* Note: * Only a write of 0 for flag clearing is possible IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A, IRQAEC, IRQ4, IRQ3, IRQ1, or IRQ0 interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 85 of 658 REJ09B0042-0800 Bit 7—Timer A Interrupt Request Flag (IRRTA) Bit 7 IRRTA

0 Clearing condition: (initial value)

When IRRTA = 1, it is cleared by writing 0

1 Setting condition:

When the timer A counter value overflows Bit 6—Reserved Bit 6 is reserved; it can only be written with 0. Bit 5—Reserved Bit 5 is reserved; it is always read as 1 and cannot be modified. Bits 4 and 3—IRQ 4 and IRQ3 Interrupt Request Flags (IRRI4 and IRRI3) Bit n IRRIn When IRRIn = 1, it is cleared by writing 0 When pin IRQn is designated for interrupt input and the designated signal edge is input (n = 4 or 3) Bit 2—IRQAEC Interrupt Request Flag (IRREC2) Bit 2 IRREC2 When IRREC2 = 1, it is cleared by writing 0 When pin IRQAEC is designated for interrupt input and the designated signal edge is input

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 86 of 658 REJ09B0042-0800 Bits 1 and 0—IRQ 1 and IRQ0 Interrupt Request Flags (IRRI1 and IRRI0) Bit n IRRIn When IRRIn = 1, it is cleared by writing 0 When pin IRQn is designated for interrupt input and the designated signal edge is input (n = 1 or 0) Interrupt Request Register 2 (IRR2) Bit Initial value Read/Write IRRDT R/(W)* IRRAD R/(W)* W IRRTG R/(W)* IRRTFH R/(W)* IRREC R/(W)* IRRTFL R/(W)* IRRTC R/(W)* Note: * Only a write of 0 for flag clearing is possible IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct transfer, A/D converter, Timer G, Timer FH, Timer FL, Timer C, or asynchronous event counter interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Bit 7—Direct Transfer Interrupt Request Flag (IRRDT) Bit 7 IRRDT When IRRDT = 1, it is cleared by writing 0 When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in SYSCR2

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 87 of 658 REJ09B0042-0800 Bit 6—A/D Converter Interrupt Request Flag (IRRAD) Bit 6 IRRAD When IRRAD = 1, it is cleared by writing 0 When A/D conversion is completed and ADSF is cleared to 0 in ADSR Bit 5—Reserved Bit 5 is reserved: it can only be written with 0. Bit 4—Timer G Interrupt Request Flag (IRRTG) Bit 4 IRRTG When IRRTG = 1, it is cleared by writing 0 When the TMIG pin is designated for TMIG input and the designated signal edge is input, and when TCG overflows while OVIE is set to 1 in TMG Bit 3—Timer FH Interrupt Request Flag (IRRTFH) Bit 3 IRRTFH When IRRTFH = 1, it is cleared by writing 0 When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH) and OCRF (OCRFL, OCRFH) match in 16-bit timer mode

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 88 of 658 REJ09B0042-0800 Bit 2—Timer FL Interrupt Request Flag (IRRTFL) Bit 2 IRRTFL When IRRTFL = 1, it is cleared by writing 0 When TCFL and OCRFL match in 8-bit timer mode Bit 1—Timer C Interrupt Request Flag (IRRTC) Bit 1 IRRTC When IRRTC = 1, it is cleared by writing 0 When the timer C counter value overflows or underflows Bit 0—Asynchronous Event Counter Interrupt Request Flag (IRREC) Bit 0 IRREC When IRREC = 1, it is cleared by writing 0 When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit counter mode

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 89 of 658 REJ09B0042-0800 Wakeup Interrupt Request Register (IWPR) Bit Initial value Read/Write IWPF7 R/(W)* IWPF6 R/(W)* IWPF5 R/(W)* IWPF4 R/(W)* IWPF3 R/(W)* IWPF0 R/(W)* IWPF2 R/(W)* IWPF1 R/(W)* Note: * Only a write of 0 for flag clearing is possible IWPR is an 8-bit read/write register containing wakeup interrupt request flags. When one of pins WKP7 to WKP0 is designated for wakeup input and a rising or falling edge is input at that pin, the corresponding flag in IWPR is set to 1. A flag is not cleared automatically when the corresponding interrupt is accepted. Flags must be cleared by writing 0. Bits 7 to 0—Wakeup Interrupt Request Flags (IWPF7 to IWPF0) Bit n IWPFn When IWPFn= 1, it is cleared by writing 0 When pin WKPn is designated for wakeup input and a rising or falling edge is input at that pin (n = 7 to 0)

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 90 of 658 REJ09B0042-0800 Wakeup Edge Select Register (WEGR) Bit Initial value Read/Write WKEGS7 R/W WKEGS6 R/W WKEGS5 R/W WKEGS4 R/W WKEGS3 R/W WKEGS0 R/W WKEGS2 R/W WKEGS1 R/W WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn. WEGR is initialized to H'00 by a reset. Bit n— WKPn Edge Select (WKEGSn) Bit n selects WKPn pin input sensing. Bit n WKEGSn

0 WKPn pin falling edge detected (initial value)

1 WKPn pin rising edge detected

(n = 7 to 0)

3.3.3 External Interrupts

There are 13 external interrupts: WKP7 to WKP0, IRQ4, IRQ3, IRQ1, IRQ0, and IRQAEC. Interrupts WKP7 to WKP0 Interrupts WKP7 to WKP0 are requested by either rising or falling edge input to pins WKP7 to WKP0. When these pins are designated as pins WKP7 to WKP0 in port mode register 5 and a rising or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt. Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR. When WKP7 to WKP0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector number 9 is assigned to interrupts WKP7 to WKP0. All eight interrupt sources have the same vector number, so the interrupt-handling routine must discriminate the interrupt source.

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 91 of 658 REJ09B0042-0800 Interrupts IRQ4, IRQ3, IRQ1 and IRQ0 Interrupts IRQ4, IRQ3, IRQ1, and IRQ0 are requested by input signals to pins IRQ4, IRQ3, IRQ1, and IRQ0. These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG4, IEG3, IEG1, and IEG0 in IEGR. When these pins are designated as pins IRQ4, IRQ3, IRQ1, and IRQ0 in port mode register B, 2, and 1 and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Recognition of these interrupt requests can be disabled individually by clearing bits IEN4, IEN3, IEN1, and IEN0 to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR. When IRQ4, IRQ3, IRQ1, and IRQ0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector numbers 8, 7, 5, and 4 are assigned to interrupts IRQ4, IRQ3, IRQ1, and IRQ0. The order of priority is from IRQ0 (high) to IRQ4 (low). Table 3.2 gives details. IRQAEC Interrupt The IRQAEC interrupt is requested by an input signal to pin IRQAEC and IECPWM (output of PWM for AEC). When the IRQAEC input pin is to be used as an external interrupt, set ECPWME in AEGSR to 0. This interrupt is detected by rising edge, falling edge, or both edge sensing, depending on the settings of bits AIEGS1 and AIEGS0 in AEGSR. When bit IENEC2 in IENR1 is 1 and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. When IRQAEC interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector number 6 is assigned to the IRQAEC interrupt exception handling. Table 3.2 gives details.

3.3.4 Internal Interrupts

There are 9 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 18 and 16 to 11 are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts from on-chip peripheral modules.

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 92 of 658 REJ09B0042-0800

3.3.5 Interrupt Operations

Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance. Interrupt controllerPriority decision logic Interrupt request CCR (CPU)I External or internal interrupts External interrupts or internal interrupt enable signals Figure 3.2 Block Diagram of Interrupt Controller Interrupt operation is described as follows.

• When an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller.
• When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
• From among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (Refer to table 3.2 for a list of interrupt priorities.)
• The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is accepted; if the I bit is 1, the interrupt request is held pending.

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• If the interrupt request is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling.
• The I bit of CCR is set to 1, masking further interrupts.
• The vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (I = 1). 2. If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed.

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 94 of 658 REJ09B0042-0800 PC contents saved CCR contents saved I ← 1 I = 0 Program execution state No Yes Yes No [Legend] PC: CCR: Program counter Condition code register I bit of CCR IEN0 = 1 No Yes IENDT = 1 No Yes IRRDT = 1 No Yes Branch to interrupt handling routine IRRI0 = 1 No Yes IEN1 = 1 No Yes IRRI1 = 1 No Yes IENEC2 = 1 No Yes IRREC2 = 1 Figure 3.3 Flow up to Interrupt Acceptance

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 96 of 658 REJ09B0042-0800 Vector fetch φ Internal address bus Internal read signal Internal write signal (2)Internal data bus (16 bits) Interrupt request signal (9) (1) Internal processing Prefetch instruction of interrupt-handling routine (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP − 2 (6) SP − 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector) (10) First instruction of interrupt-handling routine (3) (9)(8)(6)(5) (4) (1) (7) (10) Stack accessInternal processing Instruction prefetch Interrupt level decision and wait for end of instruction Interrupt is accepted Figure 3.5 Interrupt Sequence

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3.3.6 Interrupt Response Time

Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item States Total Waiting time for completion of executing instruction* 1 to 13 15 to 27 Saving of PC and CCR to stack 4 Vector fetch 2 Instruction fetch 4 Internal processing 4 Note: * Not including EEPMOV instruction.

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3.4 Application Notes

3.4.1 Notes on Stack Area Use

When word data is accessed in the LSI, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6. PC PC R1L PC SP SP SP H'FEFC H'FEFD H'FEFF H L L MOV. B R1L, @−R7 SP set to H'FEFF Stack accessed beyond SP BSR instruction Contents of PC are lostH [Legend] PCH: PCL: R1L: SP: Upper byte of program counter Lower byte of program counter General register R1L Stack pointer Figure 3.6 Operation when Odd Address is Set in SP When CCR contents are saved to the stack during interrupt exception handling or restored when RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to CCR while the odd address contents are ignored.

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3.4.2 Notes on Rewriting Port Mode Registers

When a port mode register is rewritten to switch the functions of external interrupt pins and when the value of ECPWME in AEGSR is rewritten to switch between selection/non-selection of IRQAEC, the following points should be observed. When an external interrupt pin function is switched by rewriting the port mode register that controls pins IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt request flag to 0 after switching pin functions. When the value of ECPWME in AEGSR that sets selection/non-selection of IRQAEC is rewritten, the interrupt request flag may be set to 1, even if a valid edge has not arrived on the selected IRQAEC or IECPWM (PWM output for AEC). Therefore, be sure to clear the interrupt request flag to 0 after switching the pin function. Table 3.5 shows the conditions under which interrupt request flags are set to 1 in this way. Table 3.5 Conditions under which Interrupt Request Flag is Set to 1 Interrupt Request Flags Set to 1 Conditions IRR1 IRRI4 When PMR1 bit IRQ4 is changed from 0 to 1 while pin IRQ4 is low and IEGR bit IEG4 = 0. When PMR1 bit IRQ4 is changed from 1 to 0 while pin IRQ4 is low and IEGR bit IEG4 = 1. IRRI3 When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR bit IEG3 = 0. When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR bit IEG3 = 1. IRREC2 When an edge as designated by AIEGS1 and AIEGS0 in AEGSR is detected because the values on the IRQAEC pin and of IECPWM at switching are different (e.g., when the rising edge has been selected and ECPWME in AEGSR is changed from 1 to 0 while pin IRQAEC is low and IECPWM = 1). IRRI1 When PMRB bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR bit IEG1 = 0. When PMRB bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR bit IEG1 = 1. IRRI0 When PMR2 bit IRQ0 is changed from 0 to 1 while pin IRQ0 is low and IEGR bit IEG0 = 0. When PMR2 bit IRQ0 is changed from 1 to 0 while pin IRQ0 is low and IEGR bit IEG0 = 1.

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 100 of 658 REJ09B0042-0800 Interrupt Request Flags Set to 1 Conditions IWPR IWPF7 When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low and WEGR bit WKEGS7 = 0. When PMR5 bit WKP7 is changed from 1 to 0 while pin WKP7 is low and WEGR bit WKEGS7 = 1. IWPF6 When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low and WEGR bit WKEGS6 = 0. When PMR5 bit WKP6 is changed from 1 to 0 while pin WKP6 is low and WEGR bit WKEGS6 = 1. IWPF5 When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5 is low and WEGR bit WKEGS5 = 0. When PMR5 bit WKP5 is changed from 1 to 0 while pin WKP5 is low and WEGR bit WKEGS5 = 1. IWPF4 When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4 is low and WEGR bit WKEGS4 = 0. When PMR5 bit WKP4 is changed from 1 to 0 while pin WKP4 is low and WEGR bit WKEGS4 = 1. IWPF3 When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3 is low and WEGR bit WKEGS3 = 0. When PMR5 bit WKP3 is changed from 1 to 0 while pin WKP3 is low and WEGR bit WKEGS3 = 1. IWPF2 When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low and WEGR bit WKEGS2 = 0. When PMR5 bit WKP2 is changed from 1 to 0 while pin WKP2 is low and WEGR bit WKEGS2 = 1. IWPF1 When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP1 is low and WEGR bit WKEGS1 = 0. When PMR5 bit WKP1 is changed from 1 to 0 while pin WKP1 is low and WEGR bit WKEGS1 = 1. IWPF0 When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP0 is low and WEGR bit WKEGS0 = 0. When PMR5 bit WKP0 is changed from 1 to 0 while pin WKP0 is low and WEGR bit WKEGS0 = 1. Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register (or AEGSR). After accessing the port mode register (or AEGSR), execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag is

Section 3 Exception Handling Rev. 8.00 Mar. 09, 2010 Page 101 of 658 REJ09B0042-0800 executed immediately after the port mode register (or AEGSR) access without executing an intervening instruction, the flag will not be cleared. An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur. However, the procedure in Figure 3.7 is recommended because IECPWM is an internal signal and determining its value is complicated. CCR I bit 1 Set port mode register (or AEGSR) bit Execute NOP instruction Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.) After setting the port mode register (or AEGSR) bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0 Interrupt mask cleared Clear interrupt request flag to 0 CCR I bit 0← Figure 3.7 Port Mode Register (or AEGSR) Setting and Interrupt Request Flag Clearing Procedure

3.4.3 Method for Clearing Interrupt Request Flags

Use the recommended method, given below when clearing the flags of interrupt request registers (IRR1, IRR2, IWPR).

• Recommended method Use a single instruction to clear flags. The bit control instruction and byte-size data transfer instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 of IRR1) are given below. BCLR #1, @IRR1:8 MOV.B R1L, @IRR1:8 (set the value of R1L to B'11111101)

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• Example of a malfunction When flags are cleared with multiple instructions, other flags might be cleared during execution of the instructions, even though they are currently set, and this will cause a malfunction. Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1 (bit 1 of IRR1). In the above example, it is assumed that an IRQ0 interrupt is generated while the AND.B instruction is executing. The IRQ0 interrupt is disabled because, although the original objective is clearing IRRI1, IRRI0 is also cleared.

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 103 of 658 REJ09B0042-0800 Section 4 Clock Pulse Generators

4.1 Overview

Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. In the H8/38124 Group, the system clock pulse generator includes an on-chip oscillator.

4.1.1 Block Diagram

Figure 4.1 shows a block diagram of the clock pulse generators of the H8/38024, H8/38024S, and H8/38024R Group. Figure 4.2 shows a block diagram of the clock pulse generators of the H8/38124 Group. System clock oscillator System clock divider (1/2) Subclock oscillator Subclock divider (1/2, 1/4, 1/8) System clock divider System clock pulse generator Subclock pulse generator Prescaler S (13 bits) Prescaler W (5 bits) OSC OSC X X φOSC (fOSC) φW φW (fW) φOSC/2 φW/2 φW/8 φSUB φ/2 to φ/8192 φ W/2 φW/4 φW/8 to φW/128 φφOSC/128 φOSC/64 φOSC/32 φOSC/16 φW/4 Figure 4.1(1) Block Diagram of Clock Pulse Generators (H8/38024 Group, H8/38024S Group, H8/38024R Group)

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 104 of 658 REJ09B0042-0800 System clock oscillator Subclock oscillator Subclock divider (1/2, 1/4, 1/8) System clock divider (1/2) System clock divider Prescaler S (13 bits) Prescaler W (5 bits) OSC1 Latch On-chip oscillator Internal reset signal (other than watchdog timer or low-voltage detect circuit reset) C DQIRQAEC OSC2 System clock pulse generator Subclock pulse generator φOSC (fOSC) ROSC φW (fW) φW/2 φW/4 φSUB φW φ/2 to φ/8192 φ φW/2 φW/4 φW/8 to φW/128 φW/8 φOSC/2 φOSC/16 φOSC/32 φOSC/64 φOSC/128 Figure 4.2 Block Diagram of Clock Pulse Generators (H8/38124 Group)

4.1.2 System Clock and Subclock

The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φSUB. Four of the clock signals have names: φ is the system clock, φSUB is the subclock, φOSC is the oscillator clock, and φW is the watch clock. The clock signals available for use by peripheral modules are φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, and φW/128. The clock requirements differ from one module to another.

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4.1.3 Register Descriptions

Table 4.1 lists the registers that control the clock pulse generators. The registers listed in table 4.1 are only implemented in the H8/38124 Group. Table 4.1 Clock Pulse Generator Control Registers Name Abbreviation R/W Initial Value Address Clock pulse generator control register OSCCR R/W — H'FFF5 Clock Pulse Generator Control Register (OSCCR) Bit 7 6 5 4 3 2 1 0 SUBSTP — — — — IRQAECF OSCF — Initial value 0 0 0 0 0 — — 0 Read/Write R/W R R/W R/W R/W R R R/W OSCCR is an 8-bit read/write register that contains the flag indicating the selection of system clock oscillator or on-chip oscillator, indicates the input level of the IRQAEC pin during resets, and controls whether the subclock oscillator operates or not. Bit 7—Subclock Oscillator Stop Control (SUBSTP) Bit 7 controls whether the subclock oscillator operates or not. It can be set to 1 only in the active mode (high-speed/medium-speed). Setting bit 7 to 1 in the subactive mode will cause the LSI to stop operating. Bit 7 SUBSTP

0 Subclock oscillator operates (initial value)

1 Subclock oscillator stopped

Bit 6—Reserved This bit is reserved. It is always read as 0 and cannot be written to. Bits 5 to 3—Reserved These bits are read/write enabled reserved bits.

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 106 of 658 REJ09B0042-0800 Bit 2—IRQAEC Flag (IRQAECF) This bit indicates the IRQAEC pin input level set during resets. Bit 2 IRQAECF

0 IRQAEC pin set to GND during resets

1 IRQAEC pin set to V CC during resets

Bit 1—OSC Flag (OSCF) This bit indicates the oscillator operating with the system clock pulse generator. Bit 1 OSCF

0 System clock oscillator operating (on-chip oscillator stopped)

1 On-chip oscillator operating (system clock oscillator stopped)

Bit 0—Reserved This bit is reserved. Never write 1 to this bit, as it can cause the LSI to malfunction.

4.2 System Clock Generator

Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. As shown in figure 4.2, the H8/38124 Group supports selection between a system clock oscillator and an on-chip oscillator. See section 4.2, On-Chip Oscillator Selection Method, for information on selecting the on-chip oscillator. Connecting a Crystal Oscillator Figure 4.3(1) shows a typical method of connecting a crystal oscillator to the H8/38024 or H8/38024R Group, and figure 4.3(2) shows a typical method of connecting a crystal oscillator to the H8/38024S and H8/38124 Group.

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 107 of 658 REJ09B0042-0800 OSC1 OSC2 R = 1 M ±20%f Ω Rf Frequency Note: Circuit constants should be determined in consultation with the resonator manufacturer. Crystal oscillator C1, C2 Recommendation value 12 pF ±20%NDK4.19 MHz Figure 4.3(1) Typical Connection to Crystal Oscillator (H8/38024, H8/38024R Group) OSC1 OSC2 Frequency Crystal oscillator C1, C2 Recommendation value Products name Rf R = 1 M ±20%f Ω

4.0 MHz NDK NR-18 12 pF ±20%

Note: Circuit constants should be determined in consultation with the resonator manufacturer. Figure 4.3(2) Typical Connection to Crystal Oscillator (H8/38024S, H8/38124 Group) Figure 4.3 shows the equivalent circuit of a crystal oscillator. An oscillator having the characteristics given in table 4.2 should be used. CS RS OSC1 OSC2 LS Figure 4.4 Equivalent Circuit of Crystal Oscillator

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 108 of 658 REJ09B0042-0800 Table 4.2 Crystal Oscillator Parameters Frequency (MHz) 4 4.193 RS max (Ω) 100 100 C0 max (pF) 16 16 Connecting a Ceramic Oscillator Figure 4.5(1) shows a typical method of connecting a ceramic oscillator to the H8/38024 or H8/38024R Group, and figure 4.5(2) shows a typical method of connecting a crystal oscillator to the H8/38024S and H8/38124 Group. OSC OSC Rf R = 1 M ±20%f Ω Frequency Ceramic oscillator

4.0 MHz Murata 30 pF ±10%

C1, C2 Recommendation value Figure 4.5(1) Typical Connection to Ceramic Oscillator (H8/38024, H8/38024R Group) Frequency

2.0 MHz

10.0 MHz

16.0 MHz*1

20.0 MHz*2

Rf = 1 MΩ ±20%OSC1 OSC2 Rf CSTCC2M00G53-B0 CSTCC2M00G56-B0 CSTLS10M0G53-B0 CSTLS10M0G56-B0 CSTLS16M0X53-B0 CSTLS20M0X53-B0 15 pF ±20% 47 pF ±20% 15 pF ±20% 47 pF ±20% 15 pF ±20% 15 pF ±20% C1, C2 Recommendation value Notes: Circuit constants should be determined in consultation with the resonator manufacturer. 1. This does not apply to the H8/38024S Group. 2. H8/38124 Group only Figure 4.5(2) Typical Connection to Ceramic Oscillator (H8/38024S, H8/38124 Group)

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 109 of 658 REJ09B0042-0800 Notes on Board Design When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (See figure 4.6.) The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2. OSC OSC Signal A Signal B To be avoided ×× Figure 4.6 Board Design of Oscillator Circuit Note: The circuit parameters above are recommended by the crystal or ceramic oscillator manufacturer. The circuit parameters are affected by the crystal or ceramic oscillator and floating capacitance when designing the board. When using the oscillator, consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters.

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 110 of 658 REJ09B0042-0800 External Clock Input Method Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.7 shows a typical connection. OSC1 OSC2 External clock input Open Figure 4.7 External Clock Input (Example) Frequency Oscillator Clock ( φOSC) Duty cycle 45% to 55% On-Chip Oscillator Selection Method (H8/38124 Group Only) The on-chip oscillator is selected by setting the IRQAEC pin input level during resets.* Table 4.3 lists the methods for selecting the system clock oscillator and the on-chip oscillator. The IRQAEC pin input level set during resets must be fixed at VCC or GND, based on the oscillator to be selected. It is not necessary to connect an oscillator to pins OSC1 and OSC2 if the on-chip oscillator is selected. In this case, pin OSC1 should be fixed at VCC or GND. Note: The system clock oscillator must be selected in order to program or erase flash memory as part of operations such as on-board programming. Also, when using the on-chip emulator, an oscillator should be connected, or an external clock input, even if the on-chip oscillator is selected. * Other than watchdog timer or low-voltage detect circuit reset. Table 4.3 System Clock Oscillator and On-Chip Oscillator Selection Methods IRQAEC pin input level (during resets) 0 1 System clock oscillator Enabled Disabled On-chip oscillator Disabled Enabled

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4.3 Subclock Generator

Connecting a 32.768 kHz/38.4 kHz Crystal Oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz/38.4 kHz crystal oscillator, as shown in figure 4.8. Follow the same precautions as noted under 3. notes on board design for the system clock in section 4.2. Note that only operation at 32.768 kHz is guaranteed on the H8/38124 Group. X X C = C = 7 pF (typ.)1 2 Frequency 32.768 kHz* Crystal oscillator EPSON TOYOCOM. Products Name C-001R Motion Resistance 35 kΩ max Notes: Circuit constants should be detemined in consultation with the resonator manufacture. * H8/38124 Group only. C = C = 15 pF (typ.)1 2 Frequency 38.4 kHz 32.768 kHz Crystal oscillator Seiko Instruments Inc. Nihon Denpa Kogyo Products Name VTC-200 MX73P Figure 4.8 Typical Connection to 32.768 kHz/38.4 kHz Crystal Oscillator (Subclock) Figure 4.9 shows the equivalent circuit of the 32.768 kHz/38.4 kHz crystal oscillator. CS LR S X1 X2 C = 1.5 pF typ R = 14 k typ f = 32.768 kHz/38.4 kHz S W Ω S Figure 4.9 Equivalent Circuit of 32.768 kHz/38.4 kHz Crystal Oscillator

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 113 of 658 REJ09B0042-0800 Frequency Subclock ( φw) Duty 45% to 55% Method for Disabling Subclock Oscillator (H8/38124 Group Only) The subclock oscillator can be disabled by programs by setting the SUBSTP bit in the OSCCR register to 1. The register setting to disable the subclock oscillator should be made in the active mode. When restoring operation of the subclock oscillator after it has been disabled using the OSCCR register, it is necessary to wait for the oscillation stabilization time (typ: 8s) to elapse before using the subclock.

4.4 Prescalers

The H8/38024 Group is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a 5-bit counter using a 32.768 kHz or 38.4 kHz signal divided by 4 ( φ W/4) as its input clock. Its prescaled outputs are used by timer A as a time base for timekeeping. Prescaler S (PSS) Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by timer A, timer C, timer F, timer G, SCI3, the A/D converter, the LCD controller, watchdog timer, and the 10-bit PWM. The divider ratio can be set separately for each on-chip peripheral function. In active (medium-speed) mode the clock input to prescaler S is φosc/16, φosc/32, φosc/64, or φosc/128.

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 114 of 658 REJ09B0042-0800 Prescaler W (PSW) Prescaler W is a 5-bit counter using a 32.768 kHz/38.4 kHz signal divided by 4 ( φW/4) as its input clock. Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins X1 and X2. Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA). Output from prescaler W can be used to drive timer A, in which case timer A functions as a time base for timekeeping.

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4.5 Note on Oscillators

Oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask ROM and ZTAT versions, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the oscillator element manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding its maximum rating. (Vss) P17 Vss OSC2 OSC1 TEST Figure 4.12 Example of Crystal and Ceramic Oscillator Element Arrangement Figure 4.13 (1) shows an example measuring circuit with the negative resistance suggested by the resonator manufacturer. Note that if the negative resistance of the circuit is less than that suggested by the resonator manufacturer, it may be difficult to start the main oscillator. If it is determined that oscillation is not occurring because the negative resistance is lower than the level suggested by the resonator manufacturer, the circuit may be modified as shown in figure 4.13 (2) through (4). Which of the modification suggestions to use and the capacitor capacitance should be decided based upon an evaluation of factors such as the negative resistance and the frequency deviation.

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 116 of 658 REJ09B0042-0800 (1) Negative Resistance Measuring Circuit (2) Oscillator Circuit Modification Suggestion 1 (3) Oscillator Circuit Modification Suggestion 2 (4) Oscillator Circuit Modification Suggestion 3 OSC1 OSC2 Rf Negative resistance, addition of −R OSC1 OSC2 Rf Modification point Modification point Modification point OSC1 OSC2 Rf OSC1 OSC2 Rf Figure 4.13 Negative Resistance Measurement and Circuit Modification Suggestions

4.5.1 Definition of Oscillation Stabilization Wait Time

Figure 4.14 shows the oscillation waveform (OSC2), system clock (φ), and microcomputer operating mode when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock oscillator. As shown in figure 4.13, as the system clock oscillator is halted in standby mode, watch mode, and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the sum of the following two times (oscillation stabilization time and wait time) is required.

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 117 of 658 REJ09B0042-0800 1. Oscillation stabilization time (t rc) The time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes. 2. Wait time The time required for the CPU and peripheral functions to begin operating after the oscillation waveform frequency and system clock have stabilized. The wait time setting is selected with standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in system control register 1 (SYSCR1)). Oscillation waveform (OSC2) System clock (φ) Oscillation stabilization time Operating mode Standby mode, watch mode, or subactive mode Wait time Oscillation stabilization wait time Active (high-speed) mode or active (medium-speed) mode Interrupt accepted Figure 4.14 Oscillation Stabilization Wait Time When standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to change at the point at which the interrupt is accepted. Therefore, when an oscillator element is connected in standby mode, watch mode, or subactive mode, since the system clock oscillator is halted, the time from the point at which this oscillation waveform starts to change until the

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 118 of 658 REJ09B0042-0800 amplitude of the oscillation waveform increases and the oscillation frequency stabilizes—that is, the oscillation stabilization time—is required. The oscillation stabilization time in the case of these state transitions is the same as the oscillation stabilization time at power-on (the time from the point at which the power supply voltage reaches the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time t rc" in the AC characteristics. Meanwhile, once the system clock has halted, a wait time of at least 8 states is necessary in order for the CPU and peripheral functions to operate normally. Thus, the time required from interrupt generation until operation of the CPU and peripheral functions is the sum of the above described oscillation stabilization time and wait time. This total time is called the oscillation stabilization wait time, and is expressed by equation (1) below. Oscillation stabilization wait time = oscillation stabilization time + wait time = t (up to 131,072 states) *2 Notes: 1. H8/38024 Group 2. H8/38124 Group Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock oscillator, careful evaluation must be carried out on the installation circuit before deciding on the oscillation stabilization wait time. In particular, since the oscillation stabilization time is affected by installation circuit constants, stray capacitance, and so forth, suitable constants should be determined in consultation with the oscillator element manufacturer. Element) When a microcomputer operates, the internal power supply potential fluctuates slightly in synchronization with the system clock. Depending on the individual crystal oscillator element characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation stabilization wait time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential. In this state, the oscillation waveform may be disrupted, leading to an unstable system clock and erroneous operation of the microcomputer. If erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in system control register 1 (SYSCR1)) to give a longer wait time.

Section 4 Clock Pulse Generators Rev. 8.00 Mar. 09, 2010 Page 119 of 658 REJ09B0042-0800 For example, if erroneous operation occurs with a wait time setting of 16 states, check the operation with a wait time setting of 1,024* states or more. If the same kind of erroneous operation occurs after a reset as after a state transition, hold the RES pin low for a longer period. Note: * This figure applies to the H8/38024, H8/38024S, and H8/38024R Groups. The number of states on the H8/38124 Group is 8,192 or more.

4.5.3 Note on Use of HD64F38024

When using the HD64F38024, the oscillators may not operate if an initial voltage of 10 mV is applied to the VCC pin during power-on. This problem is caused by uncertainty about the state of the oscillation control signals. It can be corrected by cutting off power and allowing the V CC pin voltage to drop to ground potential before powering-on once again.

4.6 Notes on H8/38124 Group

When using the on-chip emulator, system clock precision is necessary for programming or erasing the flash memory. However, the on-chip oscillator frequency can vary due to changes in conditions such as voltage or temperature. Consequently, even if the on-chip oscillator is selected when using the on-chip emulator, pins OSC1 and OSC2 should be connected to an oscillator, or an external clock should be supplied. In this case, the LSI uses the on-chip oscillator when user programs are being executed and the system clock oscillator when programming or erasing flash memory. The process is controlled by the on-chip emulator.

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Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 121 of 658 REJ09B0042-0800 Section 5 Power-Down Modes

5.1 Overview

The LSI has nine modes of operation after a reset. These include eight power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the nine operating modes. Table 5.1 Operating Modes Operating Mode Description Active (high-speed) mode The CPU and all on-chip peripheral functions are operable on the system clock in high-speed operation Active (medium-speed) mode The CPU and all on-chip peripheral functions are operable on the system clock in low-speed operation Subactive mode The CPU and all on-chip peripheral functions are operable on the subclock in low-speed operation Sleep (high-speed) mode The CPU halts. On-chip peripheral functions are operable on the system clock Sleep (medium-speed) mode The CPU halts. On-chip peripheral functions operate at a frequency of 1/128, 1/64, 1/32, or 1/16 of the system clock frequency Subsleep mode The CPU halts. The time-base function of timer A, timer C, timer F, timer G, SCI3, AEC, and LCD controller/driver are operable on the subclock Watch mode The CPU halts. The time-base function of timer A, timer F, timer G, AEC and LCD controller/driver are operable on the subclock Standby mode The CPU and all on-chip peripheral functions halt Module standby mode Individual on-chip peripheral functions specified by software enter standby mode and halt Of these nine operating modes, all but the active (high-speed) mode are power-down modes. In this section the two active modes (high-speed and medium speed) will be referred to collectively as active mode. Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal states in each mode.

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 122 of 658 REJ09B0042-0800 Program halt state SLEEP instruction*e SLEEP instruction*c SLEEP instruction*h SLEEP instruction*i SLEEP instruction*g SLEEP instruction*f Program execution state SLEEP instruction*a Program halt state SLEEP instruction Power-down modes A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that interrupts are enabled. Details on the mode transition conditions are given in the explanations of each mode, in sections 5.2 to 5.8. Notes: 1. Mode Transition Conditions (1) LSON MSON SSBY DTON *: Don't care Mode Transition Conditions (2) Interrupt Sources Timer A, Timer F, Timer G interrupt, IRQ0 interrupt, WKP7 to WKP0 interrupts Timer A, Timer C, Timer F, Timer G, SCI3 interrupt, IRQ4, IRQ3, IRQ1 and IRQ0 interrupts, IRQAEC, WKP7 to WKP0 interrupts, AEC All interrupts IRQ1 or IRQ0 interrupt, WKP7 to WKP0 interrupts *2*1 Standby mode Watch mode Subactive mode Active (medium-speed) mode Active (high-speed) mode Sleep (high-speed) mode Sleep (medium-speed) mode Subsleep mode SLEEP instruction SLEEP instruction SLEEP instruction SLEEP instruction*b SLEE P instruction SLE EP instruct ion SLEE P instructio n*b TMA3 SLEEP instruction Reset state Figure 5.1 Mode Transition Diagram

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 123 of 658 REJ09B0042-0800 Table 5.2 Internal State in Each Operating Mode Active Mode Sleep Mode Function High- Speed Medium- Speed High- Speed Medium- Speed Watch Mode Subactive Mode Subsleep Mode Standby Mode System clock oscillator Functions Functions Functions Functions Halted Halted Halted Halted Subclock oscillator Functions Functions Functions Functions Functions Functions Functions Functions Instructions Functions Functions Halted Halted Halted Functions Halted Halted CPU operations RAM Retained Retained Retained Retained Retained Registers I / O p o r t s R e t a i n e d *1 IRQ0 Functions Functions Functions Functions F unctions Functions Functions Functions External interrupts IRQ1 R e t a i n e d *6 I R Q A E C R e t a i n e d *6 IRQ 3 IRQ 4 WKP 0 Functions Functions Functions Functions Functions Functions Functions Functions WKP 1 WKP 2 WKP 3 WKP 4 WKP 5 WKP 6 WKP 7 Timer A Functions Functions Functions Functions Functions *5 Functions*5 Functions*5 Retained Peripheral functions Asynchronous event counter F u n c t i o n s *8 Functions Functions Functions *8 T i m e r C R e t a i n e d F u n c t i o n s / Retained*2 Functions/ Retained*2 Retained W D T F u n c t i o n s / Retained*10 Functions/ Retained*7 Functions/ Retained*10 Functions/ Retained*11 Timer F Timer G F u n c t i o n s / Retained*9 Functions/ Retained*9 Functions/ Retained*9 Retained SCI3 Reset Functions/ Retained*3 Functions/ Retained*3 Reset PWM Retained Retained Retained Retained A/D converter Retained Retained Retained Retained L C D F u n c t i o n s / Retained*4 Functions/ Retained*4 Functions/ Retained*4 Retained LVD Functions Functions Functions Function s Functions Functions Functions Functions Notes: 1. Register contents are retained, but output is high-impedance state. Port 5 of the HD64F38024 retains the previous pin state. 2. Functions if an external clock or the φW/4 internal clock is selected; otherwise halted and retained. 3. Functions if φW/2 is selected as the internal clock; otherwise halted and retained. 4. Functions if φW, φW/2 or φW/4 is selected as the operating clock; otherwise halted and retained. 5. Functions if the timekeeping time-base function is selected. 6. External interrupt requests are ignored. Interrupt request register contents are not altered. 7. On the H8/38124 Group, operates when φ W/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38024, H8/38024S, and H8/38024R Group, operates when φW/32 is selected as the internal clock; otherwise stops and stands by. 8. Incrementing is possible, but interrupt generation is not. 9. Functions if φ W/4 is selected as the internal clock; otherwise halted and retained. 10. On the H8/38124 Group, operates when φW/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38024, H8/38024S, and H8/38024R Group, stops and stands by.

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 124 of 658 REJ09B0042-0800 11. On the H8/38124 Group, operates only when the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38024, H8/38024S, and H8/38024R Group, stops and stands by.

5.1.1 System Control Registers

The operation mode is selected using the system control registers described in table 5.3. Table 5.3 System Control Registers Name Abbreviation R/W Initial Value Address System control register 1 SYSCR1 R/W H'07 H'FFF0 System control register 2 SYSCR2 R/W H'F0 H'FFF1 System Control Register 1 (SYSCR1) Bit Initial value Read/Write SSBY R/W STS2 R/W STS1 R/W STS0 R/W LSON R/W MA0 R/W MA1 R/W SYSCR1 is an 8-bit read/write register for control of the power-down modes. Upon reset, SYSCR1 is initialized to H'07. Bit 7—Software Standby (SSBY) This bit designates transition to standby mode or watch mode. Bit 7 SSBY 0 • When a SLEEP instruction is executed in active mode, (initial value) a transition is made to sleep mode

• When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode 1 • When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 125 of 658 REJ09B0042-0800 Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation stabilization time. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024R Group and for the H8/38124 Group are different.

• H8/38024, H8/38024S, H8/38024R Group Bit 6 STS2 Bit 5 STS1 Bit 4 STS0

0 0 0 Wait time = 8,192 states (initial value) 0 0 1 Wait time = 16,384 states 0 1 0 Wait time = 1,024 states 0 1 1 Wait time = 2,048 states 1 0 0 Wait time = 4,096 states 1 0 1 Wait time = 2 states (External clock input mode) 1 1 0 Wait time = 8 states 1 1 1 Wait time = 16 states

• H8/38124 Group Bit 6 STS2 Bit 5 STS1 Bit 4 STS0

0 0 0 Wait time = 8,192 states (initial value) 0 0 1 Wait time = 16,384 states 0 1 0 Wait time = 32,768 states 0 1 1 Wait time = 65,536 states 1 0 0 Wait time = 131,072 states 1 0 1 Wait time = 2 states (External clock input mode) 1 1 0 Wait time = 8 states 1 1 1 Wait time = 16 states Note: If an external clock is being input, set standby timer select to external clock mode before mode transition. Also, do not set standby timer select to external clock mode if no external clock is used. 8,192 states (STS2 = STS1 = STS0 = 0) is recommended if the on-chip oscillator is used on the H8/38124 Group.

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 126 of 658 REJ09B0042-0800 Bit 3—Low Speed on Flag (LSON) This bit chooses the system clock (φ) or subclock (φSUB) as the CPU operating clock when watch mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input. Bit 3 LSON

0 The CPU operates on the system clock ( φ) (initial value)

1 The CPU operates on the subclock ( φSUB)

Bit 2—Reserved Bit 2 is reserved: it is always read as 1 and cannot be modified. Bits 1 and 0—Active (Medium-Speed) Mode Clock Select (MA1, MA0) Bits 1 and 0 choose φ osc/128, φosc/64, φosc/32, or φosc/16 as the operating clock in active (medium- speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high- speed) mode or subactive mode. Bit 1 MA1 Bit 0 MA0 0 0 φosc/16 0 1 φosc/32 1 0 φosc/64 1 1 φosc/128 (initial value) System Control Register 2 (SYSCR2) Bit Initial value Read/Write NESEL R/W DTON R/W SA0 R/W MSON R/W SA1 R/W SYSCR2 is an 8-bit read/write register for power-down mode control. Bits 7 to 5—Reserved These bits are reserved; they are always read as 1, and cannot be modified.

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 127 of 658 REJ09B0042-0800 Bit 4—Noise Elimination Sampling Frequency Select (NESEL) This bit selects the frequency at which the watch clock signal (φW) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (φOSC) generated by the system clock pulse generator. When φOSC = 2 to 20 MHz, clear NESEL to 0. Bit 4 NESEL

0 Sampling rate is φOSC/16

1 Sampling rate is φOSC/4 (initial value)

Bit 3—Direct Transf er on Flag (DTON) This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of other control bits. Bit 3 DTON 0 • When a SLEEP instruction is executed in active mode, (initial value) a transition is made to standby mode, watch mode, or sleep mode

• When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode 1 • When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1 Bit 2—Medium Speed on Flag (MSON) After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode.

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 128 of 658 REJ09B0042-0800 Bit 2 MSON

0 Operation in active (high-speed) mode (initial value)

1 Operation in active (medium-speed) mode

Bits 1 and 0—Subactive Mode Clock Select (SA1, SA0) These bits select the CPU clock rate (φW/2, φW/4, or φW/8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1 SA1 Bit 0 SA0 0 0 φW/8 (initial value) 0 1 φW/4 1 * φW/2 *: Don’t care

5.2 Sleep Mode

5.2.1 Transition to Sleep Mode

1. Transition to sleep (high-speed) mode The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON and DTON bits in SYSCR2 are cleared to 0. In sleep mode CPU operation is halted but the on-chip peripheral functions. CPU register contents are retained. 2. Transition to sleep (medium-speed) mode The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed) mode, as in sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral functions are operational. The clock frequency in sleep (medium-speed) mode is determined by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained. Furthermore, it sometimes acts with half state early timing at the time of transition to sleep (medium-speed) mode.

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5.2.2 Clearing Sleep Mode

Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous event counter, IRQAEC, IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, SCI3, A/D converter), or by input at the RES pin.

• Clearing by interrupt When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep (medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt enable register. To synchronize the interrupt request signal with the system clock, up to 2/φ(s) delay may occur after the interrupt request signal occurrence, before the interrupt exception handling start.
• Clearing by RES input When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.

5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode

Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1.

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5.3 Standby Mode

5.3.1 Transition to Standby Mode

The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O ports go to the high-impedance state. Port 5 of the HD64F38024 retains the previous pin state.

5.3.2 Clearing Standby Mode

Standby mode is cleared by an interrupt (IRQ 1 or IRQ0), WKP7 to WKP0 or by input at the RES pin.

• Clearing by interrupt When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. Operation resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON = 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register.
• Clearing by RES input When the RES pin goes low, the system clock pulse generator starts. After the pulse generator output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin should be kept at the low level until the pulse generator output stabilizes.

5.3.3 Oscillator Stabilization Time after Standby Mode Is Cleared

Bits STS2 to STS0 in SYSCR1 should be set as follows. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024R Group and for the H8/38124 Group are different.

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• When a oscillator is used The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a wait time at least as long as the oscillation stabilization time. Table 5.4(1) Clock Frequency and Stabilization Time (H8/38024, H8/38024S, H8/38024R Group) (Unit: ms) STS2 STS1 STS0 Wait Time 5 MHz 2 MHz 0 0 0 8,192 states 1.638 4.1 1 16,384 states 3.277 8.2 1 0 1,024 states 0.205 0.512 1 2,048 states 0.410 1.024 1 0 0 4,096 states 0.819 2.048 1 2 states (Use prohibited with other than external clock) 0.0004 0.001 1 0 8 states 0.002 0.004 1 16 states 0.003 0.008 Table 5.4(2) Clock Frequency and Stabilization Time (H8/38124 Group) (Unit: ms) STS2 STS1 STS0 Wait Time 5 MHz 2 MHz 0 0 0 8,192 states 1.638 4.1 1 16,384 states 3.277 8.2 1 0 32,768 states 6.554 16.4 1 65,536 states 13.108 32.8 1 0 0 131,072 states 26.216 65.5 1 2 states (Use prohibited with other than external clock) 0.0004 0.001 1 0 8 states 0.002 0.004 1 16 states 0.003 0.008
• When an external clock is used STS2 = 1, STS1 = 0, and STS0 = 1 should be set. Other values possible use, but CPU sometimes will start operation before wait time completion.

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• When the on-chip oscillator is used 8,192 states (STS2 = STS1 = STS0 = 0) is recommended if the on-chip oscillator is used on the H8/38124 Group.

5.3.4 Standby Mode Transition and Pin States

When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed) mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the high- impedance state (except pins for which the pull-up MOS is designated as on). Port 5 of the HD64F38024 retains the previous pin state. Figure 5.2 shows the timing in this case. SLEEP instruction fetch Internal data bus Fetch of next instruction Port outputPins High-impedance Active (high-speed) mode or active (medium-speed) mode Standby mode SLEEP instruction execution Internal processing φ Figure 5.2 Standby Mode Transition and Pin States

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5.3.5 Notes on External Input Signal Changes before/after Standby Mode

1. When external input signal changes before/after standby mode or watch mode When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and low-level widths of the signal must be at least two cycles of system clock φ or subclock φSUB (referred to together in this section as the internal clock). As the internal clock stops in standby mode and watch mode, the width of external input signals requires careful attention when a transition is made via these operating modes. Ensure that external input signals conform to the conditions stated in 3, Recommended timing of external input signals, below 2. When external input signals cannot be captured because internal clock stops The case of falling edge capture is illustrated in figure 5.3. As shown in the case marked "Capture not possible," when an external input signal falls immediately after a transition to active (high-speed or medium-speed) mode or subactive mode, after oscillation is started by an interrupt via a different signal, the external input signal cannot be captured if the high-level width at that point is less than 2 t cyc or 2 tsubcyc. 3. Recommended timing of external input signals To ensure dependable capture of an external input signal, high- and low-level signal widths of at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as shown in “Capture possible: case 1” in figure 5.3. External input signal capture is also possible with the timing shown in “Capture possible: case 2” and “Capture possible: case 3” in figure 5.3, in which a 2 tcyc or 2 tsubcyc level width is secured.

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 134 of 658 REJ09B0042-0800 tcyc tsubcyc Operating mode φ or φSUB Capture possible: case 1 Capture possible: case 2 Capture possible: case 3 Capture not possible Interrupt by different signal External input signal Active (high-speed, medium-speed) mode or subactive mode Active (high-speed, medium-speed) mode or subactive mode Standby mode or watch mode Wait for oscillation to settle tcyc tsubcyc tcyc tsubcyc tcyc tsubcyc Figure 5.3 External Input Signal Capture when Signal Changes before/after Standby Mode or Watch Mode 4. Input pins to which these notes apply: IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, IRQAEC, TMIC, TMIF, TMIG, ADTRG.

5.4 Watch Mode

5.4.1 Transition to Watch Mode

The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F, timer G, AEC and the LCD controller/driver (for which operation or halting can be set) is halted. As long as a minimum required voltage is applied, the contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules, are retained. I/O ports keep the same states as before the transition.

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5.4.2 Clearing Watch Mode

Watch mode is cleared by an interrupt (timer A, timer F, timer G, IRQ0, or WKP7 to WKP0) or by input at the RES pin.

• Clearing by interrupt When watch mode is cleared by interrupt, the mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition is to active (medium-speed) mode; if LSON = 1, transition is to subactive mode. When the transition is to active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. Watch mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register.
• Clearing by RES input Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in section 5.3.2, Clearing Standby Mode.

5.4.3 Oscillator StabilizationTime after Watch Mode Is Cleared

The wait time is the same as for standby mode; see section 5.3.3, Oscillator Stabilization Time after Standby Mode is Cleared.

5.4.4 Notes on External Input Signal Changes before/after Watch Mode

See section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode.

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5.5 Subsleep Mode

5.5.1 Transition to Subsleep Mode

The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D converter and PWM is in active state. As long as a minimum required voltage is applied, the contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition.

5.5.2 Clearing Subsleep Mode

Subsleep mode is cleared by an interrupt (timer A, timer C, timer F, timer G, asynchronous event counter, SCI3, IRQAEC, IRQ 4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0) or by a low input at the RES pin.

• Clearing by interrupt When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. To synchronize the interrupt request signal with the system clock, up to 2/φSUB(s) delay may occur after the interrupt request signal occurrence, before the interrupt exception handling start.
• Clearing by RES input Clearing by RES pin is the same as for standby mode; see Clearing by RES pin in section 5.3.2, Clearing Standby Mode.

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5.6 Subactive Mode

5.6.1 Transition to Subactive Mode

Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ0, or WKP7 to WKP0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer C, timer F, timer G, asynchronous event counter, SCI3, IRQAEC, IRQ 4, IRQ3, IRQ1, IRQ0, or WKP7 to WKP0 interrupt is requested. A transition to subactive mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register.

5.6.2 Clearing Subactive Mode

Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin.

• Clearing by SLEEP instruction If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep mode is entered. Direct transfer to active mode is also possible; see section 5.8, Direct Transfer, below.
• Clearing by RES pin Clearing by RES pin is the same as for standby mode; see Clearing by RES pin in section 5.3.2, Clearing Standby Mode.

5.6.3 Operating Frequency in Subactive Mode

The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices are φW/2, φW/4, and φW/8.

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 138 of 658 REJ09B0042-0800

5.7 Active (Medium-Speed) Mode

5.7.1 Transition to Active (Medium-Speed) Mode

If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ0, IRQ1 or WKP7 to WKP0 interrupts in standby mode, timer A, timer F, timer G, IRQ0, or WKP7 to WKP0 interrupts in watch mode, or any interrupt in sleep mode. A transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. Furthermore, it sometimes acts with half state early timing at the time of transition to active (medium-speed) mode.

5.7.2 Clearing Active (Medium-Speed) Mode

Active (medium-speed) mode is cleared by a SLEEP instruction.

• Clearing by SLEEP instruction A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1 when a SLEEP instruction is executed. When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed, sleep mode is entered. Direct transfer to active (high-speed) mode or to subactive mode is also possible. See section 5.8, Direct Transfer, below for details.
• Clearing by RES pin When the RES pin is driven low, a transition is made to the reset state and active (medium- speed) mode is cleared.

5.7.3 Operating Frequency in Active (Medium-Speed) Mode

Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1.

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 139 of 658 REJ09B0042-0800

5.8 Direct Transfer

5.8.1 Overview of Direct Transfer

The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt exception handling starts. If the direct transfer interrupt is disabled in interrupt enable register 2 (IENR2), a transition is made instead to sleep mode or watch mode. Note that if a direct transition is attempted while the I bit in CCR is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt.

• Direct transfer from active (high-speed) mode to active (medium-speed) mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode.
• Direct transfer from active (medium-speed) mode to active (high-speed) mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode.
• Direct transfer from active (high-speed) mode to subactive mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (high-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed.

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 140 of 658 REJ09B0042-0800

• Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (medium-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed.

5.8.2 Direct Transition Times

1. Time for direct transition from active (high-speed) mode to active (medium-speed) mode A direct transition from active (high-speed) mode to active (medium-speed) mode is performed by executing a SLEEP instruction in active (high-speed) mode while bits SSBY and LSON are both cleared to 0 in SYSCR1, and bits MSON and DTON are both set to 1 in SYSCR2. The time from execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition time) is given by equation (1) below. Direct transition time = { (Number of SLEEP in struction execution states) + (number of internal processing states) } × (tcyc before transition) + (number of interrupt exception handling execution states) × (tcyc after transition) Example: Direct transition time = (2 + 1) × 2tosc + 14 × 16tosc = 230tosc (when φ/8 is selected as the CPU operating clock) [Legend] tosc: OSC clock cycle time tcyc: System clock ( φ) cycle time

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 141 of 658 REJ09B0042-0800 2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2. The time from execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition time) is given by equation (2) below. Direct transition time = { (Number of SLEEP in struction execution states) + (number of internal processing states) } × (tcyc before transition) + (number of interrupt exception handling execution states) × (tcyc after transition) Example: Direct transition time = (2 + 1) × 16tosc + 14 × 2tosc = 76tosc (when φ/8 is selected as the CPU operating clock) [Legend] tosc: OSC clock cycle time tcyc: System clock ( φ) cycle time 3. Time for direct transition from subactive mode to active (high-speed) mode A direct transition from subactive mode to active (high-speed) mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2, and bit TMA3 is set to 1 in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition time) is given by equation (3) below. Direct transition time = { (Number of SLEEP in struction execution states) + (number of internal processing states) } × (tsubcyc before transition) + { (wait time set in STS2 to STS0) + (number of interrupt exception handling execution Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 2tosc = 24tw + 16412tosc (when φw/8 is selected as the CPU operating clock, and wait time = 8192 states) [Legend] tosc: OSC clock cycle time tw: Watch clock cycle time tcyc: System clock ( φ) cycle time tsubcyc: Subclock ( φ SUB) cycle time

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 142 of 658 REJ09B0042-0800 4. Time for direct transition from subactive mode to active (medium-speed) mode A direct transition from subactive mode to active (medium-speed) mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set to 1 in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition time) is given by equation (4) below. Direct transition time = { (Number of SLEEP in struction execution states) + (number of internal processing states) } × (tsubcyc before transition) + { (wait time set in STS2 to STS0) + (number of interrupt exception handling execution Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 16tosc = 24tw + 131296tosc (when φw/8 or φ/8 is selected as the CPU operating clock, and wait time = 8192 states) [Legend] tosc: OSC clock cycle time tw: Watch clock cycle time tcyc: System clock ( φ) cycle time tsubcyc: Subclock ( φ SUB) cycle time

5.8.3 Notes on External Input Signal Changes before/after Direct Transition

1. Direct transition from active (high-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode. 2. Direct transition from active (medium-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode. 3. Direct transition from subactive mode to active (high-speed) mode Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode. 4. Direct transition from subactive mode to active (medium-speed) mode Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode.

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5.9 Module Standby Mode

5.9.1 Setting Module Standby Mode

Module standby mode is set for individual peripheral functions. All the on-chip peripheral modules can be placed in module standby mode. When a module enters module standby mode, the system clock supply to the module is stopped and operation of the module halts. This state is identical to standby mode. Module standby mode is set for a particular module by setting the corresponding bit to 0 in clock stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5.5.)

5.9.2 Clearing Module Standby Mode

Module standby mode is cleared for a particular module by setting the corresponding bit to 1 in clock stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5.5.) Following a reset, clock stop register 1 (CKSTPR1) and clock stop register 2 (CKSTPR2) are both initialized to H'FF. Table 5.5 Setting and Clearing Module Standby Mode by Clock Stop Register Register Name Bit Name Operation CKSTPR1 TACKSTP 1 Timer A module standby mode is cleared

0 Timer A is set to module standby mode

TCCKSTP 1 Timer C module standby mode is cleared

0 Timer C is set to module standby mode

TFCKSTP 1 Timer F module standby mode is cleared

0 Timer F is set to module standby mode

TGCKSTP 1 Timer G module standby mode is cleared

0 Timer G is set to module standby mode

ADCKSTP 1 A/D converter module standby mode is cleared

0 A/D converter is set to module standby mode

S32CKSTP 1 SCI3 module standby mode is cleared

0 SCI3 is set to module standby mode

Section 5 Power-Down Modes Rev. 8.00 Mar. 09, 2010 Page 144 of 658 REJ09B0042-0800 Register Name Bit Name Operation CKSTPR2 LDCKSTP 1 LCD module standby mode is cleared

0 LCD is set to module standby mode

PW1CKSTP 1 PWM1 module standby mode is cleared

0 PWM1 is set to module standby mode

WDCKSTP 1 Watchdog timer module standby mode is cleared

0 Watchdog timer is set to module standby mode

AECKSTP 1 Asynchronous event counter module standby mode is cleared

0 Asynchronous event counter is set to module standby

PW2CKSTP 1 PWM2 module standby mode is cleared

0 PWM2 is set to module standby mode

LVDCKSTP * 1 LVD module standby mode is cleared

0 LVD is set to module standby mode

Notes: For details of module operation, see the sections on the individual modules. * LVDCKSTP is implemented on the H8/38124 group only.

5.10 Usage Note

5.10.1 Contention Between Module Standby and Interrupts

If, due to timing with which a peripheral module issues interrupt requests, the module in question is set to module standby mode before an interrupt is processed, the module will stop with the interrupt request still pending. In this situation, interrupt processing will be repeated indefinitely unless interrupts are prohibited. It is therefore necessary to ensure that no interrupts are generated when a module is set to module standby mode. The surest way to do this is to specify the module standby mode setting only when interrupts are prohibited (interrupts prohibited using the interrupt enable register or interrupts masked using bit CCR-1).

Rev. 8.00 Mar. 09, 2010 Page 145 of 658 REJ09B0042-0800 Section 6 ROM

6.1 Overview

The H8/38024, H8/38024S, and H8/38124 have 32 Kbytes of on-chip mask ROM, the H8/38023, H8/38023S, and H8/38123 have 24 Kbytes, the H8/38022, H8/38022S, and H8/38122 have 16 Kbytes, the H8/38021, H8/38021S, and H8/38121 have 12 Kbytes, and the H8/38020, H8/38020S, and H8/38120 have 8 Kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. The H8/38024 has a ZTAT version and F-ZTAT version with 32-Kbyte PROM and flash memory. F-ZTAT™ versions of the H8/38124 and H8/38122 are available. The former has 32 Kbytes, and the latter 16 Kbytes, of flash memory.

6.1.1 Block Diagram

Figure 6.1 shows a block diagram of the on-chip ROM. H'7FFE H'7FFF Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Even-numbered address Odd-numbered address H'7FFE H'0002 H'0000 H'0000 H'0002 H'0001 H'0003 On-chip ROM Figure 6.1 ROM Block Diagram (H8/38024)

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6.2 H8/38024 PROM Mode

6.2.1 Setting to PROM Mode

If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C101 EPROM. However, page programming is not supported. Table 6.1 shows how to set the chip to PROM mode. Table 6.1 Setting to PROM Mode Pin Name Setting TEST High level PB0/AN0 Low level PB1/AN1 PB2/AN2 High level

6.2.2 Socket Adapter Pin A rrangement and Memory Map

A standard PROM programmer can be used to program the PROM. A socket adapter is required for conversion to 32 pins. Figure 6.2 shows the pin-to-pin wiring of the socket adapter. Figure 6.3 shows a memory map.

Rev. 8.00 Mar. 09, 2010 Page 147 of 658 REJ09B0042-0800 HN27C101 (32-pin) Pin V PP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 CE OE PGM V CC VSS Note: Pins not indicated in the figure should be left open. EPROM socket FP-80A, TFP-80C FP-80B Pin RES P61 P62 P63 P64 P65 P66 P67 P40 P41 P32 P33 P34 P35 P36 P37 P70 P43 P72 P73 P74 P75 P76 P93 P94 P77 P71 P92 VCC AVCC TEST PB P90 P91 P95 VSS VSS = AVSS PB0 PB1 H8/38024 Figure 6.2 Socket Adapter Pin Correspondence (with HN27C101)

Rev. 8.00 Mar. 09, 2010 Page 148 of 658 REJ09B0042-0800 Address in MCU mode Address in PROM mode H'0000 H'0000 H'1FFFF H'7FFF H'7FFF On-chip PROM Uninstalled area* The output data is not guaranteed if this address area is read in PROM mode. Therefore, when programming with a PROM programmer, be sure to specify addresses from H'0000 to H'7FFF. If programming is inadvertently performed from H'8000 onward, it may not be possible to continue PROM programming and verification. When programming, H'FF should be set as the data in this address area (H'8000 to H'1FFFF). Note: * Figure 6.3 H8/38024 Memory Map in PROM Mode

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6.3 H8/38024 Programming

The write, verify, and other modes are selected as shown in table 6.2 in H8/38024 PROM mode. Table 6.2 Mode Selection in PROM Mode (H8/38024) Pins Mode CE OE PGM VPP V CC EO 7 to EO0 EA 16 to EA0 Write L H L V PP V CC Data input Address input Verify L L H V PP V CC Data output Address input Programming L L L V PP V CC High impedance Address input disabled L H H H L L H H H [Legend] L: Low level H: High level V PP: V PP level VCC: V CC level The specifications for writing and reading are identical to those for the standard HN27C101 EPROM. However, page programming is not supported, and so page programming mode must not be set. A PROM programmer that only supports page programming mode cannot be used. When selecting a PROM programmer, ensure that it supports high-speed, high-reliability byte-by-byte programming. Also, be sure to specify addresses from H'0000 to H'7FFF.

6.3.1 Writing and Verifying

An efficient, high-speed, high-reliability method is available for writing and verifying the PROM data. This method achieves high speed without voltage stress on the device and without lowering the reliability of written data. The basic flow of this high-speed, high-reliability programming method is shown in figure 6.4.

Rev. 8.00 Mar. 09, 2010 Page 150 of 658 REJ09B0042-0800 Start Set write/verify mode V = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 VCC PP Address = 0 n = 0 n + 1 n→ PW Verify Write time t = 0.2n msOPW Last address? Set read mode V = 5.0 V ± 0.25 V, V = V CC PP CC Read all addresses? End Error n < 25 Address + 1 address→ No Yes No Yes Yes No No Yes Write time t = 0.2 ms ± 5% Figure 6.4 High-Speed, High-Reliability Programming Flowchart

Rev. 8.00 Mar. 09, 2010 Page 151 of 658 REJ09B0042-0800 Tables 6.3 and 6.4 give the electrical characteristics in programming mode. Table 6.3 DC Characteristics Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Typ Max Unit Test Condition Input high-level voltage EO7 to EO0, EA16 to EA0, OE, CE, PGM VIH 2.4 — V CC + 0.3 V Input low- level voltage EO7 to EO0, EA16 to EA0, OE, CE, PGM VIL –0.3 — 0.8 V Output high-level voltage EO7 to EO0 V OH 2.4 — — V I OH = –200 µA Output low-level voltage EO7 to EO0 V OL — — 0.45 V I OL = 0.8 mA Input leakage current EO7 to EO0, EA16 to EA0, OE, CE, PGM |ILI| — — 2 µA V in = 5.25 V/ 0.5 V VCC current I CC — — 40 mA VPP current I PP — — 40 mA

Rev. 8.00 Mar. 09, 2010 Page 152 of 658 REJ09B0042-0800 Table 6.4 AC Characteristics Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25°C ±5°C Item Symbol Min Typ Max Unit Test Condition Address setup time t AS 2 — — µs Figure 6.5 *1 OE setup time t OES 2 — — µs Data setup time t DS 2 — — µs Address hold time t AH 0 — — µs Data hold time t DH 2 — — µs Data output disable time t DF*2 — — 130 ns VPP setup time t VPS 2 — — µs Programming pulse width t PW 0.19 0.20 0.21 ms PGM pulse width for overwrite programming tOPW*3 0.19 — 5.25 ms CE setup time t CES 2 — — µs VCC setup time t VCS 2 — — µs Data output delay time t OE 0 — 200 ns Notes: 1. Input pulse level: 0.45 V to 2.4 V Input rise time/fall time ≤ 20 ns Timing reference levels Input: 0.8 V, 2.0 V Output: 0.8 V, 2.0 V 2. t DF is defined at the point at which the output is floating and the output level cannot be read. 3. t OPW is defined by the value given in figure 6.4, High-Speed, High-Reliability Programming Flow Chart.

Rev. 8.00 Mar. 09, 2010 Page 154 of 658 REJ09B0042-0800

6.3.2 Programming Precautions

• Use the specified programming voltage and timing. The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Renesas specifications for the HN27C101 will result in correct VPP of 12.5 V.
• Make sure the index marks on the PROM programmer socket, socket adapter, and chip are properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before programming, be sure that the chip is properly mounted in the PROM programmer.
• Avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors.
• Take care when setting the programming mode, as page programming is not supported.
• When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'7FFF. If programming is inadvertently performed from H'8000 onward, it may not be possible to continue PROM programming and verification. When programming, H'FF should be set as the data in address area H'8000 to H'1FFFF.

Rev. 8.00 Mar. 09, 2010 Page 155 of 658 REJ09B0042-0800

6.4 Reliability of Programmed Data

A highly effective way to improve data retention characteristics is to bake the programmed chips at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 6.6 shows the recommended screening procedure. Program chip and verify programmed data Bake chip for 24 to 48 hours at 125°C to 150°C with power off Read and check program Install Figure 6.6 Recommended Screening Procedure If a series of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects. Please inform Renesas Technology of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.

Rev. 8.00 Mar. 09, 2010 Page 156 of 658 REJ09B0042-0800

6.5 Flash Memory Overview

6.5.1 Features

The features of the 32-Kbyte or 16-Kbyte flash memory built into the flash memory versions are summarized below.

• Programming/erase methods ⎯ The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. On the HD64F38024, HD64F38024R, and HD64F38124 the flash memory is configured as follows: 1 Kbyte × 4 blocks, 28 Kbytes × 1 block. On the HD64F38122 the flash memory is configured as follows: 1 Kbyte × 4 blocks, 12 Kbytes × 1 block. To erase the entire flash memory, each block must be erased in turn.
• Reprogramming capability ⎯ The HD64F38024R, HD64F38124, and HD64F38122 can be reprogrammed up to 1,000 times and the HD64F38024 up to 100 times.
• On-board programming ⎯ On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed.
• Programmer mode ⎯ Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode.
• Automatic bit rate adjustment ⎯ For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host.
• Programming/erasing protection ⎯ Sets software protection against flash memory programming/erasing.
• Power-down mode ⎯ The power supply circuit is partly halted in the subactive mode and can be read in the power-down mode. Note: The system clock oscillator must be used when programming or erasing the flash memory of the HD64F38124 and HD64F38122.

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6.5.2 Block Diagram

Internal data bus (16 bits) FLMCR1 Bus interface/controller Operating mode TES pin P95 pin P34 pin [Legend] FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR: Erase block register FLPWCR: Flash memory power control register FENR: Flash memory enable register FLMCR2 EBR FLPWCR FENR Flash memory Figure 6.7 Block Diagram of Flash Memory

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6.5.3 Block Configuration

Figure 6.8 shows the block configuration of the flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. In versions with

32 Kbytes of flash memory, the flash memory is divided into 1 Kbyte × 4 blocks and 28 Kbytes ×

1 block. In versions with 16 Kbytes of flash memory, the flash memory is divided into 1 Kbyte × 4 blocks and 12 Kbytes × 1 block. Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80. H'007FH'0000 H'0001 H'0002 H'00FFH'0080 H'0081 H'0082 H'03FFH'0380 H'0381 H'0382 H'047FH'0400 H'0401 H'0402 H'04FFH'0480 H'0481 H'0482 H'07FFH'0780 H'0781 H'0782 H'087FH'0800 H'0801 H'0802 H'08FFH'0880 H'0881 H'0882 H'0BFFH'0B80 H'0B81 H'0B82 H'0C7FH'0C00 H'0C01 H'0C02 H'0CFFH'0C80 H'0C81 H'0C82 H'0FFFH'0F80 H'0F81 H'0F82 H'107FH'1000 H'1001 H'1002 H'10FFH'1080 H'1081 H'1082 H'7FFFH'7F80 H'7F81 H'7F82 Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes

28 Kbytes

Figure 6.8(1) Block Configuration of 32-Kbyte Flash Memory

Rev. 8.00 Mar. 09, 2010 Page 159 of 658 REJ09B0042-0800 H'007FH'0000 H'0001 H'0002 H'00FFH'0080 H'0081 H'0082 H'03FFH'0380 H'0381 H'0382 H'047FH'0400 H'0401 H'0402 H'04FFH'0480 H'0481 H'0482 H'07FFH'0780 H'0781 H'0782 H'087FH'0800 H'0801 H'0802 H'08FFH'0880 H'0881 H'0882 H'0BFFH'0B80 H'0B81 H'0B82 H'0C7FH'0C00 H'0C01 H'0C02 H'0CFFH'0C80 H'0C81 H'0C82 H'0FFFH'0F80 H'0F81 H'0F82 H'107FH'1000 H'1001 H'1002 H'10FFH'1080 H'1081 H'1082 H'3FFFH'3F80 H'3F81 H'3F82 Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes Figure 6.8(2) Block Configuration of 16-Kbyte Flash Memory

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6.5.4 Register Configuration

Table 6.5 lists the register configuration to control the flash memory when the built in flash memory is effective. Table 6.5 Register Configuration Register Name Abbreviation R/W Initial Value Address Flash memory control register 1 FLMCR1 R/W H'00 H'F020 Flash memory control register 2 FLMCR2 R H'00 H'F021 Flash memory power control register FLPWCR R/W H'00 H'F022 Erase block register EBR R/W H'00 H'F023 Flash memory enable register FENR R/W H'00 H'F02B Note: FLMCR1, FLMCR2, FLPWCR, EBR, and FENR are 8 bit registers. Only byte access is enabled which are two-state access. These registers are dedicated to the product in which flash memory is included. The product in which PROM or ROM is included does not have these registers. When the corresponding address is read in these products, the value is undefined. A write is disabled.

6.6 Descriptions of Registers of the Flash Memory

6.6.1 Flash Memory Control Register 1 (FLMCR1)

— SWE ESU PSU EV PV E P Initial value 0 0 0 0 0 0 0 0 Read/Write — R/W R/W R/W R/W R/W R/W R/W FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 6.8, Flash Memory Programming/Erasing. By setting this register, the flash memory enters program mode, erase mode, program-verify mode, or erase-verify mode. Read the data in the state that bits 6 to 0 of this register are cleared when using flash memory as normal built-in ROM. Bit 7—Reserved This bit is always read as 0 and cannot be modified.

Rev. 8.00 Mar. 09, 2010 Page 161 of 658 REJ09B0042-0800 Bit 6—Software Write Enable (SWE) This bit is to set enabling/disabling of programming/enabling of flash memory (set when bits 5 to 0 and the EBR register are to be set). Bit 6 SWE 0 Programming/erasing is disabled. Other FLMCR1 register bits and all EBR bits cannot be set. (initial value) 1 Flash memory programming/erasing is enabled. Bit 5—Erase Setup (ESU) This bit is to prepare for changing to erase mode. Set this bit to 1 before setting the E bit to 1 in FLMCR1 (do not set SWE, PSU, EV, PV, E, and P bits at the same time). Bit 5 ESU

0 The erase setup state is cancelled (initial value)

1 The flash memory changes to the erase setup state. Set this bit to 1 before setting the E bit to 1 in FLMCR1. Bit 4—Program Setup (PSU) This bit is to prepare for changing to program mode. Set this bit to 1 before setting the P bit to 1 in FLMCR1 (do not set SWE, ESU, EV, PV, E, and P bits at the same time). Bit 4 PSU

0 The program setup state is cancelled (initial value)

1 The flash memory changes to the program setup state. Set this bit to 1 before setting the P bit to 1 in FLMCR1. Bit 3—Erase-Verify (EV) This bit is to set changing to or cancelling erase-verify mode (do not set SWE, ESU, PSU, PV, E, and P bits at the same time).

Rev. 8.00 Mar. 09, 2010 Page 162 of 658 REJ09B0042-0800 Bit 3 EV

0 Erase-verify mode is cancelled (initial value)

1 The flash memory changes to erase-verify mode

Bit 2—Program-Verify (PV) This bit is to set changing to or cancelling program-verify mode (do not set SWE, ESU, PSU, EV, E, and P bits at the same time). Bit 2 PV

0 Program-verify mode is cancelled (initial value)

1 The flash memory changes to program-verify mode

Bit 1—Erase (E) This bit is to set changing to or cancelling erase mode (do not set SWE, ESU, PSU, EV, PV, and P bits at the same time). Bit 1 E

0 Erase mode is cancelled (initial value)

1 When this bit is set to 1, while the SWE = 1 and ESU = 1, the flash memory

changes to erase mode. Bit 0—Program (P) This bit is to set changing to or cancelling program mode (do not set SWE, ESU, PSU, EV, PV, and E bits at the same time). Bit 0 P

0 Program mode is cancelled (initial value)

1 When this bit is set to 1, while the SWE = 1 and PSU = 1, the flash memory

changes to program mode.

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6.6.2 Flash Memory Control Register 2 (FLMCR2)

Initial value 0 0 0 0 0 0 0 0 FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit 7—Flash Memory Error (FLER) This bit is set when the flash memory detects an error and goes to the error-protection state during programming or erasing to the flash memory. See section 6.9.3, Error Protection, for details. Bit 7 FLER 0 The flash memory operates normally. (initial value)

1 Indicates that an error has occurred during an operation on flash memory

(programming or erasing). Bits 6 to 0—Reserved These bits are always read as 0 and cannot be modified.

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6.6.3 Erase Block Register (EBR)

— — — EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 Read/Write — — — R/W R/W R/W R/W R/W EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be automatically cleared to 0. When each bit is set to 1 in EBR, the corresponding block can be erased. Other blocks change to the erase-protection state. See table 6.6 for the method of dividing blocks of the flash memory. When the whole bits are to be erased, erase them in turn in unit of a block. Table 6.6 Division of Blocks to Be Erased EBR Bit Name Block (Size) Address

0 EB0 EB0 (1 Kbyte) H'0000 to H'03FF

1 EB1 EB1 (1 Kbyte) H'0400 to H'07FF

2 EB2 EB2 (1 Kbyte) H'0800 to H'0BFF

3 EB3 EB3 (1 Kbyte) H'0C00 to H'0FFF

4 EB4 EB4 (12 Kbytes) H'1000 to H'3FFF (HD64F38122)

EB4 (28 Kbytes) H'1000 to H'7FFF (HD64F38124, HD64F38024, HD64F38024R)

6.6.4 Flash Memory Power Control Register (FLPWCR)

Initial value 0 0 0 0 0 0 0 0 FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. The power supply circuit can be read in the subactive mode, although it is partly halted in the power-down mode.

Rev. 8.00 Mar. 09, 2010 Page 165 of 658 REJ09B0042-0800 Bit 7—Power-down Disable (PDWND) This bit selects the power-down mode of the flash memory when a transition to the subactive mode is made. Bit 7 PDWND

0 When this bit is 0 and a transition is made to the subactive mode, the flash memory

enters the power-down mode. (initial value)

1 When this bit is 1, the flash memory remains in the normal mode even after a

transition is made to the subactive mode. Bits 6 to 0—Reserved These bits are always read as 0 and cannot be modified.

6.6.5 Flash Memory Enable Register (FENR)

Initial value 0 0 0 0 0 0 0 0 FENR controls CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR, and FLPWCR. Bit 7—Flash Memory Control Register Enable (FLSHE) This bit controls access to the flash memory control registers. Bit 7 FLSHE

0 Flash memory control registers cannot be accessed (initial value)

1 Flash memory control registers can be accessed

Bits 6 to 0—Reserved These bits are always read as 0 and cannot be modified.

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6.7 On-Board Programming Modes

There are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, the series of HD64F38024, HD64F38024R, HD64F38124, and HD64F38122 changes to a mode depending on the TEST pin settings, P95 pin settings, and input level of each port, as shown in table 6.7. The input level of each pin must be defined four states before the reset ends. When changing to boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI3. After erasing the entire flash memory, the programming control program is executed. This can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. Table 6.7 Setting Programming Modes TEST P95 P34 PB0 PB1 PB2 LSI State after Reset End 0 1 X X X X User Mode 0 0 1 X X X Boot Mode

1 X X 0 0 0 Programmer Mode

X: Don’t care

6.7.1 Boot Mode

Table 6.8 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 6.8, Flash Memory Programming/Erasing. 2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. The inversion function of TXD and RXD pins by the SPCR register is set to “Not to be inverted,” so do not put the circuit for inverting a value between the host and this LSI.

Rev. 8.00 Mar. 09, 2010 Page 167 of 658 REJ09B0042-0800 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host. The reset should end with the RXD pin high. The RXD and TXD pins should be pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 6.9. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to H'FEEF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. Before branching to the programming control pr ogram, the chip terminates transfer operations by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TXD pin is high (PCR42 = 1, P42 = 1). The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at least 20 states, and then setting the TEST pin and P95 pin. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the TEST pin and P95 pin input levels in boot mode.

Rev. 8.00 Mar. 09, 2010 Page 168 of 658 REJ09B0042-0800 Table 6.8 Boot Mode Operation Item Host Operation LSI Operation Branches to boot program at reset-start. Processing Contents Processing Contents Bit rate adjustment Flash memory erase Continuously transmits data H'00 at specified bit rate.

• Measures low-level period of receive data H'00.
• Calculates bit rate and sets it in BRR of SCI3.
• Transmits data H'00 to the host to indicate that the adjustment has ended. Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.) Transmits data H'55 when data H'00 is received and no error occurs. Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) Transmits 1-byte of programming control program Transfer of programming control program Execution of Programming control program Transfer of programming control program (repeated for N times) Echobacks the 2-byte received data to host. Transmits 1-byte data H'AA to host. Branches to programming control program transferred to on-chip RAM and starts execution. Echobacks received data to host and also transfers it to RAM. Table 6.9 Oscillating Frequencies (f OSC) for which Automatic Adjustment of LSI Bit Rate Is Possible Product Group Host Bit Rate Oscillating Frequencie s (fOSC) Range of LSI 4,800 bps 8 to 10 MHz 2,400 bps 4 to 10 MHz F-ZTAT version of H8/38024 Group and F-ZTAT version of H8/38024R Group 1,200 bps 2 to 10 MHz 19,200 bps 16 to 20 MHz F-ZTAT version of H8/38124 Group 9,600 bps 8 to 20 MHz 4,800 bps 6 to 20 MHz 2,400 bps 2 to 20 MHz 1,200 bps 2 to 20 MHz

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6.7.2 Programming/Erasing in User Program Mode

The term user mode refers to the status when a user program is being executed. On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 6.9 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 6.8, Flash Memory Programming/Erasing. Yes No Program/erase? Transfer user program/erase control program to RAM Reset-start Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Branch to flash memory application program Figure 6.9 Programming/Erasing Flowchart Example in User Program Mode

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6.7.3 Notes on On-Board Programming

1. You must use the system clock oscillator when programming or erasing flash memory on the H8/38124 Group. The on-chip oscillator should not be used for programming or erasing flash memory. See section 4.2, On-Chip Oscillator Selection Method, for information on switching between the system clock oscillator and the on-chip oscillator. 2. On the H8/38124 Group the watchdog timer operates after a reset is canceled. When executing a program prepared by the user that performs programming and erasing in the user mode, the watchdog timer’s overflow cycle should be set to an appropriate value. Refer to section 6.8.1, Program/Program-Verify, for information on the appropriate watchdog timer overflow cycle for programming, and refer to section 6.8.2, Erase/Erase-Verify, for information on the appropriate watchdog timer overflow cycle for erasing.

6.8 Flash Memory Programming/Erasing

A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 6.8.1, Program/Program-Verify and section 6.8.2, Erase/Erase-Verify, respectively.

6.8.1 Program/Program-Verify

When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 6.10 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. Perform

Rev. 8.00 Mar. 09, 2010 Page 171 of 658 REJ09B0042-0800 reprogramming data computation according to table 6.10, and additional programming data computation according to table 6.11. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. Do not use RTS instruction from data transfer to setting P bit to 1. (This does not apply to the HD64F38124 and HD64F38122.) 5. The time during which the P bit is set to 1 is the programming time. Figure 6.12 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately 6.6 ms is allowed. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit is b'0. Verify data can be read in word size from the address to which a dummy write was performed. Do not use RTS instruction from dummy write to verify data read. (This does not apply to the HD64F38124 and HD64F38122.) 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.

Rev. 8.00 Mar. 09, 2010 Page 172 of 658 REJ09B0042-0800 START End of programming Set SWE bit in FLMCR1 Write pulse application subroutine Wait 1 μs Apply Write Pulse End Sub Set PSU bit in FLMCR1 WDT enable Disable WDT Wait 50 μs Set P bit in FLMCR1 Wait (Wait time = programming time) Clear P bit in FLMCR1 Wait 5 μs Clear PSU bit in FLMCR1 Wait 5 μs n = 1 m = 0 No No No Yes Yes Yes Yes Wait 4 μs Wait 2 μs Wait 2 μs Apply Write pulse Set PV bit in FLMCR1 H'FF dummy write to verify address Read verify data Reprogram data computation Clear PV bit in FLMCR1 Clear SWE bit in FLMCR1 Increment address Programming failure Clear SWE bit in FLMCR1 Wait 100 μs No Yes No Yes No Wait 100 μs n ≤ 1000 ? Write 128-byte data in RAM reprogram data area consecutively to flash memory Store 128-byte program data in program data area and reprogram data area Apply Write Pulse Sub-Routine-Call Successively write 128-byte data from additional-programming data area in RAM to flash memory Set block start address as verify address n ← n + 1 m = 1 m = 0 ? n ≤ 6? 128-byte data verification completed? n ≤ 6 ? Additional-programming data computation Verify data = write data? Figure 6.10 Program/Program-Verify Flowchart

Rev. 8.00 Mar. 09, 2010 Page 173 of 658 REJ09B0042-0800 Table 6.10 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 — 1 1 1 Remains in erased state Table 6.11 Additional-Program Data Computation Table Reprogram Data Verify Data Additional-Program Data Comments 0 0 0 Additional-program bit 0 1 1 No additional programming 1 0 1 No additional programming 1 1 1 No additional programming Table 6.12 Programming Time n (Number of Writes) Programming Time In Additional Programming Comments 1 to 6 30 10 7 to 1,000 200 — Note: Time shown in μs.

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6.8.2 Erase/Erase-Verify

When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An overflow cycle of approximately 19.8 ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit is b'0. Verify data can be read in word size from the address to which a dummy write was performed. Do not use RTS instruction from dummy write to verify data read. (This does not apply to the HD64F38124 and HD64F38122.) 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase- verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100.

6.8.3 Interrupt Handling when Programming/Erasing Flash Memory

All interrupts, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.

Rev. 8.00 Mar. 09, 2010 Page 175 of 658 REJ09B0042-0800 Erase start Set EBR Enable WDT Wait 1 μs Wait 100 μs SWE bit ← 1 n ← 1 ESU bit ← 1 E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 μs ESU bit ← 0 Wait 10 μs Disable WDT Read verify data Increment address Verify data = all 1s ? Last address of block ? All erase block erased ? Set block start address as verify address H'FF dummy write to verify address Wait 20 μs Wait 2 μs EV bit ← 1 Wait 100 μs End of erasing SWE bit ← 0 Wait 4 μs EV bit ← 0 n ≤100 ? Wait 100 μs Erase failure SWE bit ← 0 Wait 4μs EV bit ← 0 n ← n + 1 Yes No Yes Yes Yes No No No Figure 6.11 Erase/Erase-Verify Flowchart

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6.9 Program/Erase Protection

There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection.

6.9.1 Hardware Protection

Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode, or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register (EBR) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section.

6.9.2 Software Protection

Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register (EBR), erase protection can be set for individual blocks. When EBR is set to H'00, erase protection is set for all blocks.

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6.9.3 Error Protection

In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered.

• When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch)
• Immediately after exception handling excluding a reset during programming/erasing
• When a SLEEP instruction is executed during programming/erasing The FLMCR1, FLMCR2, and EBR settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a power-on reset.

6.10 Programmer Mode

In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU device type with the on-chip Renesas Technology 64-Kbyte flash memory (F-ZTAT64V3). A 10- MHz input clock is required. For the conditions for transition to programmer mode, see table 6.7.

6.10.1 Socket Adapter

The socket adapter converts the pin allocation of the HD64F38024, HD64F38024R, HD64F38124, and HD64F38122 to that of the discrete flash memory HN28F101. The address of the on-chip flash memory is H'0000 to H'7FFF. Figure 6.12(1) shows a socket-adapter-pin correspondence diagram of the HD64F38024 and HD64F38024R. Figure 6.12(2) shows a socket- adapter-pin correspondence diagram of the HD64F38124 and HD64F38122.

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6.10.2 Programmer Mode Commands

The following commands are supported in programmer mode.

• Memory Read Mode
• Auto-Program Mode
• Auto-Erase Mode
• Status Read Mode Status polling is used for auto-programming, auto-erasing, and status read modes. In status read mode, detailed internal information is output after the execution of auto-programming or auto- erasing. Table 6.13 shows the sequence of each command. In auto-programming mode, 129 cycles are required since 128 bytes are written at the same time. In memory read mode, the number of cycles depends on the number of address write cycles (n). Table 6.13 Command Sequence in Programmer Mode 1st Cycle 2nd Cycle Command Name Number of Cycles Mode Address Data Mode Address Data Memory read 1 + n Write X H'00 Read RA Dout Auto-program 129 Write X H'40 Write WA Din Auto-erase 2 Write X H'20 Write X H'20 Status read 2 Write X H'71 Write X H'71 n: the number of address write cycles

Rev. 8.00 Mar. 09, 2010 Page 179 of 658 REJ09B0042-0800 HD64F38024, HD64F38024R FP-80A TFP-80C FP-80B Socket Adapter (Conversion to 32-Pin Arrangement) Pin No. Pin Name 12, 11 P71 P77 P92 P60 P61 P62 P63 P64 P65 P66 P67 P40 P41 P32 P33 P34 P35 P36 P37 P70 P42 P72 P73 P74 P75 P76 P43 Vcc AVcc TEST Vcc P94 P95 Vss Vss PB0 PB1 PB2 OSC1, OSC2 RES (OPEN) HN28F101 (32 Pins) Pin No.Pin Name FWE A16 A15 WE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 OE A10 A11 A12 A13 A14 CE Vcc Vss 10, 9 Power-on reset circuit Oscillator circuit Other than the above [Legend] FWE: Flash-write enable I/O7 to I/O0: Data input/output A16 to A0: Address input CE: Chip enable OE: Output enable WE: Write enable Note: The oscillation frequency of the oscillator circuit should be 10 MHz. Figure 6.12(1) Socket Adapter Pin Correspondence Diagram (HD64F38024, HD64F38024R)

Rev. 8.00 Mar. 09, 2010 Page 180 of 658 REJ09B0042-0800 HD64F38124, HD64F38122 FP-80A TFP-80C Pin No. Pin No.Pin Name Pin Name P71 P77 P92 P60 P61 P62 P63 P64 P65 P66 P67 P40 P41 P32 P33 P34 P35 P36 P37 P70 P42 P72 P73 P74 P75 P76 P43 Vcc AVcc TEST Vcc P94 CVcc, P95 Vss Vss PB0 PB1 PB2 OSC1,OSC2 RES (OPEN) HN28F101 (32 Pins) FWE A16 A15 WE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 OE A10 A11 A12 A13 A14 CE Vcc Vss 4, 59 10,9 Power-on reset circuit Oscillator circuit Socket Adapter (Conversion to 32-Pin Arrangement) Other than the above [Legend] FWE: Flash-write enable I/O7 to I/O0: Data input/output A16 to A0: Address input CE: Chip enable OE: Output enable WE: Write enable Note: The oscillation frequency of the oscillator circuit should be 10 MHz. Figure 6.12(2) Socket Adapter Pin Correspondence Diagram (HD64F38124, HD64F38122)

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6.10.3 Memory Read Mode

1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. Once memory read mode has been entered, consecutive reads can be performed. 2. In memory read mode, command writes can be performed in the same way as in the command wait state. 3. After powering on, memory read mode is entered. 4. Tables 6.14 to 6.16 show the AC characteristics. Table 6.14 AC Characteristics in Transition to Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Notes Command write cycle t nxtc 20 — µs Figure 6.13 CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns WE rise time t r — 30 ns WE fall time t f — 30 ns CE OE CE A15−A0 OE WE I/O7−I/O0 Note: Data is latched on the rising edge of WE. tceh twep tf tr tces tnxtc Address stable tds tdh Command write Memory read mode Figure 6.13 Timing Waveforms for Memory Read after Memory Write

Rev. 8.00 Mar. 09, 2010 Page 182 of 658 REJ09B0042-0800 Table 6.15 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Notes Command write cycle t nxtc 20 — µs Figure 6.14 CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns WE rise time t r — 30 ns WE fall time t f — 30 ns CE A15−A0 OE WE I/O7−I/O0 Note: Do not enable WE and OE at the same time. tceh twep tf tr tcestnxtc Address stable tds tdh Other mode command writeMemory read mode Figure 6.14 Timing Waveforms in Transition from Memory Read Mode to Another Mode

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6.10.4 Auto-Program Mode

1. When reprogramming previously programmed addresses, perform auto-erasing before auto- programming. 2. Perform auto-programming once only on the same address block. It is not possible to program an address block that has already been programmed. 3. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 4. The lower 7 bits of the transfer address must be low. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 5. Memory address transfer is performed in the second cycle (figure 6.17). Do not perform transfer after the third cycle. 6. Do not perform a command write during a programming operation. 7. Perform one auto-program operation for a 128-byte block for each address. Two or more additional programming operations cannot be performed on a previously programmed address block. 8. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-program operation end decision pin). 9. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. 10. Table 6.17 shows the AC characteristics.

Rev. 8.00 Mar. 09, 2010 Page 185 of 658 REJ09B0042-0800 Table 6.17 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Notes Command write cycle t nxtc 20 — µs Figure 6.17 CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns Status polling start time t wsts 1 — ms Status polling access time t spa — 150 ns Address setup time t as 0 — ns Address hold time t ah 60 — ns Memory write time t write 1 3000 ms WE rise time t r — 30 ns WE fall time t f — 30 ns CE A15−A0 OE WE I/O7 I/O6 I/O5−I/O0 twep tds tdh tf tr tas tah twsts twrite tspa tces tceh tnxtc tnxtc Address stable H'40 H'00 Data transfer 1 to 128 bytes Write operation end decision signal Write normal end decision signal Figure 6.17 Auto-Program Mode Timing Waveforms

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6.10.5 Auto-Erase Mode

1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. 5. Table 6.18 shows the AC characteristics. Table 6.18 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Notes Command write cycle t nxtc 20 — µs Figure 6.18 CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns Status polling start time t ests 1 — ms Status polling access time t spa — 150 ns Memory erase time t erase 100 40000 ms WE rise time t r — 30 ns WE fall time t f — 30 ns

Rev. 8.00 Mar. 09, 2010 Page 187 of 658 REJ09B0042-0800 CE A15−A0 OE WE I/O7 I/O6 I/O5−I/O0 twep tds tdh tf tr tests terase tspa tces tceh tnxtc tnxtc H'20 H'20 H'00 Erase end decision signal Erase normal end decision signal Figure 6.18 Auto-Erase Mode Timing Waveforms

6.10.6 Status Read Mode

1. Status read mode is provided to identify th e kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than a status read mode command write is executed. 3. Table 6.19 shows the AC characteristics and 6.20 shows the return codes.

Rev. 8.00 Mar. 09, 2010 Page 188 of 658 REJ09B0042-0800 Table 6.19 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Notes Read time after command write t nxtc 20 — µs Figure 6.19 CE hold time t ceh 0 — ns CE setup time t ces 0 — ns Data hold time t dh 50 — ns Data setup time t ds 50 — ns Write pulse width t wep 70 — ns OE output delay time t oe — 150 ns Disable delay time t df — 100 ns CE output delay time t ce — 150 ns WE rise time t r — 30 ns WE fall time t f — 30 ns CE A15−A0 OE WE I/O7−I/O0 twep tf tr toe tdftdstds tdhtdh tces tceh tce tcehtnxtc tnxtc tnxtctces H'71 twep tf tr H'71 Note: I/O2 and I/O3 are undefined. Figure 6.19 Status Read Mode Timing Waveforms

Rev. 8.00 Mar. 09, 2010 Page 189 of 658 REJ09B0042-0800 Table 6.20 Status Read Mode Return Codes Pin Name Initial Value Indications I/O7 0 1: Abnormal end 0: Normal end I/O6 0 1: Command error 0: Otherwise I/O5 0 1: Programming error 0: Otherwise I/O4 0 1: Erasing error 0: Otherwise I/O3 0 ⎯ I/O2 0 ⎯ I/O1 0 1: Over counting of writing or erasing 0: Otherwise I/O0 0 1: Effective address error 0: Otherwise

6.10.7 Status Polling

1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. Table 6.21 Status Polling Output Truth Table I/O7 I/O6 I/O0 to 5 Status 0 0 0 During internal operation 1 0 0 Abnormal end 1 1 0 Normal end 0 1 0 —

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6.10.8 Programmer Mode Transition Time

Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 6.22 Stipulated Transition Times to Command Wait State Item Symbol Min Max Unit Notes Oscillation stabilization time(crystal oscillator) T osc1 10 — ms Figure 6.20 Oscillation stabilization time(ceramic oscillator) T osc1 5 — ms Programmer mode setup time T bmv 10 — ms Vcc hold time T dwn 0 — ms tosc1 tbmv tdwn Vcc RES Auto-program mode Auto-erase mode Figure 6.20 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence

6.10.9 Notes on Memory Programming

1. When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. 2. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level.

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6.11 Power-Down States for Flash Memory

In user mode, the flash memory will operate in either of the following states:

• Normal operating mode The flash memory can be read and written to at high speed.
• Power-down operating mode The power supply circuit of the flash memory is partly halted and can be read under low power consumption.
• Standby mode All flash memory circuits are halted. Table 6.23 shows the correspondence between the operating modes of this LSI and the flash memory. In subactive mode, the flash memory can be set to operate in power-down mode with the PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from power-down mode or standby mode, a period to stabilize the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the external clock is being used. Table 6.23 Flash Memory Operating States Flash Memory Operating State LSI Operating State PDWND = 0 (Initial value) PDWND = 1 Active mode Normal operating mode Normal operating mode Subactive mode Power-down mode Normal operating mode Sleep mode Normal operating mode Normal operating mode Subsleep mode Standby mode Standby mode Standby mode Standby mode Standby mode Watch mode Standby mode Standby mode

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Rev. 8.00 Mar. 09, 2010 Page 193 of 658 REJ09B0042-0800 Section 7 RAM

7.1 Overview

The H8/38024, H8/38023, H8/38022, H8/38124, H8/38123, H8/38122, H8/38024S, H8/38023S, and H8/38022S have 1 Kbyte of high-speed static RAM on-chip, and the H8/38021, H8/38020, H8/38121, H8/38120, H8/38021S, and H8/38020S have 512 bytes. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data.

7.1.1 Block Diagram

Figure 7.1 shows a block diagram of the on-chip RAM. H'FF7E H'FF7F Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Even-numbered address Odd-numbered address H'FF7E H'FB82 H'FB80 H'FB80 H'FB82 H'FB81 H'FB83 On-chip RAM Figure 7.1 RAM Block Diagram (H8/38024)

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Rev. 8.00 Mar. 09, 2010 Page 195 of 658 REJ09B0042-0800 Section 8 I/O Ports

8.1 Overview

The LSI is provided with five 8-bit I/O ports, two 4-bit I/O ports, one 3-bit I/O port, one 8-bit input-only port, one 1-bit input-only port, and one 6-bit output-only port. Table 8.1 indicates the functions of each port. Each port has of a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data. Input or output can be assigned to individual bits. See section 2.9.2, Notes on Bit Manipulation, for information on executing bit-manipulation instructions to write data in PCR or PDR. Ports 5, 6, 7, 8, and A are also used as liquid crystal display segment and common pins, selectable in 4-bit units. Block diagrams of each port are given in Appendix C, I/O Port Block Diagrams. Table 8.1 Port Functions Port Port 1 P1 7/IRQ3/TMIF External interrupt 3, timer event input pin TMIF PMR1 TCRF P1 6*1 None P1 4/IRQ4/ADTRG External interrupt 4, A/D converter external trigger PMR1 AMR

• 4-bit I/O port
• MOS input pull-up option P13/TMIG Timer G input capture PMR1 PMR2 Port 3 P3 7/AEVL P36/AEVH Asynchronous counter event input pins AEVL, AEVH PMR3 ECCR P3 5 to P33 None PMR2 P3 2, TMOFH P31, TMOFL Timer F output compare output PMR3
• 8-bit I/O port
• MOS input pull-up option
• Large-current port*2
• MOS open drain output selectable (only P3 P30/UD Timer C count up/down selection input PMR3

Rev. 8.00 Mar. 09, 2010 Page 196 of 658 REJ09B0042-0800 Port 3/IRQ0 External interrupt 0 PMR2

• 1-bit input port
• 3-bit I/O port P42/TXD32 P41/RXD32 P40/SCK32 SCI3 data output (TXD32), data input (RXD32), clock input/output (SCK32) SCR3 SMR3 SPCR Port 5 • 8-bit I/O port
• MOS input pull-up option P57 to P50/ WKP7 to WKP0/ SEG8 to SEG1 Wakeup input (WKP7 to WKP0), segment output (SEG8 to SEG1) PMR5 LPCR Port 6 • 8-bit I/O port
• MOS input pull-up option P67 to P60/ SEG16 to SEG9 Segment output (SEG16 to SEG9) LPCR Port 7 • 8-bit I/O port P77 to P70/ SEG24 to SEG17 Segment output (SEG24 to SEG17) LPCR Port 8 • 8-bit I/O port P87 to P80/ SEG32 to SEG25 Segment output (SEG32 to SEG25) LPCR Port 9 P9 5 to P92 (P95, P94, P92, P93/Vref)*4 None (LVD reference voltage external input pin)*4 (LVDSR)*4
• Dedicated 6-bit output port
• High-voltage, large- current port*3 P91, P90/ PWM2, PWM1 10-bit PWM output PMR9
• High-voltage port *3 IRQAEC None Port A • 4-bit I/O port PA3 to PA0/ COM4 to COM1 Common output (COM4 to COM1) LPCR Port B • Dedicated 8-bit input port PB7 to PB4/ AN7 to AN4 A/D converter analog input (AN7 to AN4) AMR PB 3/AN3/IRQ1 A/D converter analog input (AN3), external interrupt 1, timer event input (TMIC) AMR PMRB TMC PB 2/AN2 A/D converter analog input AMR PB 1/AN1/(extU)*4 PB0/AN0/(extD)*4 A/D converter analog input (LVD detect voltage external input pin)*4 AMR (LVDCR)*4 Notes: 1. Pin 16 and the associated function are not implemented on the H8/38124 Group. 2. Applies to the HD64338024, HD64338023, HD64338022, HD64338021, HD64338020, and H8/38124 Group only. 3. Standard voltage on H8/38024S Group and H8/38124 Group. 4. Applies to H8/38124 Group only.

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8.2 Port 1

8.2.1 Overview

Port 1 is a 4-bit I/O port. Figure 8.1 shows its pin configuration. P17/IRQ3/TMIF P16* P14/IRQ4/ADTRG P13/TMIG Port 1 Note: * Pin 16 and the associated function are not implemented on the H8/38124 Group. Figure 8.1 Port 1 Pin Configuration

8.2.2 Register Configuration and Description

Table 8.2 shows the port 1 register configuration. Table 8.2 Port 1 Registers Name Abbr. R/W Initial Value Address Port data register 1 PDR1 R/W — H'FFD4 Port control register 1 PCR1 W — H'FFE4 Port pull-up control register 1 PUCR1 R/W — H'FFE0 Port mode register 1 PMR1 R/W — H'FFC8 Port mode register 2 PMR2 R/W H'D8 H'FFC9

Rev. 8.00 Mar. 09, 2010 Page 198 of 658 REJ09B0042-0800 Port Data Register 1 (PDR1) Bit 7 6 5 4 3 2 1 0 P1 7 P1 6* — P1 4 P1 3 — — — Initial value 0 0 — 0 0 — — — Read/Write R/W R/W — R/W R/W — — — PDR1 is an 8-bit register that stores data for port 1 pins P17, P16*, P14, and P13. If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read. Note: * Pin 1 6 and the associated function are not implemented on the H8/38124 Group. The register is both readable and writeable. Port Control Register 1 (PCR1) Bit 7 6 5 4 3 2 1 0 PCR1 7 PCR1 6* — PCR1 4 PCR1 3 — — — Initial value 0 0 — 0 0 — — — Read/Write W W W W W W W W PCR1 is an 8-bit register for controlling whether each of the port 1 pins P1 7, P16*, P14, and P13 functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I/O pin. PCR1 is a write-only register, which is always read as all 1s. Note: * Pin 1 6 and the associated function are not implemented on the H8/38124 Group.

Rev. 8.00 Mar. 09, 2010 Page 199 of 658 REJ09B0042-0800 Port Pull-Up Control Register 1 (PUCR1) Bit 7 6 5 4 3 2 1 0 PUCR1 7 PUCR16* — PUCR1 4 PUCR13 — — — Initial value 0 0 — 0 0 — — — Read/Write R/W R/W W R/W R/W W W W PUCR1 controls whether the MOS pull-up of each of the port 1 pins P17, P16*, P14, and P13 is on or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Note: * Pin 1 6 and the associated function are not implemented on the H8/38124 Group. The register is both readable and writeable. Port Mode Register 1 (PMR1) Bit 7 6 5 4 3 2 1 0 Initial value 0 1 — 0 0 — 1 — Read/Write R/W — W R/W R/W W — W PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Bit 7—P1 7/IRQ3/TMIF Pin Function Switch (IRQ3) This bit selects whether pin P17/IRQ3/TMIF is used as P17 or as IRQ3/TMIF. Bit 7 IRQ3

0 Functions as P1 7 I/O pin (initial value)

1 Functions as IRQ3/TMIF input pin

Note: Rising or falling edge sensing can be designated for IRQ3, TMIF. For details on TMIF settings, see 3. Timer Control Register F (TCRF) in section 9.4.2, Register Descriptions. Bit 6—Reserved This bit is reserved; it is always read as 1 and cannot be modified. Bit 5—Reserved This bit is reserved; it can only be written with 0.

Rev. 8.00 Mar. 09, 2010 Page 200 of 658 REJ09B0042-0800 Bit 4—P1 4/IRQ4/ADTRG Pin Function Switch (IRQ4) This bit selects whether pin P14/IRQ4/ADTRG is used as P14 or as IRQ4/ADTRG. Bit 4 IRQ4

0 Functions as P1 4 I/O pin (initial value)

1 Functions as IRQ4/ADTRG input pin

Note: For details of ADTRG pin setting, see section 12.3.2, Start of A/D Conversion by External Trigger Input. Bit 3—P1 3/TMIG Pin Function Switch (TMIG) This bit selects whether pin P13/TMIG is used as P13 or as TMIG. Bit 3 TMIG

0 Functions as P1 3 I/O pin (initial value)

1 Functions as TMIG input pin

Bits 2 and 0—Reserved These bits are reserved; they can only be written with 0. Bit 1—Reserved This bit is reserved; it is always read as 1 and cannot be modified. Port Mode Register 2 (PMR2) Bit 7 6 5 4 3 2 1 0 — — POF1 — — WDCKS NCS IRQ0 Initial value 1 1 0 1 1 0 0 0 Read/Write — — R/W — — R/W R/W R/W PMR2 is an 8-bit read/write register. It controls whether the PMOS transistor internal to P35 is on or off, the selection of the watchdog timer clock, the selection of TMIG noise cancellation, and switching of the P4 3/IRQ0 pin functions. Upon reset, PMR2 is initialized to H'D8.

Rev. 8.00 Mar. 09, 2010 Page 201 of 658 REJ09B0042-0800 This section only deals with the bits related to timer G and the watchdog timer. For the functions of the bits, see the descriptions of port 3 (POF1) and port 4 (IRQ0). Bit 2—Watchdog Timer Source Clock (WDCKS) This bit selects the watchdog timer source clock. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024R Group and for the H8/38124 Group are different.

• H8/38024, H8/38024S, H8/38024R Group Bit 2 WDCKS

0 Selects φ/8192 (initial value)

1 Selects φW/32

• H8/38124 Group Bit 2 WDCKS

0 Selects clock based on timer mode register W (TMW) setting * (initial value)

Note: * See section 9.6, Watchdog Timer, for details. Bit 1—TMIG Noise Canceller Select (NCS) This bit selects controls the noise cancellation circuit of the input capture input signal (TMIG). Bit 1 NCS

0 No noise cancellation circuit (initial value)

1 Noise cancellation circuit

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8.2.3 Pin Functions

Table 8.3 shows the port 1 pin functions. Table 8.3 Port 1 Pin Functions Pin Pin Functions and Selection Method P17/IRQ3/TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR17 in PCR1. IRQ 3 0 1 PCR1 7 0 1 * CKSL2 to CKSL0 * Not 0 0 Pin function P1 7 input pin P1 7 output pin IRQ3 input pin IRQ3/TMIF input pin Note: When this pin is used as the TMIF input pin, clear bit IEN3 to 0 in IENR1 to disable the IRQ3 interrupt. P16 The pin function depends on bit PCR1 6 in PCR1. PCR1 6 0 1 Pin function P1 6 input pin P1 6 output pin Note: Pin 16 and the associated function are not implemented on the H8/38124 Group. P14/IRQ4 ADTRG The pin function depends on bit IRQ4 in PMR1, bit TRGE in AMR, and bit PCR14 in PCR1. IRQ4 0 1 PCR1 4 0 1 * TRGE * 0 1 Pin function P1 4 input pin P1 4 output pin IRQ4 input pin IRQ4/ADTRG input pin Note: When this pin is used as the ADTRG input pin, clear bit IEN4 to 0 in IENR1 to disable the IRQ4 interrupt. P13/TMIG The pin function depends on bit TMIG in PMR1 and bit PCR1 3 in PCR1. TMIG 0 1 PCR1 3 0 1 * Pin function P1 3 input pin P1 3 output pin TMIG input pin *: Don’t care

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8.2.4 Pin States

Table 8.4 shows the port 1 pin states in each operating mode. Table 8.4 Port 1 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P17/IRQ3/TMIF P16*1 P14/IRQ4/ADTRG P13/TMIG High- impedance Retains previous state Retains previous state High- impedance* Retains previous state Functional Functional Notes: 1. Pin 1 6 and the associated function are not implemented on the H8/38124 Group. 2. A high-level signal is output when the MOS pull-up is in the on state.

8.2.5 MOS Input Pull-Up

Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset. PCR1n 0 0 1 PUCR1n 0 1 * MOS input pull-up Off On Off (n = 7, 6, 4, 3) *: Don’t care

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8.3 Port 3

8.3.1 Overview

Port 3 is an 8-bit I/O port, configured as shown in figure 8.2. P3 /AEVL P3 /AEVH Port 3 P3 /TMOFH P3 /TMOFL1 P3 /UD0 Figure 8.2 Port 3 Pin Configuration

8.3.2 Register Configuration and Description

Table 8.5 shows the port 3 register configuration. Table 8.5 Port 3 Registers Name Abbr. R/W Initial Value Address Port data register 3 PDR3 R/W H'00 H'FFD6 Port control register 3 PCR3 W H'00 H'FFE6 Port pull-up control register 3 PUCR3 R/W H'00 H'FFE1 Port mode register 2 PMR2 R/W H'D8 H'FFC9 Port mode register 3 PMR3 R/W — H'FFCA

Rev. 8.00 Mar. 09, 2010 Page 205 of 658 REJ09B0042-0800 Port Data Register 3 (PDR3) Bit Initial value Read/Write R/W R/W R/W R/W R/W P30 R/W R/W R/W 215476 3 PDR3 is an 8-bit register that stores data for port 3 pins P37 to P30. If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read. Upon reset, PDR3 is initialized to H'00. Port Control Register 3 (PCR3) Bit Initial value Read/Write PCR3 W PCR3 W PCR3 W PCR3 W PCR3 W PCR30 W PCR3 W PCR3 W 2154 376 PCR3 is an 8-bit register for controlling whether each of the port 3 pins P3 7 to P30 functions as an input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only when the corresponding pin is designated in PMR3 as a general I/O pin. Upon reset, PCR3 is initialized to H'00. PCR3 is a write-only register, which is always read as all 1s.

Rev. 8.00 Mar. 09, 2010 Page 206 of 658 REJ09B0042-0800 Port Pull-Up Control Register 3 (PUCR3) Bit Initial value Read/Write PUCR3 R/W PUCR3 R/W PUCR3 R/W PUCR3 R/W PUCR3 R/W PUCR30 R/W PUCR3 R/W PUCR3 R/W 2 15 4376 PUCR3 controls whether the MOS pull-up of each of the port 3 pins P37 to P30 is on or off. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR3 is initialized to H'00. Port Mode Register 2 (PMR2) Bit 7 6 5 4 3 2 1 0 — — POF1 — — WDCKS NCS IRQ0 Initial value 1 1 0 1 1 0 0 0 Read/Write — — R/W — — R/W R/W R/W PMR2 is an 8-bit read/write register. It controls whether the PMOS transistor internal to P35 is on or off, the selection of the watchdog timer clock, the selection of TMIG noise cancellation, and switching of the P43/IRQ0 pin functions. Upon reset, PMR2 is initialized to H'D8. This section only deals with the bit that controls whether the PMOS transistor internal to pin P35 is on or off. For the functions of the other bits, see the descriptions of port 1 (WDCKS and NCS) and port 4 (IRQ0). Bit 5—Pin P3 5 PMOS Transistor Control (POF1) This bit selects whether the PMOS transistor of the output buffer for pin P3 5 is on or off. Bit 5 POF1

0 CMOS output (initial value)

1 NMOS open-drain output

Note: The pin is an NMOS open-drain output when this bit is set to 1 and P3 5 is an output.

Rev. 8.00 Mar. 09, 2010 Page 207 of 658 REJ09B0042-0800 Port Mode Register 3 (PMR3) Bit Initial value Read/Write AEVL R/W AEVH R/W W W W UD R/W TMOFH R/W TMOFL R/W PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Bit 7—P3 7/AEVL Pin Function Switch (AEVL) This bit selects whether pin P37/AEVL is used as P37 or as AEVL. Bit 7 AEVL

0 Functions as P3 7 I/O pin (initial value)

1 Functions as AEVL input pin

Bit 6—P3 6/AEVH Pin Function Switch (AEVH) This bit selects whether pin P36/AEVH is used as P36 or as AEVH. Bit 6 AEVH

0 Functions as P3 6 I/O pin (initial value)

1 Functions as AEVH input pin

Bits 5 to 3—Reserved These bits are reserved; they can only be written with 0. Bit 2—P3 2/TMOFH Pin Function Switch (TMOFH) This bit selects whether pin P32/TMOFH is used as P32 or as TMOFH. Bit 2 TMOFH

0 Functions as P3 2 I/O pin (initial value)

1 Functions as TMOFH output pin

Rev. 8.00 Mar. 09, 2010 Page 208 of 658 REJ09B0042-0800 Bit 1—P3 1/TMOFL Pin Function Switch (TMOFL) This bit selects whether pin P31/TMOFL is used as P31 or as TMOFL. Bit 1 TMOFL

0 Functions as P3 1 I/O pin (initial value)

1 Functions as TMOFL output pin

Bit 0—P3 0/UD Pin Function Switch (UD) This bit selects whether pin P30/UD is used as P30 or as UD. Bit 0 UD

0 Functions as P3 0 I/O pin (initial value)

1 Functions as UD input pin

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8.3.3 Pin Functions

Table 8.6 shows the port 3 pin functions. Table 8.6 Port 3 Pin Functions Pin Pin Functions and Selection Method P37/AEVL The pin function depends on bit AEVL in PMR3 and bit PCR3 7 in PCR3. AEVL 0 1 PCR3 7 0 1 * Pin function P3 7 input pin P3 7 output pin AEVL input pin P36/AEVH The pin function depends on bit AEVH in PMR3 and bit PCR3 6 in PCR3. AEVH 0 1 PCR3 6 0 1 * Pin function P3 6 input pin P3 6 output pin AEVH input pin P35 to P33 The pin function depends on the corresponding bit in PCR3. PCR3n 0 1 Pin function P3 n input pin P3 n output pin (n = 5 to 3) P32/TMOFH The pin function depends on bit TMOFH in PMR3 and bit PCR3 2 in PCR3. TMOFH 0 1 PCR3 2 0 1 * Pin function P3 2 input pin P3 2 output pin TMOFH output pin P31/TMOFL The pin function depends on bit TMOFL in PMR3 and bit PCR3 1 in PCR3. TMOFL 0 1 PCR3 1 0 1 * Pin function P3 1 input pin P3 1 output pin THOFL output pin P30/UD The pin function depends on bit UD in PMR3 and bit PCR30 in PCR3. UD 0 1 PCR3 0 0 1 * Pin function P3 0 input pin P3 0 output pin UD input pin *: Don’t care

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8.3.4 Pin States

Table 8.7 shows the port 3 pin states in each operating mode. Table 8.7 Port 3 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P37/AEVL P36/AEVH P35 P34 P33 P32/TMOFH P31/TMOFL P30/UD High- impedance Retains previous state Retains previous state High- impedance* Retains previous state Functional Functional Note: * A high-level signal is output when the MOS pull-up is in the on state.

8.3.5 MOS Input Pull-Up

Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR3n 0 0 1 PUCR3n 0 1 * MOS input pull-up Off On Off (n = 7 to 0) *: Don’t care

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8.4 Port 4

8.4.1 Overview

Port 4 is a 3-bit I/O port and 1-bit input port, configured as shown in figure 8.3. /IRQ /TXD32 /RXD32 /SCK32 Port 4 Figure 8.3 Port 4 Pin Configuration

8.4.2 Register Configuration and Description

Table 8.8 shows the port 4 register configuration. Table 8.8 Port 4 Registers Name Abbr. R/W Initial Value Address Port data register 4 PDR4 R/W H'F8 H'FFD7 Port control register 4 PCR4 W H'F8 H'FFE7 Port mode register 2 PMR2 R/W H'D8 H'FFC9 Port Data Register 4 (PDR4) Bit Initial value Read/Write R R/W R/W R/W 3210 PDR4 is an 8-bit register that stores data for port 4 pins P42 to P40. If port 4 is read while PCR4 bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is read while PCR4 bits are cleared to 0, the pin states are read. Upon reset, PDR4 is initialized to H'F8.

Rev. 8.00 Mar. 09, 2010 Page 212 of 658 REJ09B0042-0800 Port Control Register 4 (PCR4) Bit Initial value Read/Write PCR4 W PCR4 W PCR4 W 21 0 PCR4 is an 8-bit register for controlling whether each of port 4 pins P4 2 to P40 functions as an input pin or output pin. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. PCR4 and PDR4 settings are valid when the corresponding pins are designated for general-purpose input/output by SCR3. Upon reset, PCR4 is initialized to H'F8. PCR4 is a write-only register, which is always read as all 1s. Port Mode Register 2 (PMR2) Bit Initial value Read/Write POF1 R/W IRQ0 R/W WDCKS R/W NCS R/W PMR2 is an 8-bit read/write register. It controls whether the PMOS transistor internal to P35 is on or off, the selection of the watchdog timer clock, the selection of TMIG noise cancellation, and switching of the P43/IRQ0 pin functions. Upon reset, PMR2 is initialized to H'D8. This section only deals with the bit that controls switching of the P43/IRQ0 pin functions. For the functions of the other bits, see the descriptions of port 1 (WDCKS and NCS) and port 3 (POF1). Bit 0—P4 3/IRQ0 Pin Function Switch (IRQ0) This bit selects whether pin P43/IRQ0 is used as P43 or as IRQ0. Bit 0 IRQ0

0 Functions as P4 3 input pin (initial value)

1 Functions as IRQ0 input pin

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8.4.3 Pin Functions

Table 8.9 shows the port 4 pin functions. Table 8.9 Port 4 Pin Functions Pin Pin Functions and Selection Method P43/IRQ0 The pin function depends on bit IRQ0 in PMR2. IRQ0 0 1 Pin function P4 3 input pin IRQ0 input pin P42/TXD32 The pin function depends on bit TE in SCR3, bit SPC32 in SPCR, and bit PCR4 2 in PCR4. SPC32 0 1 TE 0 1 PCR4 2 0 1 * Pin function P4 2 input pin P4 2 output pin TXD 32 output pin P41/RXD32 The pin function depends on bit RE in SCR3 and bit PCR4 1 in PCR4. RE 0 1 PCR4 1 0 1 * Pin function P4 1 input pin P4 1 output pin RXD 32 input pin P40/SCK32 The pin function depends on bit CKE1 and CKE0 in SCR3, bit COM in SMR3, and bit PCR40 in PCR4. CKE1 0 1 CKE0 0 1 * COM 0 1 * * PCR4 0 0 1 * * Pin function P4 0 input pin P4 0 output pin SCK 32 output pin SCK32 input pin *: Don’t care

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8.4.4 Pin States

Table 8.10 shows the port 4 pin states in each operating mode. Table 8.10 Port 4 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P43/IRQ0 P42/TXD32 P41/RXD32 P40/SCK32 High- impedance Retains previous state Retains previous state High- impedance Retains previous state Functional Functional

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8.5 Port 5

8.5.1 Overview

Port 5 is an 8-bit I/O port, configured as shown in figure 8.4. P57/WKP7/SEG8 P56/WKP6/SEG7 P55/WKP5/SEG6 P54/WKP4/SEG5 P53/WKP3/SEG4 P52/WKP2/SEG3 P51/WKP1/SEG2 P50/WKP0/SEG1 Port 5 Figure 8.4 Port 5 Pin Configuration

8.5.2 Register Configuration and Description

Table 8.11 shows the port 5 register configuration. Table 8.11 Port 5 Registers Name Abbr. R/W Initial Value Address Port data register 5 PDR5 R/W H'00 H'FFD8 Port control register 5 PCR5 W H'00 H'FFE8 Port pull-up control register 5 PUCR5 R/W H'00 H'FFE2 Port mode register 5 PMR5 R/W H'00 H'FFCC

Rev. 8.00 Mar. 09, 2010 Page 216 of 658 REJ09B0042-0800 Port Data Register 5 (PDR5) Bit 7 6 5 4 3 2 1 0 P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read. Upon reset, PDR5 is initialized to H'00. Port Control Register 5 (PCR5) Bit Initial value Read/Write PCR5 W PCR5 W PCR5 W PCR5 W PCR5 W PCR5 W PCR5 W PCR5 W 76 54 3 210 PCR5 is an 8-bit register for controlling whether each of the port 5 pins P5 7 to P50 functions as an input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. PCR5 and PDR5 settings are valid when the corresponding pins are designated for general-purpose input/output by PMR5 and bits SGS3 to SGS0 in LPCR. Upon reset, PCR5 is initialized to H'00. PCR5 is a write-only register, which is always read as all 1s.

Rev. 8.00 Mar. 09, 2010 Page 217 of 658 REJ09B0042-0800 Port Pull-Up Control Register 5 (PUCR5) Bit Initial value Read/Write PUCR5 R/W PUCR5 R/W PUCR5 R/W PUCR5 R/W PUCR5 R/W PUCR5 R/W PUCR5 R/W PUCR5 R/W 76 54 3 210 PUCR5 controls whether the MOS pull-up of each of port 5 pins P57 to P50 is on or off. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR5 is initialized to H'00. Port Mode Register 5 (PMR5) Bit 7 6 5 4 3 2 1 0 WKP 7 WKP 6 WKP 5 WKP 4 WKP 3 WKP 2 WKP 1 WKP 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00. Bit n—P5 n/WKPn/SEGn+1 Pin Function Switch (WKPn) When pin P5n/WKPn/SEGn+1 is not used as SEGn+1, these bits select whether the pin is used as P5n or WKPn. Bit n WKPn

0 Functions as P5n I/O pin (initial value)

1 Functions as WKPn input pin

(n = 7 to 0) Note: For use as SEG n+1, see section 13.2.1, LCD Port Control Register (LPCR).

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8.5.3 Pin Functions

Table 8.12 shows the port 5 pin functions. Table 8.12 Port 5 Pin Functions Pin Pin Functions and Selection Method P57/WKP7/ SEG8 to The pin function depends on bits WKP7 to WKP0 in PMR5, bits PCR57 to PCR50 in PCR5, and bits SGS3 to SGS0 in LPCR. P50/WKP0/ SEG1 P57 to P54 (n = 7 to 4) SGS3 to SGS0 Other than 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001 WKP n 0 1 * PCR5 n 0 1 * * Pin function P5 n input pin P5 n output pin WKPn input pin SEGn+1 output pin P5 3 to P50 (m= 3 to 0) SGS3 to SGS0 Other than 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000 WKP m 0 1 * PCR5 m 0 1 * * Pin function P5 m input pin P5 m output pin WKPm output pin SEGm+1 output pin *: Don’t care

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8.5.4 Pin States

Table 8.13 shows the port 5 pin states in each operating mode. Table 8.13 Port 5 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P57/WKP7/ SEG8 to P50/ WKP0/SEG1 High- impedance Retains previous state Retains previous state High- impedance* Retains previous state Functional Functional Note: * A high-level signal is output when the MOS pull-up is in the on state. In the HD64F38024 the previous pin state is retained.

8.5.5 MOS Input Pull-Up

Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR5n 0 0 1 PUCR5n 0 1 * MOS input pull-up Off On Off (n = 7 to 0) *: Don’t care

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8.6 Port 6

8.6.1 Overview

Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8.5. P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9 Port 6 Figure 8.5 Port 6 Pin Configuration

8.6.2 Register Configuration and Description

Table 8.14 shows the port 6 register configuration. Table 8.14 Port 6 Registers Name Abbr. R/W Initial Value Address Port data register 6 PDR6 R/W H'00 H'FFD9 Port control register 6 PCR6 W H'00 H'FFE9 Port pull-up control register 6 PUCR6 R/W H'00 H'FFE3

Rev. 8.00 Mar. 09, 2010 Page 221 of 658 REJ09B0042-0800 Port Data Register 6 (PDR6) Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 2105476 3 PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60. If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read. Upon reset, PDR6 is initialized to H'00. Port Control Register 6 (PCR6) Bit Initial value Read/Write PCR67 W PCR66 W PCR65 W PCR64 W PCR63 W PCR60 W PCR62 W PCR61 W PCR6 is an 8-bit register for controlling whether each of the port 6 pins P6 7 to P60 functions as an input pin or output pin. Setting a PCR6 bit to 1 makes the corresponding pin (P67 to P60) an output pin, while clearing the bit to 0 makes the pin an input pin. PCR6 and PDR6 settings are valid when the corresponding pins are designated for general-purpose input/output by bits SGS3 to SGS0 in LPCR. Upon reset, PCR6 is initialized to H'00. PCR6 is a write-only register, which is always read as all 1s.

Rev. 8.00 Mar. 09, 2010 Page 222 of 658 REJ09B0042-0800 Port Pull-Up Control Register 6 (PUCR6) Bit Initial value Read/Write PUCR6 R/W PUCR6 R/W PUCR6 R/W PUCR6 R/W PUCR6 R/W PUCR6 R/W PUCR6 R/W PUCR6 R/W 2 105 4376 PUCR6 controls whether the MOS pull-up of each of the port 6 pins P67 to P60 is on or off. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR6 is initialized to H'00.

8.6.3 Pin Functions

Table 8.15 shows the port 6 pin functions. Table 8.15 Port 6 Pin Functions Pin Pin Functions and Selection Method P67/SEG16 to P60/SEG9 The pin function depends on bits PCR67 to PCR60 in PCR6 and bits SGS3 to SGS0 in LPCR. P67 to P64 (n = 7 to 4) SGS3 to SGS0 Other than 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011 PCR6 n 0 1 * Pin function P6 n input pin P6 n output pin SEG n+9 output pin P6 3 to P60 (m = 3 to 0) SGS3 to SGS0 Other than 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010 PCR6 m 0 1 * Pin function P6 m input pin P6 m output pin SEG m+9 output pin *: Don’t care

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8.6.4 Pin States

Table 8.16 shows the port 6 pin states in each operating mode. Table 8.16 Port 6 Pin States Pin Reset Sleep Subsleep Standby Watch Subactive Active P67/SEG16 to P60/SEG9 High- impedance Retains previous state Retains previous state High- impedance* Retains previous state Functional Functional Note: * A high-level signal is output when the MOS pull-up is in the on state.

8.6.5 MOS Input Pull-Up

Port 6 has a built-in MOS pull-up function that can be controlled by software. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR6n 0 0 1 PUCR6n 0 1 * MOS input pull-up Off On Off (n = 7 to 0) *: Don’t care

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8.7 Port 7

8.7.1 Overview

Port 7 is an 8-bit I/O port, configured as shown in figure 8.6. P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 Port 7 P72/SEG19 P71/SEG18 P70/SEG17 Figure 8.6 Port 7 Pin Configuration

8.7.2 Register Configuration and Description

Table 8.17 shows the port 7 register configuration. Table 8.17 Port 7 Registers Name Abbr. R/W Initial Value Address Port data register 7 PDR7 R/W H'00 H'FFDA Port control register 7 PCR7 W H'00 H'FFEA

Rev. 8.00 Mar. 09, 2010 Page 225 of 658 REJ09B0042-0800 Port Data Register 7 (PDR7) Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 76 54 3 21 0 PDR7 is an 8-bit register that stores data for port 7 pins P77 to P70. If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read. Upon reset, PDR7 is initialized to H'00. Port Control Register 7 (PCR7) Bit Initial value Read/Write PCR7 W PCR7 W PCR7 W PCR7 W PCR7 W PCR7 W PCR7 W PCR7 W 76 54 3 21 0 PCR7 is an 8-bit register for controlling whether each of the port 7 pins P7 7 to P70 functions as an input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. PCR7 and PDR7 settings are valid when the corresponding pins are designated for general-purpose input/output by bits SGS3 to SGS0 in LPCR. Upon reset, PCR7 is initialized to H'00. PCR7 is a write-only register, which is always read as all 1s.

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8.7.3 Pin Functions

Table 8.18 shows the port 7 pin functions. Table 8.18 Port 7 Pin Functions Pin Pin Functions and Selection Method P77/SEG24 to P70/SEG17 The pin function depends on bits PCR77 to PCR70 in PCR7 and bits SGS3 to SGS0 in LPCR. P77 to P74 (n = 7 to 4) SGS3 to SGS0 Other than 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101 PCR7 n 0 1 * Pin function P7 n input pin P7 n output pin SEG n+17 output pin P7 3 to P70 (m = 3 to 0) SGS3 to SGS0 Other than 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100 PCR7 m 0 1 * Pin function P7 m input pin P7 m output pin SEG m+17 output pin *: Don’t care

8.7.4 Pin States

Table 8.19 shows the port 7 pin states in each operating mode. Table 8.19 Port 7 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P77/SEG24 to P70/SEG17 High- impedance Retains previous state Retains previous state High- impedance Retains previous state Functional Functional

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8.8 Port 8

8.8.1 Overview

Port 8 is an 8-bit I/O port configured as shown in figure 8.7. P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 Port 8 Figure 8.7 Port 8 Pin Configuration

8.8.2 Register Configuration and Description

Table 8.20 shows the port 8 register configuration. Table 8.20 Port 8 Registers Name Abbr. R/W Initial Value Address Port data register 8 PDR8 R/W H'00 H'FFDB Port control register 8 PCR8 W H'00 H'FFEB

Rev. 8.00 Mar. 09, 2010 Page 228 of 658 REJ09B0042-0800 Port Data Register 8 (PDR8) Bit Initial value Read/Write P87 R/W P86 R/W P85 R/W P84 R/W P83 R/W R/W P82 R/W P81 R/W PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read. Upon reset, PDR8 is initialized to H'00. Port Control Register 8 (PCR8) Bit Initial value Read/Write PCR87 W PCR86 W PCR85 W PCR84 W PCR83 W PCR80 W PCR82 W PCR81 W PCR8 is an 8-bit register for controlling whether the port 8 pins P87 to P80 functions as an input or output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. PCR8 and PDR8 settings are valid when the corresponding pins are designated for general-purpose input/output by bits SGS3 to SGS0 in LPCR. Upon reset, PCR8 is initialized to H'00. PCR8 is a write-only register, which is always read as all 1s.

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8.8.3 Pin Functions

Table 8.21 shows the port 8 pin functions. Table 8.21 Port 8 Pin Functions Pin Pin Functions and Selection Method The pin function depends on bits PCR87 to PCR80 in PCR8 and bits SGS3 to SGS0 in LPCR. P87 to P84 (n = 7 to 4) P87/SEG32 to P80/SEG25 SGS3 to SGS0 Other than 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111 PCR8 n 0 1 * Pin function P8 n input pin P8 n output pin SEG n+25 output pin P8 3 to P80 (m = 3 to 0) SGS3 to SGS0 Other than 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110 PCR8 m 0 1 * Pin function P8 m input pin P8 m output pin SEG m+25 output pin *: Don’t care

8.8.4 Pin States

Table 8.22 shows the port 8 pin states in each operating mode. Table 8.22 Port 8 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P87/SEG32 to P80/SEG25 High- impedance Retains previous state Retains previous state High- impedance Retains previous state Functional Functional

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8.9 Port 9

8.9.1 Overview

Port 9 is a 6-bit output port, configured as shown in figure 8.8. P95 P94 P93/Vref* P92 P91/PWM2 P90/PWM1 Port 9 Note: * The Vref pin is implemented on the H8/38124 Group only. Figure 8.8 Port 9 Pin Configuration

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8.9.2 Register Configuration and Description

Table 8.23 shows the port 9 register configuration. Table 8.23 Port 9 Registers Name Abbr. R/W Initial Value Address Port data register 9 PDR9 R/W H'FF H'FFDC Port mode register 9 PMR9 R/W — H'FFEC Port Data Register 9 (PDR9) Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W 54 3 210 PDR9 is an 8-bit register that stores data for port 9 pins P95 to P90. Upon reset, PDR9 is initialized to H'FF. Port Mode Register 9 (PMR9) Bit Initial value Read/Write Note: * Readable/writable reserved bit in the H8/38024S Group and H8/38124 Group. PIOFF/⎯* R/W PWM1 R/W W PWM R/W PMR9 is an 8-bit read/write register controlling the selection of the P90 and P91 pin functions.

Rev. 8.00 Mar. 09, 2010 Page 232 of 658 REJ09B0042-0800 Bit 3— P9 2 to P90 Step-Up Circuit Control (PIOFF) Bit 3 turns the P92 to P90 step-up circuit on and off. This bit is reserved in the H8/38024S Group and H8/38124 Group. Bit 3 PIOFF

0 Large-current port step-up circuit is turned on (initial value)

1 Large-current port step-up circuit is turned off

Note: In the H8/38024 ZTAT version and mask ROM version, and the HD64F38024R, the following precautions should be followed when accessing the PIOFF bit. When turning the voltage boost circuit on or off, always write to the register when the buffer NMOS is off (port data set to 1). Also, when turning on the voltage boost circuit, first clear PIOFF to 0 and then after waiting 30 system clock cycles turn on the buffer NMOS (port data cleared to 0). If 30 system clock cycles have not elapsed the voltage boost circuit will not start operating and it will not be possible to produce a large current flow, resulting in unstable operation. In the HD64F38024, the following precautions should be followed when accessing the PIOFF bit. In the HD64F38024, if port data bits are cleared from 1 to 0 while the PIOFF bit is set to 1, repeated charge-discharge cycles will occur in the voltage boost circuit, causing the current consumption to rise and fall cyclically. The amount of rise in the current consumption in this case is between several tens of µA and 100 µA above the normal level. Therefore, the following points should be kept in mind. (1) Not Using Subclock Regardless of whether or not port 9 is used, the PIOFF bit should be left at its initial value (0) and not changed. (2) Not Using Port 9 Port data should be used unchanged with the PIOFF bit either at its initial value (0) or set to 1. In the latter case the current consumption will vary, due to the intermittent operation of the voltage boost circuit, by about 1 µA (standby mode or watch mode, V CC (3) Using Port 9 with PIOFF Always Cleared to 0 This case applies to instances in which the voltage boost circuit is used constantly to generate a large current glow, or an increase in current consumption due to the operation of the voltage boost circuit is permissible even in the standby mode or watch mode (see (2) above). In this case the PIOFF bit should be left at its initial value (0) and not changed. (4) Using Port 9 with PIOFF Set to 1 This case applies to instances in which it is necessary to change the value of the PIOFF bit due to operating conditions or where it is desirable to keep the PIOFF bit set to 1 because no large current is required (for example, shutting down the voltage boost circuit to reduce current consumption in the watch mode). In this case, clear port data

Rev. 8.00 Mar. 09, 2010 Page 233 of 658 REJ09B0042-0800 from 1 to 0 only when the PIOFF bit is cleared to 0. Also, if a large current flow is required, the PIOFF bit should be set to 1 and all the port data bits set to 1. Then clear PIOFF to 0 and, after allowing 30 clock cycles to permit stabilization of the voltage boost circuit, clear the port data bits to 0. If time is not provided to allow the voltage boost circuit to stabilize, it will not be possible to produce a large current flow. There are no such restrictions when setting port data bits from 0 to 1, regardless of the size of the current flow. To shut down the voltage boost circuit, set PIOFF to 1 after programming the port data bits. An example of the sequence of steps is provided below. (Example Procedure) Shutting Down the in the Watch Mode without a Large Current Flow to Port 9 Other operation PIOFF = 0 (voltage boost circuit on) PDR9 operation or other operation PIOFF = 1 (voltage boost circuit off) Execute SLEEP instruction Watch mode Cancel watch mode Bit 2—Reserved This bit is reserved; it can only be written with 0. Bits 1 and 0—P9 n/PWM Pin Function Switches These pins select whether pin P9n/PWMn+1 is used as P9n or as PWMn+1. Bit n WKPn+1

0 Functions as P9 n output pin (initial value)

1 Functions as PWM n+1 output pin

(n = 0 or 1)

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8.9.3 Pin Functions

Table 8.24 shows the port 9 pin functions. Table 8.24 Port 9 Pin Functions Pin Pin Functions and Selection Method P93/Vref* VREFSEL 0 1 Pin function P9 3 output pin V ref input pin (n = 1 or 0) P91/PWMn+1 to P90/PWMn+1 PMR9n 0 1 Pin function P9 n output pin PWM n+1 output pin Note: * The V ref pin is the input pin for the LVD’s external reference voltage. It is implemented on the H8/38124 Group only.

8.9.4 Pin States

Table 8.25 shows the port 9 pin states in each operating mode. Table 8.25 Port 9 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P95 to P92 P9n/PWMn+1 to P9n/PWMn+1 High- impedance Retains previous state Retains previous state High- impedance Retains previous state Functional Functional (n = 1 or 0)

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8.10 Port A

8.10.1 Overview

Port A is a 4-bit I/O port, configured as shown in figure 8.9. PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 Port A Figure 8.9 Port A Pin Configuration

8.10.2 Register Configuration and Description

Table 8.26 shows the port A register configuration. Table 8.26 Port A Registers Name Abbr. R/W Initial Value Address Port data register A PDRA R/W H'F0 H'FFDD Port control register A PCRA W H'F0 H'FFED Port Data Register A (PDRA) Bit Initial value Read/Write PA R/W PA R/W PA R/W PA R/W 3 210 PDRA is an 8-bit register that stores data for port A pins PA3 to PA0. If port A is read while PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If port A is read while PCRA bits are cleared to 0, the pin states are read. Upon reset, PDRA is initialized to H'F0.

Rev. 8.00 Mar. 09, 2010 Page 236 of 658 REJ09B0042-0800 Port Control Register A (PCRA) Bit Initial value Read/Write PCRA W PCRA W PCRA W PCRA W 3 210 PCRA controls whether each of port A pins PA3 to PA0 functions as an input pin or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. PCRA and PDRA settings are valid when the corresponding pins are designated for general-purpose input/output by LPCR. Upon reset, PCRA is initialized to H'F0. PCRA is a write-only register, which is always read as all 1s.

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8.10.3 Pin Functions

Table 8.27 shows the port A pin functions. Table 8.27 Port A Pin Functions Pin Pin Functions and Selection Method PA3/COM4 The pin function depends on bit PCRA 3 in PCRA and bits SGS3 to SGS0. SGS3 to SGS0 0000 0000 Not 0000 PCRA 3 0 1 * Pin function PA 3 input pin PA 3 output pin COM 4 output pin PA2/COM3 The pin function depends on bit PCRA 2 in PCRA and bits SGS3 to SGS0. SGS3 to SGS0 0000 0000 Not 0000 PCRA 2 0 1 * Pin function PA 2 input pin PA 2 output pin COM 3 output pin PA1/COM2 The pin function depends on bit PCRA 1 in PCRA and bits SGS3 to SGS0. SGS3 to SGS0 0000 0000 Not 0000 PCRA 1 0 1 * Pin function PA 1 input pin PA 1 output pin COM 2 output pin PA0/COM1 The pin function depends on bit PCRA 0 in PCRA and bits SGS3 to SGS0. SGS3 to SGS0 0000 Not 0000 PCRA 0 0 1 * Pin function PA 0 input pin PA 0 output pin COM 1 output pin *: Don’t care

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8.10.4 Pin States

Table 8.28 shows the port A pin states in each operating mode. Table 8.28 Port A Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 High- impedance Retains previous state Retains previous state High- impedance Retains previous state Functional Functional

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8.11 Port B

8.11.1 Overview

Port B is an 8-bit input-only port, configured as shown in figure 8.10. PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 PB3/AN3/IRQ1/TMIC PB2/AN2 PB1/AN1/extU* PB0/AN0/extD* Port B Note: * The extU and extD pins are implemented on the H8/38124 Group only. Figure 8.10 Port B Pin Configuration

8.11.2 Register Configuration and Description

Table 8.29 shows the port B register configuration. Table 8.29 Port B Register Name Abbr. R/W Initial Value Address Port data register B PDRB R — H'FFDE Port mode register B PMRB R/W H'F7 H'FFEE

Rev. 8.00 Mar. 09, 2010 Page 240 of 658 REJ09B0042-0800 Port Data Register B (PDRB) Bit Read/Write PB7 R PB6 R PB5 R PB4 R PB R PB R PB R PB R 32 10 Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input voltage. Port Mode Register B (PMRB) Bit Initial value Read/Write IRQ1 R/W PMRB is an 8-bit read/write register controlling the selection of the PB3 pin function. Upon reset, PMRB is initialized to H'F7. Bits 7 to 4 and 2 to 0—Reserved Bits 7 to 4 and 2 to 0 are reserved; they are always read as 1 and cannot be modified. Bit 3—PB 3/AN3/IRQ1 Pin Function Switch (IRQ1) These bits select whether pin PB3/AN3/IRQ1 is used as PB3/AN3 or as IRQ1/TMIC. Bit 3 IRQ1

0 Functions as PB 3/AN3 input pin (initial value)

1 Functions as IRQ1/TMIC input pin

Note: Rising or falling edge sensing can be selected for the IRQ1/TMIC pin. For TMIC pin setting information, see the Timer More Register C (TMC) description in section 9.3.2, Register Descriptions.

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8.11.3 Pin Functions

Table 8.30 shows the port B pin functions. Table 8.30 Port B Pin Functions Pin Pin Functions and Selection Method PB7/AN7 The pin function depends on bits CH3 to CH0 in AMR. CH3 to CH0 Not 1011 1011 Pin function PB 7 input pin AN 7 input pin PB6/AN6 The pin function depends on bits CH3 to CH0 in AMR. CH3 to CH0 Not 1010 1010 Pin function PB 6 input pin AN 6 input pin PB5/AN5 The pin function depends on bits CH3 to CH0 in AMR. CH3 to CH0 Not 1001 1001 Pin function PB 5 input pin AN 5 input pin PB4/AN4 The pin function depends on bits CH3 to CH0 in AMR. CH3 to CH0 Not 1000 1000 Pin function PB 4 input pin AN 4 input pin PB3/AN3/IRQ1/ TMIC The pin function depends on bits CH3 to CH0 in AMR and bit IRQ1 in PMRB and bits TMC2 to TMC0 in TMC. IRQ 1 0 1 CH3 to CH0 Not 0111 0111 * TMC2 to TMC0 * Not 111 111 Pin function PB 3 input pin AN 3 input pin IRQ1 input pin TMIC input pin Note: When this pin is used as the TMIC input pin, clear IEN1 to 0 in IENR1 to disable the IRQ1 interrupt. PB2/AN2 The pin function depends on bits CH3 to CH0 in AMR. CH3 to CH0 Not 0110 0110 Pin function PB 2 input pin AN 2 input pin

Rev. 8.00 Mar. 09, 2010 Page 242 of 658 REJ09B0042-0800 Pin Pin Functions and Selection Method PB1/AN1/extU Switching is accomplished by combining CH3 to CH0 in AMR and VINTUSEL in LVDCR as shown below. Note that VINTUSEL is implemented on the H8/38124 Group only. VINTUSEL 0 1 CH3 to CH0 Not B'0101 B'0101 * Pin function PB 1 input pin AN 1 input pin extU input pin Note: The extU pin is implemented on the H8/38124 Group only. PB0/AN0/extD Switching is accomplished by combining CH3 to CH0 in AMR and VINTDSEL in LVDCR as shown below. Note that VINTDSEL is implemented on the H8/38124 Group only. VINTDSEL 0 1 CH3 to CH0 Not B'0100 B'0100 * Pin function PB 0 input pin AN 0 input pin extD input pin Note: The extD pin is implemented on the H8/38124 Group only. *: Don’t care

8.12 Input/Output Data Inversion Function

8.12.1 Overview

With input pin RXD32 and output pin TXD32, the data can be handled in inverted form. SCINV2 RXD32P41/RXD32 SCINV3 TXD32P42/TXD32 Figure 8.11 Input/Output Data Inversion Function

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8.12.2 Register Configuration and Descriptions

Table 8.31 shows the registers used by the input/output data inversion function. Table 8.31 Register Configuration Name Abbr. R/W Address Serial port control register SPCR R/W H'FF91 Serial Port Control Register (SPCR) Bit Initial value Read/Write SPC32 R/W W SCINV3 R/W W SCINV2 R/W W SPCR is an 8-bit readable/writable register that performs RXD32 and TXD32 pin input/output data inversion switching. Bits 7 and 6—Reserved Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified. Bit 5—P4 2/TXD32 Pin Function Switch (SPC32) This bit selects whether pin P42/TXD32 is used as P42 or as TXD32. Bit 5 SPC32

0 Functions as P4 2 I/O pin (initial value)

1 Functions as TXD 32 output pin*

Note: * Set the TE bit in SCR3 after setting this bit to 1. Bit 4—Reserved Bit 4 is reserved; it can only be written with 0.

Rev. 8.00 Mar. 09, 2010 Page 244 of 658 REJ09B0042-0800 Bit 3—TXD 32 Pin Output Data Inversion Switch Bit 3 specifies whether or not TXD32 pin output data is to be inverted. Bit 3 SCINV3

0 TXD 32 output data is not inverted (initial value)

1 TXD 32 output data is inverted

Bit 2—RXD 32 Pin Input Data Inversion Switch Bit 2 specifies whether or not RXD32 pin input data is to be inverted. Bit 2 SCINV2

0 RXD 32 input data is not inverted (initial value)

1 RXD 32 input data is inverted

Bits 1 and 0—Reserved Bits 1 and 0 are reserved; they can only be written with 0.

8.12.3 Note on Modification of Serial Port Control Register

When a serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying a serial port control register, do so in a state in which data changes are invalidated.

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8.13 Application Note

8.13.1 The Management of the Un-Use Terminal

If an I/O pin not used by the user system is floating, pull it up or down.

• If an unused pin is an input pin, handle it in one of the following ways: ⎯ Pull it up to VCC with an on-chip pull-up MOS. ⎯ Pull it up to VCC with an external resistor of approximately 100 kΩ. ⎯ Pull it down to VSS with an external resistor of approximately 100 kΩ. ⎯ For a pin also used by the A/D converter, pull it up to AVCC.
• If an unused pin is an output pin, handle it in one of the following ways: ⎯ Set the output of the unused pin to high and pull it up to VCC with an on-chip pull-up MOS. ⎯ Set the output of the unused pin to high and pull it up to VCC with an external resistor of approximately 100 kΩ. ⎯ Set the output of the unused pin to low and pull it down to GND with an external resistor of approximately 100 kΩ.

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Rev. 8.00 Mar. 09, 2010 Page 247 of 658 REJ09B0042-0800 Section 9 Timers

9.1 Overview

This LSI provides six timers: timers A, C, F, G, and a watchdog timer, and an asynchronous event counter. The functions of these timers are outlined in table 9.1. Table 9.1 Timer Functions Name Functions Internal Clock Event Input Pin Waveform Output Pin Remarks Timer A • 8-bit timer — —

• Interval function φ/8 to φ/8192 (8 choices)
• Time base φw/128 (choice of 4 overflow periods) Timer C • 8-bit timer
• Interval function
• Event counting function
• Up-count/down-count selectable φ/4 to φ/8192, φW/4 (7 choices) TMIC — Up-count/ down-count controllable by software or hardware Timer F • 16-bit timer
• Event counting function
• Also usable as two independent 8-bit timers
• Output compare output function φ/4 to φ/32, φw/4 (4 choices) TMIF TMOFL TMOFH Timer G • 8-bit timer
• Input capture function
• Interval function φ/2 to φ/64, φW/4 (4 choices) TMIG — Counter clearing option Built-in capture input signal noise canceler Watchdog timer*
• Reset signal generated when 8-bit counter overflows φ/8192 φW/32 — — H8/38024, H8/38024S, H8/38024R Group φ/64 to φ/8192 φW/32 On-chip oscillator H8/38124 Group

Rev. 8.00 Mar. 09, 2010 Page 248 of 658 REJ09B0042-0800 Name Functions Internal Clock Event Input Pin Waveform Output Pin Remarks Asynchro- nous event counter

• 16-bit counter
• Also usable as two independent 8-bit counters
• Counts events asynchronous to φ and φw
• Can count asynchronous events (rising/falling/both edges) independ-ently of the MCU's internal clock φ/2 to φ/8 (3 choices) AEVL AEVH IRQAEC Note: * The watchdog timer functions differently on the H8/38024, H8/38024S, H8/38024R Group and H8/38124 Group. See section 9.6, Watchdog Timer, for details.

9.2 Timer A

9.2.1 Overview

Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768 kHz crystal resonator is connected as the subclock.

Features

Features of timer A are given below.

• Choice of eight internal clock sources (φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32, φ/8).
• Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock time base (using a 32.768 kHz crystal resonator is connected as the subclock).
• An interrupt is requested when the counter overflows.
• Use of module standby mode enables this module to be placed in standby mode independently when not used.

Rev. 8.00 Mar. 09, 2010 Page 250 of 658 REJ09B0042-0800 Register Configuration Table 9.2 shows the register configuration of timer A. Table 9.2 Timer A Registers Name Abbr. R/W Initial Value Address Timer mode register A TMA R/W — H'FFB0 Timer counter A TCA R H'00 H'FFB1 Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA

9.2.2 Register Descriptions

Timer Mode Register A (TMA) Bit Initial value Read/Write W W W TMA3 R/W TMA0 R/W TMA2 R/W TMA1 R/W TMA is an 8-bit read/write register for selecting the prescaler, and input clock. Bits 7 to 5—Reserved Bits 7 to 5 are reserved; only 0 can be written to these bits. Bit 4—Reserved Bit 4 is reserved; it is always read as 1, and cannot be modified.

Rev. 8.00 Mar. 09, 2010 Page 251 of 658 REJ09B0042-0800 Bits 3 to 0—Internal Clock Select (TMA3 to TMA0) Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Prescaler and Divider Ratio or Overflow Period Function 0 0 0 0 PSS, φ/8192 (initial value) Interval timer

1 PSS, φ/4096

1 0 PSS, φ/2048

1 PSS, φ/512

1 0 0 PSS, φ/256

1 PSS, φ/128

1 0 PSS, φ/32

1 PSS, φ/8

1 0 0 0 PSW, 1 s Clock time 1 PSW, 0.5 s base 1 0 PSW, 0.25 s (when using 1 PSW, 0.03125 s 32.768 kHz) 1 0 0 PSW and TCA are reset 1 0

Rev. 8.00 Mar. 09, 2010 Page 252 of 658 REJ09B0042-0800 Timer Counter A (TCA) Bit Initial value Read/Write TCA7 R TCA6 R TCA5 R TCA4 R TCA3 R TCA0 R TCA2 R TCA1 R TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1. TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11. Upon reset, TCA is initialized to H'00. Clock Stop Register 1 (CKSTPR1) ⎯ TFCKSTP TCCKSTP TACKSTP⎯ S32CKSTPA DCKSTP TGCKSTP 7 65 4 3210 1 1111111 ⎯ R/WR /WR /W⎯ R/WR /W R/W Bit: Initial value: Read/Write: CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer A is described here. For details of the other bits, see the sections on the relevant modules. Bit 0—Timer A Module Standby Mode Control (TACKSTP) Bit 0 controls setting and clearing of module standby mode for timer A. TACKSTP Description

1 Timer A module standby mode is cleared (initial value)

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9.2.3 Timer Operation

When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected. After the count value in TCA reaches H'FF, the next clock signal input causes timer A to overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt enable register 1 (IENR1), a CPU interrupt is requested.* At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. Note: * For details on interrupts, see section 3.3, Interrupts. Real-Time Clock Time Base Operation When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00.

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9.2.4 Timer A Operation States

Table 9.3 summarizes the timer A operation states. Table 9.3 Timer A Operation States Operation Mode Reset Active Sleep Watch Sub- active Sub- sleep Standby Module Standby TCA Interval Reset Functions Functions Halted Halted Halted Halted Halted Clock time base Reset Functions Functions Functions Functions Functions Halted Halted TMA Reset Functions Retained Retained Functions Retained Retained Retained Note: When the real-time clock time base function is selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/φ (s) in the count cycle.

9.2.5 Application Note

When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of the timer mode register A (TMA) cannot be rewritten. Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3) of the timer mode register A (TMA).

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9.3 Timer C

9.3.1 Overview

Timer C is an 8-bit timer that increments or decrements each time a clock pulse is input. This timer has two operation modes, interval and auto reload. Features of timer C are given below.

• Choice of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/64, φ/16, φ/4, φ W/4) or an external clock (can be used to count external events).
• An interrupt is requested when the counter overflows.
• Up/down-counter switching is possible by hardware or software.
• Subactive mode or subsleep mode operation is possible when φW/4 is selected as the internal clock, or when an external clock is selected.
• Use of module standby mode enables this module to be placed in standby mode independently when not used.

Rev. 8.00 Mar. 09, 2010 Page 257 of 658 REJ09B0042-0800 Register Configuration Table 9.5 shows the register configuration of timer C. Table 9.5 Timer C Registers Name Abbr. R/W Initial Value Address Timer mode register C TMC R/W H'18 H'FFB4 Timer counter C TCC R H'00 H'FFB5 Timer load register C TLC W H'00 H'FFB5 Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA

9.3.2 Register Descriptions

Timer Mode Register C (TMC) Bit Initial value Read/Write TMC7 R/W TMC6 R/W TMC5 R/W TMC0 R/W TMC2 R/W TMC1 R/W TMC is an 8-bit read/write register for selecting the auto-reload function and input clock, and performing up/down-counter control. Upon reset, TMC is initialized to H'18. Bit 7—Auto-Reload Func tion Select (TMC7) Bit 7 selects whether timer C is used as an interval timer or auto-reload timer. Bit 7 TMC7

0 Interval timer function selected (initial value)

1 Auto-reload function selected

Rev. 8.00 Mar. 09, 2010 Page 258 of 658 REJ09B0042-0800 Bits 6 and 5—Counter Up/Down Control (TMC6, TMC5) Selects whether TCC up/down control is performed by hardware using UD pin input, or whether TCC functions as an up-counter or a down-counter. Bit 6 TMC6 Bit 5 TMC5 0 0 TCC is an up-counter (initial value) 0 1 TCC is a down-counter 1 * Hardware control by UD pin input UD pin input high: Down-counter UD pin input low: Up-counter *: Don't care Bits 4 and 3—Reserved Bits 4 and 3 are reserved; they are always read as 1 and cannot be modified. Bits 2 to 0—Clock Select (TMC2 to TMC0) Bits 2 to 0 select the clock input to TCC. For external event counting, either the rising or falling edge can be selected. Bit 2 TMC2 Bit 1 TMC1 Bit 0 TMC0 0 0 0 Internal clock: φ/8192 (initial value) 0 0 1 Internal clock: φ/2048 0 1 0 Internal clock: φ/512 0 1 1 Internal clock: φ/64 1 0 0 Internal clock: φ/16 1 0 1 Internal clock: φ/4 1 1 0 Internal clock: φW/4 1 1 1 External event (TMIC): rising or falling edge * Note: * The edge of the external event signal is selected by bit IEG1 in the IRQ edge select register (IEGR). See IRQ Edge Select Register (IEGR) in section 3.3.2, Interrupt Control Registers, for details. IRQ1 in port mode register B (PMRB) must be set to 1 before setting 111 in bits TMC2 to TMC0.

Rev. 8.00 Mar. 09, 2010 Page 259 of 658 REJ09B0042-0800 Timer Counter C (TCC) Bit Initial value Read/Write TCC7 R TCC6 R TCC5 R TCC4 R TCC3 R TCC0 R TCC2 R TCC1 R TCC is an 8-bit read-only up/down-counter, which is incremented or decremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode register C (TMC). TCC values can be read by the CPU at any time. When TCC overflows from H'FF to H'00 or to the value set in TLC, or underflows from H'00 to H'FF or to the value set in TLC, the IRRTC bit in IRR2 is set to 1. TCC is allocated to the same address as TLC. Upon reset, TCC is initialized to H'00. Timer Load Register C (TLC) Bit Initial value Read/Write TLC7 W TLC6 W TLC5 W TLC4 W TLC3 W TLC0 W TLC2 W TLC1 W TLC is an 8-bit write-only register for setting the reload value of timer counter C (TCC). When a reload value is set in TLC, the same value is loaded into timer counter C as well, and TCC starts counting up/down from that value. When TCC overflows or underflows during operation in auto-reload mode, the TLC value is loaded into TCC. Accordingly, overflow/underflow period can be set within the range of 1 to 256 input clocks. The same address is allocated to TLC as to TCC. Upon reset, TLC is initialized to H'00.

Rev. 8.00 Mar. 09, 2010 Page 260 of 658 REJ09B0042-0800 Clock Stop Register 1 (CKSTPR1) ⎯ TFCKSTP TCCKSTP TACKSTP⎯ S32CKSTPA DCKSTP TGCKSTP 7 65 4 3210 1 1111111 ⎯ R/WR /WR /W⎯ R/WR /W R/W Bit: Initial value: Read/Write: CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer C is described here. For details of the other bits, see the sections on the relevant modules. Bit 1—Timer C Module Standby Mode Control (TCCKSTP) Bit 1 controls setting and clearing of module standby mode for timer C. TCCKSTP Description

1 Timer C module standby mode is cleared (initial value)

9.3.3 Timer Operation

When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit interval timer. Upon reset, TCC is initialized to H'00 and TMC to H'18, so TCC continues up-counting as an interval up-counter without halting immediately after a reset. The timer C operating clock is selected from seven internal clock signals output by prescalers S and W, or an external clock input at pin TMIC. The selection is made by bits TMC2 to TMC0 in TMC. TCC up/down-count control can be performed either by software or hardware. The selection is made by bits TMC6 and TMC5 in TMC. After the count value in TCC reaches H'FF (H'00), the next clock input causes timer C to overflow (underflow), setting bit IRRTC in IRR2 to 1. If IENTC = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested. At overflow (underflow), TCC returns to H'00 (H'FF) and starts counting up (down) again.

Rev. 8.00 Mar. 09, 2010 Page 261 of 658 REJ09B0042-0800 During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC), the same value is set in TCC. Note: For details on interrupts, see section 3.3, Interrupts. Auto-Reload Timer Operation Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC, becoming the value from which TCC starts its count. After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow/underflow. The TLC value is then loaded into TCC, and the count continues from that value. The overflow/underflow period can be set within a range from 1 to 256 input clocks, depending on the TLC value. The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval mode. In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in TCC. Event Counter Operation Timer C can operate as an event counter, counting rising or falling edges of an external event signal input at pin TMIC. External event counting is selected by setting bits TMC2 to TMC0 in timer mode register C (TMC) to all 1s (111). TCC counts up/down at the rising/falling edge of an external event signal input at pin TMIC. When timer C is used to count external event input, bit IRQ1 in PMRB should be set to 1 and bit IEN1 in IENR1 cleared to 0 to disable interrupt IRQ1 requests. TCC Up/Down Control by Hardware With timer C, TCC up/down control can be performed by UD pin input. When bit TMC6 in TMC is set to 1, TCC functions as an up-counter when UD pin input is low, and as a down-counter when high. When using UD pin input, set bit UD in PMR3 to 1.

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9.3.4 Timer C Operation States

Table 9.6 summarizes the timer C operation states. Table 9.6 Timer C Operation States Operation Mode Reset Active Sleep Watch Sub- active Sub- sleep Standby Module Standby TCC Interval Reset Functions Functions Halted Functions/ Halted* Functions/ Halted* Halted Halted Auto reload Reset Functions Functions Halted Functions/ Halted* Functions/ Halted* Halted Halted TMC Reset Functions Retained Retained Functions Retained Retained Retained Note: * When φw/4 is selected as the TCC internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/φ (s). When the counter is operated in subactive mode or subsleep mode, either select φw/4 as the internal clock or select an external clock. The counter will not operate on any other internal clock. If φw/4 is selected as the internal clock for the counter when φw/8 has been selected as subclock φSUB, the lower 2 bits of the counter operate on the same cycle, and the operation of the least significant bit is unrelated to the operation of the counter.

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9.4 Timer F

9.4.1 Overview

Timer F is a 16-bit timer with a built-in output compare function. As well as counting external events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH and timer FL). Features of timer F are given below.

• Choice of four internal clock sources (φ/32, φ/16, φ/4, φw/4) or an external clock (can be used as an external event counter)
• TMOFH/TMOFL pin toggle output provided using a single compare match signal (toggle output initial value can be set)
• Counter resetting by a compare match signal
• Two interrupt sources: one compare match, one overflow
• Can operate as two independent 8-bit timers (timer FH and timer FL) (in 8-bit mode). Timer FH 8-Bit Timer* Timer FL 8-Bit Timer/Event Counter Internal clock Choice of 4 ( φ/32, φ/16, φ/4, φw/4) Event input — TMIF pin Toggle output One compare match signal, output to TMOFH pin(initial value settable) One compare match signal, output to TMOFL pin (initial value settable) Counter reset Counter can be reset by compare match signal Interrupt sources One compare match One overflow Note: * When timer F operates as a 16-bit timer, it operates on the timer FL overflow signal.
• Operation in watch mode, subactive mode, and subsleep mode When φw/4 is selected as the internal clock, timer F can operate in watch mode, subactive mode, and subsleep mode.
• Use of module standby mode enables this module to be placed in standby mode independently when not used.

Rev. 8.00 Mar. 09, 2010 Page 265 of 658 REJ09B0042-0800 Pin Configuration Table 9.7 shows the timer F pin configuration. Table 9.7 Pin Configuration Name Abbr. I/O Function Timer F event input TMIF Input Event input pin for input to TCFL Timer FH output TMOFH Output Timer FH toggle output pin Timer FL output TMOFL Output Timer FL toggle output pin Register Configuration Table 9.8 shows the register configuration of timer F. Table 9.8 Timer F Registers Name Abbr. R/W Initial Value Address Timer control register F TCRF W H'00 H'FFB6 Timer control/status register F TCSRF R/W H'00 H'FFB7 8-bit timer counter FH TCFH R/W H'00 H'FFB8 8-bit timer counter FL TCFL R/W H'00 H'FFB9 Output compare register FH OCRFH R/W H'FF H'FFBA Output compare register FL OCRFL R/W H'FF H'FFBB Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA

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9.4.2 Register Descriptions

16-bit Timer Counter (TCF) 8-bit Timer Counter (TCFH) 8-bit Timer Counter (TCFL) 15 1 4 13 12 11 10 9 8 TCF TCFH T CFL 7 65 4 3210 0000000000000000 R/W Bit: Initial value: Read/Write: R/WR /WR /WR /WR /WR /WR /WR /WR /WR /WR /WR /WR /WR /WR /W TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL. In addition to the use of TCF as a 16-bit counter with TCFH as the upper 8 bits and TCFL as the lower 8 bits, TCFH and TCFL can also be used as independent 8-bit counters. TCFH and TCFL can be read and written by the CPU, but when they are used in 16-bit mode, data transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP, see section 9.4.3, CPU Interface. TCFH and TCFL are each initialized to H'00 upon reset. a. 16-bit mode (TCF) When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input clock is selected by bits CKSL2 to CKSL0 in TCRF. TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF. When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an interrupt request is sent to the CPU. b. 8-bit mode (TCFL/TCFH) When CKSH2 is set to 1 in TCRF, TCFH, and TCFL operate as two independent 8-bit counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to CKSL0) in TCRF. TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH (CCLRL) in TCSRF. When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF. If OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU.

Rev. 8.00 Mar. 09, 2010 Page 267 of 658 REJ09B0042-0800 16-bit Output Compare Register (OCRF) 8-bit Output Compare Register (OCRFH) 8-bit Output Compare Register (OCRFL) 15 1 4 13 12 11 10 9 8 OCRF OCRFH O CRFL 7 65 4 3210 1111111111111111 R/WR /WR /WR /WR /WR /WR /WR /WR /WR /WR /WR /WR /WR /WR /WR /W Bit: Initial value: Read/Write: OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers. OCRFH and OCRFL can be read and written by the CPU, but when they are used in 16-bit mode, data transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP, see section 9.4.3, CPU Interface. OCRFH and OCRFL are each initialized to H'FF upon reset. a. 16-bit mode (OCRF) When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents are constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. At the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Toggle output can be provided from the TMOFH pin by means of compare matches, and the output level can be set (high or low) by means of TOLH in TCRF. b. 8-bit mode (OCRFH/OCRFL) When CKSH2 is set to 1 in TCRF, OCRFH, and OCRFL operate as two independent 8-bit registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL. When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare matches, and the output level can be set (high or low) by means of TOLH (TOLL) in TCRF.

Rev. 8.00 Mar. 09, 2010 Page 268 of 658 REJ09B0042-0800 Timer Control Register F (TCRF) TOLH CKSL2C KSL1C KSL0CKSH2C KSH1C KSH0 TOLL 7 65 4 3210 0 0000000 W WWWWWW W Bit: Initial value: Read/Write: TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources or external event input, and sets the output level of the TMOFH and TMOFL pins. TCRF is initialized to H'00 upon reset. Bit 7—Toggle Output Level H (TOLH) Bit 7 sets the TMOFH pin output level. The output level is effective immediately after this bit is written. Bit 7 TOLH

0 Low level (initial value)

1 High level

Bits 6 to 4—Clock Select H (CKSH2 to CKSH0) Bits 6 to 4 select the clock input to TCFH from among four internal clock sources or TCFL overflow. Bit 6 CKSH2 Bit 5 CKSH1 Bit 4 CKSH0 0 0 0 16-bit mode, counting on TCFL overflow signal (initial value) 0 0 1 0 1 0 0 1 1 Use prohibited 1 0 0 Internal clock: counting on φ/32 1 0 1 Internal clock: counting on φ/16 1 1 0 Internal clock: counting on φ/4 1 1 1 Internal clock: counting on φw/4

Rev. 8.00 Mar. 09, 2010 Page 269 of 658 REJ09B0042-0800 Bit 3—Toggle Output Level L (TOLL) Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is written. Bit 3 TOLL Bits 2 to 0—Clock Select L (CKSL2 to CKSL0) Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event input. Bit 2 CKSL2 Bit 1 CKSL1 Bit 0 CKSL0 Counting on external event (TMIF) rising/falling edge* (initial value) 0 1 0 0 1 1 Use prohibited 1 0 0 Internal clock: counting on φ/32 1 0 1 Internal clock: counting on φ/16 1 1 0 Internal clock: counting on φ/4 1 1 1 Internal clock: counting on φw/4 Note: * External event edge selection is set by IEG3 in the IRQ edge select register (IEGR). For details, see IRQ Edge Select Register (IEGR) in section 3.3.2, Interrupt Control Registers. Note that the timer F counter may increment if the setting of IRQ3 in port mode register 1 (PMR1) is changed from 0 to 1 or from 1 to 0 while the TMIF pin is low in order to change the TMIF pin function.

Rev. 8.00 Mar. 09, 2010 Page 270 of 658 REJ09B0042-0800 Timer Control/Status Register F (TCSRF) OVFH CMFL OVIEL CCLRLCMFH OVIEH CCLRH OVFL 7 6543210 0 0000000 R/(W)* R/(W)* R/W R/WR/(W)* R/W R/W R/(W)* Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. Bit: Initial value: Read/Write: TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests. TCSRF is initialized to H'00 upon reset. Bit 7—Timer Overflow Flag H (OVFH) Bit 7 is a status flag indicating that TCFH has overflowed from H'FF to H'00. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7 OVFH After reading OVFH = 1, cleared by writing 0 to OVFH Set when TCFH overflows from H’FF to H’00 Bit 6—Compare Match Flag H (CMFH) Bit 6 is a status flag indicating that TCFH has matched OCRFH. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6 CMFH After reading CMFH = 1, cleared by writing 0 to CMFH Set when the TCFH value matches the OCRFH value

Rev. 8.00 Mar. 09, 2010 Page 271 of 658 REJ09B0042-0800 Bit 5—Timer Overflow Interrupt Enable H (OVIEH) Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows. Bit 5 OVIEH

0 TCFH overflow interrupt request is disabled (initial value)

1 TCFH overflow interrupt request is enabled

Bit 4—Counter Clear H (CCLRH) In 16-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match. In 8-bit mode, bit 4 selects whether TCFH is cleared when TCFH and OCRFH match. Bit 4 CCLRH 0 16-bit mode: TCF clearing by compare match is disabled 8-bit mode: TCFH clearing by compare match is disabled (initial value) 1 16-bit mode: TCF clearing by compare match is enabled 8-bit mode: TCFH clearing by compare match is enabled Bit 3—Timer Overflow Flag L (OVFL) Bit 3 is a status flag indicating that TCFL has overflowed from H'FF to H'00. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 3 OVFL After reading OVFL = 1, cleared by writing 0 to OVFL Set when TCFL overflows from H’FF to H’00

Rev. 8.00 Mar. 09, 2010 Page 272 of 658 REJ09B0042-0800 Bit 2—Compare Match Flag L (CMFL) Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2 CMFL After reading CMFL = 1, cleared by writing 0 to CMFL Set when the TCFL value matches the OCRFL value Bit 1—Timer Overflow Interrupt Enable L (OVIEL) Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows. Bit 1 OVIEL

0 TCFL overflow interrupt request is disabled (initial value)

1 TCFL overflow interrupt request is enabled

Bit 0—Counter Clear L (CCLRL) Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match. Bit 0 CCLRL

0 TCFL clearing by compare match is disabled (initial value)

1 TCFL clearing by compare match is enabled

Rev. 8.00 Mar. 09, 2010 Page 273 of 658 REJ09B0042-0800 Clock Stop Register 1 (CKSTPR1) ⎯ TFCKSTP TCCKSTP TACKSTP⎯ S32CKSTPA DCKSTP TGCKSTP 7 65 4 3210 1 1111111 ⎯ R/WR /WR /W⎯ R/WR /W R/W Bit: Initial value: Read/Write: CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer F is described here. For details of the other bits, see the sections on the relevant modules. Bit 2—Timer F Module Standby Mode Control (TFCKSTP) Bit 2 controls setting and clearing of module standby mode for timer F. TFCKSTP Description

1 Timer F module standby mode is cleared (initial value)

9.4.3 CPU Interface

TCF and OCRF are 16-bit read/write registers, but the CPU is connected to the on-chip peripheral modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit temporary register (TEMP). When performing TCF read/write access or OCRF write access in 16-bit mode, data will not be transferred correctly if only the upper byte or only the lower byte is accessed. Access must be performed for all 16 bits (using two consecutive byte-size MOV instructions), and the upper byte must be accessed before the lower byte. In 8-bit mode, there are no restrictions on the order of access. Write Access Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next, write access to the lower byte results in transfer of the data in TEMP to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte.

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9.4.4 Operation

Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is constantly compared with the value set in output compare register F, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can also function as two independent 8-bit timers. Timer F Operation Timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in each of these modes is described below. a. Operation in 16-bit timer mode When CKSH2 is cleared to 0 in timer control register F (TCRF), timer F operates as a 16-bit timer. Following a reset, timer counter F (TCF) is initialized to H'0000, output compare register F (OCRF) to H'FFFF, and timer control register F (TCRF) and timer control/status register F (TCSRF) to H'00. The counter starts incrementing on external event (TMIF) input. The external event edge selection is set by IEG3 in the IRQ edge select register (IEGR). The timer F operating clock can be selected from three internal clocks output by prescaler S or an external clock by means of bits CKSL2 to CKSL0 in TCRF. OCRF contents are constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU, and at the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF is cleared. TMOFH pin output can also be set by TOLH in TCRF. When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU. b. Operation in 8-bit timer mode When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH and TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to CKSL0 in TCRF. When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in TCSRF. If IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at the same time, TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF is 1, TCFH/TCFL is cleared. TMOFH pin/TMOFL pin output can also be set by TOLH/TOLL in TCRF. When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request is sent to the CPU.

Rev. 8.00 Mar. 09, 2010 Page 277 of 658 REJ09B0042-0800 TCF Increment Timing TCF is incremented by clock input (internal clock or external event input). a. Internal clock operation Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock sources (φ/32, φ/16, φ/4, or φw/4) created by dividing the system clock (φ or φw). b. External event operation External event input is selected by clearing CKSL2 to 0 in TCRF. TCF can increment on either the rising or falling edge of external event input. External event edge selection is set by IEG3 in the interrupt controller’s IEGR register. An external event pulse width of at least 2 system clocks (φ) is necessary. Shorter pulses will not be counted correctly. TMOFH/TMOFL Output Timing In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is toggled by the occurrence of a compare match. Figure 9.6 shows the output timing. φ TMIF (when IEG3 = 1) Count input clock TCF OCRF TMOFH TMOFL Compare match signal NN NN N+1 N+1 Figure 9.6 TMOFH/TMOFL Output Timing

Rev. 8.00 Mar. 09, 2010 Page 278 of 658 REJ09B0042-0800 TCF Clear Timing TCF can be cleared by a compare match with OCRF. Timer Overflow Flag (OVF) Set Timing OVF is set to 1 when TCF overflows from H'FFFF to H'0000. Compare Match Flag Set Timing The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match. The compare match signal is generated in the last state during which the values match (when TCF is updated from the matching value to a new value). When TCF matches OCRF, the compare match signal is not generated until the next counter clock. Timer F Operation Modes Timer F operation modes are shown in table 9.9. Table 9.9 Timer F Operation Modes Operation Mode Reset Active Sleep Watch Sub- active Sub- sleep Standby Module Standby TCF Reset Functions Functions Functions/ Halted* Functions/ Halted* Functions/ Halted* Halted Halted OCRF Reset Functions Held Held Functions Held Held Held TCRF Reset Functions Held Held Functions Held Held Held TCSRF Reset Functions Held Held Functions Held Held Held Note: * When φw/4 is selected as the TCF internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/φ (s). When the counter is operated in subactive mode, watch mode, or subsleep mode, φ w/4 must be selected as the internal clock. The counter will not operate if any other internal clock is selected.

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9.4.5 Application Notes

The following types of contention and operation can occur when timer F is used. 16-bit Timer Mode In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin should be used as a port pin. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped. Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated. Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied. When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not output. 8-bit Timer Mode a. TCFH, OCRFH In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write. If an OCRFH write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point. The compare match signal is output in synchronization with the TCFH clock. If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not output.

Rev. 8.00 Mar. 09, 2010 Page 280 of 658 REJ09B0042-0800 b. TCFL, OCRFL In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLL data is output to the TMOFL pin as a result of the TCRF write. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped. If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not output. Clear Timer FH, Timer FL Interrupt Request Flags (IRRTFH, IRRTFL), Timer Overflow Flags H, L (OVFH, OVFL) and Compare Match Flags H, L (CMFH, CMFL) When φw/4 is selected as the internal clock, “Interrupt factor generation signal” will be operated with φw and the signal will be outputted with φw width. And, “Overflow signal” and “Compare match signal” are controlled with 2 cycles of φw signals. Those signals are outputted with 2 cycles width of φw (figure 9.7) In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the term of validity of “Interrupt factor generation signal”, same interrupt request flag is set. (figure 9.7 (1)) And, you cannot be cleared timer overflow flag and compare match flag during the term of validity of “Overflow signal” and “Compare match signal”. For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time timer FH, timer FL interrupt might be repeated. (figure 9.7 (2)) Therefore, to definitely clear interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and compare match flag, clear should be processed after read timer control status register F (TCSRF) after the time that calculated with below (1) formula. For ST of (1) formula, please substitute the longest number of execution states in used instruction. (10 states of RTE instruction when MULXU, DIVXU instruction is not used, 14 states when MULXU, DIVXU instruction is used) In subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and compare match flag clear.

Rev. 8.00 Mar. 09, 2010 Page 281 of 658 REJ09B0042-0800 The term of validity of “Interrupt factor generation signal” = 1 cycle of φw + waiting time for completion of executing instruction ST: Executing number of execution states Method 1 is recommended to operate for time efficiency. Method 1 1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0). 2. After program process returned normal handling, clear interrupt request flags (IRRTFH, IRRTFL) after more than that calculated with (1) formula. 3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). 4. Operate interrupt permission (set IENFH, IENFL to 1). Method 2 1. Set interrupt handling routine time to more than time that calculated with (1) formula. 2. Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine. 3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). All above attentions are also applied in 16-bit mode and 8-bit mode.

Rev. 8.00 Mar. 09, 2010 Page 282 of 658 REJ09B0042-0800 Program process φW Interrupt request flag (IRRTFH, IRRTFL) Interrupt factor generation signal (Internal signal, nega-active) Overflow signal, Compare match signal (Internal signal, nega-active) Interrupt Interrupt Normal Interrupt request flag clear Interrupt request flag clear (1) (2) Figure 9.7 Clear Interrupt Request Flag when Interrupt Factor Generation Signal is Valid Timer Counter (TCF) Read/Write When φw/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on TCF is impossible. And, when read TCF, as the system clock and internal clock are mutually asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF read value error of ±1. When read/write TCF in active (high-speed, medium-speed) mode is needed, please select internal clock except for φw/4 before read/write. In subactive mode, even φw/4 is selected as the internal clock, normal read/write TCF is possible.

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9.5 Timer G

9.5.1 Overview

Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of pulses input from the input capture input pin (input capture input signal). High-frequency component noise in the input capture input signal can be eliminated by a noise canceler, enabling accurate measurement of the input capture input signal duty cycle. If input capture input is not set, timer G functions as an 8-bit interval timer. Features of timer G are given below.

• Choice of four internal clock sources (φ/64, φ/32, φ/2, φw/4)
• Dedicated input capture functions for rising and falling edges
• Level detection at counter overflow It is possible to detect whether overflow occurred when the input capture input signal was high or when it was low.
• Selection of whether or not the counter value is to be cleared at the input capture input signal rising edge, falling edge, or both edges
• Two interrupt sources: one input capture, one overflow. The input capture input signal rising or falling edge can be selected as the interrupt source.
• A built-in noise canceler eliminates high-frequency component noise in the input capture input signal.
• Watch mode, subactive mode, or subsleep mode operation is possible when φw/4 is selected as the internal clock.
• Use of module standby mode enables this module to be placed in standby mode independently when not used.

Rev. 8.00 Mar. 09, 2010 Page 285 of 658 REJ09B0042-0800 Register Configuration Table 9.11 shows the register configuration of timer G. Table 9.11 Timer G Registers Name Abbr. R/W Initial Value Address Timer control register G TMG R/W H'00 H'FFBC Timer counter G TCG — H'00 — Input capture register GF ICRGF R H'00 H'FFBD Input capture register GR ICRGR R H'00 H'FFBE Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA

9.5.2 Register Descriptions

Timer Counter G (TCG) TCG7 T CG2 TCG1 TCG0TCG6 TCG5 TCG4 T CG3 7 65 4 3210 0 0000000 Bit: Initial value: Read/Write: TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by bits CKS1 and CKS0 in TMG. TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the rising edge, falling edge, or both edges of the input capture input signal, according to the setting made in TMG. When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU. For details of the interrupt, see section 3.3, Interrupts. TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset. Note: * An input capture signal may be generated when TMIG is modified.

Rev. 8.00 Mar. 09, 2010 Page 286 of 658 REJ09B0042-0800 Input Capture Register GF (ICRGF) ICRGF7 I CRGF2 ICRGF1 ICRGF0ICRGF6 ICRGF5 ICRGF4 I CRGF3 7 65 4 3210 0 0000000 R RRRRRR R Bit: Initial value: Read/Write: ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time, IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU. For details of the interrupt, see section 3.3, Interrupts. To ensure dependable input capture operation, the pulse width of the input capture input signal must be at least 2φ or 2φ SUB (when the noise canceler is not used). ICRGF is initialized to H'00 upon reset. Input Capture Register GR (ICRGR) ICRGR7I CRGR2 ICRGR1 ICRGR0ICRGR6 ICRGR5 ICRGR4I CRGR3 7 65 4 3210 0 0000000 R RRRRRR R Bit: Initial value: Read/Write: ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 0 at this time, IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU. For details of the interrupt, see section 3.3, Interrupts. To ensure dependable input capture operation, the pulse width of the input capture input signal must be at least 2φ or 2φSUB (when the noise canceler is not used). ICRGR is initialized to H'00 upon reset.

Rev. 8.00 Mar. 09, 2010 Page 287 of 658 REJ09B0042-0800 Timer Mode Register G (TMG) OVFH CCLR0 CKS1 CKS0OVFL OVIE IIE GS CCLR1 7 6543210 0 0000000 R/(W)* R/W R/W R/WR/(W)* R/W R/W R/W Bit: Initial value: Read/Write: Note: * Bits 7 and 6 can only be written with 0, for flag clearing. TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock sources, counter clear selection, and edge selection for the input capture input signal interrupt request, controls enabling of overflow interrupt requests, and also contains the overflow flags. TMG is initialized to H'00 upon reset. Bit 7—Timer Overflow Flag H (OVFH) Bit 7 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture input signal is high. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7 OVFH

0 Clearing condition:

After reading OVFH = 1, cleared by writing 0 to OVFH (initial value) Set when input capture input signal is high level and TCG overflows from H'FF to H'00 Bit 6—Timer Overflow Flag L (OVFL) Bit 6 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture input signal is low, or in interval operation. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6 OVFL After reading OVFL = 1, cleared by writing 0 to OVFL (initial value) Set when TCG overflows from H'FF to H'00 while input capture input signal is high level or during interval operation

Rev. 8.00 Mar. 09, 2010 Page 288 of 658 REJ09B0042-0800 Bit 5—Timer Overflow Interrupt Enable (OVIE) Bit 5 selects enabling or disabling of interrupt generation when TCG overflows. Bit 5 OVIE

0 TCG overflow interrupt request is disabled (initial value)

1 TCG overflow interrupt request is enabled

Bit 4—Input Capture Interrupt Edge Select (IIEGS) Bit 4 selects the input capture input signal edge that generates an interrupt request. Bit 4 IIEGS

0 Interrupt generated on rising edge of input capture input signal (initial value)

1 Interrupt generated on falling edge of input capture input signal

Bits 3 and 2—Counter Clear 1 and 0 (CCLR1, CCLR0) Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges of the input capture input signal. Bit 3 CCLR1 Bit 2 CCLR0 0 0 TCG clearing is disabled (initial value) 0 1 TCG cleared by falling edge of input capture input signal 1 0 TCG cleared by rising edge of input capture input signal 1 1 TCG cleared by both edges of input capture input signal

Rev. 8.00 Mar. 09, 2010 Page 289 of 658 REJ09B0042-0800 Bits 1 and 0—Clock Select (CKS1, CKS0) Bits 1 and 0 select the clock input to TCG from among four internal clock sources. Bit 1 CKS1 Bit 0 CKS0 0 0 Internal clock: counting on φ/64 (initial value) 0 1 Internal clock: counting on φ/32 1 0 Internal clock: counting on φ/2 1 1 Internal clock: counting on φw/4 Clock Stop Register 1 (CKSTPR1) ⎯ TFCKSTP TCCKSTP TACKSTP⎯ S32CKSTPA DCKSTP TGCKSTP 7 65 4 3210 1 1111111 ⎯ R/WR /WR /W⎯ R/WR /W R/W Bit: Initial value: Read/Write: CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer G is described here. For details of the other bits, see the sections on the relevant modules. Bit 3—Timer G Module Standby Mode Control (TGCKSTP) Bit 3 controls setting and clearing of module standby mode for timer G. TGCKSTP Description

1 Timer G module standby mode is cleared (initial value)

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9.5.3 Noise Canceler

The noise canceler consists of a digital low-pass filter that eliminates high-frequency component noise from the pulses input from the input capture input pin. The noise canceler is set by NCS * in PMR2. Figure 9.9 shows a block diagram of the noise canceler. C DQ Latch C DQ Latch C DQ Latch C DQ Latch C DQ Latch Match detector Noise canceler output Sampling clock Input capture input signal Sampling clock Δt Δt: Set by CKS1 and CKS0 Figure 9.9 Noise Canceler Block Diagram The noise canceler consists of five latch circuits connected in series and a match detector circuit. When the noise cancellation function is not used (NCS = 0), the system clock is selected as the sampling clock. When the noise cancellation function is used (NCS = 1), the sampling clock is the internal clock selected by CKS1 and CKS0 in TMG, the input capture input is sampled on the rising edge of this clock, and the data is judged to be correct when all the latch outputs match. If all the outputs do not match, the previous value is retained. After a reset, the noise canceler output is initialized when the falling edge of the input capture input signal has been sampled five times. Therefore, after making a setting for use of the noise cancellation function, a pulse with at least five times the width of the sampling clock is a dependable input capture signal. Even if noise cancellation is not used, an input capture input signal pulse width of at least 2φ or 2φ SUB is necessary to ensure that input capture operations are performed properly Note: * An input capture signal may be generated when the NCS bit is modified. Figure 9.10 shows an example of noise canceler timing.

Rev. 8.00 Mar. 09, 2010 Page 291 of 658 REJ09B0042-0800 In this example, high-level input of less than five times the width of the sampling clock at the input capture input pin is eliminated as noise. Input capture input signal Sampling clock Noise canceler output Eliminated as noise Figure 9.10 Noise Canceler Timing (Example)

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9.5.4 Operation

Timer G is an 8-bit timer with built-in input capture and interval functions. Timer G Functions Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval timer function. The operation of these two functions is described below. a. Input capture timer operation When the TMIG bit in port mode register 1 (PMR1) is set to 1, timer G functions as an input capture timer*. In a reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF (ICRGF), and input capture register GR (ICRGR) are all initialized to H'00. Following a reset, TCG starts counting on the φ/64 internal clock. The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in TMG. When a rising edge/falling edge is detected in the input capture signal input from the TMIG pin, the TCG value at that time is transferred to ICRGR/ICRGF. When the edge selected by IIEGS in TMG is input, IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU. For details of the interrupt, see section 3.3, Interrupts. TCG can be cleared by a rising edge, falling edge, or both edges of the input capture signal, according to the setting of bits CCLR1 and CCLR0 in TMG. If TCG overflows when the input capture signal is high, the OVFH bit in TMG is set; if TCG overflows when the input capture signal is low, the OVFL bit in TMG is set. If the OVIE bit in TMG is 1 when these bits are set, IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1, timer G sends an interrupt request to the CPU. For details of the interrupt, see section 3.3, Interrupts. Timer G has a built-in noise canceler that enables high-frequency component noise to be eliminated from pulses input from the TMIG pin. For details, see section 9.5.3, Noise Canceler. Note: * An input capture signal may be generated when TMIG is modified.

Rev. 8.00 Mar. 09, 2010 Page 296 of 658 REJ09B0042-0800 Timer G Operation Modes Timer G operation modes are shown in table 9.12. Table 9.12 Timer G Operation Modes Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Module Standby TCG Input capture Reset Functions * Functions* Functions/ halted* Functions/ halted* Functions/ halted* Halted Halted Interval Reset Functions * Functions* Functions/ halted* Functions/ halted* Functions/ halted* Halted Halted ICRGF Reset Functions * Functions* Functions/ halted* Functions/ halted* Functions/ halted* Retained Retained ICRGR Reset Functions * Functions* Functions/ halted* Functions/ halted* Functions/ halted* Retained Retained TMG Reset Functions Retained Retained Functions Retained Retained Retained Note: * When φw/4 is selected as the TCG internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/φ(s). When φw/4 is selected as the TCG internal clock in watch mode, TCG and the noise canceler operate on the φw/4 internal clock without regard to the φ SUB subclock (φw/8, φw/4, φw/2). Note that when another internal clock is selected, TCG and the noise canceler do not operate, and input of the input capture input signal does not result in input capture. To operate the timer G in subactive mode or subsleep mode, select φw/4 as the TCG internal clock and φw/2 as the subclock φSUB. Note that when other internal clock is selected, or when φw/8 or φw/4 is selected as the subclock φSUB, TCG and the noise canceler do not operate.

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9.5.5 Application Notes

Internal Clock Switching and TCG Operation Depending on the timing, TCG may be incremented by a switch between different internal clock sources. Table 9.13 shows the relation between internal clock switchover timing (by write to bits CKS1 and CKS0) and TCG operation. When TCG is internally clocked, an increment pulse is generated on detection of the falling edge of an internal clock signal, which is divided from the system clock (φ) or subclock (φw). For this reason, in a case like No. 3 in table 9.13 where the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing TCG to increment. Table 9.13 Internal Clock Switching and TCG Operation No. Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation

1 Goes from low level to low level Clock before

2 Goes from low level to high level Clock before

Rev. 8.00 Mar. 09, 2010 Page 298 of 658 REJ09B0042-0800 No. Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation

3 Goes from high level to low level

4 Goes from high level to high level

Note: * The switchover is seen as a falling edge, and TCG is incremented. Notes on Port Mode Register Modification The following points should be noted when a port mode register is modified to switch the input capture function or the input capture input noise canceler function.

• Switching input capture input pin function Note that when the pin function is switched by modifying TMIG in port mode register 1 (PMR1), which performs input capture input pin control, an edge will be regarded as having been input at the pin even though no valid edge has actually been input. Input capture input signal input edges, and the conditions for their occurrence, are summarized in table 9.14.

Rev. 8.00 Mar. 09, 2010 Page 299 of 658 REJ09B0042-0800 Table 9.14 Input Capture Input Signal Input Edges Due to Input Capture Input Pin Switching, and Conditions for Their Occurrence Input Capture Input Signal Input Edge Conditions Generation of rising edge When TMIG is modified from 0 to 1 while the TMIG pin is high When NCS is modified from 0 to 1 while the TMIG pin is high, then TMIG is modified from 0 to 1 before the signal is sampled five times by the noise canceler Generation of falling edge When TMIG is modified from 1 to 0 while the TMIG pin is high When NCS is modified from 0 to 1 while the TMIG pin is low, then TMIG is modified from 0 to 1 before the signal is sampled five times by the noise canceler When NCS is modified from 0 to 1 while the TMIG pin is high, then TMIG is modified from 1 to 0 after the signal is sampled five times by the noise canceler Note: When the P1 3 pin is not set as an input capture input pin, the timer G input capture input signal is low.

• Switching input capture input noise canceler function When performing noise canceler function switching by modifying NCS in port mode register 2 (PMR2), which controls the input capture input noise canceler, TMIG should first be cleared to 0. Note that if NCS is modified without first clearing TMIG, an edge will be regarded as having been input at the pin even though no valid edge has actually been input. Input capture input signal input edges, and the conditions for their occurrence, are summarized in table 9.15. Table 9.15 Input Capture Input Signal Input Edges Due to Noise Canceler Function Switching, and Conditions for Their Occurrence Input Capture Input Signal Input Edge Conditions Generation of rising edge When the TMIG pin is modified from 0 to 1 while TMIG is 1, then NCS is modified from 0 to 1 before the signal is sampled five times by the noise canceler Generation of falling edge When the TMIG pin is modified from 1 to 0 while TMIG is 1, then NCS is modified from 1 to 0 before the signal is sampled five times by the noise canceler

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9.5.6 Timer G Application Example

Using timer G, it is possible to measure the high and low widths of the input capture input signal as absolute values. For this purpose, CCLR1 and CCLR0 in TMG should both be set to 1. Figure 9.16 shows an example of the operation in this case. Counter clearedTCG H'FF H'00 Input capture input signal Input capture register GF Input capture register GR Figure 9.16 Timer G Application Example

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9.6 Watchdog Timer

9.6.1 Overview

The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024R Group and for the H8/38124 Group are different. Features of the watchdog timer are given below.

• Incremented by internal clock source (φ/8192 or φw/32) on the H8/38024, H8/38024S, and H8/38024R Group.
• On the H8/38124 Group, 10 internal clocks (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φw/32, or watchdog on-chip oscillator) are available for selection for use by the counter.
• A reset signal is generated when the counter overflows. The overflow period can be set from 1 to 256 times the selected clock (from approximately 4 ms to 1,000 ms when φ = 2.00 MHz).
• Use of module standby mode enables this module to be placed in standby mode independently when not used. See section 5.9, Module Standby Mode, for details.

Rev. 8.00 Mar. 09, 2010 Page 303 of 658 REJ09B0042-0800 Block Diagram Figures 9.17(1) and 9.17(2) show a block diagram of the watchdog timer. PSS TCSRW TCW φ/8192 [Legend] TCSRW: TCW: PSS: φ φW/32 Internal data bus Reset signal Timer control/status register W Timer counter W Prescaler S Figure 9.17(1) Block Diagram of Watchdog Timer (H8/38024, H8/38024S, H8/38024R Group)

Rev. 8.00 Mar. 09, 2010 Page 304 of 658 REJ09B0042-0800 TCSRW TMW TCW Internal data bus PSS Watchdog on-chip oscillator φ φW/32 Internal reset signal or interrupt request signal Interrupt/reset controller [Legend] TCSRW: TCW: TMW: PSS: Timer control/status register W Timer counter W Timer mode register W Prescaler S Figure 9.17(2) Block Diagram of Watchdog Timer (H8/38124 Group) Register Configuration Table 9.16 shows the register configuration of the watchdog timer. Table 9.16 Watchdog Timer Registers Name Abbr. R/W Initial Value Address Timer control/status register W TCSRW R/W H'AA H'FFB2 Timer counter W TCW R/W H'00 H'FFB3 Timer mode register W* TMW R/W H'FF H'FFF8 Clock stop register 2 CKSTPR2 R/W H'FF H'FFFB Port mode register 2 PMR2 R/W H'D8 H'FFC9 Note: * This register is implemented on the H8/38124 Group only.

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9.6.2 Register Descriptions

Timer Control/Status Register W (TCSRW) Bit Initial value Read/Write B6WI R TCWE (R/W)*1 B4WI R TCSRWE (R/W)*1 B2WI R WRST (R/W)*1 WDON 0/1*2 (R/W)*1 B0WI R Notes: 1. Write is enabled only under certain conditions, which are given in the descriptions of the individual bits. 2. I nitial value is 0 on H8/38024, H8/38024S, and H8/38024R Group; initial value i s 1 on H8/38124 Group. TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself, controls watchdog timer operations, and indicates operating status. Bit 7—Bit 6 Write Disable (B6WI) Bit 7 controls the writing of data to bit 6 in TCSRW. Bit 7 B6WI

0 Bit 6 is write-enabled

1 Bit 6 is write-protected (initial value)

This bit is always read as 1. Data written to this bit is not stored. Bit 6—Timer Counter W Write Enable (TCWE) Bit 6 controls the writing of data to TCW. Bit 6 TCWE

0 Data cannot be written to TCW (initial value)

1 Data can be written to TCW

Rev. 8.00 Mar. 09, 2010 Page 306 of 658 REJ09B0042-0800 Bit 5—Bit 4 Write Disable (B4WI) Bit 5 controls the writing of data to bit 4 in TCSRW. Bit 5 B4WI

0 Bit 4 is write-enabled

1 Bit 4 is write-protected (initial value)

This bit is always read as 1. Data written to this bit is not stored. Bit 4—Timer Control/Status Register W Write Enable (TCSRWE) Bit 4 controls the writing of data to bits 2 and 0 in TCSRW. Bit 4 TCSRWE

0 Data cannot be written to bits 2 and 0 (initial value)

1 Data can be written to bits 2 and 0

Bit 3—Bit 2 Write Inhibit (B2WI) Bit 3 controls the writing of data to bit 2 in TCSRW. Bit 3 B2WI

0 Bit 2 is write-enabled

1 Bit 2 is write-protected (initial value)

This bit is always read as 1. Data written to this bit is not stored. Bit 2—Watchdog Timer On (WDON) Bit 2 enables watchdog timer operation.

Rev. 8.00 Mar. 09, 2010 Page 307 of 658 REJ09B0042-0800 Bit 2 WDON

0 Watchdog timer operation is disabled (initial value) *

Clearing conditions: Reset, or when TCSRWE is set to 1 and 0 is written to B2WI and WDON. Note that a reset clears WDON to 0 on the H8/38024, H8/38024S, and H8/38024R Group, but sets WDON to 1 on the H8/38124 Group. Note: * Initial value is 0 on H8/38024, H8/38024S, and H8/38024R Group; initial value is 1 on H8/38124 Group.

1 Watchdog timer operation is enabled

Setting condition: When TCSRWE is set to 1 and 0 is written to B2WI and 1 is written to WDON Counting starts when this bit is set to 1, and stops when this bit is cleared to 0. Bit 1—Bit 0 Write Inhibit (B0WI) Bit 1 controls the writing of data to bit 0 in TCSRW. Bit 1 B0WI

0 Bit 0 is write-enabled

1 Bit 0 is write-protected (initial value)

This bit is always read as 1. Data written to this bit is not stored. Bit 0—Watchdog Timer Reset (WRST) Bit 0 indicates that TCW has overflowed, generating an internal reset signal. The internal reset signal generated by the overflow resets the entire chip. WRST is cleared to 0 by a reset from the RES pin, or when software writes 0. Bit 0 WRST

0 Clearing conditions:

When TCSRWE = 1, and 0 is written in both BOWI and WRST When TCW overflows and an internal reset signal is generated

Rev. 8.00 Mar. 09, 2010 Page 308 of 658 REJ09B0042-0800 Timer Counter W (TCW) Bit Initial value Read/Write TCW7 R/W TCW6 R/W TCW5 R/W TCW4 R/W TCW3 R/W TCW0 R/W TCW2 R/W TCW1 R/W For the H8/38024, H8/38024S, and H8/38024R groups, the clock source is φ/8,192 or φw/32. For the H8/38124 group, the clock source is selected based on the timer mode register (TMW) setting if WDCKS is 0 and is φw/32 if WDCKS is 1. When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to 1 in TCSRW. Upon reset, TCW is initialized to H'00. Timer Mode Register (TMW) Bit 7 6 5 4 3 2 1 0 — — — — CKS3 CKS2 CKS1 CKS0 Initial value 1 1 1 1 1 1 1 1 Read/Write — — — — R/W R/W R/W R/W The TMW register is only implemented on the H8/38124. The input clock is selected using combinations of CKS3 to CKS0. Bits 7 to 4—Reserved These bits are always read as 1. Bits 3 to 0—Clock Select (CKS3 to CKS0) These bits are used to select the clock input to TCW from among 10 internal options. Clock source selection using this register is enabled when WDCKS in port mode register 2 (PMR2) is cleared to 0. If WDCKS is set to 1 the φw/32 clock source is selected, regardless of the settings of the bits in this register.

Rev. 8.00 Mar. 09, 2010 Page 309 of 658 REJ09B0042-0800 Bit 3 CKS3 Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 1 0 0 0 Internal clock: φ/64 count

1 Internal clock: φ/128 count

1 0 Internal clock: φ/256 count

1 Internal clock: φ/512 count

1 0 0 Internal clock: φ/1024 count

1 Internal clock: φ/2048 count

1 0 Internal clock: φ/4096 count

1 Internal clock: φ/8192 count (initial value)

0 X X X Watchdog on-chip oscillator

Note: X: Don't care Clock Stop Register 2 (CKSTPR2) LVDCKSTD* WDCKSTP PW1CKSTP LDCKSTP⎯⎯ PW2CKSTP AECKSTP 7 6543210 1 1111111 R/W R/W R/W R/W⎯⎯ R/W R/W Bit Initial value Read/Write Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group. CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the watchdog timer is described here. For details of the other bits, see the sections on the relevant modules. Bit 2—Watchdog Timer Module Standby Mode Control (WDCKSTP) Bit 2 controls setting and clearing of module standby mode for the watchdog timer. WDCKSTP Description

1 Watchdog timer module standby mode is cleared (initial value)

Note: WDCKSTP is valid when the WDON bit is cleared to 0 in timer control/status register W (TCSRW). If WDCKSTP is set to 0 while WDON is set to 1 (during watchdog timer operation), 0 will be set in WDCKSTP but the watchdog timer will continue its watchdog function and will not enter module standby mode. When the watchdog function ends and WDON is cleared to 0 by software, the WDCKSTP setting will become valid and the watchdog timer will enter module standby mode.

Rev. 8.00 Mar. 09, 2010 Page 310 of 658 REJ09B0042-0800 Port Mode Register 2 (PMR2) Bit 7 6 5 4 3 2 1 0 — — POF1 — — WDCKS NCS IRQ0 Initial value 1 1 0 1 1 0 0 0 Read/Write — — R/W — — R/W R/W R/W PMR2 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 2. Only the bit relating to the watchdog timer is described here. For details of the other bits, see section 8, I/O Ports. Bit 2—Watchdog Timer Source Clock Select (WDCKS) This bit selects the watchdog timer source clock. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024R Group and for the H8/38124 Group are different.

• H8/38024, H8/38024S, H8/38024R Group WDCKS Description 0 φ/8192 selected (initial value) 1 φw/32 selected
• H8/38124 Group WDCKS Description

0 Selects clock based on timer mode register W (TMW) setting (initial value)

1 φw/32 selected

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9.6.3 Timer Operation

The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input. The input clock is selected by the WDCKS in port mode register 2 (PMR2): on the H8/38024, H8/38024S, and H8/38024R Group, φ/8192 is selected when WDCKS is cleared to 0, and φw/32 when set to 1. On the H8/38124 Group, if WDCKS is cleared to 0 the clock selection is specified by the setting of timer mode register W (TMW), and if WDCKS is set to 1 the φw/32 clock source is selected. When TCSRWE = 1 in TCSRW, if 0 is written in B2WI and 1 is simultaneously written in WDON, TCW starts counting up. (Write access to TCSRW is required twice to turn on the watchdog timer. However, on the H8/38124 Group WDON is set to 1 after a reset is cancelled, TCW starts to be incremented even without gaining write access to TCSRW.) When the TCW count value reaches H'FF, the next clock input causes the watchdog timer to overflow, and an internal reset signal is generated one base clock (φ or φ SUB) cycle later. The internal reset signal is output for 512 clock cycles of the φOSC clock. It is possible to write to TCW, causing TCW to count up from the written value. The overflow period can be set in the range from 1 to 256 input clocks, depending on the value written in TCW. Figure 9.18 shows an example of watchdog timer operations. H'F8 TCW overflow Start H'F8 is written in TCW H'F8 is written in TCW Reset Internal reset signal 512 φOSC clock cycles H'FF H'00 TCW count value Example: φ = 2 MHz and the desired overflow period is 30 ms. The value set in TCW should therefore be 256 − 8 = 248 (H'F8). 2 • 106  30  10−3 = 7.3 8192 Figure 9.18 Typical Watchdog Timer Operations (Example)

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9.6.4 Watchdog Timer Operation States

Table 9.17(1) and table 9.17(2) summarize the watchdog timer operation states for the H8/38024, H8/38024S, and H8/38024R Group, and for the H8/38124 Group, respectively. Table 9.17(1) Watchdog Timer Operation States (H8/38024, H8/38024S, H8/38024R Group) Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Module Standby TCW Reset Functions Functions Halted Functions/ Halted* Halted Halted Halted TCSRW Reset Functions Functions Retained Functions/ Halted* Retained Retained Retained Note: * Functions when φw/32 is selected as the input clock. Table 9.17(2) Watchdog Timer Operation States (H8/38124 Group) Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Module Standby TCW Reset Functions Functions Functions/ Halted*1 Functions/ Halted*1 Functions/ Halted*1 Functions/ Halted*2 Halted TCSRW Reset Functions Functions Functions/ Retained*1 Functions/ Halted*1 Functions/ Retained*1 Functions/ Retained*2 Retained TMW Reset Functions Functions Functions/ Retained*1 Functions/ Halted*1 Functions/ Retained*1 Functions/ Retained*2 Retained Notes: 1. Operates when φw/32 or the on-chip oscillator is selected as the internal clock. 2. Operates only when the on-chip oscillator is selected.

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9.7 Asynchronous Event Counter (AEC)

9.7.1 Overview

The asynchronous event counter is incremented by external event clock or internal clock input. Features of the asynchronous event counter are given below.

• Can count asynchronous events Can count external events input asynchronously without regard to the operation of base clocks φ and φ SUB. The counter has a 16-bit configuration, enabling it to count up to 65536 (216) events.
• Can also be used as two independent 8-bit event counter channels.
• Can be used as single-channel independent 16-bit event counter.
• Event/clock input is enabled only when IRQAEC is high or event counter PWM output (IECPWM) is high.
• Both edge sensing can be used for IRQAEC or event counter PWM output (IECPWM) interrupts. When the asynchronous counter is not used, independent interrupt function use is possible.
• When an event counter PWM is used, event clock input enabling/disabling can be performed automatically in a fixed cycle.
• External event input or a prescaler output clock can be selected by software for the ECH and ECL clock sources. φ/2, φ/4, or φ/8 can be selected as the prescaler output clock.
• Both edge counting is possible for AEVL and AEVH.
• Counter resetting and halting of the count-up function controllable by software
• Automatic interrupt generation on detection of event counter overflow
• Use of module standby mode enables this module to be placed in standby mode independently when not used.

Rev. 8.00 Mar. 09, 2010 Page 315 of 658 REJ09B0042-0800 Pin Configuration Table 9.18 shows the asynchronous event counter pin configuration. Table 9.18 Pin Configuration Name Abbr. I/O Function Asynchronous event input H AEVH Input Event input pin for input to event counter H Asynchronous event input L AEVL Input Event input pin for input to event counter L Event input enable interrupt input IRQAEC Input Input pin for interrupt enabling event input Register Configuration Table 9.19 shows the register configuration of the asynchronous event counter. Table 9.19 Asynchronous Event Counter Registers Name Abbr. R/W Initial Value Address Event counter PWM compare register H ECPWCRH R/W H'FF H'FF8C Event counter PWM compare register L ECPWCRL R/W H'FF H'FF8D Event counter PWM data register H ECPWDRH W H'00 H'FF8E Event counter PWM data register L ECPWDRL W H'00 H'FF8F Input pin edge select register AEGSR R/W H'00 H'FF92 Event counter control register ECCR R/W H'00 H'FF94 Event counter control/status register ECCSR R/W H'00 H'FF95 Event counter H ECH R H'00 H'FF96 Event counter L ECL R H'00 H'FF97 Clock stop register 2 CKSTPR2 R/W H'FF H'FFFB

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9.7.2 Register Configurations

Event Counter PWM Compare Register H (ECPWCRH) Bit Initial value Read/Write ECPWCRH7 R/W ECPWCRH6 R/W ECPWCRH5 R/W ECPWCRH4 R/W ECPWCRH3 R/W ECPWCRH0 R/W ECPWCRH2 R/W ECPWCRH1 R/W Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH should not be modified. When changing the conversion period, event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWCRH. ECPWCRH is an 8-bit read/write register that sets the event counter PWM waveform conversion period. Event Counter PWM Compare Register L (ECPWCRL) Bit Initial value Read/Write ECPWCRL7 R/W ECPWCRL6 R/W ECPWCRL5 R/W ECPWCRL4 R/W ECPWCRL3 R/W ECPWCRL0 R/W ECPWCRL2 R/W ECPWCRL1 R/W Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRL should not be modified. When changing the conversion period, event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWCRL. ECPWCRL is an 8-bit read/write register that sets the event counter PWM waveform conversion period.

Rev. 8.00 Mar. 09, 2010 Page 317 of 658 REJ09B0042-0800 Event Counter PWM Data Register H (ECPWDRH) Bit Initial value Read/Write ECPWDRH7 W ECPWDRH6 W ECPWDRH5 W ECPWDRH4 W ECPWDRH3 W ECPWDRH0 W ECPWDRH2 W ECPWDRH1 W Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWDRH should not be modified. When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWDRH. ECPWDRH is an 8-bit write-only register that controls event counter PWM waveform generator data. Event Counter PWM Data Register L (ECPWDRL) Bit Initial value Read/Write ECPWDRL7 W ECPWDRL6 W ECPWDRL5 W ECPWDRL4 W ECPWDRL3 W ECPWDRL0 W ECPWDRL2 W ECPWDRL1 W Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWDRL should not be modified. When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWDRL. ECPWDRL is an 8-bit write-only register that controls event counter PWM waveform generator data. Input Pin Edge Selection Register (AEGSR) Bit Initial value Read/Write AHEGS1 R/W AHEGS0 R/W ALEGS1 R/W ALEGS0 R/W AIEGS1 R/W R/W AIEGS0 R/W ECPWME R/W AEGSR is an 8-bit read/write register that selects rising, falling, or both edge sensing for the AEVH, AEVL, and IRQAEC pins.

Rev. 8.00 Mar. 09, 2010 Page 318 of 658 REJ09B0042-0800 Bits 7 and 6—AEC Edge Select H Bits 7 and 6 select rising, falling, or both edge sensing for the AEVH pin. Bit 7 AHEGS1 Bit 6 AHEGS0 0 0 Falling edge on AEVH pin is sensed (initial value)

1 Rising edge on AEVH pin is sensed

1 0 Both edges on AEVH pin are sensed

1 Use prohibited

Bits 5 and 4—AEC Edge Select L Bits 5 and 4 select rising, falling, or both edge sensing for the AEVL pin. Bit 5 ALEGS1 Bit 4 ALEGS0 0 0 Falling edge on AEVL pin is sensed (initial value)

1 Rising edge on AEVL pin is sensed

1 0 Both edges on AEVL pin are sensed Bits 3 and 2—IRQAEC Edge Select Bits 3 and 2 select rising, falling, or both edge sensing for the IRQAEC pin. Bit 3 AIEGS1 Bit 2 AIEGS0 0 0 Falling edge on IRQAEC pin is sensed (initial value)

1 Rising edge on IRQAEC pin is sensed

1 0 Both edges on IRQAEC pin are sensed

Rev. 8.00 Mar. 09, 2010 Page 319 of 658 REJ09B0042-0800 Bit 1—Event Counter PWM Enable Bit 1 controls enabling/disabling of event counter PWM and selection/deselection of IRQAEC. Bit 1 ECPWME

0 AEC PWM halted, IRQAEC selected (initial value)

1 AEC PWM operation enabled, IRQAEC deselected

Bit 0—Reserved Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset. Note: Do not set this bit to 1. Event Counter Control Register (ECCR) Bit Initial value Read/Write ACKH1 R/W ACKH0 R/W ACKL1 R/W ACKL0 R/W PWCK2 R/W R/W PWCK1 R/W PWCK0 R/W ECCR performs counter input clock and IRQAEC/IECPWM control. Bits 7 and 6—AEC Clock Select H (ACKH1, ACKH0) Bits 7 and 6 select the clock used by ECH. Bit 7 ACKH1 Bit 6 ACKH0 0 0 AEVH pin input (initial value) 1 φ/2 1 0 φ/4 1 φ/8

Rev. 8.00 Mar. 09, 2010 Page 320 of 658 REJ09B0042-0800 Bits 5 and 4—AEC Clock Select L (ACKL1, ACKL0) Bits 5 and 4 select the clock used by ECL. Bit 5 ACKL1 Bit 4 ACKL0 0 0 AEVL pin input (initial value) 1 φ/2 1 0 φ/4 1 φ/8 Bits 3 to 1—Event Counter PWM Clock Select (PWCK2, PWCK1, PWCK0) Bits 3 to 1 select the event counter PWM clock. Bit 3 PWCK2 Bit 2 PWCK1 Bit 1 PWCK0 0 0 0 φ/2 (initial value) 1 φ/4 1 0 φ/8 1 φ/16 1 * 0 φ/32 1 φ/64 *: Don’t care Bit 0—Reserved Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset. Note: Do not set this bit to 1.

Rev. 8.00 Mar. 09, 2010 Page 321 of 658 REJ09B0042-0800 Event Counter Control/Status Register (ECCSR) OVH C UEL CRCH CRCLOVL ⎯ CH2 C UEH 7 6543210 0 0000000 R/W* R/W R/W R/WR/W* R/W R/W R/W Bit Note: * Bits 7 and 6 can only be written with 0, for flag clearing. Initial Value Read/Write ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting, and halting of the count-up function. ECCSR is initialized to H'00 upon reset. Bit 7—Counter Overflow H (OVH) Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by reading it when set to 1, then writing 0. When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000. Bit 7 OVH

0 ECH has not overflowed (initial value)

Clearing condition: After reading OVH = 1, cleared by writing 0 to OVH

1 ECH has overflowed

Setting condition: Set when ECH overflows from H’FF to H’00 Bit 6—Counter Overflow L (OVL) Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by reading it when set to 1, then writing 0.

Rev. 8.00 Mar. 09, 2010 Page 322 of 658 REJ09B0042-0800 Bit 6 OVL

0 ECL has not overflowed (initial value)

Clearing condition: After reading OVL = 1, cleared by writing 0 to OVL

1 ECL has overflowed

Setting condition: Set when ECL overflows from H'FF to H'00 Bit 5—Reserved Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset. Bit 4—Channel Select (CH2) Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two independent 8-bit event counter channels. When CH2 is cleared to 0, ECH and ECL function as a 16-bit event counter which is incremented each time an event clock is input to the AEVL pin. In this case, the overflow signal from ECL is selected as the ECH input clock. When CH2 is set to 1, ECH and ECL function as independent 8-bit event counters which are incremented each time an event clock is input to the AEVH or AEVL pin, respectively. Bit 4 CH2

0 ECH and ECL are used together as a single-channel 16-bit event counter

(initial value)

1 ECH and ECL are used as two independent 8-bit event counter channels

Bit 3—Count-up Enable H (CUEH) Bit 3 enables event clock input to ECH. When 1 is written to this bit, event clock input is enabled and increments the counter. When 0 is written to this bit, event clock input is disabled and the ECH value is held. The AEVH pin or the ECL overflow signal can be selected as the event clock source by bit CH2. Bit 3 CUEH

0 ECH event clock input is disabled (initial value)

1 ECH event clock input is enabled

Rev. 8.00 Mar. 09, 2010 Page 323 of 658 REJ09B0042-0800 Bit 2—Count-up Enable L (CUEL) Bit 2 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled and increments the counter. When 0 is written to this bit, event clock input is disabled and the ECL value is held. Bit 2 CUEL

0 ECL event clock input is disabled (initial value)

1 ECL event clock input is enabled

Bit 1—Counter Reset Control H (CRCH) Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to this bit, the counter reset is cleared and the ECH count-up function is enabled. Bit 1 CRCH

0 ECH is reset (initial value)

1 ECH reset is cleared and count-up function is enabled

Bit 0—Counter Reset Control L (CRCL) Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to this bit, the counter reset is cleared and the ECL count-up function is enabled. Bit 0 CRCL

0 ECL is reset (initial value)

1 ECL reset is cleared and count-up function is enabled

Event Counter H (ECH) ECH7 E CH2 ECH1 ECH0ECH6 ECH5 ECH4 E CH3 7 65 4 3210 0 0000000 R RRRRRR R Bit Initial Value Read/Write

Rev. 8.00 Mar. 09, 2010 Page 324 of 658 REJ09B0042-0800 ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. The external asynchronous event AEVH pin, φ/2, φ/4, φ/8, or the overflow signal from lower 8-bit counter ECL can be selected as the input clock source. ECH can be cleared to H'00 by software, and is also initialized to H'00 upon reset. Event Counter L (ECL) ECL7 E CL2 ECL1 ECL0ECL6 ECL5 ECL4 E CL3 7 65 4 3210 0 0000000 R RRRRRR R Bit Initial Value Read/Write ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. The event clock from the external asynchronous event AEVL pin, φ/2, φ/4, or φ/8 is used as the input clock source. ECL can be cleared to H'00 by software, and is also initialized to H'00 upon reset. Clock Stop Register 2 (CKSTPR2) LVDCKSTP* WDCKSTP PW1CKSTP LDCKSTP⎯⎯ PW2CKSTP AECKSTP 7 65 4 3210 1 1111111 R/W R/WR /WR /W⎯⎯ R/W R/W Bit Initial value Read/Write Note: * Bi ts 6 and 5 are also reserved on products other than the H8/38124 Group. CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the asynchronous event counter is described here. For details of the other bits, see the sections on the relevant modules. Bit 3—Asynchronous Event Counter Module Standby Mode Control (AECKSTP) Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter. AECKSTP Description

0 Asynchronous event counter is set to module standby mode

1 Asynchronous event counter module standby mode is cleared (initial value)

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9.7.3 Operation

16-bit Event Counter Operation When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter. Any of four input clock sources— φ/2, φ/4, φ/8, or AEVL pin input—can be selected by means of bits ACKL1 and ACKL0 in ECCR. When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0. The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is low or IECPWM is low, the input clock is not input to the counter, which therefore does not operate. Figure 9.20 shows an example of the software processing when ECH and ECL are used as a 16-bit event counter. Start End Clear CH2 to 0 Set ACKL1, ACKL0, ALEGS1, and ALEGS0 Clear CUEH, CUEL, CRCH, and CRCL to 0 Clear OVH and OVL to 0 Set CUEH, CUEL, CRCH, and CRCL to 1 Figure 9.20 Example of Software Processing when Using ECH and ECL as 16-Bit Event Counter As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset, and as ACKL1 and ACKL0 are cleared to 00, the operating clock is asynchronous event input from the AEVL pin (using falling edge sensing). When the next clock is input after the count value reaches H'FF in both ECH and ECL, ECH and ECL overflow from H'FFFF to H'0000, the OVH flag is set to 1 in ECCSR, the ECH and ECL count values each return to H'00, and counting up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU.

Rev. 8.00 Mar. 09, 2010 Page 326 of 658 REJ09B0042-0800 8-bit Event Counter Operation When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters. φ/2, φ/4, φ/8, or AEVH pin input can be selected as the input clock source for ECH by means of bits ACKH1 and ACKH0 in ECCR, and φ/2, φ/4, φ/8, or AEVL pin input can be selected as the input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR. Input sensing is selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and with bits ALEGS1 and ALEGS0 when AEVL pin input is selected. The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is low or IECPWM is low, the input clock is not input to the counter, which therefore does not operate. Figure 9.21 shows an example of the software processing when ECH and ECL are used as 8-bit event counters. Start End Set CH2 to 1 Set ACKH1, ACKH0, ACKL1, ACKL0, AHEGS1, AHEGS0, ALEGS1, and ALEGS0 Clear CUEH, CUEL, CRCH, and CRCL to 0 Clear OVH to 0 Set CUEH, CUEL, CRCH, and CRCL to 1 Figure 9.21 Example of Software Processing when Using ECH and ECL as 8-Bit Event Counters ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown in the example in figure 9.21. When the next clock is input after the ECH count value reaches H'FF, ECH overflows, the OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00, and counting up is restarted. Similarly, when the next clock is input after the ECL count value reaches H'FF, ECL overflows, the OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00, and counting up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU.

Rev. 8.00 Mar. 09, 2010 Page 327 of 658 REJ09B0042-0800 IRQAEC Operation When ECPWME in AEGSR is 0, the ECH and ECL input clocks are enabled only when IRQAEC is high. When IRQAEC is low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled from outside by controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually. IRQAEC can also operate as an interrupt source. In this case the vector number is 6 and the vector addresses are H'000C and H'000D. Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated, IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an interrupt request is sent to the CPU. Rising, falling, or both edge sensing can be selected for the IRQAEC input pin, with bits AIAGS1 and AIAGS0 in AEGSR. Note: On the H8/38124 Group, control of switching between the system clock oscillator and the on-chip oscillator during resets should be performed by setting the IRQAEC input level. Refer to section 4, Clock Pulse Generators, for details. Event Counter PWM Operation When ECPWME in AEGSR is 1, the ECH and ECL input clocks are enabled only when event counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled cyclically from outside by controlling event counter PWM. In this case, ECH and ECL cannot be controlled individually. IECPWM can also operate as an interrupt source. In this case the vector number is 6 and the vector addresses are H'000C and H'000D. Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated, IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an interrupt request is sent to the CPU. Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits AIAGS1 and AIAGS0 in AEGSR.

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9.7.4 Asynchronous Event Counter Operation Modes

Asynchronous event counter operation modes are shown in table 9.21. Table 9.21 Asynchronous Ev ent Counter Operation Modes Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Module Standby AEGSR Reset Functions Functions Retained *1 Functions Functions Retained *1 Retained ECCR Reset Functions Functions Retained *1 Functions Functions Retained *1 Retained ECCSR Reset Functions Functions Retained *1 Functions Functions Retained *1 Retained ECH Reset Functions Functions Functions *1*2 Functions*2 Functions*2 Functions*1*2 Halted ECL Reset Functions Functions Functions *1*2 Functions*2 Functions*2 Functions*1*2 Halted IRQAEC Reset Functions Functions Retained *3 Functions Functions Retained *3 Retained *4 Event counter PWM Reset Functions Functions Retained Retained Retained Retained Retained Notes: 1. When an asynchronous external event is input, the counter increments but the counter overflow H/L flags are not affected. 2. Operates when asynchronous external events are selected; halted and retained otherwise. 3. Clock control by IRQAEC operates, but interrupts do not. 4. As the clock is stopped in module standby mode, IRQAEC has no effect.

9.7.5 Application Notes

1. When reading the values in ECH and ECL, the correct value will not be returned if the event counter increments during the read operation. Therefore, if the counter is being used in the 8- bit mode, clear bits CUEH and CUEL in ECCSR to 0 before reading ECH or ECL. If the counter is being used in the 16-bit mode, clear CUEL only to 0 before reading ECH or ECL. 2. Use a clock with a frequency of up to 16 MHz for input to the AEVH and AEVL pins, and ensure that the high and low widths of the clock are at least half the OSC clock cycle duration. The duty cycle is immaterial.

Rev. 8.00 Mar. 09, 2010 Page 331 of 658 REJ09B0042-0800 Mode Maximum AEVH/AEVL Pin Input Clock Frequency Active (high-speed), sleep (high-speed) 16 MHz Active (medium-speed), sleep (medium-speed) (φ/16) ( φ/32) ( φ/64) fOSC = 1 MHz to 4 MHz ( φ/128) 2 • fOSC fOSC 1/2 • fOSC 1/4 • fOSC Watch, subactive, subsleep, standby ( φw/2) ( φw/4) φw = 32.768 kHz or 38.4 kHz* ( φw/8) 1000 kHz 500 kHz 250 kHz Note: * Does not apply to H8/38124 Group. 3. When using the clock in the 16-bit mode, set CUEH to 1 first, then set CRCH to 1 in ECCSR. Or, set CUEH and CRCH simultaneously before inputting the clock. After that, do not change the CUEH value while using in the 16-bit mode. Otherwise, an error counter increment may occur. Also, to reset the counter, clear CRCH and CRCL to 0 simultaneously or clear CRCL and CRCH to 0 sequentially, in that order. 4. When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH, ECPWCRL, ECPWDRH, and ECPWDRL should not be modified. When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying these registers. 5. The event counter PWM data register and event counter PWM compare register must be set so that event counter PWM data register < event counter PWM compare register. If the settings do not satisfy this condition, do not set ECPWME to 1 in AEGSR. 6. As synchronization is established internally when an IRQAEC interrupt is generated, a maximum error of 1 t cyc will occur between clock halting and interrupt acceptance.

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Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 333 of 658 REJ09B0042-0800 Section 10 Serial Communication Interface

10.1 Overview

The H8/38024 Group is provided with one serial communication interface, SCI3. Serial communication interface 3 (SCI3) can carry out serial data communication in either asynchronous or synchronous mode.

10.1.1 Features

Features of SCI3 are listed below.

• Choice of asynchronous or synchronous mode for serial data communication ⎯ Asynchronous mode Serial data communication is performed asynchronously, with synchronization provided character by character. In this mode, serial data can be exchanged with standard asynchronous communication LSIs such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). There is a choice of 12 data transfer formats. Data length 7, 8, 5 bits Stop bit length 1 or 2 bits Parity Even, odd, or none Receive error detection Parity, overrun, and framing errors Break detection Break detected by reading the RXD 32 pin level directly when a framing error occurs ⎯ Synchronous mode Serial data communication is synchronized with a clock. In this mode, serial data can be exchanged with another LSI that has a synchronous communication function. Data length 8 bits Receive error detection Overrun errors

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• Full-duplex communication Separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously. The transmission and reception units are both double-buffered, allowing continuous transmission and reception.
• On-chip baud rate generator, allowing any desired bit rate to be selected
• Choice of an internal or external clock as the transmit/receive clock source
• Six interrupt sources: transmit end, transmit data empty, receive data full, overrun error, framing error, and parity error Note: On the H8/38124 Group, the system clock generator must be used when carrying out this function.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 335 of 658 REJ09B0042-0800

10.1.2 Block Diagram

Figure 10.1 shows a block diagram of SCI3. Clock TXD32 RXD32 SCK BRR SMR SCR3 SSR TDR RDR TSR RSR SPCR Transmit/receive control circuit Internal data bus [Legend] RSR: RDR: TSR: TDR: SMR: SCR3: SSR: BRR: BRC: SPCR: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register 3 Serial status register Bit rate register Bit rate counter Serial port control register Interrupt request (TEI, TXI, RXI, ERI) Internal clock (φ/64, φ/16, φW/2, φ)External clock BRC Baud rate generator Figure 10.1 SCI3 Block Diagram

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10.1.3 Pin Configuration

Table 10.1 shows the SCI3 pin configuration. Table 10.1 Pin Configuration Name Abbr. I/O Function SCI3 clock SCK 32 I/O SCI3 clock input/output SCI3 receive data input RXD 32 Input SCI3 receive data input SCI3 transmit data output TXD 32 Output SCI3 transmit data output

10.1.4 Register Configuration

Table 10.2 shows the SCI3 register configuration. Table 10.2 Registers Name Abbr. R/W Initial Value Address Serial mode register SMR R/W H'00 H'FFA8 Bit rate register BRR R/W H'FF H'FFA9 Serial control register 3 SCR3 R/W H'00 H'FFAA Transmit data register TDR R/W H'FF H'FFAB Serial status register SSR R/W H'84 H'FFAC Receive data register RDR R H'00 H'FFAD Transmit shift register TSR Protected — — Receive shift register RSR Protected — — Bit rate counter BRC Protected — — Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA Serial port control register SPCR R/W — H'FF91

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 337 of 658 REJ09B0042-0800

10.2 Register Descriptions

10.2.1 Receive Shift Register (RSR)

RSR is a register used to receive serial data. Serial data input to RSR from the RXD32 pin is set in the order in which it is received, starting from the LSB (bit 0), and converted to parallel data. When one byte of data is received, it is transferred to RDR automatically. RSR cannot be read or written directly by the CPU.

10.2.2 Receive Data Register (RDR)

R RDR6 R RDR5 R RDR4 R RDR3 R RDR0 R RDR2 R RDR1 R RDR is an 8-bit register that stores received serial data. When reception of one byte of data is finished, the received data is transferred from RSR to RDR, and the receive operation is completed. RSR is then able to receive data. RSR and RDR are double-buffered, allowing consecutive receive operations. RDR is a read-only register, and cannot be written by the CPU. RDR is initialized to H'00 upon reset, and in standby, module standby or watch mode.

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10.2.3 Transmit Shift Register (TSR)

TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR, and serial data transmission is carried out by sending the data to the TXD32 pin in order, starting from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is transferred to TDR, and transmission started, automatically. Data transfer from TDR to TSR is not performed if no data has been written to TDR (if bit TDRE is set to 1 in the serial status register (SSR)). TSR cannot be read or written directly by the CPU.

10.2.4 Transmit Data Register (TDR)

TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit data written in TDR is transferred to TSR, and serial data transmission is started. Continuous transmission is possible by writing the next transmit data to TDR during TSR serial data transmission. TDR can be read or written by the CPU at any time. TDR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.

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10.2.5 Serial Mode Register (SMR)

SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. SMR can be read or written by the CPU at any time. SMR is initialized to H'00 upon reset, and in standby, module standby, or watch mode. Bit 7—Communication Mode (COM) Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode. Bit 7 COM

0 Asynchronous mode (initial value)

1 Synchronous mode

Bit 6—Character Length (CHR) Bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. In synchronous mode the data length is always 8 bits, irrespective of the bit 6 setting. Bit 6 CHR 0 8-bit data/5-bit data *2 (initial value) 1 7-bit data *1/5-bit data*2 Notes: 1. When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. 2. When 5-bit data is selected, set both PE and MP to 1. The three most significant bits (bits 7, 6, and 5) of TDR are not transmitted.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 340 of 658 REJ09B0042-0800 Bit 5—Parity Enable (PE) Bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. In synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting. Bit 5 PE

0 Parity bit addition and checking disabled *2 (initial value)

1 Parity bit addition and checking enabled *1/*2

Notes: 1. When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit data before it is sent, and the received parity bit is checked against the parity designated by bit PM. 2. For the case where 5-bit data is selected, see table 10.11. Bit 4—Parity Mode (PM) Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity bit addition and checking is disabled. Bit 4 PM

0 Even parity *1 (initial value)

1 Odd parity *2

Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. 2. When odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an odd number.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 341 of 658 REJ09B0042-0800 Bit 3—Stop Bit Length (STOP) Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP 0 1 stop bit *1 (initial value) 1 2 stop bits *2 Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character. 2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character. In reception, only the first of the received stop bits is checked, irrespective of the STOP bit setting. If the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next transmit character. Bit 2—5 Bit Communication (MP) When this bit is one, the format of 5 bits communication becomes possible. In the case of writing 1 to this bit, bit 5 (PE) should be written with 1 all at once. Bit 2 MP 0 5 bit communication disabled (initial value) 1 5 bit communication enabled

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 342 of 658 REJ09B0042-0800 Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0) Bits 1 and 0 choose φ/64, φ/16, φw/2, or φ as the clock source for the baud rate generator. For the relation between the clock source, bit rate register setting, and baud rate, see section 10.2.8, Bit rate register (BRR). Bit 1 CKS1 Bit 0 CKS0 0 0 φ clock (initial value) 0 1 φ w/2 clock*1/φ w clock*2 1 0 φ/16 clock 1 1 φ/64 clock Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. φ w clock in subactive mode and subsleep mode. In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.

10.2.6 Serial Control Register 3 (SCR3)

SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock output, interrupt request enabling or disabling, and the transmit/receive clock source. SCR3 can be read or written by the CPU at any time. SCR3 is initialized to H'00 upon reset, and in standby, module standby or watch mode. Bit 7—Transmit Interrupt Enable (TIE) Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when transmit data is transferred from the transmit data register (TDR) to the transmit shift register (TSR), and bit TDRE in the serial status register (SSR) is set to 1. TXI can be released by clearing bit TDRE or bit TIE to 0.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 343 of 658 REJ09B0042-0800 Bit 7 TIE

0 Transmit data empty interrupt request (TXI) disabled (initial value)

1 Transmit data empty interrupt request (TXI) enabled

Bit 6—Receive Interrupt Enable (RIE) Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR) to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1. There are three kinds of receive error: overrun, framing, and parity. RXI and ERI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by clearing bit RIE to 0. Bit 6 RIE

0 Receive data full interrupt request (RXI) and receive error interrupt

request (ERI) disabled (initial value)

1 Receive data full interrupt request (RXI) and receive error interrupt

request (ERI) enabled Bit 5—Transmit Enable (TE) Bit 5 selects enabling or disabling of the start of transmit operation. Bit 5 TE

0 Transmit operation disabled *1 (TXD32 pin is I/O port) (initial value)

1 Transmit operation enabled *2 (TXD32 pin is transmit data pin)

Notes: 1. Bit TDRE in SSR is fixed at 1. 2. When transmit data is written to TDR in this state, bit TDRE in SSR is cleared to 0 and serial data transmission is started. Be sure to carry out serial mode register (SMR) settings, and setting of bit SPC32 in SPCR, to decide the transmission format before setting bit TE to 1.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 344 of 658 REJ09B0042-0800 Bit 4—Receive Enable (RE) Bit 4 selects enabling or disabling of the start of receive operation. Bit 4 RE

0 Receive operation disabled *1 (RXD32 pin is I/O port) (initial value)

1 Receive operation enabled *2 (RXD32 pin is receive data pin)

Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is cleared to 0, and retain their previous state. 2. In this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. Be sure to carry out serial mode register (SMR) settings to decide the reception format before setting bit RE to 1. Bit 3—Reserved (MPIE) It’s a reserved bit. Bit 2—Transmit End Interrupt Enable (TEIE) Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid transmit data in TDR when MSB data is to be sent. Bit 2 TEIE

0 Transmit end interrupt request (TEI) disabled (initial value)

1 Transmit end interrupt request (TEI) enabled *

Note: * TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by clearing bit TEIE to 0.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 345 of 658 REJ09B0042-0800 Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0) Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK 32 pin. The combination of CKE1 and CKE0 determines whether the SCK32 pin functions as an I/O port, a clock output pin, or a clock input pin. The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0 should be cleared to 0. After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR). For details on clock source selection, see table 10.9. Description Bit 1 CKE1 Bit 0 CKE0 Communication Mode Clock Source SCK 32 Pin Function 0 0 Asynchronous Internal clock I/O port *1 Synchronous Internal clock Serial clock output *1 0 1 Asynchronous Internal clock Clock output *2 Synchronous Reserved 1 0 Asynchronous External clock Clock input *3 Synchronous External clock Serial clock input 1 1 Asynchronous Reserved Synchronous Reserved Notes: 1. Initial value 2. A clock with the same frequency as the bit rate is output. 3. Input a clock with a frequency 16 times the bit rate.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 346 of 658 REJ09B0042-0800

10.2.7 Serial Status Register (SSR)

R/(W)* RDRF R/(W)* OER R/(W)* FER R/(W)* PER R/(W)* MPBT R/W TEND R MPBR R Note: * Only a write of 0 for flag clearing is possible. SSR is an 8-bit register containing status flags that indicate the operational status of SCI3. SSR can be read or written to by the CPU at any time, but 1 cannot be written to bits TDRE, RDRF, OER, PER, and FER. Bits TEND and MPBR are read-only bits, and cannot be modified. SSR is initialized to H'84 upon reset, and in standby, module standby, or watch mode. Bit 7—Transmit Data Register Empty (TDRE) Bit 7 indicates that transmit data has been transferred from TDR to TSR. Bit 7 TDRE

0 Transmit data written in TDR has not been transferred to TSR

Clearing conditions: After reading TDRE = 1, cleared by writing 0 to TDRE When data is written to TDR by an instruction

1 Transmit data has not been written to TDR, or transmit data written in

TDR has been transferred to TSR Setting conditions: When bit TE in SCR3 is cleared to 0 When data is transferred from TDR to TSR (initial value)

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 347 of 658 REJ09B0042-0800 Bit 6—Receive Data Register Full (RDRF) Bit 6 indicates that received data is stored in RDR. Bit 6 RDRF

0 There is no receive data in RDR (initial value)

Clearing conditions: After reading RDRF = 1, cleared by writing 0 to RDRF When RDR data is read by an instruction

1 There is receive data in RDR

Setting condition: When reception ends normally and receive data is transferred from RSR to RDR Note: If an error is detected in the receive data, or if the RE bit in SCR3 has been cleared to 0, RDR and bit RDRF are not affected and retain their previous state. Note that if data reception is completed while bit RDRF is still set to 1, an overrun error (OER) will result and the receive data will be lost. Bit 5—Overrun Error (OER) Bit 5 indicates that an overrun error has occurred during reception. Bit 5 OER

0 Reception in progress or completed *1 (initial value)

Clearing condition: After reading OER = 1, cleared by writing 0 to OER

1 An overrun error has occurred during reception *2

Setting condition: When reception is completed with RDRF set to 1 Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous state. 2. RDR retains the receive data it held before the overrun error occurred, and data received after the error is lost. Reception cannot be continued with bit OER set to 1, and in synchronous mode, transmission cannot be continued either.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 348 of 658 REJ09B0042-0800 Bit 4—Framing Error (FER) Bit 4 indicates that a framing error has occurred during reception in asynchronous mode. Bit 4 FER Clearing condition: After reading FER = 1, cleared by writing 0 to FER

1 A framing error has occurred during reception

Setting condition: When the stop bit at the end of the receive data is checked for a value of 1 at the end of reception, and the stop bit is 0* Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous state. 2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. When a framing error occurs the receive data is transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER set to 1. In synchronous mode, neither transmission nor reception is possible when bit FER is set to 1. Bit 3—Parity Error (PER) Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous mode. Bit 3 PER Clearing condition: After reading PER = 1, cleared by writing 0 to PER

1 A parity error has occurred during reception *2

Setting condition: When the number of 1 bits in the receive data plus parity bit does not match the parity designated by bit PM in the serial mode register (SMR) Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous state. 2. Receive data in which a parity error has occurred is still transferred to RDR, but bit RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous mode, neither transmission nor reception is possible when bit FER is set to 1.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 349 of 658 REJ09B0042-0800 Bit 2—Transmit End (TEND) Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent. Bit 2 is a read-only bit and cannot be modified. Bit 2 TEND

0 Transmission in progress

Clearing conditions: After reading TDRE = 1, cleared by writing 0 to TDRE When data is written to TDR by an instruction

1 Transmission ended (initial value)

Setting conditions: When bit TE in SCR3 is cleared to 0 When bit TDRE is set to 1 when the last bit of a transmit character is sent Bit 1—Reserved (MPBR) It’s a reserved read-only bit. Bit 0—Reserved (MPBT) The write value should always be 0.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 350 of 658 REJ09B0042-0800

10.2.8 Bit Rate Register (BRR)

BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR). BRR can be read or written by the CPU at any time. BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode. Table 10.3 shows examples of BRR settings in asynchronous mode. The values shown are for active (high-speed) mode. Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) φ 16.4 kHz 19.2 kHz 1 MHz 1.2288 MHz 2 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 150 — — — 0 3 0 2 12 0.16 3 3 0 2 25 0.16 200 — — — 0 2 0 2 9 –2.34 3 2 0 3 4 –2.34 250 0 1 2.5 — — — 3 1 –2.34 0 153 –0.26 2 15 –2.34 300 — — — 0 1 0 0 103 0.16 3 1 0 2 12 0.16 600 — — — 0 0 0 0 51 0.16 3 0 0 0 103 0.16 1200 — — — 0 25 0.16 2 1 0 0 51 0.16 2400 — — — 0 12 0.16 2 0 0 0 25 0.16 4800 — — — — — — 0 7 0 0 12 0.16

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 351 of 658 REJ09B0042-0800 Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) φ

5 MHz 8 MHz 10 MHz

(bit/s) n N Error (%) n N Error (%) n N Error (%) 110 3 21 0.88 3 35 –1.36 3 43 0.88 150 3 15 1.73 3 25 0.16 3 32 –1.36 200 3 11 1.73 3 19 –2.34 3 23 1.73 250 3 9 –2.34 3 15 –2.34 3 19 –2.34 300 3 7 1.73 3 12 0.16 3 15 1.73 600 3 3 1.73 2 25 0.16 3 7 1.73 1200 3 1 1.73 2 12 0.16 3 3 1.73 2400 3 0 1.73 0 103 0.16 3 1 1.73 4800 2 1 1.73 0 51 0.16 3 0 1.73 9600 2 0 173 0 25 0.16 2 1 1.73 19200 0 7 1.73 0 12 0.16 2 0 1.73 31250 0 4 0 0 7 0 0 9 0 38400 0 3 1.73 — — — 0 7 1.73 Notes: No indication: Setting not possible. —: Setting possible, but errors may result. 1. The value set in BRR is given by the following equation: φ N = (32 × 22n × B) – 1 where B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 ≤ N ≤ 255) φ: System clock frequency n: Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10.4.) 2. The error in table 10.3 is the value obtained from the following equation, rounded to two decimal places. B (rate obtained from n, N, OSC) – R(bit rate in left-hand column in table 10.3.) Error (%) = R (bit rate in left-hand column in table 10.3.) × 100

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 352 of 658 REJ09B0042-0800 Table 10.4 Relation between n and Clock SMR Setting n Clock CKS1 CKS0 0 φ 0 0 0 φw/2*1/φw*2 0 1 2 φ/16 1 0 3 φ/64 1 1 Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. φ w clock in subactive mode and subsleep mode In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only. Table 10.5 shows the maximum bit rate for each frequency. The values shown are for active (high-speed) mode. Table 10.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Setting OSC (MHz) φ (MHz) Maximum Bit Rate (bit/s) n N 0.0384* 0.0192 600 0 0 2 1 31250 0 0 2.4576 1.2288 38400 0 0 4 2 62500 0 0 10 5 156250 0 0 16 8 250000 0 0 20 10 312500 0 0 Note: * When SMR is set up to CKS1 = 0, CKS0 = 1.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 353 of 658 REJ09B0042-0800 Table 10.6 shows examples of BRR settings in synchronous mode. The values shown are for active (high-speed) mode. Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1) φ 19.2 kHz 1 MHz 2 MHz Bit Rate (bit/s) n N Error n N Error n N Error 1K 0 249 0 — — — 2.5K 0 99 0 0 199 0 5K 0 49 0 0 99 0 10K 0 24 0 0 49 0 25K 0 9 0 0 19 0 50K 0 4 0 0 9 0 100K — — — 0 4 0 250K 0 0 0 0 1 0 500K 0 0 0 1 M

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 354 of 658 REJ09B0042-0800 Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2) φ

5 MHz 8 MHz 10 MHz Bit Rate

(bit/s) n N Error n N Error n N Error 250 — — — 3 124 0 2 624 0 500 — — — 2 249 0 0 4999 0 1K — — — 2 124 0 0 2499 0 2.5K — — — 2 49 0 0 999 0 5K 0 249 0 2 24 0 0 499 0 10K 0 124 0 0 199 0 0 249 0 25K 0 49 0 0 79 0 0 99 0 50K 0 24 0 0 39 0 0 49 0 100K — — — 0 19 0 0 24 0 250K 0 4 0 0 7 0 0 9 0 500K — — — 0 3 0 0 4 0 Blank: Cannot be set. — : A setting can be made, but an error will result. Notes: The value set in BRR is given by the following equation: φ N = (4 × 22n × B) – 1 where B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 ≤ N ≤ 255) φ: System clock frequency n: Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10.7.)

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 355 of 658 REJ09B0042-0800 Table 10.7 Relation between n and Clock SMR Setting n Clock CKS1 CKS0 0 φ 0 0 0 φw/2*1/φw*2 0 1 2 φ/16 1 0 3 φ/64 1 1 Notes: 1. φw/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. φw clock in subactive mode and subsleep mode In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 356 of 658 REJ09B0042-0800

10.2.9 Clock stop register 1 (CKSTPR1)

⎯ TFCKSTP TCCKSTP TACKSTP⎯ S32CKSTP ADCKSTP TGCKSTP 76543210 1 1111111 ⎯ R/W R/W R/W⎯ R/W R/W R/W Bit Initial value Read/Write CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the sections on the relevant modules. Bit 5—SCI3 Module Standby Mode Control (S32CKSTP) Bit 5 controls setting and clearing of module standby mode for SCI3. S32CKSTP Description

0 SCI3 is set to module standby mode *

1 SCI3 module standby mode is cleared (initial value)

Note: * All SCI3 register is initialized in module standby mode.

10.2.10 Serial Port Control Register (SPCR)

W SCINV3 R/W W SCINV2 R/W W SPCR is an 8-bit readable/writable register that performs RXD32 and TXD32 pin input/output data inversion switching. Bits 7 and 6—Reserved Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 357 of 658 REJ09B0042-0800 Bit 5—P4 2/TXD32 Pin Function Switch (SPC32) This bit selects whether pin P42/TXD32 is used as P42 or as TXD32. Bit 5 SPC32 Note: * Set the TE bit in SCR3 after setting this bit to 1. Bit 4—Reserved Bit 4 is reserved; only 0 can be written to this bit. Bit 3—TXD 32 Pin Output Data Inversion Switch Bit 3 specifies whether or not TXD32 pin output data is to be inverted. Bit 3 SCINV3 Bit 2—RXD 32 Pin Input Data Inversion Switch Bit 2 specifies whether or not RXD32 pin input data is to be inverted. Bit 2 SCINV2 Bits 1 and 0—Reserved Bits 1 and 0 are reserved; only 0 can written to these bits.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 358 of 658 REJ09B0042-0800

10.3 Operation

10.3.1 Overview

SCI3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. The serial mode register (SMR) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10.8. The clock source for SCI3 is determined by bit COM in SMR and bits CKE1 and CKE0 in SCR3, as shown in table 10.9. Asynchronous Mode

• Choice of 5-, 7-, or 8-bit data length
• Choice of parity addition, and addition of 1 or 2 stop bits. (The combination of these parameters determines the data transfer format and the character length.)
• Framing error (FER), parity error (PER), overrun error (OER), and break detection during reception
• Choice of internal or external clock as the clock source When internal clock is selected: SCI3 operates on the baud rate generator clock, and a clock with the same frequency as the bit rate can be output. When external clock is selected: A clock with a frequency 16 times the bit rate must be input. (The on-chip baud rate generator is not used.) Synchronous Mode
• Data transfer format: Fixed 8-bit data length
• Overrun error (OER) detection during reception
• Choice of internal or external clock as the clock source When internal clock is selected: SCI3 operates on the baud rate generator clock, and a serial clock is output. When external clock is selected: The on-chip baud rate generator is not used, and SCI3 operates on the input serial clock.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 359 of 658 REJ09B0042-0800 Table 10.8 SMR Settings and Corresponding Data Transfer Formats SMR Data Transfer Format Bit 7 COM Bit 6 CHR Bit 2 MP Bit 5 PE Bit 3 STOP Mode Data Length Parity Bit Stop Bit Length 0 0 0 0 0 8-bit data No 1 bit 1 2 bits 1 0 Asynchronous mode Yes 1 bit 1 2 bits 1 0 0 7-bit data No 1 bit 1 2 bits 1 0 Yes 1 bit 1 2 bits 0 1 0 0 Setting prohibited 1 0 5-bit data No 1 bit Asynchronous mode 2 bits 1 0 0 Setting prohibited 1 0 5-bit data Yes 1 bit Asynchronous mode 2 bits 1 * 0 * * Synchronous mode 8-bit data No No *: Don’t care Table 10.9 SMR and SCR3 Setting s and Clock Source Selection SMR SCR3 Bit 7 Bit 1 Bit 0 Transmit/Receive Clock COM CKE1 CKE0 Mode Clock Source SCK 32 Pin Function 0 0 0 Internal I/O port (SCK 32 pin not used) Asynchronous mode Outputs clock with same frequency as bit rate 1 0 External Inputs clock with frequency 16 times bit rate 1 0 0 Internal Outputs serial clock 1 0 Synchronous mode External Inputs serial clock 0 1 1 Reserved (Do not specify these combinations) 1 0 1 1 1 1

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 360 of 658 REJ09B0042-0800 Interrupts and Continuous Transmission/Reception SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These interrupts are shown in table 10.10. Table 10.10 Transmit/Receive Interrupts Interrupt Flags Interrupt Request Conditions Notes RXI RDRF RIE When serial reception is performed normally and receive data is transferred from RSR to RDR, bit RDRF is set to 1, and if bit RIE is set to 1 at this time, RXI is enabled and an interrupt is requested. (See figure 10.2(a).) The RXI interrupt routine reads the receive data transferred to RDR and clears bit RDRF to 0. Continuous reception can be performed by repeating the above operations until reception of the next RSR data is completed. TXI TDRE TIE When TSR is found to be empty (on completion of the previous transmission) and the transmit data placed in TDR is transferred to TSR, bit TDRE is set to 1. If bit TIE is set to 1 at this time, TXI is enabled and an interrupt is requested. (See figure 10.2(b).) The TXI interrupt routine writes the next transmit data to TDR and clears bit TDRE to 0. Continuous transmission can be performed by repeating the above operations until the data transferred to TSR has been transmitted. TEI TEND TEIE When the last bit of the character in TSR is transmitted, if bit TDRE is set to 1, bit TEND is set to 1. If bit TEIE is set to 1 at this time, TEI is enabled and an interrupt is requested. (See figure 10.2(c).) TEI indicates that the next transmit data has not been written to TDR when the last bit of the transmit character in TSR is sent.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 362 of 658 REJ09B0042-0800

10.3.2 Operation in Asynchronous Mode

In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication. As the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. Data Transfer Format The general data transfer format in asynchronous communication is shown in figure 10.3. Serial data Start bit 1 bit Transmit/receive data Parity bit Stop bit(s) 5, 7, or 8 bits One transfer data unit (character or frame) 1 bit or none 1 or 2 bits Mark state 1(MSB)(LSB) Figure 10.3 Data Format in Asynchronous Communication In asynchronous communication, the communication line is normally in the mark state (high level). SCI3 monitors the communication line and when it detects a space (low level), identifies this as a start bit and begins serial data communication. One transfer data character consists of a start bit (low level), followed by transmit/receive data (LSB-first format, starting from the least significant bit), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, synchronization is performed by the falling edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 363 of 658 REJ09B0042-0800 Table 10.11 shows the 16 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in the serial mode register (SMR). Table 10.11 Data Transfer Formats (Asynchronous Mode) 1CHR PE MP STOP 2 3 4 5 8-bit data Serial Data Transfer Format and Frame LengthSMR STOPS 6789 1 0 1 1 12 8-bit dataS 7-bit data STOP STOP S STOP 7-bit dataS STOP STOP 5-bit dataS STOP 5-bit dataS STOP STOP 8-bit data PS STOP 8-bit data PS STOP STOP Setting prohibited Setting prohibited Setting prohibited Setting prohibited 7-bit data PS TOPS STOP7-bit data STOPS 5-bit data STOPP P P S 5-bit data STOP STOPS [Legend] STOP: MPB: Start bit Stop bit Parity bit Multiprocessor bit

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 364 of 658 REJ09B0042-0800 Clock Either an internal clock generated by the baud rate generator or an external clock input at the SCK32 pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10.9 for details on clock source selection. When an external clock is input at the SCK 32 pin, the clock frequency should be 16 times the bit rate. When SCI3 operates on an internal clock, the clock can be output at the SCK32 pin. In this case the frequency of the output clock is the same as the bit rate, and the phase is such that the clock rises at the center of each bit of transmit/receive data, as shown in figure 10.4. 1 character (1 frame)

0 D 0D 1D 2D 3D 4D 5D 6D 70 / 1 1 1

Figure 10.4 Phase Relationship between Output Clock and Transfer Data (Asynchronous Mode) (8-bit data, parity, 2 stop bits) Data Transfer Operations

• SCI3 initialization Before data is transferred on SCI3, bits TE and RE in SCR3 must first be cleared to 0, and then SCI3 must be initialized as follows. Note: If the operation mode or data transfer format is changed, bits TE and RE must first be cleared to 0. When bit TE is cleared to 0, bit TDRE is set to 1. Note that the RDRF, PER, FER, and OER flags and the contents of RDR are retained when RE is cleared to 0. When an external clock is used in asynchronous mode, the clock should not be stopped during operation, including initialization. When an external clock is used in synchronous mode, the clock should not be supplied during operation, including initialization.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 367 of 658 REJ09B0042-0800 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. Serial data is transmitted from the TXD32 pin using the relevant data transfer format in table 10.11. When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If bit TDRE is set to 1, bit TEND in SSR bit is set to 1the mark state, in which 1s are transmitted, is established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI request is made. Figure 10.7 shows an example of the operation when transmitting in asynchronous mode. 1 frame Start bit Start bit Transmit data Transmit data Parity bit Stop bit Parity bit Stop bit Mark state 1 frame

01 D0 D1 D7 0/1 1 1 1 0 D0 D1 D7 0/1Serial

Figure 10.7 Example of Operation when Transmitting in Asynchronous Mode (8-bit data, parity, 1 stop bit)

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 369 of 658 REJ09B0042-0800 Start receive error processing End of receive error processing [4] Clear bits OER, PER, FER to 0 in SSR Yes OER = 1? Yes Yes FER = 1? Break? YesPER = 1? No No No No Overrun error processing Framing error processing (A)Parity error processing If a receive error has occurred, read bits OER, PER, and FER in SSR to identify the error, and after carrying out the necessary error processing, ensure that bits OER, PER, and FER are all cleared to 0. Reception cannot be resumed if any of these bits is set to 1. In the case of a framing error, a break can be detected by reading the value of the RXD 32 pin. [4] Figure 10.8 Example of Data Reception Flowchart (Asynchronous Mode) (cont)

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 370 of 658 REJ09B0042-0800 SCI3 operates as follows when receiving data. SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. Reception is carried out in accordance with the relevant data transfer format in table 10.11. The received data is first placed in RSR in LSB-to-MSB order, and then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks.

• Parity check SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even) set in bit PM in the serial mode register (SMR).
• Stop bit check SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
• Status check SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR. If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify a receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested. Table 10.12 shows the conditions for detecting a receive error, and receive data processing. Note: No further receive operations are possible wh ile a receive error flag is set. Bits OER, FER, PER, and RDRF must therefore be cleared to 0 before resuming reception. Table 10.12 Receive Error Detection Co nditions and Receive Data Processing Receive Error Abbr. Detection Conditions Receive Data Processing Overrun error OER When the next date receive operation is completed while bit RDRF is still set to 1 in SSR Receive data is not transferred from RSR to RDR Framing error FER When the stop bit is 0 Receive data is transferred from RSR to RDR Parity error PER When the parity (odd or even) set in SMR is different from that of the received data Receive data is transferred from RSR to RDR

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 371 of 658 REJ09B0042-0800 Figure 10.9 shows an example of the operation when receiving in asynchronous mode. 1 frame Start bit Start bit Receive data Receive data Parity bit Stop bit Parity bit Stop bit Mark state (idle state) 1 frame

01 D0 D1 D7 0/1 1 0 1 0 D0 D1 D7 0/1Serial

RDR data read Framing error processing RXI request 0 start bit detected ERI request in response to framing error Figure 10.9 Example of Operation when Receiving in Asynchronous Mode (8-Bit Data, Parity, 1 Stop Bit)

10.3.3 Operation in Synchronous Mode

In synchronous mode, SCI3 transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. SCI3 has separate transmission and reception units, allowing full-duplex communication with a shared clock. As the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 372 of 658 REJ09B0042-0800 Data Transfer Format The general data transfer format in asynchronous communication is shown in figure 10.10. Serial clock Serial data Note: * High level except in continuous transmission/reception LSB MSB * * Bit 1Bit 0B it 2B it 3B it 4 8 bits One transfer data unit (character or frame) Bit 5B it 6 Bit 7 Don't care Don't care Figure 10.10 Data Format in Synchronous Communication In synchronous communication, data on the communication line is output from one falling edge of the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of the serial clock. One transfer data character begins with the LSB and ends with the MSB. After output of the MSB, the communication line retains the MSB state. When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial clock. The data transfer format uses a fixed 8-bit data length. Parity bit cannot be added. Clock Either an internal clock generated by the baud rate generator or an external clock input at the SCK 32 pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM in SMR and bits CKE1 and CKE0 in SCR3. See table 10.9 for details on clock source selection. When SCI3 operates on an internal clock, the serial clock is output at the SCK32 pin. Eight pulses of the serial clock are output in transmission or reception of one character, and when SCI3 is not transmitting or receiving, the clock is fixed at the high level.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 378 of 658 REJ09B0042-0800 Notes: 1. When switching from transmission to simultaneous transmission/reception, check that SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set bits TE and RE to 1 simultaneously. 2. When switching from reception to simu ltaneous transmission/reception, check that SCI3 has finished receiving, clear bit RE to 0, then check that bit RDRF and the error flags (OER, FER, and PER) are cleared to 0, and finally set bits TE and RE to 1 simultaneously.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 379 of 658 REJ09B0042-0800

10.4 Interrupts

SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). These interrupts have the same vector address. The various interrupt requests are shown in table 10.13. Table 10.13 SCI3 Interrupt Requests Interrupt Abbr. Interrupt Request Vector Address RXI Interrupt request initiated by receive data full flag (RDRF) H'0024 TXI Interrupt request initiated by transmit data empty flag (TDRE) TEI Interrupt request initiated by transmit end flag (TEND) ERI Interrupt request initiated by receive error flag (OER, FER, PER) Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR3. When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in SSR, a TEI interrupt is requested. These two interrupts are generated during transmission. The initial value of bit TDRE in SSR is 1. Therefore, if the transmit data empty interrupt request (TXI) is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR, a TXI interrupt will be requested even if the transmit data is not ready. Also, the initial value of bit TEND in SSR is 1. Therefore, if the transmit end interrupt request (TEI) is enabled by setting bit TEIE to 1 in SCR3 before transmit data is transferred to TDR, a TEI interrupt will be requested even if the transmit data has not been sent. Effective use of these interrupt requests can be made by having processing that transfers transmit data to TDR carried out in the interrupt service routine. To prevent the generation of these interrupt requests (TXI and TEI), on the other hand, the enable bits for these interrupt requests (bits TIE and TEIE) should be set to 1 after transmit data has been transferred to TDR. When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during reception. For further details, see section 3.3, Interrupts.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 380 of 658 REJ09B0042-0800

10.5 Application Notes

The following points should be noted when using SCI3. 1. Relation between writes to TDR and bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1. Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR once only (not two or more times). 2. Operation when a number of receive errors occur simultaneously If a number of receive errors are detected simultaneously, the status flags in SSR will be set to the states shown in table 10.14. If an overrun error is detected, data transfer from RSR to RDR will not be performed, and the receive data will be lost. Table 10.14 SSR Status Flag States and Receive Data Transfer SSR Status Flags RDRF* OER FER PER Receive Data Transfer RSR → RDR Receive Error Status 1 1 0 0 X Overrun error 0 0 1 0 O Framing error 0 0 0 1 O Parity error 1 1 1 0 X Overrun error + framing error 1 1 0 1 X Overrun error + parity error 0 0 1 1 O Framing error + parity error 1 1 1 1 X Overrun error + framing error + parity error O : Receive data is transferred from RSR to RDR. X : Receive data is not transferred from RSR to RDR. Note: * Bit RDRF retains its state prior to data reception. However, note that if RDR is read after an overrun error has occurred in a frame because reading of the receive data in the previous frame was delayed, RDRF will be cleared to 0.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 381 of 658 REJ09B0042-0800 3. Break detection and processing When a framing error is detected, a break can be detected by reading the value of the RXD32 pin directly. In a break, the input from the RXD32 pin becomes all 0s, with the result that bit FER is set and bit PER may also be set. SCI3 continues the receive operation even after receiving a break. Note, therefore, that even though bit FER is cleared to 0 it will be set to 1 again. 4. Mark state and break detection When bit TE is cleared to 0, the TXD32 pin functions as an I/O port whose input/output direction and level are determined by PDR and PCR. This fact can be used to set the TXD 32 pin to the mark state, or to detect a break during transmission. To keep the communication line in the mark state (1 state) until bit TE is set to 1, set PCR = 1 and PDR = 1. Since bit TE is cleared to 0 at this time, the TXD32 pin functions as an I/O port and 1 is output. To detect a break, clear bit TE to 0 after setting PCR = 1 and PDR = 0. When bit TE is cleared to 0, the transmission unit is initialized regardless of the current transmission state, the TXD 32 pin functions as an I/O port, and 0 is output from the TXD32 pin. 5. Receive error flags and transmit operation (synchronous mode only) When a receive error flag (OER, PER, or FER) is set to 1, transmission cannot be started even if bit TDRE is cleared to 0. The receive error flags must be cleared to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if bit RE is cleared to 0. 6. Receive data sampling timing and receive margin in asynchronous mode In asynchronous mode, SCI3 operates on a basic clock with a frequency 16 times the transfer rate. When receiving, SCI3 performs internal synchronization by sampling the falling edge of the start bit with the basic clock. Receive data is latched internally at the 8th rising edge of the basic clock. This is illustrated in figure 10.16.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 382 of 658 REJ09B0042-0800 0 7 15 0 7 15 0 Internal basic clock Receive data (RXD32) Start bit D0 16 clock pulses 8 clock pulses Synchronization sampling timing Data sampling timing Figure 10.16 Receive Data Sampling Timing in Asynchronous Mode Consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1). where M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock frequency deviation Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in equation (1), a receive margin of 46.875% is given by equation (2). When D = 0.5 and F = 0, However, this is only a computed value, and a margin of 20% to 30% should be allowed when carrying out system design.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 383 of 658 REJ09B0042-0800 7. Relation between RDR reads and bit RDRF In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred. When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if bit RDR is read more than once, the second and subsequent read operations will be performed while bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. This is illustrated in figure 10.17. Communication line RDRF RDR Frame 1 Frame 2 Frame 3 Data 1 Data 1 RDR read RDR read Data 1 is read at point (A) Data 2 Data 3 Data 2 (A) Data 2 is read at point (B) (B) Figure 10.17 Relation between RDR Read Timing and Data In this case, only a single RDR read operation (not two or more) should be performed after first checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is sufficient margin in an RDR read operation before reception of the next frame is completed. To be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in synchronous mode, or before the STOP bit is transferred in asynchronous mode.

Section 10 Serial Communication Interface Rev. 8.00 Mar. 09, 2010 Page 384 of 658 REJ09B0042-0800 8. Transmit and receive operations when making a state transition Make sure that transmit and receive operations have completely finished before carrying out state transition processing. 9. Switching SCK32 function If pin SCK32 is used as a clock output pin by SCI3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock (φ) cycle immediately after it is switched. This can be prevented by either of the following methods according to the situation. a. When an SCK32 function is switched from clock output to non clock-output When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3 to 1 and 0, respectively. In this case, bit COM in SMR should be left 1. The above prevents SCK32 from being used as a general input/output pin. To avoid an intermediate level of voltage from being applied to SCK32, the line connected to SCK32 should be pulled up to the VCC level via a resistor, or supplied with output from an external device. b. When an SCK32 function is switched from clock output to general input/output When stopping data transfer, (i) Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3 to 1 and 0, respectively. (ii) Clear bit COM in SMR to 0 (iii) Clear bits CKE1 and CKE0 in SCR3 to 0 Note that special care is also needed here to avoid an intermediate level of voltage from being applied to SCK 32. 10. Set up at subactive or subsleep mode At subactive or subsleep mode, SCI3 becomes possible use only at CPU clock is φw/2. 11. Oscillator use with serial communications interface (H8/38124 Group only) When implementing the serial communications interface on the H8/38124 Group, the system clock oscillator must be used. The on-chip oscillator should not be used in this case. See on-chip oscillator selection method in section 4.2, System Clock Generator, for information on switching between the system clock oscillator and the on-chip oscillator.

Rev. 8.00 Mar. 09, 2010 Page 385 of 658 REJ09B0042-0800 Section 11 10-Bit PWM

11.1 Overview

The H8/38024 Group is provided with two on-chip 10-bit PWMs (pulse width modulators), designated PWM1 and PWM2, with identical functions. The PWMs can be used as D/A converters by connecting a low-pass filter. In this section the suffix m (m = 1 or 2) is used with register names, etc., as in PWDRLm, which denotes the PWDRL registers for each PWM.

11.1.1 Features

Features of the 10-bit PWMs are as follows.

• Choice of four conversion periods Any of the following conversion periods can be chosen: 4,096/φ, with a minimum modulation width of 4/φ 2,048/φ, with a minimum modulation width of 2/φ 1,024/φ, with a minimum modulation width of 1/φ 512/φ, with a minimum modulation width of 1/2 φ
• Pulse division method for less ripple
• Use of module standby mode enables this module to be placed in standby mode independently when not used. On the H8/38124 Group it is possible to select between two types of PWM output: pulse-division PWM and event counter PWM (PWM incorporating AEC). (The H8/38024 Group, H8/38024F- ZTAT Group, and H8/38024S Group can only produce pulse-division PWM output.) Refer to section 9.7, Asynchronous Event Counter, for information on event counter PWM.

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11.1.2 Block Diagram

Figure 11.1(1) shows a block diagram of the 10-bit PWM of the H8/38024 Group, H8/38024F- ZTAT Group, and H8/38024S Group. Figure 11.1(2) shows a block diagram of the 10-bit PWM of the H8/38124 Group. Internal data bus PWDRLm PWDRUm PWCRm PWM waveform generator φ/2 φ/4 φ/8 φ [Legend] PWDRLm: PWDRUm: PWCRm: PWM data register L PWM data register U PWM control register m = 1 or 2 PWMm Figure 11.1(1) Block Diagram of the 10-bit PWM (H8/38024 Group, H8/38024F-ZTAT Group, and H8/38024S Group: 1-Channel Configuration)

Rev. 8.00 Mar. 09, 2010 Page 387 of 658 REJ09B0042-0800 PWDRLm PWDRUm PWCRm PWM waveform generator φ/2 φ/4 φ/8 φ PWMm (IECPWM) IECPWM Internal data bus [Legend] PWCRm: PWDRLm: PWDRUm: PWMm: IECPWM: PWM control register PWM data register L PWM data register U PWM output pin Event counter PWM (PWM incorporating AEC) m = 1 or 2 Figure 11.1(2) Figure 11.1(1) Block Diagram of the 10-bit PWM (H8/38124 Group: 1-Channel Configuration)

11.1.3 Pin Configuration

Table 11.1 shows the output pin assigned to the 10-bit PWM. Table 11.1 Pin Configuration Name Abbr. I/O Function PWM1 output pin PWM1 Output Pulse-division PWM waveform output (PWM1)/ event counter PWM output (IECPWM)* PWM2 output pin PWM2 Output Pulse-division PWM waveform output (PWM2)/ event counter PWM output (IECPWM)* Note: * Implemented on H8/38124 Group only.

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11.1.4 Register Configuration

Table 11.2 shows the register configuration of the 10-bit PWM. Table 11.2 Register Configuration Name Abbr. R/W Initial Value Address PWM1 control register PWCR1 W H'FC/H'F8 * H'FFD0 PWM1 data register U PWDRU1 W H'FC H'FFD1 PWM1 data register L PWDRL1 W H'00 H'FFD2 PWM2 control register PWCR2 W H'FC/H'F8 * H'FFCD PWM2 data register U PWDRU2 W H'FC H'FFCE PWM2 data register L PWDRL2 W H'00 H'FFCF Clock stop register 2 CKSTPR2 R/W H'FF H'FFFB Note: * Implemented on H8/38124 Group only.

11.2 Register Descriptions

11.2.1 PWM Control Register (PWCRm)

Note: * I mplemented on H8/38124 Group only. PWCRm0 W 1/0* ⎯/W* PWCRm1 W PWCRm2* On the H8/38024 Group, H8/38024F-ZTAT Group, and H8/38024S Group, PWCRm is an 8-bit write-only register for input clock selection. Upon reset, PWCRm is initialized to H'FC. On the H8/38124 Group, PWCRm is an 8-bit write- only register used to select the input clock and PWM output type. At reset PWCRm is initialized to H'F8.

Rev. 8.00 Mar. 09, 2010 Page 389 of 658 REJ09B0042-0800 Bits 7 to 2—Reserved/Bits 7 to 3—Reserved * Bits 7 to 2 are reserved; they are always read as 1, and cannot be modified. Note: * Implemented on H8/38124 Group only. Bit 2—Output Format Select (PWCRm2) * This bit selects the format of the output from the PWMm output pin. This bit is write-only. Reading it always returns 1. Bit 2 PWCRm2

0 Pulse-division PWM (initial value)

1 Event counter PWM

Note: * Implemented on H8/38124 Group only. Bits 1 and 0—Clock Select 1 and 0 (PWCRm1, PWCRm0) Bits 1 and 0 select the clock supplied to the 10-bit PWM. These bits are write-only bits; they are always read as 1. Bit 1 PWCRm1 Bit 0 PWCRm0 0 0 The input clock is φ (tφ* = 1/φ) (initial value) The conversion period is 512/φ, with a minimum modulation width of 1/2φ 0 1 The input clock is φ/2 (tφ* = 2/φ) The conversion period is 1,024/φ, with a minimum modulation width of 1/φ 1 0 The input clock is φ/4 (tφ* = 4/φ) The conversion period is 2,048/φ, with a minimum modulation width of 2/φ 1 1 The input clock is φ/8 (tφ* = 8/φ) The conversion period is 4,096/φ, with a minimum modulation width of 4/φ Note: * Period of PWM input clock.

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11.2.2 PWM Data Registers U and L (PWDRUm, PWDRLm)

W PWDRUm1 W PWDRUm Bit Initial value Read/Write PWDRLm7 W PWDRLm6 W PWDRLm5 W PWDRLm4 W PWDRLm3 W PWDRLm0 W PWDRLm2 W PWDRLm1 W PWDRLm PWDRUm and PWDRLm form a 10-bit write-only register, with the upper 2 bits assigned to PWDRUm and the lower 8 bits to PWDRLm. The value written to PWDRUm and PWDRLm gives the total high-level width of one PWM waveform cycle. When 10-bit data is written to PWDRUm and PWDRLm, the register contents are latched in the PWM waveform generator, updating the PWM waveform generation data. The 10-bit data should always be written in the following sequence: 1. Write the lower 8 bits to PWDRLm. 2. Write the upper 2 bits to PWDRUm for the same channel. PWDRUm and PWDRLm are write-only registers. If they are read, all bits are read as 1. Upon reset, PWDRUm is initialized to H'FC, and PWDRLm to H'00.

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11.2.3 Clock Stop Register 2 (CKSTPR2)

LVDCKSTP* WDCKSTP PW1CKSTP LDCKSTP—— PW2CKSTP AECKSTP 76543 21 0 1 1111111 R/W R/WR /WR /W—— R/W R/W Bit Initial value Read/Write Note: * Bi ts 6 and 5 are also reserved on products other than the H8/38124 Group. CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the PWM is described here. For details of the other bits, see the sections on the relevant modules. Bits 4 and 1—PWM Module Standby Mode Control (PWmCKSTP) Bits 4 and 1 control setting and clearing of module standby mode for the PWMm. PWmCKSTP Description

0 PWMm is set to module standby mode

1 PWMm module standby mode is cleared (initial value)

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11.3 Operation

11.3.1 Operation

When using the 10-bit PWM, set the registers in the following sequence. 1. Set PWM1 or PWM2 in PMR9 to 1 for the PWM channel to be used, so that pin P9 0/PWM1 or P91/PWM2 is designated as the PWM output pin, or both are designated as PWM output pins. 2. Set bits PWCRm1 and PWCRm0 in the PWM control register (PWCRm) to select a conversion period of 4,096/φ (PWCRm1 = 1, PWCRm0 = 1), 2,048/φ (PWCRm1 = 1, PWCRm0 = 0), 1,024/φ (PWCRm1 = 0, PWCRm0 = 1), or 512/φ (PWCRm1 = 0, PWCRm0 = 0). In the case of the H8/38124 Group, select between pulse-division PWM (PWCRm2 = 0) and event counter PWM (PWCRm2 = 1) output. Refer to section 9.7, Asynchronous Event Counter (AEC), for information on the event counter PWM (PWM incorporating AEC) output format. 3. Set the output waveform data in PWDRUm and PWDRLm. Be sure to write in the correct sequence, first PWDRLm then PWDRUm for the same channel. When data is written to PWDRUm, the data will be latched in the PWM waveform generator, updating the PWM waveform generation in synchronization with internal signals. One conversion period consists of 4 pulses, as shown in figure 11.2. The total of the high-level pulse widths during this period (T H) corresponds to the data in PWDRUm and PWDRLm. This relation can be represented as follows. TH = (data value in PWDRUm and PWDRLm + 4) × tφ/2 where tφ is the PWM input clock period: 1/φ (PWCRm = H'0), 2/φ (PWCRm = H'1), 4/φ (PWCRm = H'2), or 8/φ (PWCRm = H'3). Example: Settings in order to obtain a conversion period of 1,024 µs: When PWCRm1 = 0 and PWCRm0 = 0, the conversion period is 512/φ, so φ must be 0.5 MHz. In this case, tfn = 256 µs, with 1/2φ (resolution) = 1.0 µs. When PWCRm1 = 0 and PWCRm0 = 1, the conversion period is 1,024/φ, so φ must be 1 MHz. In this case, tfn = 256 µs, with 1/φ (resolution) = 1.0 µs. When PWCRm1 = 1 and PWCRm0 = 0, the conversion period is 2,048/φ , so φ must be 2 MHz. In this case, tfn = 256 µs, with 2/φ (resolution) = 1.0 µs. When PWCRm1 = 1 and PWCRm0 = 1, the conversion period is 4,096/φ, so φ must be 4 MHz. In this case, tfn = 256 µs, with 4/φ (resolution) = 1.0 µs Accordingly, for a conversion period of 1,024 µs, the system clock frequency ( φ) must be 0.5 MHz, 1 MHz, 2 MHz, or 4 MHz.

Rev. 8.00 Mar. 09, 2010 Page 393 of 658 REJ09B0042-0800 1 conversion period tf1 tH1 tH2 tH3 tH4 tf2 tf3 tf4 TH = tH1 + tH2 + tH3 + tH4 tf1 = tf2 = tf3 = tf4 Figure 11.2 PWM Output Waveform

11.3.2 PWM Operation Modes

PWM operation modes are shown in table 11.3. Table 11.3 PWM Operation Modes Operation Mode Reset Active Sleep Watch Sub- active Sub- sleep Standby Module Standby PWCRm Reset Functions Functions Retained Retained Retained Retained Retained PWDRUm Reset Functions Functions Retained Retained Retained Retained Retained PWDRLm Reset Functions Functions Retained Retained Retained Retained Retained

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Rev. 8.00 Mar. 09, 2010 Page 395 of 658 REJ09B0042-0800 Section 12 A/D Converter

12.1 Overview

This LSI includes on-chip a resistance-ladder-based successive-approximation analog-to-digital converter, and can convert up to 8 channels of analog input.

12.1.1 Features

The A/D converter has the following features.

• 10-bit resolution
• Eight input channels
• Conversion time: approx. 12.4 µs per channel (at 5-MHz operation)/6.2 µs (at 10-MHz operation)*
• Built-in sample-and-hold function
• Interrupt requested on completion of A/D conversion
• A/D conversion can be started by external trigger input
• Use of module standby mode enables this module to be placed in standby mode independently when not used. Note: * H8/38124 group only.

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12.1.2 Block Diagram

Figure 12.1 shows a block diagram of the A/D converter. Internal data bus AMR ADSR ADRRH ADRRL Control logic Com- parator AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG AV AV CC SS Multiplexer Reference voltage IRRAD AVCC AVSS [Legend] AMR: ADSR: ADRR: IRRAD: A/D mode register A/D start register A/D result register A/D conversion end interrupt request flag Figure 12.1 Block Diagram of the A/D Converter

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12.1.3 Pin Configuration

Table 12.1 shows the A/D converter pin configuration. Table 12.1 Pin Configuration Name Abbr. I/O Function Analog power supply AV CC Input Power supply and reference voltage of analog part Analog ground AV SS Input Ground and reference voltage of analog part Analog input 0 AN 0 Input Analog input channel 0 Analog input 1 AN 1 Input Analog input channel 1 Analog input 2 AN 2 Input Analog input channel 2 Analog input 3 AN 3 Input Analog input channel 3 Analog input 4 AN 4 Input Analog input channel 4 Analog input 5 AN 5 Input Analog input channel 5 Analog input 6 AN 6 Input Analog input channel 6 Analog input 7 AN 7 Input Analog input channel 7 External trigger input ADTRG Input External trigger input for starting A/D conversion

12.1.4 Register Configuration

Table 12.2 shows the A/D converter register configuration. Table 12.2 Register Configuration Name Abbr. R/W Initial Value Address A/D mode register AMR R/W H'30 H'FFC6 A/D start register ADSR R/W H'7F H'FFC7 A/D result register H ADRRH R Not fixed H'FFC4 A/D result register L ADRRL R Not fixed H'FFC5 Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA

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12.2 Register Descriptions

12.2.1 A/D Result Registers (ADRRH, ADRRL)

R Unde- fined R Unde- fined R Unde- fined R Unde- fined R Unde- fined R Unde- fined R Unde- fined R Unde- fined R Unde- fined R ADR9 ADR8 ADR7 ADR6 ADR5 ADR2ADR4 ADR3 ADR1 ADR0 ⎯⎯⎯ ⎯ ⎯⎯ ADRRH and ADRRL together comprise a 16-bit read-only register for holding the results of analog-to-digital conversion. The upper 8 bits of the data are held in ADRRH, and the lower 2 bits in ADRRL. ADRRH and ADRRL can be read by the CPU at any time, but the ADRRH and ADRRL values during A/D conversion are not fixed. After A/D conversion is complete, the conversion result is stored as 10-bit data, and this data is held until the next conversion operation starts. ADRRH and ADRRL are not cleared on reset.

12.2.2 A/D Mode Register (AMR)

AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger option, and the analog input pins. Upon reset, AMR is initialized to H'30.

Rev. 8.00 Mar. 09, 2010 Page 399 of 658 REJ09B0042-0800 Bit 7—Clock Select (CKS) Bit 7 sets the A/D conversion speed. Conversion Time Bit 7 CKS Conversion Period φ = 1 MHz φ = 5 MHz φ = 10 MHz*2 0 62/ φ (initial value) 62 µs 12.4 µs 6.2 µs 1 31/ φ 31 µs — *1 — *1 Notes: 1. With the H8/38024, H8/38024S, and H8/38024F-ZTAT operation cannot be guaranteed if the conversion time is less than 12.4 µs. Make sure to select a setting that gives a conversion time of 12.4 µs or more. With the H8/38124 Group operation cannot be guaranteed if the conversion time is less than 6.2 μs. Make sure to select a setting that gives a conversion time of 6.2 μs or more. 2. H8/38124 Group only. Bit 6—External Trigger Select (TRGE) Bit 6 enables or disables the start of A/D conversion by external trigger input. Bit 6 TRGE

0 Disables start of A/D conversion by external trigger (initial value)

1 Enables start of A/D conversion by rising or falling edge of external trigger at pin

ADTRG* Note: * The external trigger ( ADTRG) edge is selected by bit IEG4 of IEGR. See 1. IRQ edge select register (IEGR) in section 3.3.2, Interrupt Control Registers, for details. Bits 5 and 4—Reserved Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.

Rev. 8.00 Mar. 09, 2010 Page 400 of 658 REJ09B0042-0800 Bits 3 to 0—Channel Select (CH3 to CH0) Bits 3 to 0 select the analog input channel. The channel selection should be made while bit ADSF is cleared to 0. Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 Analog Input Channel 0 0 * * No channel selected (initial value) 0 1 0 0 AN 0 0 1 0 1 AN 1 0 1 1 0 AN 2 0 1 1 1 AN 3 1 0 0 0 AN 4 1 0 0 1 AN 5 1 0 1 0 AN 6 1 0 1 1 AN 7 1 1 * * Setting prohibited *: Don’t care

12.2.3 A/D Start Register (ADSR)

The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D conversion. A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the converted data is set in ADRRH and ADRRL, and at the same time ADSF is cleared to 0.

Rev. 8.00 Mar. 09, 2010 Page 401 of 658 REJ09B0042-0800 Bit 7—A/D Start Flag (ADSF) Bit 7 controls and indicates the start and end of A/D conversion. Bit 7 ADSF

0 Read: Indicates the completion of A/D conversion (initial value)

Write: Stops A/D conversion

1 Read: Indicates A/D conversion in progress

Write: Starts A/D conversion Bits 6 to 0—Reserved Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified.

12.2.4 Clock Stop Register 1 (CKSTPR1)

⎯ TFCKSTP TCCKSTP TACKSTP⎯ S32CKSTP ADCKSTP TGCKSTP 76543210 1 1111111 ⎯ R/W R/W R/W⎯ R/W R/W R/W Bit Initial value Read/Write CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the A/D converter is described here. For details of the other bits, see the sections on the relevant modules. Bit 4—A/D Converter Module Standby Mode Control (ADCKSTP) Bit 4 controls setting and clearing of module standby mode for the A/D converter. ADCKSTP Description

1 A/D converter module standby mode is cleared (initial value)

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12.3 Operation

12.3.1 A/D Conversion Operation

The A/D converter operates by successive approximations, and yields its conversion result as 10- bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is set to 1. If the conversion time or input channel needs to be changed in the A/D mode register (AMR) during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction.

12.3.2 Start of A/D Conversion by External Trigger Input

The A/D converter can be made to start A/D conversion by input of an external trigger signal. External trigger input is enabled at pin ADTRG when bit IRQ4 in PMR1 is set to 1 and bit TRGE in AMR is set to 1. Then when the input signal edge designated in bit IEG4 of interrupt edge select register (IEGR) is detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D conversion. Figure 12.2 shows the timing. φ Pin ADTRG (when bit IEG4 = 0) ADSF A/D conversion Figure 12.2 External Trigger Input Timing

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12.3.3 A/D Converter Operation Modes

A/D converter operation modes are shown in table 12.3. Table 12.3 A/D Converter Operation Modes Operation Mode Reset Active Sleep Watch Sub- active Sub- sleep Standby Module Standby AMR Reset Functions Functions Retained Retained Retained Retained Retained ADSR Reset Functions Functions Retained Retained Retained Retained Retained ADRRH Retained * Functions Functions Retained Retained Retained Retained Retained ADRRL Retained * Functions Functions Retained Retained Retained Retained Retained Note: * Undefined in a power-on reset.

12.4 Interrupts

When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2 (IRR2) is set to 1. A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 2 (IENR2). For further details see section 3.3, Interrupts.

12.5 Typical Use

An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as the analog input channel. Figure 12.3 shows the operation timing. 1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN 1 the analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. 2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is stored in ADRRH and ADRRL. At the same time ADSF is cleared to 0, and the A/D converter goes to the idle state. 3. Bit IENAD = 1, so an A/D conversion end interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The A/D conversion result is read and processed. 6. The A/D interrupt handling routine ends.

Rev. 8.00 Mar. 09, 2010 Page 404 of 658 REJ09B0042-0800 If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter. Idle A/D conversion (1) Idle A/D conversion (2) Idle Interrupt (IRRAD) IENAD ADSF Channel 1 (AN1) operation state ADRRH ADRRL Set* Set* Set* Read conversion result Read conversion result A/D conversion result (1) A/D co nversion result (2) A/D conversion starts Note: * ( ) indicates instruction execution by software. Figure 12.3 Typical A/D Converter Operation Timing

Rev. 8.00 Mar. 09, 2010 Page 405 of 658 REJ09B0042-0800 Start Set A/D conversion speed and input channel Perform A/D conversion? End Yes No Disable A/D conversion end interrupt Start A/D conversion ADSF = 0? No Yes Read ADSR Read ADRRH/ADRRL data Figure 12.4 Flow Chart of Procedure for Using A/D Converter (Polling by Software)

Rev. 8.00 Mar. 09, 2010 Page 406 of 658 REJ09B0042-0800 Start Set A/D conversion speed and input channel Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? Yes No End Yes No Clear bit IRRAD to 0 in IRR2 Read ADRRH/ADRRL data Perform A/D conversion? Figure 12.5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used)

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12.6 A/D Conversion Accuracy Definitions

This LSI's A/D conversion accuracy definitions are given below.

• Resolution The number of A/D converter digital output codes
• Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 12.6).
• Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 12.7).
• Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 12.7).
• Nonlinearity error The error with respect to the ideal A/D conversion characteristics between zero voltage and full-scale voltage. Does not include offset error, full-scale error, or quantization error.
• Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, full- scale error, quantization error, and nonlinearity error.

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12.7 Application Notes

12.7.1 Permissible Signal Source Impedance

This LSI’s analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 kΩ or less. This specification is provided to enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it may not be possible to guarantee A/D conversion precision. However, a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 kΩ, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/μs or greater) (see figure 12.8). When converting a high-speed analog signal, a low- impedance buffer should be inserted.

12.7.2 Influences on Absolute Precision

Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND. Care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board. A/D converter equivalent circuit This LSI 20 pFCin = 15 pF 10 kΩUp to 10 kΩ Low-pass filter C to 0.1 μF Sensor output impedance Sensor input Figure 12.8 Analog Input Circuit Example

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12.7.3 Additional Usage Notes

• Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D start register (ADSR) is cleared to 0.
• Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy.
• When A/D conversion is started after clearing module standby mode, wait for 10 φ clock cycles before starting.
• In active mode or sleep mode, analog power supply current (AISTOP1) flows into the ladder resistance even when the A/D converter is not operating. Therefore, if the A/D converter is not used, it is recommended that AVCC be connected to the system power supply and the ADCKSTP (A/D converter module standby mode control) bit be cleared to 0 in clock stop register 1 (CKSTPR1).

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 411 of 658 REJ09B0042-0800 Section 13 LCD Controller/Driver

13.1 Overview

This LSI has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit, enabling it to directly drive an LCD panel.

13.1.1 Features

Features of the LCD controller/driver are given below.

• Display capacity Duty Cycle Internal Driver Static 32 seg 1/2 32 seg 1/3 32 seg 1/4 32 seg
• LCD RAM capacity 8 bits × 16 bytes (128 bits)
• Word access to LCD RAM
• All four segment output pins can be used individually as port pins.
• Common output pins not used because of the duty cycle can be used for common double- buffering (parallel connection).
• Display possible in operating modes other than standby mode
• Choice of 11 frame frequencies
• Built-in power supply split-resistance, supplying LCD drive power
• Use of module standby mode enables this module to be placed in standby mode independently when not used.
• A or B waveform selectable by software
• Removal of split-resistance can be controlled in software. Note that this capability is implemented in the H8/38124 Group only.

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 412 of 658 REJ09B0042-0800

13.1.2 Block Diagram

Figures 13.1(1) and 13.1(2) show a block diagram of the LCD controller/driver. φ/256 to φ/2 φW SEGn LPCR LCR LCR2 Display timing generator LCD RAM (16 bytes) Internal data bus 32-bit shift register LCD drive power supply Segment driver Common data latch Common driver VSS COM1 COM4 SEG32 SEG1 [Legend] LPCR: LCD port control register LCR: LCD control register LCR2: LCD control register 2 VCC Figure 13.1(1) Block Diagram of H8/38024, H8/38024S, and H8/38024F-ZTAT Group LCD Controller/Driver

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 413 of 658 REJ09B0042-0800 φ/256 to φ/2 φw SEGn LPCR LCR LCR2 VSS COM1 COM4 SEG32 SEG1 VCC Internal data bus Display timing generator LCD RAM (16 bytes) 32-bit shift register LCD drive power supply Segment driver Common data latch Common driver [Legend] LPCR: LCD port control register LCR: LCD control register LCR2: LCD control register 2 Figure 13.1(2) Block Diagram of H8/38124 Group LCD Controller/Driver

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13.1.3 Pin Configuration

Table 13.1 shows the LCD controller/driver pin configuration. Table 13.1 Pin Configuration Name Abbr. I/O Function Segment output pins SEG 32 to SEG1 Output LCD segment drive pins All pins are multiplexed as port pins (setting programmable) Common output pins COM 4 to COM1 Output LCD common drive pins Pins can be used in parallel with static or 1/2 duty LCD power supply pins V 1, V2, V3 — Used when a bypass capacitor is connected externally, and when an external power supply circuit is used

13.1.4 Register Configuration

Table 13.2 shows the register configuration of the LCD controller/driver. Table 13.2 LCD Controller/Driver Registers Name Abbr. R/W Initial Value Address LCD port control register LPCR R/W — H'FFC0 LCD control register LCR R/W H'80 H'FFC1 LCD control register 2 LCR2 R/W — H'FFC2 LCD RAM — R/W Undefined H'F740 to H'F74F Clock stop register 2 CKSTPR2 R/W H'FF H'FFFB

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 415 of 658 REJ09B0042-0800

13.2 Register Descriptions

13.2.1 LCD Port Control Register (LPCR)

W SGS3 R/W SGS0 R/W SGS2 R/W SGS1 R/W LPCR is an 8-bit read/write register which selects the duty cycle and LCD driver pin functions. Bits 7 to 5—Duty Cycle Select 1 and 0 (DTS 1, DTS0), Common Function Select (CMX) The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty. CMX specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when not all common pins are used because of the duty setting. Bit 7 DTS1 Bit 6 DTS0 Bit 5 CMX Duty Cycle Common Drivers Notes 0 0 0 Static COM 1 (initial value) Do not use COM 4, COM3, and COM2.

1 C O M 4 to COM1 COM 4, COM3, and COM2 output

the same waveform as COM1. 0 1 0 1/2 duty COM 2 and COM1 Do not use COM 4 and COM3.

1 C O M 4 to COM1 COM 4 outputs the same waveform

as COM3, and COM2 outputs the same waveform as COM1. 1 0 0 1/3 duty COM 3 to COM1 Do not use COM 4. 1 C O M 4 to COM1 Do not use COM 4. 1 1 0 1/4 duty COM 4 to COM1 — Bit 4—Reserved Bit 4 is reserved. It can only be written with 0.

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 416 of 658 REJ09B0042-0800 Bits 3 to 0—Segment Driver Select 3 to 0 (SGS3 to SGS0) Bits 3 to 0 select the segment drivers to be used. Function of Pins SEG 32 to SEG1 Bit 3 SGS3 Bit 2 SGS2 Bit 1 SGS1 Bit 0 SGS0 SEG32 to SEG29 SEG28 to SEG25 SEG24 to SEG21 SEG20 to SEG17 SEG16 to SEG13 SEG12 to SEG9 SEG8 to SEG5 SEG4 to SEG1 Notes 0 0 0 0 Port Port Port Port Port Port Port Port (Initial value)

1 Port Port Port Port Port Port Port SEG

1 0 Port Port Port Port Port Port SEG SEG

1 Port Port Port Port Port SEG SEG SEG

1 0 0 Port Port Port Port SEG SEG SEG SEG

1 Port Port Port SEG SEG SEG SEG SEG

1 0 Port Port SEG SEG SEG SEG SEG SEG

1 Port SEG SEG SEG SEG SEG SEG SEG

1 0 0 0 SEG SEG SEG SEG SEG SEG SEG SEG

1 SEG SEG SEG SEG SEG SEG SEG Port

1 0 SEG SEG SEG SEG SEG SEG Port Port

1 SEG SEG SEG SEG SEG Port Port Port

1 0 0 SEG SEG SEG SEG Port Port Port Port

1 SEG SEG SEG Port Port Port Port Port

1 0 SEG SEG Port Port Port Port Port Port

1 SEG Port Port Port Port Port Port Port

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 417 of 658 REJ09B0042-0800

13.2.2 LCD Control Register (LCR)

LCR is an 8-bit read/write register which performs LCD drive power supply on/off control and display data control, and selects the frame frequency. LCR is initialized to H'80 upon reset. Bit 7—Reserved Bit 7 is reserved; it is always read as 1 and cannot be modified. Bit 6—LCD Drive Power Supply On/Off Control (PSW) Bit 6 can be used to turn the LCD drive power supply off when LCD display is not required in a power-down mode, or when an external power supply is used. When the ACT bit is cleared to 0, or in standby mode, the LCD drive power supply is turned off regardless of the setting of this bit. Bit 6 PSW

0 LCD drive power supply off (initial value)

1 LCD drive power supply on

Bit 5—Display Function Activate (ACT) Bit 5 specifies whether or not the LCD controller/driver is used. Clearing this bit to 0 halts operation of the LCD controller/driver. The LCD drive power supply is also turned off, regardless of the setting of the PSW bit. However, register contents are retained. Bit 5 ACT

0 LCD controller/driver operation halted (initial value)

1 LCD controller/driver operates

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 418 of 658 REJ09B0042-0800 Bit 4—Display Data Control (DISP) Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless of the LCD RAM contents. Bit 4 DISP

0 Blank data is displayed (initial value)

1 LCD RAM data is display

Bits 3 to 0—Frame Frequency Select 3 to 0 (CKS3 to CKS0) Bits 3 to 0 select the operating clock and the frame frequency. In subactive mode, watch mode, and subsleep mode, the system clock (φ) is halted, and therefore display operations are not performed if one of the clocks from φ/2 to φ/256 is selected. If LCD display is required in these modes, φw, φw/2, or φw/4 must be selected as the operating clock. Frame Frequency *2 Bit 3 CKS3 Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Operating Clock φ = 2 MHz φ = 250 kHz*1 0 * 0 0 φw 128 Hz *3 (initial value) 0 * 0 1 φw/2 64 Hz *3 0 * 1 * φw/4 32 Hz *3 1 0 0 0 φ/2 — 244 Hz 1 0 0 1 φ/4 977 Hz 122 Hz 1 0 1 0 φ/8 488 Hz 61 Hz 1 0 1 1 φ/16 244 Hz 30.5 Hz 1 1 0 0 φ/32 122 Hz — 1 1 0 1 φ/64 61 Hz — 1 1 1 0 φ/128 30.5 Hz — 1 1 1 1 φ/256 — — *: Don’t care Notes: 1. This is the frame frequency in active (medium-speed, φosc/16) mode when φ = 2 MHz. 2. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown. 3. This is the frame frequency when φw = 32.768 kHz.

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13.2.3 LCD Control Register 2 (LCR2)

LCDAB — — — CDS3 * CDS2 * CDS1 * CDS0 * Initial value 0 1 1 — 0 0 0 0 Read/Write R/W — — R/W R/W R/W R/W R/W Note: * Applies to the H8/38124 Group only. On the H8/38024, H8/38024S, and H8/38024F-ZTAT Group, these bits are reserved like bit 4. LCR2 is an 8-bit read/write register which controls switching between the A waveform and B waveform and removal of split-resistance. Note that removal of split-resistance control is only implemented on the H8/38124 Group. Bit 7—A Waveform/B Waveform Switching Control (LCDAB) Bit 7 specifies whether the A waveform or B waveform is used as the LCD drive waveform. Bit 7 LCDAB

0 Drive using A waveform (initial value)

1 Drive using B waveform

Bits 6 and 5—Reserved Bits 6 and 5 are reserved; they are always read as 1 and cannot be modified. Bit 4—Reserved Bit 4 is reserved; this can only be written with 0.

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 420 of 658 REJ09B0042-0800 Bits 3 to 0—Removal of Split-Resistance Control These bits control whether the split-resistance is removed or connected. Note that on products other than the H8/38124 Group, these bits are reserved like bit 4. Bit 3 CDS3 Bit 2 CDS2 Bit 1 CDS1 Bit 0 CDS0 Description 0 0 0 0 (initial value)

1 Split-resistance connected

1 Split-resistance removed

1 0 0 0 Split-resistance connected 1 0 1 0 0 1 0

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13.2.4 Clock Stop Register 2 (CKSTPR2)

Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group. LVDCKSTP* R/W PW2CKSTP R/W AECKSTP R/W LDCKSTP R/W WDCKSTP R/W PW1CKSTP R/W CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the LCD controller/driver is described here. For details of the other bits, see the sections on the relevant modules. Bit 0—LCD Controller/Driver Module Standby Mode Control (LDCKSTP) Bit 0 controls setting and clearing of module standby mode for the LCD controller/driver. Bit 0 LDCKSTP

0 LCD controller/driver is set to module standby mode

1 LCD controller/driver module standby mode is cleared (initial value)

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13.3 Operation

13.3.1 Settings up to LCD Display

To perform LCD display, the hardware and software related items described below must first be determined. Hardware Settings a. Using 1/2 duty When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 13.2. VCC VSS Figure 13.2 Handling of LCD Drive Power Supply when Using 1/2 Duty b. Large-panel display As the impedance of the built-in power supply split-resistance is large, it may not be suitable for driving a large panel. If the display lacks sharpness when using a large panel, refer to section 13.3.4, Boosting the LCD Drive Power Supply. When static or 1/2 duty is selected, the common output drive capability can be increased. Set CMX to 1 when selecting the duty cycle. In this mode, with a static duty cycle pins COM 4 to COM1 output the same waveform, and with 1/2 duty the COM1 waveform is output from pins COM2 and COM1, and the COM2 waveform is output from pins COM4 and COM3.

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 423 of 658 REJ09B0042-0800 Software Settings a. Duty selection Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits DTS1 and DTS0. b. Segment selection The segment drivers to be used can be selected with bits SGS3 to SGS0. c. Frame frequency selection The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency should be selected in accordance with the LCD panel specification. For the clock selection method in watch mode, subactive mode, and subsleep mode, see section 13.3.3, Operation in Power-Down Modes. d. A or B waveform selection Either the A or B waveform can be selected as the LCD waveform to be used by means of LCDAB.

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13.3.2 Relationship between LCD RAM and Display

The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles are shown in figures 13.3 to 13.6. After setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM, and display is started automatically when turned on. Word- or byte-access instructions can be used for RAM setting. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG2 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1H'F740 H'F74F SEG31SEG32SEG32SEG32SEG32 SEG31 SEG31 SEG31 COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1 Figure 13.3 LCD RAM Map (1/4 Duty)

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 425 of 658 REJ09B0042-0800 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1H'F740 H'F74F SEG31SEG32SEG32SEG32 SEG31 SEG31 COM3 COM2 COM1 COM3 COM2 COM1 Space not used for display Figure 13.4 LCD RAM Map (1/3 Duty)

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 427 of 658 REJ09B0042-0800 1 frame M Data COM1 COM2 COM3 COM4 SEGn VSS VSS VSS VSS VSS (a) Waveform with 1/4 duty 1 frame M Data COM1 COM2 COM3 SEGn VSS VSS VSS VSS 1 frame M Data COM1 COM2 SEGn V2, V3 VSS V2, V3 VSS V2, V3 VSS 1 frame M Data COM1 SEGn VSS VSS (b) Waveform with 1/3 duty (c) Waveform with 1/2 duty (d) Waveform with static output M: LCD alternation signal Figure 13.7 Output Waveforms for Each Duty Cycle (A Waveform)

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 428 of 658 REJ09B0042-0800 M Data COM1 COM2 SEGn V2, V3 VSS V2, V3 VSS M Data COM1 SEGn VSS VSS (c) Waveform with 1/2 duty M: LCD alternation signal (d) Waveform with static output 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame (b) Waveform with 1/3 duty M Data COM3 SEGn COM1 VSS COM2 VSS VSS VSS (a) Waveform with 1/4 duty M Data COM1 COM2 COM3 COM4 SEGn VSS VSS VSS VSS VSS 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame V2, V3 VSS Figure 13.8 Output Waveforms for Each Duty Cycle (B Waveform)

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 429 of 658 REJ09B0042-0800 Table 13.3 Output Levels Data 0 0 1 1 M 0 1 0 1 Static Common output V 1 V SS V 1 V SS Segment output V 1 V SS V SS V 1 1/2 duty Common output V 2, V3 V 2, V3 V 1 V SS Segment output V 1 V SS V SS V 1 1/3 duty Common output V 3 V 2 V 1 V SS Segment output V 2 V 3 V SS V 1 1/4 duty Common output V 3 V 2 V 1 V SS Segment output V 2 V 3 V SS V 1 M: LCD alternation signal

13.3.3 Operation in Power-Down Modes

This LSI the LCD controller/driver can be operated even in the power-down modes. The operating state of the LCD controller/driver in the power-down modes is summarized in table 13.4. In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and therefore, unless φw, φw/2, or φw/4 has been selected by bits CKS3 to CKS0, the clock will not be supplied and display will halt. Since there is a possibility that a direct current will be applied to the LCD panel in this case, it is essential to ensure that φw, φw/2, or φw/4 is selected. In active (medium-speed) mode, the system clock is switched, and therefore CKS3 to CKS0 must be modified to ensure that the frame frequency does not change.

Section 13 LCD Controller/Driver Rev. 8.00 Mar. 09, 2010 Page 430 of 658 REJ09B0042-0800 Table 13.4 Power-Down Modes and Display Operation Mode Reset Active Sleep Watch Sub- active Sub- sleep Standby Module Standby Clock φ Runs Runs Runs Stops Stops Stops Stops Stops *4 φw Runs Runs Runs Runs Runs Runs Stops *1 Stops *4 ACT = 0 Stops Stops Stops Stops Stops Stops Stops *2 Stops Display operation ACT = 1 Stops Functions Functions Functions *3 Functions*3 Functions*3 Stops*2 Stops Notes: 1. The subclock oscillator does not stop, but clock supply is halted. 2. The LCD drive power supply is turned off regardless of the setting of the PSW bit. 3. Display operation is performed only if φw, φw/2, or φw/4 is selected as the operating clock. 4. The clock supplied to the LCD stops.

13.3.4 Boosting the LCD Drive Power Supply

When a large panel is driven, the on-chip power supply capacity may be insufficient. If the power supply capacity is insufficient when VCC is used as the power supply, the power supply impedance must be reduced. This can be done by connecting bypass capacitors of around 0.1 to 0.3 µF to pins V1 to V3, as shown in figure 13.9, or by adding a split-resistance externally. This LSI VCC VSS R R R R = several kΩ to several MΩ C = 0.1 to 0.3 μF R Figure 13.9 Connection of External Split-Resistance

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 431 of 658 REJ09B0042-0800 Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)

14.1 Overview

This LSI can include a power-on reset circuit and low-voltage detection circuit. The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect) and LVDR (reset by low voltage detect) circuits. This circuit is used to prevent abnormal operation (runaway execution) from occurring due to the power supply voltage fall and to recreate the state before the power supply voltage fall when the power supply voltage rises again. Even if the power supply voltage falls, the unstable state when the power supply voltage falls below the guaranteed operating voltage can be removed by entering standby mode * when exceeding the guaranteed operating voltage and during normal operation. Thus, system stability can be improved. If the power supply voltage falls more, the reset state is automatically entered. If the power supply voltage rises again, the reset state is held for a specified period, then active mode is automatically entered. Figure 14.1 is a block diagram of the power-on reset circuit and the low-voltage detection circuit. Note: * The voltage maintained in standby mode is the same as the RAM data retaining voltage RAM). See section 16.8.2, DC Characteristics, for information on retaining voltage.

14.1.1 Features

The features of the power-on reset circuit and low-voltage detection circuit are described below.

• Power-on reset circuit Uses an external capacitor to generate an internal reset signal when power is first supplied.
• Low-voltage detection circuit LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the voltage falls below a specified value. LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls below or rises above respective specified values. LVI0000A_000020030300

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 432 of 658 REJ09B0042-0800 Two pairs of detection levels for reset generation voltage are available: when only the LVDR circuit is used, or when the LVDI and LVDR circuits are both used. In addition, power supply rise/drop detection voltages and a detection voltage reference voltage may be input from an external source, allowing the detection level to be set freely by the user.

14.1.2 Block Diagram

A block diagram of the power-on reset circuit and low-voltage detection circuit are shown in figure 14.1. PSS: LVDCR: LVDSR: LVDRES: LVDINT: Vreset: Vint: extD: extU: Vref: Prescaler S Low-voltage-detection control register Low-voltage-detection status register Low-voltage-detection reset signal Low-voltage-detection interrupt signal Reset detection voltage Power-supply fall/rise detection voltage Power supply drop detection voltage input pin Power supply rise detection voltage input pin Reference voltage input pin RES φ CK R PSS Vcc R S Q OVF Vreset Vref extU extD Vint External reference voltage generator On-chip reference voltage generator [Legend] LVDRES Interrupt control circuit LVDCR LVDSR Internal reset signal Power-on reset circuit Low-voltage detection circuit Interrupt request LVDINT Noise canceler Noise canceler Ladder resistor External ladder resistor External power supply Internal data bus Figure 14.1 Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 433 of 658 REJ09B0042-0800

14.1.3 Pin Description

The pins of the power-on reset circuit and low-voltage detection circuit are listed in table 14.1. Table 14.1 Pin Description Pin Symbol I/O Function Low-voltage detection circuit reference voltage input pin Vref Input Reference voltage input for low- voltage detection circuit Low-voltage detection circuit power supply drop detection voltage input pin extD Input Power supply drop detection voltage input pin for low-voltage detection circuit Low-voltage detection circuit power supply rise detection voltage input pin extU Input Power supply rise detection voltage input pin for low-voltage detection circuit

14.1.4 Register Descriptions

The registers of the power-on reset circuit and low-voltage detection circuit are listed in table 14.2. Table 14.2 Register Descriptions Name Symbol R/W Initial Value Address Low-voltage detection control register LVDCR R/W H'00 H'FF86 Low-voltage detection status register LVDSR R/W H'00 H'FF87 Low-voltage detection counter LVDCNT R H'00 H'FFC3

14.2 Individual Register Descriptions

14.2.1 Low-Voltage Detectio n Control Register (LVDCR)

LVDE — VINTDSEL VINTUSEL LVDSEL LVDRE LVDDE LVDUE Initial value 0 * 0 0 0 0 * 0 * 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: * These bits are not initialized by resets trigged by LVDR. They are initialized by power-on resets and watchdog timer resets.

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 434 of 658 REJ09B0042-0800 LVDCR is an 8-bit read/write register. It is used to control whether or not the low-voltage detection circuit is used, settings for external input of power supply rise and drop detection voltages, the LVDR detection level setting, enabling or disabling of resets triggered by the low- voltage detection reset circuit (LVDR), and enabling or disabling of interrupts triggered by power supply voltage drops or rises. Bit 7—LVD Enable (LVDE) This bit is used to control whether or not the low-voltage detection circuit is used. Bit 7 LVDE

0 Low-voltage detection circuit not used (standby status) (initial value)

1 Low-voltage detection circuit used

Bit 6—Reserved This bit is a read/write enabled reserved bit. Bit 5—Power Supply Drop (LVDD) Detection Le vel External Input Select (VINTDSEL) This bit is used to select the power supply drop detection level. Bit 5 VINTDSEL

0 LVDD detection level generated by on-chip ladder resistor (initial value)

1 LVDD detection level input to extD pin

Bit 4—Power Supply Rise (LVDU) Detection Le vel External Input Select (VINTUSEL) This bit is used to select the power supply rise detection level. Bit 4 VINTUSEL

0 LVDU detection level generated by on-chip ladder resistor (initial value)

1 LVDU detection level input to extU pin

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 435 of 658 REJ09B0042-0800 Bit 3—LVDR Detection Level Select (LVDSEL) This bit is used to select the LVDR detection level. Select 2.3 V (typical) reset if voltage rise and drop detection interrupts are to be used. For reset detection only, Select 3.3 V (typical) reset. Bit 3 LVDSEL 0 Reset detection voltage 2.3 V (typ.) (initial value) 1 Reset detection voltage 3.3 V (typ.) Bit 2—LVDR Enable (LVDRE) This bit is used to control whether resets triggered by LVDR are enabled or disabled. Bit 2 LVDRE

0 LVDR resets disabled (initial value)

1 LVDR resets enabled

Bit 1—Voltage Drop Interrupt Enable (LVDDE) This bit is used to control whether voltage drop interrupt requests are enabled or disabled. Bit 1 LVDDE

0 Voltage drop interrupt requests disabled (initial value)

1 Voltage drop interrupt requests enabled

Bit 0—Voltage Rise Interrupt Enable (LVDUE) This bit is used to control whether voltage rise interrupt requests are enabled or disabled. Bit 0 LVDUE

0 Voltage rise interrupt requests disabled (initial value)

1 Voltage rise interrupt requests enabled

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 436 of 658 REJ09B0042-0800 Table 14.3 shows the relationship between LVDCR settings and function selections. Refer to table 14.3 when making settings to LVDCR. Table 14.3 LVDCR Settings and Function Selections LVDCR Setting Value LVDE LVDSEL LVDRE LVDDE LVDUE Power-on Reset Low-Voltage Detection Reset Low-Voltage Detection Voltage Drop Interrupt Low-Voltage Detection Voltage Rise Interrupt 1 1 1 0 0 — — 1 0 0 1 0 — — 1 0 0 1 1 — 1 0 1 1 1 Note: Setting values marked with an asterisk ( *) are invalid.

14.2.2 Low-Voltage Detection Status Register (LVDSR)

OVF — — — VREFSEL — LVDDF LVDUF Initial value 0 * 0 0 0 0 0 0 * 0 * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: * These bits initialized by resets trigged by LVDR. LVDSR is an 8-bit read/write register. It is used to control external input selection, indicates when the reference voltage is stable, and indicates if the power supply voltage goes below or above a specified range. Bit 7—LVD Reference Voltage Stabilized Flag (OVF) This bit indicates when the low-voltage detection counter (LVDCNT) overflows. Bit 7 OVF 0 [Clearing condition] (initial value) When 0 is written after reading 1 1 [Setting condition] When the low-voltage detection counter (LVDCNT) overflows

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 437 of 658 REJ09B0042-0800 Bits 6 to 4—Reserved These bits are read/write enabled reserved bits. Bit 3—Reference Voltage Extern al Input Select (VREFSEL) This bit is used to select the reference voltage. Bit 3 VREFSEL

0 The on-chip circuit is used to generate the reference voltage (initial value)

1 The reference voltage is input to the Vref pin from an external source

Bit 2—Reserved This bit is reserved. It is always read as 0 and cannot be written to. Bit 1—LVD Power Supply Voltage Drop Flag (LVDDF) This bit indicates when a power supply voltage drop has been detected. Bit 1 LVDDF 0 [Clearing condition] (initial value) When 0 is written after reading 1 1 [Setting condition] When the power supply voltage drops below Vint(D) Bit 0—LVD Power Supply Voltage Rise Flag (LVDUF) This bit indicates when a power supply voltage rise has been detected. Bit 0 LVDUF 0 [Clearing condition] When 0 is written after reading 1 (initial value) 1 [Setting condition] When the power supply voltage drops below Vint(D) while the LVDUE bit in LVDCR is set to 1, and it rises above Vint(U) before dropping below Vreset1

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 438 of 658 REJ09B0042-0800

14.2.3 Low-Voltage Detection Counter (LVDCNT)

CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R LVDCNT is a read-only 8-bit up-counter. Counting begins when 1 is written to LVDE. The counter increments using φ/4 as the clock source until it overflows by switching from H'FF to H'00, at which time the OVF bit in the LVDSR register is set to 1, indicating that the on-chip reference voltage generator has stabilized. If the LVD function is used, it is necessary to stand by until the counter has overflowed. The initial value of LVDCNT is H'00.

14.2.4 Clock Stop Register 2 (CKSTPR2)

LVDCKSTP — — PW2CKSTP AECKSTP WDCKST P PW1CKSTP LDCKSTP Initial value 1 1 1 1 1 1 1 1 Read/Write R/W — — R/W R/W R/W R/W R/W CKSTPR2 is an 8-bit read/write register. It is used to control the module’s module standby mode. Only the bits relevant to the LVD function are described in this section. Refer to the sections on the other modules for information about the other bits. Bit 7—LVD Module Standby Control (LVDCKSTP) This bit is used to control setting of the LVD function to module standby status and cancellation of that status. Bit 7 LVDCKSTP

0 Sets LVD to module standby status

1 Cancels LVD module standby status (initial value)

Note: This bit is implemented on the H8/38124 Group only. On other products it is always read as 1 and cannot be written to.

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 439 of 658 REJ09B0042-0800

14.3 Operation

14.3.1 Power-On Reset Circuit

Figure 14.2 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the on-chip pull-up resistor (typ. 100 kΩ). Since the state of the RES pin is transmitted within the chip, the prescaler S and the entire chip are in their reset states. When the level on the RES pin reaches the specified value, the prescaler S is released from its reset state and it starts counting. The OVF signal is generated to release the internal reset signal after the prescaler S has counted 131,072 clock (φ) cycles. The noise cancellation circuit of approximately 100 ns is incorporated to prevent the incorrect operation of the chip by noise on the RES pin. To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles within the specified time. The maximum time required for the power supply to rise and settle after power has been supplied (t PWON) is determined by the oscillation frequency (fOSC) and capacitance which is connected to RES pin (CRES). If tPWON means the time required to reach 90 % of power supply voltage, the power supply circuit should be designed to satisfy the following formula. tPWON (ms) ≤ 80 × CRES (μF) ± 10/fOSC (MHz) (tPWON ≤ 3000 ms, CRES ≥ 0.22 μF, and fOSC = 10 in 2-MHz to 10-MHz operation) Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a power-on reset may not occur.

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 440 of 658 REJ09B0042-0800 RES Vcc PSS-reset signal Internal reset signal Vss Vss OVF 131,072 cycles PSS counter starts Reset released tPWON Vpor Figure 14.2 Operational Timing of Power-On Reset Circuit

14.3.2 Low-Voltage Detection Circuit

LVDR (Reset by Low Voltage Detect) Circuit: Figure 14.3 shows the timing of the LVDR function. The LVDR enters the module-standby state after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait for 150 μs (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized, based on overflow of LVDNT, etc., then set the LVDRE bit in LVDCR to 1. After that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDRE bit should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and LVDRE bits must not be cleared to 0 simultaneously because incorrect operation may occur. When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.3 V), the LVDR clears the LVDRES signal to 0, and resets the prescaler S. The low-voltage detection reset state remains in place until a power-on reset is generated. When the power-supply voltage rises above the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock ( φ) cycles, and then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in LVDCR are not initialized. Note that if the power supply voltage (Vcc) falls below V LVDRmin = 1.0 V and then rises from that point, the low-voltage detection reset may not occur. If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 443 of 658 REJ09B0042-0800 LVDINTD extD input voltage extU input voltage Vreset1 Vexd (4) (3) (2) (1) VSS LVDINTU LVDDF IRQ0 interrupt generated IRQ0 interrupt generated LVDUF External power supply voltage Figure 14.5 Operational Timing of Low-Voltage Detection Interrupt Circuit (Using Pins Vref, extD, and extU)

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 445 of 658 REJ09B0042-0800 Resistance Value Calculation Table Ex. No Vref (V) R (k Ω) Vreset1 Vint(D) Vint(U) R1 (k Ω) R2 (k Ω) R3 (k Ω) 1 1.30 1000 2.5 2.7 2.9 517 33 450 2 1.41 1000 2.7 2.9 3 514 16 470 3 1.57 1000 3 3.2 3.5 511 42 447 4 2.09 1000 4 4.5 4.7 536 20 444 4. Using an error calculation table like the one shown below, plug in values for R1, R2, R3, and Vref to calculate the deviation of Vreset1, Vint(D), and Vint(U). Make sure to double check the maximum and minimum values for each value. Error Calculation Table Resistance Value Error (%) Vref (V) (kΩ) (kΩ) (kΩ) 5 Comparator Error (V) Vreset1 (V) Vint(D) (V) Vint(U) (V) 0 2.49 2.84 3.05 R1-Err, R2/R3+Err 0.1 2.59 2.66 2.85 0 2.49 2.56 2.75 R1/R2/R3 No Err 0.1 2.59 2.79 2.99 0 2.49 2.69 2.89 R1/R2+Err, R3-Err 0.1 2.59 2.93 3.16 0 2.49 2.83 3.06 R1/R2-Err, R3+Err 0.1 2.59 2.67 2.84 0 2.49 2.57 2.74

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 446 of 658 REJ09B0042-0800 Operation and Cancellation Setting Procedure Using LVDR and LVDI: Settings should be made as indicated below in order to ensure proper operation of the low voltage detection circuit or to cancel operation. Figure 14.7 shows the setting timing for low voltage detection circuit operation and cancellation. 1. To turn on the low voltage detection circuit, first set the LVDE bit in LVDCR to 1. 2. After waiting for LVDCNT overflow, etc., to ensure that the stabilization time (t LVDON = 150 μs) for the reference voltage and low voltage detection power supply has elapsed, clear bits LVDDF and LVDUF in LVDSR to 0. If necessary, set the LVDRE, LVDDE, and LVDUE bits in LVDCR to 1. 3. To cancel operation of the low voltage detection circuit, clear bits LVDRE, LVDDE, and LVDUE to 0, then clear bit LVDE to 0. Bit LVDE should not be cleared at the same time as bits LVDRE, LVDDE, and LVDUE to avoid malfunction. LVDRE LVDDE LVDUE tLVDON LVDE Figure 14.7 Low Voltage Detection Circuit Operation and Cancellation Setting Timing

Section 15 Power Supply Circuit (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 447 of 658 REJ09B0042-0800 Section 15 Power Supply Circuit (H8/38124 Group Only) This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the internal voltage will be practically the same as the external voltage. It is, of course, also possible to use the same level of external power supply voltage and internal power supply voltage without using the internal power supply step-down circuit.

15.1 When Using Internal Pow er Supply Step-Down Circuit

Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1 µF between CVCC and VSS, as shown in figure 15.1. The internal step-down circuit is made effective simply by adding this external circuit. In the external circuit interface, the external power supply voltage connected to V CC and the GND potential connected to VSS are the reference levels. For example, for port input/output levels, the VCC level is the reference for the high level, and the VSS level is that for the low level. The A/D converter analog power supply is not affected by the internal step-down circuit. CVCC VSS Internal logic Step-down circuit Internal power supply Stabilization capacitance (approx. 0.1 µF) VCC VCC = 2.7 to 5.5 V Figure 15.1 Power Supply Connection when Internal Step-Down Circuit is Used PSCKT00A_000020020200

Section 15 Power Supply Circuit (H8/38124 Group Only) Rev. 8.00 Mar. 09, 2010 Page 448 of 658 REJ09B0042-0800

15.2 When Not Using Internal Power Supply Step-Down Circuit

When the internal power supply step-down circuit is not used, connect the external power supply to the CVCC pin and VCC pin, as shown in figure 15.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 2.7 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input. CVCC VSS Internal logic Step-down circuit Internal power supply VCC VCC = 2.7 to 3.6 V Figure 15.2 Power Supply Connection when Internal Step-Down Circuit is Not Used

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 449 of 658 REJ09B0042-0800 Section 16 Electrical Characteristics

16.1 H8/38024 Group ZTAT Version and Mask ROM Version Absolute

Table 16.1 lists the absolute maximum ratings. Table 16.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage V CC –0.3 to +7.0 V * Analog power supply voltage AV CC –0.3 to +7.0 V Programming voltage V PP –0.3 to +13.0 V Input voltage Ports other than Port B and IRQAEC Vin –0.3 to V CC +0.3 V Port B AV in –0.3 to AV CC +0.3 V IRQAEC HV in –0.3 to +7.3 V Port 9 pin voltage V P9 –0.3 to +7.3 V Operating temperature T opr –20 to +75 (regular specifications) –40 to +85 (wide-range specifications) Storage temperature T stg –55 to +125 °C Note: * Permanent damage may occur to the chip if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 450 of 658 REJ09B0042-0800

16.2 H8/38024 Group ZTAT Version and Mask ROM Version Electrical

16.2.1 Power Supply Voltage and Operating Range

The power supply voltage and operating range are indicated by the shaded region in the figures. Power Supply Voltage and Oscillator Frequency Range 38.4 1.8 3.0 5.5 VCC (V) fW (kHz)

• All operating Note: 2. When an oscillator is used for the subclock, hold V CC at 2.2 V to 5.5 V from power-on until the oscillation settling time has elapsed. 32.768 4.5 16.0 2.0 10.0 4.0 1.8 2.7 4.5 5.5 VCC (V) fosc (MHz)  Active (high-speed) mode  Sleep (high-speed) mode Note: 1. The fosc values are those when an oscillator is used; when an external clock is used the minimum value of fosc is 1 MHz.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 451 of 658 REJ09B0042-0800 Power Supply Voltage and Operating Frequency Range  Subactive mode  Subsleep mode (except CPU)  Watch mode (except CPU) 16.384 8.192 4.096 1.8 3.6 5.5 VCC (V) φSUB (kHz) 19.2 9.6 4.8 8.0 (0.5) 5.0 2.0 1.0 1.8 2.7 4.5 5.5 VCC (V) φ (MHz) 1000 (7.8125) 625 250 15.625 1.8 2.7 4.5 5.5 VCC (V) φ (kHz) Note: 1. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 1 MHz. Note: 2. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 15.625 kHz.  Active (high-speed) mode  Sleep (high-speed) mode (except CPU)  Active (medium-speed) mode  Sleep (medium-speed) mode (except A/D converter)

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 452 of 658 REJ09B0042-0800 Analog Power Supply Voltage and A/D Converter Operating Range φ (MHz) (0.5) 5.0 1.0 1.8 2.7 4.5 5.5 AVCC (V) φ (kHz) 500 1000 625 1.8 2.7 4.5 5.5 AVCC (V)  Active (medium-speed) mode  Sleep (medium-speed) mode  Active (high-speed) mode  Sleep (high-speed) mode Note: 3. When AV CC = 1.8 V to 2.7 V, the operating range is limited to φ = 1.0 MHz when using an oscillator, and is φ = 0.5 MHz to 1.0 MHz when using an external clock.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 453 of 658 REJ09B0042-0800

16.2.2 DC Characteristics

Table 16.2 lists the DC characteristics of the H8/38024. Table 16.2 DC Characteristics specifications), Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) (including subactive mode) unless otherwise indicated. Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes VIH 0.8 V CC — V CC + 0.3 V V CC = 4.0 V to 5.5 V Input high voltage RES, WKP0 to WKP7, IRQ0, IRQ3, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK32 0.9 VCC — V CC + 0.3 Except the above IRQ1 0.8 V CC — AV CC + 0.3 V V CC = 4.0 V to 5.5 V 0.9 V CC — AV CC + 0.3 Except the above RXD 32, UD 0.7 V CC — V CC + 0.3 V V CC = 4.0 V to 5.5 V 0.8 V CC — V CC + 0.3 Except the above OSC 1 0.8 V CC — V CC + 0.3 V V CC = 4.0 V to 5.5 V 0.9 V CC — V CC + 0.3 Except the above X 1 0.9 V CC — V CC + 0.3 V V CC = 1.8 V to 5.5 V 0.7 V CC — V CC + 0.3 V CC = 4.0 V to 5.5 V P13, P14, P16, P17, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 0.8 VCC — V CC + 0.3 V Except the above PB 0 to PB7 0.7 V CC — AV CC + 0.3 V V CC = 4.0 V to 5.5 V 0.8 V CC — AV CC + 0.3 Except the above IRQAEC 0.8 V CC — 7.3 V V CC = 4.0 V to 5.5 V 0.9 V CC — 7.3 Except the above

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 454 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes VIL –0.3 — 0.2 V CC V V CC = 4.0 V to 5.5 V Input low voltage RES, WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK –0.3 — 0.1 V CC Except the above RXD 32, UD –0.3 — 0.3 V CC V V CC = 4.0 V to 5.5 V –0.3 — 0.2 V CC Except the above OSC 1 –0.3 — 0.2 V CC V V CC = 4.0 V to 5.5 V –0.3 — 0.1 V CC Except the above X 1 –0.3 — 0.1 V CC V V CC = 1.8 V to 5.5 V –0.3 — 0.3 V CC V V CC = 4.0 V to 5.5 V P13, P14, P16, P17, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PB0 to PB7 –0.3 — 0.2 V CC Except the above Output high voltage VOH V CC – 1.0 — — V V CC = 4.0 V to 5.5 V –IOH = 1.0 mA V CC – 0.5 — — V CC = 4.0 V to 5.5 V –IOH = 0.5 mA P13, P14, P16, P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 VCC – 0.3 — — –I OH = 0.1 mA

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 455 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Output low voltage VOL — — 0.6 V V CC = 4.0 V to 5.5 V IOL = 1.6 mA P13, P14, P16, P17, P40 to P42 — — 0.5 I OL = 0.4 mA P5 0 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 — — 0.5 I OL = 0.4 mA P3 0 to P37 — — 1.5 V CC = 4.0 V to 5.5 V IOL = 10 mA — — 0.6 V CC = 4.0 V to 5.5 V IOL = 1.6 mA — — 0.5 I OL = 0.4 mA P9 0 to P92 — — 0.5 V CC = 2.2 to 5.5 V IOL = 25 mA I OL = 15 mA — — 0.5 I OL = 10 mA *6 P9 3 to P95 — — 0.5 I OL = 10 mA | IIL | RES, P43 — — 20.0 µA *2 — — 1.0 VIN = 0.5 V to VCC – 0.5 V *1 Input/output leakage current OSC 1, X1, P13, P14, P16, P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, IRQAEC, 0 to P95, PA0 to PA3 — — 1.0 µA V IN = 0.5 V to VCC – 0.5 V PB 0 to PB7 — — 1.0 V IN = 0.5 V to AVCC – 0.5 V

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 456 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Pull-up MOS current –Ip 50.0 — 300.0 µA V CC = 5 V, VIN = 0 V P13, P14, P16, P17, P30 to P37, P50 to P57, P60 to P67 VIN = 0 V Reference value Input capacitance C IN All input pins except power supply, RES, P43, PB0 to PB7 — — 15.0 pF f = 1 MHz, VIN =0 V, Ta = 25°C IRQAEC — — 30.0 RES — — 80.0 *2 — — 15.0 *1 P4 3 — — 50.0 *2 — — 15.0 *1 PB 0 to PB7 — — 15.0 IOPE1 V CC — 7.0 10.0 mA Active (high-speed) mode VCC = 5 V, fOSC = 10 MHz Active mode current dissipation IOPE2 V CC — 2.2 3.0 mA Active (medium- speed) mode VCC = 5 V, fOSC = 10 MHz φosc/128 Sleep mode current dissipation ISLEEP V CC — 3.8 5.0 mA V CC=5 V, fOSC=10 MHz Subactive mode current dissipation I SUB V CC — 15.0 30.0 µA V CC = 2.7 V, LCD on 32 kHz crystal oscillator SUB=φw/2) — 8.0 — µA V CC = 2.7 V, LCD on 32 kHz crystal oscillator SUB=φw/8) Reference value Subsleep mode current dissipation I SUBSP V CC — 7.5 16.0 µA V CC = 2.7 V, LCD on 32 kHz crystal oscillator SUB=φw/2)

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 457 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Watch mode current dissipation IWATCH V CC — 3.8 6.0 µA V CC = 2.7 V, 32 kHz crystal oscillator LCD not used 2.8 6.0 *1 Standby mode current dissipation I STBY V CC — 1.0 5.0 µA 32 kHz crystal oscillator not used RAM data retaining voltage VRAM V CC 1.5 — — V IOL Output pins except port 3 and 9 — — 2.0 mA V CC = 4.0 V to 5.5 V Port 3 — — 10.0 V CC = 4.0 V to 5.5 V Allowable output low current (per pin) Output pins except port 9 — — 0.5 P9 0 to P92 — — 25.0 V CC = 2.2 V to 5.5 V *5 — — 15.0 — — 10.0 P9 3 to P95 — — 10.0 ∑ IOL Output pins except ports 3 and 9 — — 40.0 mA V CC = 4.0 V to 5.5 V Allowable output low current (total) Port 3 — — 80.0 V CC = 4.0 V to 5.5 V Output pins except port 9 — — 20.0 Port 9 — — 80.0 –IOH All output pins — — 2.0 mA V CC = 4.0 V to 5.5 V Allowable output high current (per pin) — — 0.2 Except the above

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 458 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes ∑ – IOH All output pins — — 15.0 mA V CC = 4.0 V to 5.5 V Allowable output high current (total) — — 10.0 Except the above Notes: Connect the TEST pin to V SS. 1. Applies to the Mask ROM products. 2. Applies to the HD64738024. 3. Pin states during current measurement. Mode RES Pin Internal State Other Pins LCD Power Supply Oscillator Pins Active (high-speed) mode (IOPE1) VCC Operates V CC Halted Active (medium- speed) mode (IOPE2) Sleep mode V CC Only timers operate V CC Halted System clock oscillator: crystal Subclock oscillator: Pin X1 = GND Subactive mode V CC Operates V CC Halted Subsleep mode V CC Only timers operate, CPU stops VCC Halted Watch mode V CC Only time base operates, CPU stops VCC Halted System clock oscillator: crystal Subclock oscillator: crystal Standby mode V CC CPU and timers both stop VCC Halted System clock oscillator: crystal Subclock oscillator: Pin X1 = GND 4. Excludes current in pull-up MOS transistors and output buffers. 5. When the PIOFF bit in the port mode register 9 is 0. 6. When the PIOFF bit in the port mode register 9 is 1.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 459 of 658 REJ09B0042-0800

16.2.3 AC Characteristics

Table 16.3 lists the control signal timing, and tables 16.4 lists the serial interface timing of the H8/38024. Table 16.3 Control Signal Timing specifications), Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) (including subactive mode) unless otherwise indicated. Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure fOSC OSC 1, OSC2 2.0 — 16.0 MHz V CC = 4.5 V to 5.5 V 2.0 — 10.0 V CC = 2.7 V to 5.5 V System clock oscillation frequency 2.0 — 4.0 Except the above OSC clock (φOSC) cycle time tOSC OSC 1, OSC2 62.5 — 500 (1000) ns V CC = 4.5 V to 5.5 V Figure 16.2 100 — 500 (1000) V CC = 2.7 V to 5.5 V 250 — 500 (1000) Except the above tcyc 2 — 128 t OSC System clock (φ) cycle time — — 128 µs Subclock oscillation frequency fW X 1, X2 — 32.768 or 38.4 — kHz Watch clock (φW) cycle time tW X 1, X2 — 30.5 or 26.0 — µs Figure 16.2 Subclock (φSUB) cycle time tsubcyc 2 — 8 t W *1 Instruction cycle time 2 — — t cyc tsubcyc Oscillation stabilization time trc OSC 1, OSC2 — 20 45 µs Figure 16.9 VCC = 2.2 V to 5.5 V Figure 16.9 — — 50 ms Except the above X 1, X2 — — 2.0 s V CC = 2.7 V to 5.5 V *3 — — 10.0 V CC = 2.2 V to 5.5 V

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 461 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure UD pin minimum transition width tUDH tUDL UD 4 — — t cyc tsubcyc Figure 16.7 Notes: 1. Selected with SA1 and SA0 of system control register 2 (SYSCR2). 2. The figure in parentheses applies when an external clock is used. 3. After powering on, hold V CC at 2.2 V to 5.5 V until the chip's oscillation settling time has elapsed. Table 16.4 Serial Interface (SCI3) Timing specifications), Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) (including subactive mode) unless otherwise indicated. Values Item Symbol Min Typ Max Unit Test Conditions Reference Figure Asynchronous t scyc 4 — — t cyc or Figure 16.5 Input clock cycle Synchronous 6 — — t subcyc Input clock pulse width t SCKW 0.4 — 0.6 t scyc Figure 16.5 tTXD — — 1 t cyc or V CC = 4.0 V to 5.5 V Figure 16.6 Transmit data delay time (synchronous) — — 1 t subcyc Except the above tRXS 200.0 — — ns V CC = 4.0 V to 5.5 V Figure 16.6 Receive data setup time (synchronous) 400.0 — — Except the above Figure 16.6 tRXH 200.0 — — ns V CC = 4.0 V to 5.5 V Figure 16.6 Receive data hold time (synchronous) 400.0 — — Except the above Figure 16.6

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 462 of 658 REJ09B0042-0800

16.2.4 A/D Converter Characteristics

Table 16.5 shows the A/D converter characteristics of the H8/38024. Table 16.5 A/D Converter Characteristics VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) unless otherwise indicated. Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure Analog power supply voltage AVCC AV CC 1.8 — 5.5 V *1 Analog input voltage AVIN AN 0 to AN7 – 0.3 — AV CC + 0.3 V AIOPE AV CC — — 1.5 mA AV CC = 5.0 V Analog power supply current AISTOP1 AV CC — 600 — µA *2 Reference value AI STOP2 AV CC — — 5 µA *3 Analog input capacitance CAIN AN 0 to AN7 — — 15.0 pF Allowable signal source impedance RAIN — — 10.0 k Ω Resolution (data length) — — 10 bit Nonlinearity error — — ±2.5 LSB AV CC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V — — ±5.5 AV CC = 2.0 V to 5.5 V VCC = 2.0 V to 5.5 V — — ±7.5 Except the above *4 Quantization error — — ±0.5 LSB

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 463 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure Absolute accuracy — — ±3.0 LSB AV CC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V — — ±6.0 AV CC = 2.0 V to 5.5 V VCC = 2.0 V to 5.5 V — — ±8.0 Except the above *4 Conversion time 12.4 — 124 µs AV CC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V 62 — 124 Except the above Notes: 1. Set AV CC = VCC when the A/D converter is not used. 2. AI STOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AI STOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle. 4. Conversion time 62 µs

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 464 of 658 REJ09B0042-0800

16.2.5 LCD Characteristics

Table 16.6 shows the LCD characteristics. Table 16.6 LCD Characteristics specifications), Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) (including subactive mode) unless otherwise specified. Values Item Symbol Applicable Pins Min Typ Max Unit Test Conditions Reference Figure Segment driver drop voltage VDS SEG 1 to SEG32 — — 0.6 V I D = 2 µA V1 = 2.7 V to 5.5 V Common driver drop voltage V DC COM 1 to COM4 — — 0.3 V I D = 2 µA V1 = 2.7 V to 5.5 V LCD power supply split-resistance R LCD 0.5 3.0 9.0 M Ω Between V 1 and VSS Liquid crystal display voltage V LCD V 1 2.2 — 5.5 V * 2 Notes: 1. The voltage drop from power supply pins V 1, V2, V3, and VSS to each segment pin or common pin. 2. When the liquid crystal display voltage is supplied from an external power source, ensure that the following relationship is maintained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 465 of 658 REJ09B0042-0800

16.3 H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT

Version Absolute Maximum Ratings Table 16.7 lists the absolute maximum ratings. Table 16.7 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage V CC –0.3 to +4.3 V *1 Analog power supply voltage AV CC –0.3 to +4.3 V Input voltage Ports other than Port B and IRQAEC Vin –0.3 to V CC +0.3 V Port B AV in –0.3 to AV CC +0.3 V IRQAEC HV in –0.3 to +7.3 V Port 9 pin voltage V P9 –0.3 to +7.3 V Operating temperature T opr –20 to +75 *2 (regular specifications) –40 to +85 *2 (wide-range specifications) +75 (products shipped as chips)* Storage temperature T stg –55 to +125 °C Notes: 1. Permanent damage may occur to the chip if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 2. The operating temperature ranges for flash memory programming/erasing are Ta = –20°C to +75°C. 3. Power may be applied when the temperature is between –20 °C and +75°C.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 466 of 658 REJ09B0042-0800

16.4 H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT

Version Electrical Characteristics

16.4.1 Power Supply Voltage and Operating Range

The power supply voltage and operating range are indicated by the shaded region in the figures. Power Supply Voltage and Oscillator Frequency Range 38.4 2.7 3.6 VCC (V) fW (kHz)  All operating 32.768 2.0 10.0 2.7 3.6 VCC (V) fosc (MHz)  Active (high-speed) mode  Sleep (high-speed) mode Note: The fosc values are those when an oscillator is used; when an external clock is used the minimum value of fosc is 1 MHz.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 467 of 658 REJ09B0042-0800 Power Supply Voltage and Operating Frequency Range  Subactive mode  Subsleep mode (except CPU)  Watch mode (except CPU) 16.384 8.192 4.096 2.7 3.6 VCC (V) φSUB (kHz) 19.2 9.6 4.8 (0.5) 5.0 1.0 2.7 3.6 VCC (V) φ (MHz) (7.8125) 625 15.625 2.7 3.6 VCC (V) φ (kHz) Note: 1. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 1 MHz. Note: 2. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 15.625 kHz.  Active (high-speed) mode  Sleep (high-speed) mode (except CPU)  Active (medium-speed) mode  Sleep (medium-speed) mode (except A/D converter)

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 468 of 658 REJ09B0042-0800 Analog Power Supply Voltage and A/D Converter Operating Range φ (MHz) (0.5) 5.0 1.0 2.7 3.6 AVCC (V) φ (kHz)500 625 2.7 3.6 AVCC (V)  Active (medium-speed) mode  Sleep (medium-speed) mode  Active (high-speed) mode  Sleep (high-speed) mode

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 469 of 658 REJ09B0042-0800

16.4.2 DC Characteristics

Table 16.8 lists the DC characteristics of the HD64F38024 and HD64F38024R. Table 16.8 DC Characteristics Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Input high voltage VIH RES, WKP0 to WKP7, IRQ0, IRQ3, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK32 0.9 VCC — V CC + 0.3 V IRQ1 0.9 VCC — AV CC + 0.3 V RXD 32, UD 0.8 V CC — V CC + 0.3 V OSC 1 0.9 V CC — V CC + 0.3 V X 1 0.9 V CC — V CC + 0.3 V P1 3, P14, P16, P17, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 0.8 VCC — V CC + 0.3 V PB 0 to PB7 0.8 V CC — AV CC + 0.3 V IRQAEC, P9 5*5 0.9 V CC — 7.3 V

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 470 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Input low voltage VIL RES, WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, P95*5, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK32 –0.3 — 0.1 V CC V RXD 32, UD –0.3 — 0.2 V CC V OSC 1 –0.3 — 0.1 V CC V X 1 –0.3 — 0.1 V CC V P1 3, P14, P16, P17, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PB0 to PB7 –0.3 — 0.2 V CC V VCC – 1.0 — — V –I OH = 1.0 mA Output high voltage VOH P1 3, P14, P16, P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 VCC – 0.3 — — –I OH = 0.1 mA

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 471 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Output low voltage VOL P1 3, P14, P16, P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 — — 0.5 V I OL = 0.4 mA P9 0 to P92 — — 0.5 V I OL = 25 mA *1 I OL = 10 mA *2 P9 3 to P95 — — 0.5 V I OL = 10 mA Input/output leakage current | IIL | RES, P43, OSC1, X1, P13, P14, P16, P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, IRQAEC, 0 to P95, PA0 to PA3 — — 1.0 µA V IN = 0.5 V to VCC – 0.5 V PB 0 to PB7 — — 1.0 µA V IN = 0.5 V to AVCC – 0.5 V Pull-up MOS current p P1 3, P14, P16, P17, P30 to P37, P50 to P57, P60 to P67 30 — 180 µA V CC = 3 V, VIN = 0 V Input capacitance CIN All input pins except power supply and IRQAEC — — 15.0 pF f = 1 MHz, V IN =0 V, Ta = 25°C IRQAEC — — 30.0 pF

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 472 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Active mode current dissipation IOPE1 V CC — 1.2 — mA Active (high-speed) mode VCC = 3 V, fOSC = 2 MHz Max. guideline = 1.1 × typ. — 1.8 — mA Active (high-speed) mode VCC = 3 V, fOSC = 4 MHz Max. guideline = 1.1 × typ. — 4.0 6.0 mA Active (high-speed) mode V CC = 3 V, fOSC = 10 MHz I OPE2 V CC — 0.7 — mA Active (medium- speed) mode VCC = 3 V, fOSC = 2 MHz φosc/128 Max. guideline = 1.1 × typ. — 0.8 — mA Active (medium- speed) mode V CC = 3 V, fOSC = 4 MHz φosc/128 Max. guideline = 1.1 × typ. — 1.2 1.8 mA Active (medium- speed) mode VCC = 3 V, fOSC = 10 MHz φosc/128

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 473 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes ISLEEP V CC — 1.0 — mA V CC= 3 V, fOSC= 2 MHz Max. guideline = 1.1 × typ. Sleep mode current dissipation — 1.5 — mA V CC= 3 V, fOSC= 4 MHz Max. guideline = 1.1 × typ. — 3.2 4.8 mA V CC= 3 V, fOSC= 10 MHz Subactive mode current dissipation I SUB V CC — 10 — µA V CC = 2.7 V, LCD on 32 kHz crystal resonator SUB=φw/8) Reference value — 20 40 µA V CC = 2.7 V, LCD on 32 kHz External Clock SUB=φw/2) — 17 40 µA V CC = 2.7 V, LCD on 32 kHz crystal resonator SUB=φw/2) Subsleep mode current dissipation I SUBSP V CC — 4.8 16.0 µA V CC = 2.7 V, LCD on 32 kHz External Clock SUB=φw/2) — 5.4 16.0 µA V CC = 2.7 V, LCD on 32 kHz crystal resonator (φSUB=φw/2)

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 474 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Watch mode current dissipation IWATCH V CC — 2.0 — µA V CC = 2.7 V, Ta = 25°C 32 kHz External Clock LCD not used Reference value — 2.6 — µA V CC = 2.7 V, Ta = 25°C 32 kHz crystal resonator LCD not used — 2.0 6.0 µA V CC = 2.7 V, 32 kHz External Clock LCD not used — 2.6 6.0 µA V CC = 2.7 V, 32 kHz crystal resonator LCD not used Standby mode current dissipation ISTBY V CC — 0.3 — µA V CC = 3.0 V, Ta = 25°C 32 kHz crystal resonator not used Reference value — 1.0 5.0 µA 32 kHz crystal resonator not used RAM data retaining voltage VRAM V CC 2.0 — — V IOL Output pins except port 9 — — 0.5 mA Allowable output low current (per pin) 0 to P92 — — 25.0 mA *1 — — 10.0 *2 P9 3 to P95 — — 10.0 mA *5 ∑ IOL Output pins except port 9 — — 20.0 mA Allowable output low current (total) Port 9 — — 80.0 mA

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 475 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Allowable output high current (per pin) –IOH All output pins — — 0.2 mA Allowable output high current (total) ∑ – I OH All output pins — — 10.0 mA Notes: Connect the TEST pin to V SS. 1. Applied when the PIOFF bit in the port mode register 9 is 0. 2. Applied when the PIOFF bit in the port mode register 9 is 1. 3. Pin states during current measurement. Mode RES Pin Internal State Other Pins LCD Power Supply Oscillator Pins Active (high-speed) mode (IOPE1) VCC Operates V CC Halted Active (medium- speed) mode (IOPE2) Sleep mode V CC Only on-chip timers operate VCC Halted System clock oscillator: crystal Subclock oscillator: Pin X1 = GND Subactive mode V CC Operates V CC Halted Subsleep mode V CC Only on-chip timers operate, CPU stops VCC Halted Watch mode V CC Only time base operates, CPU stops VCC Halted System clock oscillator: crystal Subclock oscillator: crystal Standby mode V CC CPU and timers both stop VCC Halted System clock oscillator: crystal Subclock oscillator: Pin X1 = GND 4. Excludes current in pull-up MOS transistors and output buffers. 5. Used for the judgment of user mode or boot mode when the reset is released.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 476 of 658 REJ09B0042-0800

16.4.3 AC Characteristics

Table 16.9 lists the control signal timing, and tables 16.10 lists the serial interface timing of the H8/38024F. Table 16.9 Control Signal Timing Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure System clock oscillation frequency fOSC OSC 1, OSC2 2.0 — 10.0 MHz OSC clock (φOSC) cycle time tOSC OSC 1, OSC2 100 — 500 (1000) ns Figure 16.2 tcyc 2 — 128 t OSC System clock (φ) cycle time — — 128 µs Subclock oscillation frequency fW X 1, X2 — 32.768 or 38.4 — kHz Watch clock (φW) cycle time tW X 1, X2 — 30.5 or 26.0 — µs Figure 16.2 Subclock (φSUB) cycle time tsubcyc 2 — 8 t W *1 Instruction cycle time 2 — — t cyc tsubcyc Oscillation stabilization time t rc OSC 1, OSC2 — 0.8 2.0 ms Figure 16.10 (crystal oscillator) Figure 16.10 — 2.0 6.0 ms Figure 16.9 (crystal oscillator) Figure 16.9 — 20 45 µs Figure 16.10 (ceramic oscillator) Figure 16.10 — 20 45 µs Figure 16.9 (ceramic oscillator) Figure 16.9 — — 50 ms Except the above X 1, X2 — — 2.0 s

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 478 of 658 REJ09B0042-0800 Table 16.10 Serial Interface (SCI3) Timing Values Item Symbol Min Typ Max Unit Test Conditions Reference Figure Asynchronous t scyc 4 — — t cyc or Figure 16.5 Input clock cycle Synchronous 6 — — t subcyc Input clock pulse width t SCKW 0.4 — 0.6 t scyc Figure 16.5 Transmit data delay time (synchronous) tTXD — — 1 t cyc or tsubcyc Figure 16.6 Receive data setup time (synchronous) tRXS 400.0 — — ns Figure 16.6 Receive data hold time (synchronous) tRXH 400.0 — — ns Figure 16.6

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 479 of 658 REJ09B0042-0800

16.4.4 A/D Converter Characteristics

Table 16.11 shows the A/D converter characteristics of the H8/38024F. Table 16.11 A/D Converter Characteristics VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure Analog power supply voltage AVCC AV CC 2.7 — 3.6 V *1 Analog input voltage AVIN AN 0 to AN7 – 0.3 — AV CC + 0.3 V AIOPE AV CC — — 1.0 mA AV CC = 3.0 V Analog power supply current AISTOP1 AV CC — 600 — µA *2 Reference value AI STOP2 AV CC — — 5 µA *3 Analog input capacitance CAIN AN 0 to AN7 — — 15.0 pF Allowable signal source impedance R AIN — — 10.0 k Ω Resolution (data length) — — 10 bit Nonlinearity error — — ±3.5 LSB AV CC = 2.7 V to 3.6 V Quantization error — — ±0.5 LSB Absolute accuracy — ±2.0 ±4.0 LSB AV CC = 2.7 V to 3.6 V Conversion time 12.4 — 124 µs AV CC = 2.7 V to 3.6 V Notes: 1. Set AV CC = VCC when the A/D converter is not used. 2. AI STOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AI STOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 480 of 658 REJ09B0042-0800

16.4.5 LCD Characteristics

Table 16.12 shows the LCD characteristics. Table 16.12 LCD Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Conditions Reference Figure Segment driver drop voltage VDS SEG 1 to SEG32 — — 0.6 V I D = 2 µA V1 = 2.7 V to 3.6 V Common driver drop voltage VDC COM 1 to COM4 — — 0.3 V I D = 2 µA V1 = 2.7 V to 3.6 V RLCD 0.5 3.0 9.0 M Ω *3 LCD power supply split-resistance 1.5 3.0 7.0 Between V1 and VSS *4 Liquid crystal display voltage VLCD V 1 2.2 — 3.6 V * 2 Notes: 1. The voltage drop from power supply pins V 1, V2, V3, and VSS to each segment pin or common pin. 2. When the liquid crystal display voltage is supplied from an external power source, ensure that the following relationship is maintained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS. 3. Applies to the HD64F38024. 4. Applies to the HD64F38024R.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 481 of 658 REJ09B0042-0800

16.4.6 Flash Memory Characteristics

Table 16.13 lists the flash memory characteristics. Table 16.13 Flash Memory Characteristics reading), VCC = 3.0 V to 3.6 V (operating voltage range in programming/erasing), Ta = –20 to +75°C (operating temperature range in programming/erasing) Values Item Symbol Min Typ Max Unit Test Condition Programming time (per 128 bytes)*1 *2 *4 t P — 7 200 ms Erase time (per block) *1 *3 *6 t E — 100 1200 ms Maximum number of reprogrammings N WEC 1000 *8 *11 10000 — Times 100 *8 *12 10000 Data retention time t DRP 10 *10 — — Years Programming Wait time after SWE bit setting *1 x 1 — — µs Wait time after PSU bit setting *1 y 50 — — µs Wait time after P bit setting *1 *4 z1 28 30 32 µs 1 ≤ n ≤ 6 z2 198 200 202 µs 7 ≤ n ≤ 1000 z3 8 10 12 µs Additional- programming Wait time after P bit clear *1 α 5 — — µs Wait time after PSU bit clear *1 β 5 — — µs Wait time after PV bit setting *1 γ 4 — — µs Wait time after dummy write *1 ε 2 — — µs Wait time after PV bit clear *1 η 2 — — µs Wait time after SWE bit clear *1 θ 100 — — µs Maximum programming count *1 *4 *5 N — — 1000 Times Erase Wait time after SWE bit setting *1 x 1 — — µs Wait time after ESU bit setting *1 y 100 — — µs Wait time after E bit setting *1 *6 z 10 — 100 ms Wait time after E bit clear *1 α 10 — — µs Wait time after ESU bit clear *1 β 10 — — µs Wait time after EV bit setting *1 γ 20 — — µs Wait time after dummy write *1 ε 2 — — µs Wait time after EV bit clear *1 η 4 — — µs Wait time after SWE bit clear *1 θ 100 — — µs Maximum erase count *1 *6 *7 N — — 120 Times

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 482 of 658 REJ09B0042-0800 Notes: 1. Make the time settings in accordance with the program/erase algorithms. 2. The programming time for 128 bytes. (Indicates the total time for which the P bit in flash memory control register 1 (FLMCR1) is set. The program-verify time is not included.) 3. The time required to erase one block. (Indicates the time for which the E bit in flash memory control register 1 (FLMCR1) is set. The erase-verify time is not included.) 4. Programming time maximum value (t P(MAX)) = wait time after P bit setting (z) × maximum number of writes (N) 5. Set the maximum number of writes (N) according to the actual set values of z1, z2, and z3, so that it does not exceed the programming time maximum value (tP(MAX)). The wait time after P bit setting (z1, z2) should be changed as follows according to the value of the number of writes (n). Number of writes (n) 1 ≤ n ≤ 6 z1 = 30 µs 7 ≤ n ≤ 1000 z2 = 200 µs 6. Erase time maximum value (t E(max)) = wait time after E bit setting (z) × maximum number of erases (N) 7. Set the maximum number of erases (N) according to the actual set value of (z), so that it does not exceed the erase time maximum value (tE(max)). 8. The minimum number of times all characteristics are guaranteed following reprogramming. (The guarantee covers the range from 1 to the minimum value.) 9. Reference value at 25°C. (Guideline showing number of reprogrammings over which functioning will be retained under normal circumstances.) 10. Data retention characteristics within the range indicated in the specifications, including the minimum value for reprogrammings. 11. Applies to an operating voltage range when reading data of 3.0 to 3.6 V. 12. Applies to an operating voltage range when reading data of 2.7 to 3.6 V.

16.4.7 Power Supply Characteristics

Table 16.14 Power Supply Characteristics Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes Power supply startup voltage V CCSTART V CC 0 — 0.1 V *1*2 Power supply startup slope SV CC V CC 0.05 — — V/ms Notes: 1. This LSI may not start normally when it starts with the condition beyond specification shown in above (Refer to figure 16.1 for power supply voltage startup time.). 2. Applies to the F-ZTAT version.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 483 of 658 REJ09B0042-0800

16.5 H8/38024S Group Mask ROM Vers ion Absolute Maximum Ratings

Table 16.15 lists the absolute maximum ratings. Table 16.15 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage V CC –0.3 to +4.3 V *1 Analog power supply voltage AV CC –0.3 to +4.3 V Input voltage Ports other than Port B V in –0.3 to V CC +0.3 V Port B AV in –0.3 to AV CC +0.3 V Port 9 pin voltage V P9 –0.3 to V CC +0.3 V Operating temperature T opr –20 to +75 (regular specifications) –40 to +85 (wide-range specifications) +75 (products shipped as chips)*2 Storage temperature T stg –55 to +125 °C Notes: 1. Permanent damage may occur to the chip if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 2. Power may be applied when the temperature is between –20 and +75°C.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 484 of 658 REJ09B0042-0800

16.6 H8/38024S Group Mask ROM Vers ion Electrical Characteristics

16.6.1 Power Supply Voltage and Operating Range

The power supply voltage and operating range are indicated by the shaded region in the figures. Power Supply Voltage and Oscillator Frequency Range 38.4 1.8 2.7 3.6 VCC (V) fW (kHz)  All operating 32.768 2.0 4.0 10.0 2.71.8 3.6 VCC (V) fosc (MHz)  Active (high-speed) mode  Sleep (high-speed) mode Note: The fosc values are those when an oscillator is used; when an external clock is used the minimum value of fosc is 1 MHz.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 485 of 658 REJ09B0042-0800 Power Supply Voltage and Operating Frequency Range  Subactive mode  Subsleep mode (except CPU)  Watch mode (except CPU) 16.384 8.192 4.096 1.8 2.7 3.6 VCC (V) φSUB (kHz) 19.2 9.6 4.8 (0.5) 5.0 1.0 2.0 2.71.8 3.6 VCC (V) φ (MHz) Note: 1. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 1 MHz. Note: 2. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 15.625 kHz.  Active (high-speed) mode  Sleep (high-speed) mode (except CPU)  Active (medium-speed) mode  Sleep (medium-speed) mode (except A/D converter) (7.8125) 625 15.625 250 2.71.8 3.6 VCC (V) φ (kHz)

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 486 of 658 REJ09B0042-0800 Analog power Supply Voltage and A/D Converter Operating Range φ (MHz) (0.5) 5.0 1.0 2.7 3.6 AVCC (V) 1.8 φ (kHz)500 625 2.71.8 3.6 AVCC (V)  Active (medium-speed) mode  Sleep (medium-speed) mode  Active (high-speed) mode  Sleep (high-speed) mode

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 487 of 658 REJ09B0042-0800

16.6.2 DC Characteristics

Table 16.16 lists the DC characteristics of the H8/38024S. Table 16.16 DC Characteristics Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Input high voltage VIH RES, WKP0 to WKP7, IRQ0, IRQ3, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK32 0.9 VCC — V CC + 0.3 V IRQ1 0.9 VCC — AV CC + 0.3 V RXD 32, UD 0.8 V CC — V CC + 0.3 V OSC 1 0.9 V CC — V CC + 0.3 V X 1 0.9 V CC — V CC + 0.3 V P1 3, P14, P16, P17, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 0.8 VCC — V CC + 0.3 V PB 0 to PB7 0.8 V CC — AV CC + 0.3 V IRQAEC 0.9 V CC — V CC + 0.3 V

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 488 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Input low voltage VIL RES, WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK –0.3 — 0.1 V CC V RXD 32, UD –0.3 — 0.2 V CC V OSC 1 –0.3 — 0.1 V CC V X 1 –0.3 — 0.1 V CC V P1 3, P14, P16, P17, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PB0 to PB7 –0.3 — 0.2 V CC V Output high voltage VOH P1 3, P14, P16, P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 VCC – 1.0 VCC – 0.3 V –I OH = 1.0 mA VCC = 2.7 V to 3.6 V –IOH = 0.1 mA

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 489 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Output low voltage VOL P1 3, P14, P16, P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 — — 0.5 V I OL = 0.4 mA P9 0 to P95 — — 0.5 V I OL = 10 mA VCC = 2.2 V to 3.6 V — — 0.5 V I OL = 8 mA VCC = 1.8 V to 3.6 V Input/output leakage current | I IL | RES, P43, OSC1, X1, P13, P14, P16, P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, IRQAEC, P90 to P95, PA0 to PA3 — — 1.0 µA V IN = 0.5 V to VCC – 0.5 V PB 0 to PB7 — — 1.0 µA V IN = 0.5 V to AVCC – 0.5 V Pull-up MOS current –Ip P1 3, P14, P16, P17, P30 to P37, P50 to P57, P60 to P67 30 — 180 µA V CC = 3 V, VIN = 0 V Input capacitance CIN All input pins except power supply and IRQAEC — — 15.0 pF f = 1 MHz, V IN =0 V, Ta = 25°C IRQAEC — — 30.0 pF

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 490 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes IOPE1 V CC — 0.2 — mA Active (high-speed) mode VCC = 1.8 V, fOSC = 1 MHz Max. guideline = 1.1 × typ. Active mode current dissipation — 0.6 — mA Active (high-speed) mode VCC = 3 V, fOSC = 2 MHz Max. guideline = 1.1 × typ. — 1.2 — mA Active (high-speed) mode V CC = 3 V, fOSC = 4 MHz Max. guideline = 1.1 × typ. — 3.1 6.0 mA Active (high-speed) mode V CC = 3 V, fOSC = 10 MHz I OPE2 V CC — 0.03 — mA Active (medium- speed) mode V CC = 1.8 V, fOSC = 1 MHz φosc/128 Max. guideline = 1.1 × typ. — 0.1 — mA Active (medium- speed) mode VCC = 3 V, fOSC = 2 MHz φosc/128 Max. guideline = 1.1 × typ.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 491 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Active mode current dissipation IOPE2 V CC — 0.2 — mA Active (medium- speed) mode VCC = 3 V, fOSC = 4 MHz φosc/128 Max. guideline = 1.1 × typ. — 0.6 1.8 mA Active (medium- speed) mode VCC = 3 V, fOSC = 10 MHz φosc/128 ISLEEP V CC — 0.08 — mA V CC= 1.8 V, fOSC= 1 MHz Max. guideline = 1.1 × typ. Sleep mode current dissipation — 0.3 — mA V CC= 3 V, fOSC= 2 MHz Max. guideline = 1.1 × typ. — 0.5 — mA V CC= 3 V, fOSC= 4 MHz Max. guideline = 1.1 × typ. — 1.3 4.8 mA V CC= 3 V, fOSC= 10 MHz

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 492 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Subactive mode current dissipation ISUB V CC — 6.2 — µA V CC = 1.8 V, LCD on 32 kHz External Clock (φSUB=φw/2) — 5.7 — µA V CC = 1.8 V, LCD on 32 kHz crystal resonator SUB=φw/2) Reference value — 4.4 — µA V CC = 2.7 V, LCD on 32 kHz crystal resonator SUB=φw/8) — 10 40 µA V CC = 2.7 V, LCD on 32 kHz External Clock (φSUB=φw/2) — 11 40 µA V CC = 2.7 V, LCD on 32 kHz crystal resonator (φSUB=φw/2) Subsleep mode current dissipation I SUBSP V CC — 4.6 16.0 µA V CC = 2.7 V, LCD on 32 kHz External Clock (φSUB=φw/2) — 5.1 16.0 µA V CC = 2.7 V, LCD on 32 kHz crystal resonator (φSUB=φw/2) Watch mode current dissipation IWATCH V CC — 1.2 — µA V CC = 1.8 V, Ta = 25°C 32 kHz crystal resonator LCD not used Reference value — 2.0 — µA V CC = 2.7 V, Ta = 25°C 32 kHz External Clock LCD not used

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 493 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Watch mode current dissipation IWATCH V CC — 2.3 — µA V CC = 2.7 V, Ta = 25°C 32 kHz crystal resonator LCD not used Reference value — 2.0 6.0 µA V CC = 2.7 V, 32 kHz External Clock LCD not used — 2.3 6.0 µA V CC = 2.7 V, 32 kHz crystal resonator LCD not used Standby mode current dissipation I STBY V CC — 0.1 — µA V CC = 1.8 V, Ta = 25°C 32 kHz crystal resonator not used Reference value — 0.3 — µA V CC = 3.0 V, Ta = 25°C 32 kHz crystal resonator not used Reference value — 1.0 5.0 µA 32 kHz crystal resonator not used RAM data retaining voltage V RAM V CC 1.5 — — V IOL Output pins except port 9 — — 0.5 mA Allowable output low current (per pin) 0 to P95 — — 10.0 mA ∑ IOL Output pins except port 9 — — 20.0 mA Allowable output low current (total) Port 9 — — 80.0 mA Allowable output high current (per pin) OH All output pins — — 0.2 mA

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 494 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Mi n Typ Max Unit Test Condition Notes Allowable output high current (total) ∑ – IOH All output pins — — 10.0 mA Notes: Connect the TEST pin to V SS. 1. Pin states during current measurement. Mode RES Pin Internal State Other Pins LCD Power Supply Oscillator Pins Active (high-speed) mode (IOPE1) VCC Operates V CC Halted System clock oscillator: crystal Active (medium- speed) mode (I OPE2) Subclock oscillator: Pin X1 = GND Sleep mode V CC Only on-chip timers operate VCC Halted Subactive mode V CC Operates V CC Halted System clock oscillator: Subsleep mode V CC Only on-chip timers operate, CPU stops VCC Halted crystal Subclock oscillator: Watch mode V CC Only time base operates, CPU stops VCC Halted crystal Standby mode V CC CPU and timers both stop VCC Halted System clock oscillator: crystal Subclock oscillator: Pin X1 = GND 2. Excludes current in pull-up MOS transistors and output buffers.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 495 of 658 REJ09B0042-0800

16.6.3 AC Characteristics

Table 16.17 lists the control signal timing, and tables 16.10 lists the serial interface timing of the H8/38024S. Table 16.17 Control Signal Timing Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure System clock oscillation frequency fOSC OSC 1, OSC2 2.0 — 10.0 MHz V CC = 2.7 V to 3.6 V 2.0 — 4.0 MHz V CC = 1.8 V to 3.6 V OSC clock (φOSC) cycle time tOSC OSC 1, OSC2 100 — 500 (1000) ns V CC = 2.7 V to 3.6 V Figure 16.2 250 — 500 (1000) ns V CC = 1.8 V to 3.6 V tcyc 2 — 128 t OSC System clock (φ) cycle time — — 128 µs Subclock oscillation frequency fW X 1, X2 — 32.768 or 38.4 — kHz Watch clock (φW) cycle time tW X 1, X2 — 30.5 or 26.0 — µs Figure 16.2 Subclock (φSUB) cycle time tsubcyc 2 — 8 t W *1 Instruction cycle time 2 — — t cyc tsubcyc

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 496 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure Oscillation stabilization time trc OSC 1, OSC2 — 20 45 µs Ceramic oscillator VCC = 2.2 V to 3.6 V Figure 16.10 — 80 — µs Ceramic oscillator Except the above — 0.8 2 ms Crystal oscillator VCC = 2.7 V to 3.6 V — 1.2 3 ms Crystal oscillator VCC = 2.2 V to 3.6 V — — 50 ms Except the above X 1, X2 — — 2 s V CC = 2.2 V to 3.6 V — 4 — s Except the above tCPH OSC 1 40 — — ns V CC = 2.7 V to 3.6 V Figure 16.2 External clock high width 100 — — ns V CC = 1.8 V to 3.6 V X 1 — 15.26 or 13.02 — µs tCPL OSC 1 40 — — ns V CC = 2.7 V to 3.6 V Figure 16.2 External clock low width 100 — — ns V CC = 1.8 V to 3.6 V X 1 — 15.26 or 13.02 — µs tCPr OSC 1 — — 10 ns V CC = 2.7 V to 3.6 V Figure 16.2 External clock rise time — — 25 ns V CC = 1.8 V to 3.6 V X 1 — — 55.0 ns tCPf OSC 1 — — 10 ns V CC = 2.7 V to 3.6 V Figure 16.2 External clock fall time — — 25 ns V CC = 1.8 V to 3.6 V X 1 — — 55.0 ns Pin RES low width t REL RES 10 — — t cyc Figure 16.3

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 498 of 658 REJ09B0042-0800 Table 16.18 Serial Interface (SCI3) Timing Values Item Symbol Min Typ Max Unit Test Conditions Reference Figure Asynchronous t scyc 4 — — t cyc or Figure 16.5 Input clock cycle Synchronous 6 — — t subcyc Input clock pulse width t SCKW 0.4 — 0.6 t scyc Figure 16.5 Transmit data delay time (synchronous) tTXD — — 1 t cyc or tsubcyc Figure 16.6 Receive data setup time (synchronous) tRXS 400.0 — — ns Figure 16.6 Receive data hold time (synchronous) tRXH 400.0 — — ns Figure 16.6

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 499 of 658 REJ09B0042-0800

16.6.4 A/D Converter Characteristics

Table 16.19 shows the A/D converter characteristics of the H8/38024S. Table 16.19 A/D Converter Characteristics VCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure Analog power supply voltage AVCC AV CC 1.8 — 3.6 V *1 Analog input voltage AVIN AN 0 to AN7 – 0.3 — AV CC + 0.3 V AIOPE AV CC — — 1.0 mA AV CC = 3.0 V Analog power supply current AISTOP1 AV CC — 600 — µA *2 Reference value AI STOP2 AV CC — — 5 µA *3 Analog input capacitance CAIN AN 0 to AN7 — — 15.0 pF Allowable signal source impedance RAIN — — 10.0 k Ω Resolution (data length) — — 10 bit Nonlinearity error — — ±3.5 LSB AV CC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V — — ±5.5 LSB AV CC = 2.0 V to 3.6 V VCC = 2.0 V to 3.6 V — — ±7.5 LSB Other than above *4 Quantization error — — ±0.5 LSB Absolute accuracy — — ±4.0 LSB AV CC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V — — ±6.0 LSB AV CC = 2.0 V to 3.6 V VCC = 2.0 V to 3.6 V — — ±8.0 LSB Other than above *4 Conversion time 12.4 — 124 µs AV CC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V 62 — 124 µs Other than above Notes: 1. Set AV CC = VCC when the A/D converter is not used. 2. AI STOP1 is the current in active and sleep modes while the A/D converter is idle.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 500 of 658 REJ09B0042-0800 3. AI STOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle. 4. Conversion time: 62 μs.

16.6.5 LCD Characteristics

Table 16.20 shows the LCD characteristics. Table 16.20 LCD Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Conditions Reference Figure Segment driver drop voltage VDS SEG 1 to SEG32 — — 0.6 V I D = 2 µA V1 = 2.7 V to 3.6 V Common driver drop voltage V DC COM 1 to COM4 — — 0.3 V I D = 2 µA V1 = 2.7 V to 3.6 V LCD power supply split-resistance R LCD 1.5 3.0 7.0 M Ω Between V 1 and VSS Liquid crystal display voltage VLCD V 1 2.2 — 3.6 V * 2 Notes: 1. The voltage drop from power supply pins V 1, V2, V3, and VSS to each segment pin or common pin. 2. When the liquid crystal display voltage is supplied from an external power source, ensure that the following relationship is maintained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 501 of 658 REJ09B0042-0800

16.7 Absolute Maximum Ratings of H8/38124 Group F-ZTAT Version

Table 16.21 lists the absolute maximum ratings. Table 16.21 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage V CC –0.3 to +7.0 V *1 CV CC –0.3 to +4.3 V Analog power supply voltage AV CC –0.3 to +7.0 V Input voltage Other than port B V in –0.3 to V CC +0.3 V Port B AV in –0.3 to AV CC +0.3 V Port 9 pin voltage V P9 –0.3 to V CC +0.3 V Operating temperature T opr –20 to +75 *2 (regular specifications) –40 to +85 *2 (wide-range temperature specifications) Storage temperature T stg –55 to +125 °C Notes: 1. Permanent damage may result if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 2. The operating temperature ranges from –20 °C to +75°C when programming or erasing the flash memory.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 502 of 658 REJ09B0042-0800

16.8 Electrical Characteristics of H8/38124 Group F-ZTAT Version and

16.8.1 Power Supply Voltage and Operating Ranges

Power Supply Voltage and Oscillation Frequency Range (System Clock Oscillator Selected) 5.5 VCC (V) fW (kHz)  All operating modes 32.768 2.7 2.0 20.0 2.7 5.5 VCC (V) fosc (MHz)  Active (high-speed) mode  Sleep (high-speed) mode Power Supply Voltage and Oscillation Frequency Range (On-Chip Oscillator Selected) 5.5 VCC (V) fW (kHz)  All operating modes 32.768 2.7 0.7 2.0 2.7 5.5 VCC (V) fosc (MHz)  Active (high-speed) mode  Sleep (high-speed) mode

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 503 of 658 REJ09B0042-0800 Power Supply Voltage and Operating Frequency Range (System Clock Oscillator Selected)  Subactive mode  Subsleep mode (except CPU)  Watch mode (except CPU) 16.384 8.192 4.096 2.7 5.5 VCC (V) φSUB (kHz) 10.0 1.0 2.7 5.5 VCC (V) φ (MHz)  Active (high-speed) mode  Sleep (high-speed) mode (except CPU) 1250 15.625 2.7 5.5 VCC (V) φ (kHz)  Active (medium-speed) mode  Sleep (medium-speed) mode (except A/D converter)

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 504 of 658 REJ09B0042-0800 Power Supply Voltage and Operating Frequency Range (On-Chip Oscillator Selected)  Subactive mode  Subsleep mode (except CPU)  Watch mode (except CPU) 16.384 8.192 4.096 2.7 5.5 VCC (V) φSUB (kHz)1.0 0.35 2.7 5.5 VCC (V) φ (MHz)  Active (high-speed) mode  Sleep (high-speed) mode (except CPU) 125 6.25 2.7 5.5 VCC (V) φ (kHz)  Active (medium-speed) mode  Sleep (medium-speed) mode (except A/D converter)

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 505 of 658 REJ09B0042-0800 Analog Power Supply Voltage and A/D Converter Operating Range (System Clock Oscillator Selected) 10.0 1.0 2.7 5.5 AVCC (V) φ (MHz)  Active (high-speed) mode  Sleep (high-speed) mode 1000 500 2.7 5.5 AVCC (V) φ (kHz)  Active (medium-speed) mode  Sleep (medium-speed) mode Analog Power Supply Voltage and A/D Converter Operating Range (On-Chip Oscillator Selected) 1.0 0.35 2.7 5.5 AVCC (V) φ (MHz)  Active (high-speed) mode  Sleep (high-speed) mode 125 6.25 2.7 5.5 AVCC (V) φ (kHz)  Active (medium-speed) mode  Sleep (medium-speed) mode

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 506 of 658 REJ09B0042-0800

16.8.2 DC Characteristics

Table 16.22 lists the DC characteristics. Table 16.22 DC Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Input high voltage VIH V CC × 0.8 — V CC + 0.3 V V CC = 4.0 V to 5.5 V RES, WKP0 to WKP7, IRQ0, IRQ3, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK VCC × 0.9 — V CC + 0.3 Other than above IRQ1 V CC × 0.8 — AV CC + 0.3 V V CC = 4.0 V to 5.5 V VCC × 0.9 — AV CC + 0.3 Other than above RXD 32, UD V CC × 0.7 — V CC + 0.3 V V CC = 4.0 V to 5.5 V V CC × 0.8 — V CC + 0.3 Other than above OSC 1 V CC × 0.8 — V CC + 0.3 V V CC = 4.0 V to 5.5 V V CC × 0.9 — V CC + 0.3 Other than above V CC × 0.7 — V CC + 0.3 V V CC = 4.0 V to 5.5 V P13, P14, P17, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 VCC × 0.8 — V CC + 0.3 Other than above PB 0 to PB7 V CC × 0.7 — AV CC + 0.3 V V CC = 4.0 V to 5.5 V V CC × 0.8 — AV CC + 0.3 Other than above IRQAEC, P9 5*5 V CC × 0.8 — V CC + 0.3 V V CC = 4.0 V to 5.5 V V CC × 0.9 — V CC + 0.3 Other than above Note: Connect the TEST pin to V SS.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 507 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Input low voltage VIL – 0.3 — V CC × 0.2 V V CC = 4.0 V to 5.5 V RES, WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, P95*5, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK – 0.3 — V CC × 0.1 Other than above RXD 32, UD – 0.3 — V CC × 0.3 V V CC = 4.0 V to 5.5 V – 0.3 — V CC × 0.2 Other than above OSC 1 – 0.3 — V CC × 0.2 V V CC = 4.0 V to 5.5 V – 0.3 — V CC × 0.1 Other than above – 0.3 — V CC × 0.3 V V CC = 4.0 V to 5.5 V P13, P14, P17, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PB0 to PB7 – 0.3 — V CC × 0.2 Other than above VOH V CC – 1.0 — — V V CC = 4.0 V to 5.5 V –IOH = 1.0 mA Output high voltage V CC – 0.5 — — V CC = 4.0 V to 5.5 V –IOH = 0.5 mA P13, P14, P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 VCC – 0.3 — — –I OH = 0.1 mA

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 508 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Output low voltage VOL — — 0.6 V V CC = 4.0 V to 5.5 V IOL = 1.6 mA P13, P14, P17, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 — — 0.5 I OL = 0.4 mA P3 0 to P37 — — 1.0 V CC = 4.0 V to 5.5 V IOL = 10 mA — — 0.6 V CC = 4.0 V to 5.5 V IOL = 1.6 mA — — 0.5 I OL = 0.4 mA P9 0 to P95 — — 1.5 V CC = 4.0 V to 5.5 V IOL = 15 mA — — 1.0 V CC = 4.0 V to 5.5 V IOL = 10 mA — — 0.8 V CC = 4.0 V to 5.5 V IOL = 8 mA — — 1.0 I OL = 5 mA — — 0.6 I OL = 1.6 mA — — 0.5 I OL = 0.4 mA | IIL | RES, P43, P13, P14, P17, OSC1, X1, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, IRQAEC, PA0 to PA3, P90 to P95 — — 1.0 µA V IN = 0.5 V to VCC – 0.5 V Input/ output leakage current PB 0 to PB7 — — 1.0 V IN = 0.5 V to AVCC – 0.5 V –Ip 20 — 200 µA V CC = 5.0 V, VIN = 0.0 V Pull-up MOS current P13, P14, P17, P30 to P37, P50 to P57, P60 to P67 — 40 — V CC = 2.7 V, VIN = 0.0 V Refer- ence value

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 509 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Input capaci- tance Cin All input pins except power supply pin — — 15.0 pF f = 1 MHz, VIN = 0.0 V, Ta = 25°C Active mode current consump- tion I OPE1 V CC — 0.6 — mA Active (high-speed) mode VCC = 2.7 V, fOSC = 2 MHz *1 *3 *4 Approx. max. value = 1.1 × Typ. Approx. max. value = 1.1 × Typ. — 0.8 — Active (high-speed) mode VCC = 5 V, fOSC = 2 MHz *1 *3 *4 Approx. max. value = 1.1 × Typ. Approx. max. value = 1.1 × Typ. — 1.6 — Active (high-speed) mode VCC = 5 V, fOSC = 4 MHz *1 *3 *4 Approx. max. value = 1.1 × Typ. — 3.3 7.0 *1 *3 *4 — 4.0 7.0 Active (high-speed) mode VCC = 5 V, fOSC = 10 MHz *2 *3 *4

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 510 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Active mode current consump- tion IOPE2 V CC — 0.2 — mA Active (medium- speed) mode VCC = 2.7 V, fOSC = 2 MHz, φOSC/128 *1 *3 *4 Approx. max. value = 1.1 × Typ. Approx. max. value = 1.1 × Typ. — 0.4 — Active (medium- speed) mode VCC = 5 V, fOSC = 2 MHz, φOSC/128 *1 *3 *4 Approx. max. value = 1.1 × Typ. Approx. max. value = 1.1 × Typ. — 0.6 — Active (medium- speed) mode VCC = 5 V, fOSC = 4 MHz, φOSC/128 *1 *3 *4 Approx. max. value = 1.1 × Typ. — 0.9 3.0 *1 *3 *4 — 1.2 3.0 Active (medium- speed) mode VCC = 5 V, fOSC = 10 MHz, φOSC/128 *2 *3 *4

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 511 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Sleep mode current consump- tion ISLEEP V CC — 0.3 — mA V CC = 2.7 V, fOSC = 2 MHz *1 *3 *4 Approx. max. value = 1.1 × Typ. Approx. max. value = 1.1 × Typ. fOSC = 2 MHz *1 *3 *4 Approx. max. value = 1.1 × Typ. Approx. max. value = 1.1 × Typ. fOSC = 4 MHz *1 *3 *4 Approx. max. value = 1.1 × Typ. — 1.5 5.0 *1 *3 *4 — 2.2 5.0 VCC = 5 V, fOSC = 10 MHz *2 *3 *4 ISUB V CC — 11.3 — µA *1 *3 *4 Reference value Subactive mode current consump- tion — 12.7 — VCC = 2.7 V, LCD on, 32-kHz crystal resonator used (φSUB = φW/8) *2 *3 *4 Reference value — 16.3 50 *1 *3 *4 — 30 50 VCC = 2.7 V, LCD on, 32-kHz crystal resonator used (φSUB = φW/2) *2 *3 *4

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 512 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Subsleep mode current consump- tion ISUBSP V CC — 4.0 16 µA V CC = 2.7 V, LCD on, 32-kHz crystal resonator used (φSUB = φW/2) *3 *4 IWATCH V CC — 1.4 — µA *1 *3 *4 Reference value Watch mode current consump- tion — 1.8 — V CC = 2.7 V, Ta = 25°C, 32-kHz crystal resonator used, LCD not used 2 *3 *4 Reference value 32-kHz crystal resonator used, LCD not used *3 *4 ISTBY V CC — 0.3 — µA V CC = 2.7 V, Ta = 25°C, 32-kHz crystal resonator not used *1 *3 *4 Reference value Standby mode current consump- tion — 0.5 — V CC = 2.7 V, Ta = 25°C, 32-kHz crystal resonator not used 2 *3 *4 Reference value Ta = 25°C, SUBSTP (subclock oscillator control register) setting = 1 2 *4 Reference value Ta = 25°C, 32-kHz crystal resonator not used 2 *3 *4 Reference value Ta = 25°C, SUBSTP (subclock oscillator control register) setting = 1 2 *4 Reference value — 1.0 5.0 32-kHz crystal resonator not used *3 *4 RAM data retaining voltage VRAM V CC 2.0 — — V *6

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 513 of 658 REJ09B0042-0800 Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Allowable output low current (per pin) IOL Output pins except ports 3 and 9 — — 2.0 mA V CC = 4.0 V to 5.5 V Port 3 — — 10.0 V CC = 4.0 V to 5.5 V Output pins except port 9 — — 0.5 Port 9 — — 15.0 V CC = 4.0 V to 5.5 V — — 5.0 Other than above Allowable output low current (total) ∑IOL Output pins except ports 3 and 9 — — 40.0 mA V CC = 4.0 V to 5.5 V Port 3 — — 80.0 V CC = 4.0 V to 5.5 V Output pins except port 9 — — 20.0 Port 9 — — 80.0 –IOH All output pins — — 2.0 mA V CC = 4.0 V to 5.5 V Allowable output high current (per pin) — — 0.2 Other than above Allowable output high current (total) ∑–IOH All output pins — — 15.0 mA V CC = 4.0 V to 5.5 V — — 10.0 Other than above Notes: Connect the TEST pin to V SS. 1. Applies to the mask-ROM version. 2. Applies to the F-ZTAT version.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 514 of 658 REJ09B0042-0800 3. Pin states when current consumption is measured Mode RES Pin Internal State Other Pins LCD Power Supply Oscillator Pins Active (high-speed) mode (I OPE1) Active (medium- speed) mode (IOPE2) VCC Only CPU operates V CC Stops Sleep mode V CC Only all on-chip timers operate VCC Stops System clock: crystal resonator Subclock: Pin X1 = GND Subactive mode V CC Only CPU operates V CC Stops Subsleep mode V CC Only all on-chip timers operate CPU stops VCC Stops Watch mode V CC Only clock time base operates CPU stops VCC Stops System clock: crystal resonator Subclock: crystal resonator Standby mode V CC CPU and timers both stop VCC Stops System clock: crystal resonator Subclock: Pin X1 = GND 4. Except current which flows to the pull-up MOS or output buffer 5. Used when user mode or boot mode is determined after canceling a reset in the F- ZTAT version 6. Voltage maintained in standby mode

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 515 of 658 REJ09B0042-0800

16.8.3 AC Characteristics

Table 16.23 lists the control signal timing and table 16.24 lists the serial interface timing. Table 16.23 Control Signal Timing Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure fOSC OSC 1, OSC2 2.0 — 20.0 MHz System clock oscillation frequency 0.7 — 2.0 On-chip oscillator selected OSC clock (φOSC) cycle time tOSC OSC 1, OSC2 50.0 — 500 ns Figure 16.2 500 — 1429 On-chip oscillator selected tcyc 2 — 128 t OSC System clock (φ) cycle time — — 182 µs Subclock oscillation frequency fW X 1, X2 — 32.768 — kHz Watch clock (φW) cycle time tW X 1, X2 — 30.5 — µs Figure 16.2 Subclock (φSUB) cycle time tsubcyc 2 — 8 t W *1 Instruction cycle time 2 — — t cyc tsubcyc Oscillation stabilization time trc OSC 1, OSC2 — — 20 ms t rc X 1, X2 — — 2.0 s External clock high width tCPH OSC 1 20 — — ns Figure 16.2 External clock low width tCPL OSC 1 20 — — ns Figure 16.2 External clock rise time tCPr OSC 1 — — 5 ns Figure 16.2 External clock fall time tCPf OSC 1 — — 5 ns Figure 16.2 RES pin low width tREL RES 10 — — t cyc Figure 16.3

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 517 of 658 REJ09B0042-0800

16.8.4 A/D Converter Characteristics

Table 16.25 shows the A/D converter characteristics. Table 16.25 A/D Converter Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure Analog power supply voltage AV CC AV CC 2.7 — 5.5 V Analog input voltage AV IN AN 0 to AN7 – 0.3 — AV CC + 0.3 V AIOPE AV CC — — 1.5 mA AV CC = 5.0 V Analog power supply current AISTOP1 AV CC — 600 — µA *2 Reference value AI STOP2 AV CC — — 5.0 µA *3 Analog input capacitance CAIN AN 0 to AN7 — — 15.0 pF Allowable signal source impedance RAIN — — 10.0 k Ω Resolution (data length) — — 10 bit Nonlinearity error — — ±3.5 LSB AV CC = 4.0 V to 5.5 V to 5.5 V Quantization error — — ±0.5 LSB Absolute accuracy — ±2.0 ±4.0 LSB AV CC = 4.0 V to 5.5 V to 5.5 V Conversion time 6.2 — 124 µs Notes: 1. Set AV CC = VCC when the A/D converter is not used. 2. AI STOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AI STOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 518 of 658 REJ09B0042-0800

16.8.5 LCD Characteristics

Table 16.26 shows the LCD characteristics. Table 16.26 LCD Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Reference Figure Segment driver step-down voltage VDS SEG 1 to SEG32 — — 0.6 V I D = 2 µA V1 = 2.7 V to 5.5 V Common driver step-down voltage VDC COM 1 to COM4 — — 0.3 V I D = 2 µA V1 = 2.7 V to 5.5 V LCD power supply split-resistance RLCD 1.5 3.0 7.0 M Ω Between V1 and VSS Liquid crystal display voltage VLCD V 1 2.7 — 5.5 V *2 Notes: 1. The voltage step-down from power supply pins V1, V2, V3, and V SS to each segment pin or common pin. 2. When the liquid crystal display voltage is supplied from an external power supply, ensure that the following relationship is maintained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 519 of 658 REJ09B0042-0800

16.8.6 Flash Memory Characteristics

Table 16.27 Flash Memory Characteristics operating voltage when reading), VCC = 3.0 V to 5.5 V (range of operating voltage when programming/erasing), Ta = –20°C to +75°C (range of operating temperature when programming/erasing: product with regular specifications, product with wide- range temperature specifications) Values Item Symbol Min Typ Max Unit Test Conditions Programming time*1*2*4 t P — 7 200 ms/128 bytes Erase time*1*3*5 t E — 100 1200 ms/block Reprogramming count N WEC 1000 *8 10000 *9 — times Data retain period t DRP 10 *10 — — year Programming Wait time after SWE-bit setting*1 x 1 — — µs Wait time after PSU-bit setting*1 y 50 — — µs z1 28 30 32 µs 1 ≤ n ≤ 6 z2 198 200 202 µs 7 ≤ n ≤ 1000 Wait time after P-bit setting*1*4 z3 8 10 12 µs Additional programming Wait time after P-bit clear*1 α 5 — — µs Wait time after PSU-bit clear*1 β 5 — — µs Wait time after PV-bit setting*1 γ 4 — — µs Wait time after dummy write*1 ε 2 — — µs Wait time after PV-bit clear*1 η 2 — — µs Wait time after SWE-bit clear*1 θ 100 — — µs Maximum programming count*1*4*5 N — — 1000 times

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 520 of 658 REJ09B0042-0800 Values Item Symbol Min Typ Max Unit Test Conditions Wait time after SWE-bit setting*1 x 1 — — µs Wait time after ESU-bit setting*1 y 100 — — µs Wait time after E-bit setting*1*6 z 10 — 100 ms Wait time after E-bit clear*1 α 10 — — µs Wait time after ESU-bit clear*1 β 10 — — µs Wait time after EV-bit setting*1 γ 20 — — µs Wait time after dummy write*1 ε 2 — — µs Wait time after EV-bit clear*1 η 4 — — µs Erase Wait time after SWE-bit clear*1 θ 100 — — µs Maximum erase count*1*6*7 N — — 120 times Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1 is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (t P (max)) tP (max) = Wait time after P-bit setting (z) × maximum number of writes (N) 5. The maximum number of writes (N) should be set according to the actual set value of z1, z2, and z3 to allow programming within the maximum programming time (tP (max)). The wait time after P-bit setting (z1 and z2) should be alternated according to the number of writes (n) as follows: 1 ≤ n ≤ 6 z1 = 30 µs 7 ≤ n ≤ 1000 z2 = 200 µs 6. Maximum erase time (t E (max)) tE (max) = Wait time after E-bit setting (z) × maximum erase count (N) 7. The maximum number of erases (N) should be set according to the actual set value of z to allow erasing within the maximum erase time (tE (max)). 8. This minimum value guarantees all characteristics after reprogramming (the guaranteed range is from 1 to the minimum value). 9. Reference value when the temperature is 25 °C (normally reprogramming will be performed by this count). 10. This is a data retain characteristic when reprogramming is performed within the specification range including this minimum value.

16.8.7 Power Supply Voltage Detection Circuit Characteristics

VLVDRmin = 1.0 V and then rises, so thorough evaluation is called for. Table 16. 29 Power Supply Voltage Detection Circuit Characteristics (2)

1. Low-voltage detection reset should be selected for low-voltage detection reset only.
2. The values of Vint(D), Vint(U), Vreset1, and Vreset2 change relative to each other.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 522 of 658 REJ09B0042-0800 Table 16.30 Power Supply Voltage Detection Circuit Characteristics (3) Using on-chip reference voltage and detect voltage external input (VREFSEL = 0, VINTDSEL and VINTUSEL = 1) Rated Values Item Symbol Min Typ Max Unit Test Condition extD/extU interrupt detection level Vexd 0.80 1.20 1.60 V extD/extU pin input voltage*2 VextD*1 VextU*1 –0.3 — V CC + 0.3 or AVCC + 0.3, whichever is lower V V CC = 2.7 to 3.3 V whichever is lower V V CC = 3.3 to 5.5 V Notes: 1. The VextD voltage must always be greater than the VextU voltage. 2. The maximum input voltage of the extD and extU pins is 3.6 V.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 523 of 658 REJ09B0042-0800 Table 16.31 Power Supply Voltage Detection Circuit Characteristics (4) Using external reference voltage and ladder resistor (VREFSEL = 1, VINTDSEL = VINTUSEL = Rated Values Item Symbol Min Typ Max Unit Test Condition Power supply drop detection voltage Vref input voltage (Vint(D)) Vref1*2 0.98 — 1.68 V Vint(D) Power supply rise detection voltage Vref input voltage (Vint(U)) Vref2*2 0.91 — 1.55 V Vint(U) Reset detection voltage 1 Vref input voltage (Vreset1) Vref3*2 0.89 — 2.77 V Vreset1 Reset detection voltage 2 Vref input voltage (Vreset2) Vref4*2 1.08 — 1.89 V Vreset2 Notes: 1. The values of Vint(D), Vint(U), Vreset1, and Vreset2 change relative to each other. Example: If Vint(D) is the minimum value, Vint(U), Vreset1, and Vreset2 are also the minimum values. 2. The Vref input voltage is calculated using the following formula.

2.7 V (= V

CC min) < Vint(D), Vint(U), Vreset2 < 5.5 V (= V CC max) 1.5 V (= RAM retention voltage) < Vreset1 < 5.5 V (= V CC max)

Table 16. 32 Power Supply Voltage Detection Circuit Characteristics (5) Note: * The VextD voltage must always be greater than the VextU voltage.

16.8.8 Power-On Reset Circuit Characteristics

work properly if the power supply voltage, VCC, is raised from a level exceeding 100 mV.

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 525 of 658 REJ09B0042-0800

16.8.9 Watchdog Timer Characteristics

Table 16.34 Watchdog Timer Characteristics AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified Rated Values Item Symbol Applicable Pins Min Typ Max Unit Note Test Condition On-chip oscillator overflow time tOVF 0.2 0.4 — s * VCC = 5 V Note: * When the on-chip oscillator is selected, the timer counts from 0 to 255, indicating the time remaining until an internal reset is generated.

16.8.10 Power Supply Characteristics

Table 16.35 Power Supply Characteristics Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes Power supply startup voltage V CCSTART V CC 0 — 0.1 V *1*2 Power supply startup slope SV CC V CC 0.05 — — V/ms Notes: 1. This LSI may not start normally when it starts with the condition beyond specification shown in above (Refer to figure 16.1 for power supply voltage startup time.). 2. Applies to the F-ZTAT version. Voltage (V) VCCSTART VCC SVCC Time (ms) Figure 16.1 Power Supply Voltage Startup Timing

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 526 of 658 REJ09B0042-0800

16.9 Operation Timing

Figures 16.2 to 16.7 show timing diagrams. t , twOSC VIH VIL tCPH tCPL tCPr OSC1 tCPf Figure 16.2 Clock Input Timing RES VIL tREL Figure 16.3 RES Low Width VIH VIL tIL IRQ0, IRQ1, IRQ3, IRQ4, TMIC, TMIF, TMIG, ADTRG, WKP 0 to WKP7, IRQAEC, AEVL, AEVH tIH Figure 16.4 Input Timing

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 528 of 658 REJ09B0042-0800 UD VIL VIH tUDL tUDH Figure 16.7 UD Pin Minimum Transition Width Timing

16.10 Output Load Circuit

2.4 kΩ 12 kΩ30 pF Output pin Figure 16.8 Output Load Condition

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 529 of 658 REJ09B0042-0800

16.11 Resonator Equivalent Circuit

(MHz) RS (max) CO (max) 100 Ω 16 pF 4.193 100 Ω 16 pF 30 Ω 16 pF Crystal Resonator Parameters RS OSC2OSC1 LS Frequency (MHz) RS (max) CO (max) 18.3 Ω 36.94 pF 6.8 Ω 36.72 pF 4.6 Ω 32.31 pF Ceramic Resonator Parameters Figure 16.9 Resonator Equivalent Circuit (1) OSC1 LS CS CO RS OSC2 Crystal Resonator Parameters (Manufacturer's Publicly Released Values) Frequency (MHz) RS (max) CO (max) Manufacturer Nihon Dempa Kogyo Co., Ltd. Ceramic Resonator Parameters (1) (Manufacturer's Publicly Released Values) Frequency (MHz) RS (max) CO (max) Manufacturer Murata Manufacturing Co., Ltd. Manufacturer Murata Manufacturing Co., Ltd. 100 Ω 16 pF 18.3 Ω 36.94 pF Ceramic Resonator Parameters (2) (Manufacturer's Publicly Released Values) Frequency (MHz) RS (max) CO (max) 4.6 Ω 32.31 pF Figure 16.10 Resonator Equivalent Circuit (2)

Section 16 Electrical Characteristics Rev. 8.00 Mar. 09, 2010 Page 530 of 658 REJ09B0042-0800

16.12 Usage Note

The ZTAT, F-ZTAT, and mask ROM versions satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on. When system evaluation testing is carried out using the ZTAT or F-ZTAT version, the same evaluation testing should also be conducted for the mask ROM version when changing over to that version.

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 531 of 658 REJ09B0042-0800 Appendix A CPU Instruction Set A.1 Instructions Operation Notation Rd8/16 General register (destination) (8 or 16 bits) Rs8/16 General register (source) (8 or 16 bits) Rn8/16 General register (8 or 16 bits) CCR Condition code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #xx: 3/8/16 Immediate data (3, 8, or 16 bits) d: 8/16 Displacement (8 or 16 bits) @aa: 8/16 Absolute address (8 or 16 bits) + Addition – Subtraction × Multiplication ÷ Division ∧ Logical AND ∨ Logical OR ⊕ Exclusive logical OR → Move — Logical complement Condition Code Notation Symbol ↔ Modified according to the instruction result * Not fixed (value not guaranteed)

0 Always cleared to 0

— Not affected by the instruction execution result

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 532 of 658 REJ09B0042-0800 Table A.1 lists the H8/300L CPU instruction set. Table A.1 Instruction Set Mnemonic Operation I H N Z V C MOV.B #xx:8, Rd B #xx:8 →Rd8 2 ⎯⎯ 0 ⎯ 2 MOV.B Rs, Rd B Rs8 →Rd8 2 ⎯⎯ 0 ⎯ 2 MOV.B @Rs, Rd B @Rs16 →Rd8 2 ⎯⎯ 0 ⎯ 4 MOV.B @(d:16, Rs), Rd B @(d:16, Rs16) →Rd8 4 ⎯⎯ 0 ⎯ 6 MOV.B @Rs+, Rd B @Rs16 →Rd8 2 ⎯⎯ 0 ⎯ 6 Rs16+1 →Rs16 MOV.B @aa:8, Rd B @aa:8 →Rd8 2 ⎯⎯ 0 ⎯ 4 MOV.B @aa:16, Rd B @aa:16 →Rd8 4 ⎯⎯ 0 ⎯ 6 MOV.B Rs, @Rd B Rs8 →@Rd16 2 ⎯⎯ 0 ⎯ 4 MOV.B Rs, @(d:16, Rd) B Rs8 →@(d:16, Rd16) 4 ⎯⎯ 0 ⎯ 6 MOV.B Rs, @−Rd B Rd16 −1 →Rd16 2 ⎯⎯ 0 ⎯ 6 Rs8 →@Rd16 MOV.B Rs, @aa:8 B Rs8 →@aa:8 2 ⎯⎯ 0 ⎯ 4 MOV.B Rs, @aa:16 B Rs8 →@aa:16 4 ⎯⎯ 0 ⎯ 6 MOV.W #xx:16, Rd W #xx:16 →Rd 4 ⎯⎯ 0 ⎯ 4 MOV.W Rs, Rd W Rs16 →Rd16 2 ⎯⎯ 0 ⎯ 2 MOV.W @Rs, Rd W @Rs16 →Rd16 2 ⎯⎯ 0 ⎯ 4 MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) →Rd16 4 ⎯⎯ 0 ⎯ 6 MOV.W @Rs+, Rd W @Rs16 →Rd16 2 ⎯⎯ 0 ⎯ 6 Rs16+2 →Rs16 MOV.W @aa:16, Rd W @aa:16 →Rd16 4 ⎯⎯ 0 ⎯ 6 MOV.W Rs, @Rd W Rs16 →@Rd16 2 ⎯⎯ 0 ⎯ 4 MOV.W Rs, @(d:16, Rd) W Rs16 →@(d:16, Rd16) 4 ⎯⎯ 0 ⎯ 6 MOV.W Rs, @−Rd W Rd16 −2 →Rd16 2 ⎯⎯ 0 ⎯ 6 Rs16 →@Rd16 MOV.W Rs, @aa:16 W Rs16 →@aa:16 4 ⎯⎯ 0 ⎯ 6 POP Rd W @SP →Rd16 2 ⎯⎯ 0 ⎯ 6 SP+2 →SP PUSH Rs W SP −2 →SP 2 ⎯⎯ 0 ⎯ 6 Rs16 →@SP #xx: 8/16 Rn @Rn @(d:16, Rn) @−Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied No. of States Addressing Mode/ Instruction Length (bytes) Condition Code Operand Size

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 533 of 658 REJ09B0042-0800 Mnemonic Operation I H N Z V C ADD.B #xx:8, Rd B Rd8+#xx:8 →Rd8 2 ⎯ ↔ ↔ ADD.B Rs, Rd B Rd8+Rs8 →Rd8 2 ⎯ 2 ADD.W Rs, Rd W Rd16+Rs16 →Rd16 2 ⎯ (1) 2 ADDX.B #xx:8, Rd B Rd8+#xx:8 +C →Rd8 2 ⎯ (2) 2 ADDX.B Rs, Rd B Rd8+Rs8 +C →Rd8 2 ⎯ (2) 2 INC.B Rd B Rd8+1 →Rd8 2 ⎯⎯ ⎯ 2 DAA.B Rd B Rd8 decimal adjust →Rd8 2 ⎯ (3) 2 SUB.B Rs, Rd B Rd8 −Rs8 →Rd8 2 ⎯ 2 SUB.W Rs, Rd W Rd16 −Rs16 →Rd16 2 ⎯ (1) 2 SUBX.B #xx:8, Rd B Rd8 −#xx:8 −C →Rd8 2 ⎯ (2) 2 SUBX.B Rs, Rd B Rd8 −Rs8 −C →Rd8 2 ⎯ (2) 2 DEC.B Rd B Rd8 −1 →Rd8 2 ⎯⎯ ⎯ 2 DAS.B Rd B Rd8 decimal adjust →Rd8 2 ⎯ ⎯ 2 NEG.B Rd B 0 −Rd →Rd 2 ⎯ 2 CMP.B #xx:8, Rd B Rd8 −#xx:8 2 ⎯ 2 CMP.B Rs, Rd B Rd8 −Rs8 2 ⎯ 2 CMP.W Rs, Rd W Rd16 −Rs16 2 ⎯ (1) 2 #xx: 8/16 Rn @Rn @(d:16, Rn) @−Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied No. of States Addressing Mode/ Instruction Length (bytes) Condition Code Operand Size

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 534 of 658 REJ09B0042-0800 Mnemonic Operation I H N Z V C MULXU.B Rs, Rd B Rd8 ×Rs8 →Rd16 2 ⎯⎯⎯⎯⎯⎯ 14 DIVXU.B Rs, Rd B Rd16 ÷Rs8 →Rd16 2 ⎯⎯ (5) (6) ⎯⎯ 14 (RdH: remainder, RdL: quotient) AND.B #xx:8, Rd B Rd8 ∧#xx:8 →Rd8 2 ⎯⎯ 0 ⎯ 2 AND.B Rs, Rd B Rd8 ∧Rs8 →Rd8 2 ⎯⎯ 0 ⎯ 2 OR.B #xx:8, Rd B Rd8 ∨#xx:8 →Rd8 2 ⎯⎯ 0 ⎯ 2 OR.B Rs, Rd B Rd8 ∨Rs8 →Rd8 2 ⎯⎯ 0 ⎯ 2 XOR.B #xx:8, Rd B Rd8 ⊕#xx:8 →Rd8 2 ⎯⎯ 0 ⎯ 2 XOR.B Rs, Rd B Rd8 ⊕Rs8 →Rd8 2 ⎯⎯ 0 ⎯ 2 NOT.B Rd B Rd →Rd 2 ⎯⎯ 0 ⎯ 2 SHAL.B Rd B 2 ⎯⎯ 2 SHAR.B Rd B 2 ⎯⎯ 02 SHLL.B Rd B 2 ⎯⎯ 02 SHLR.B Rd B 2 ⎯⎯ 002 ROTXL.B Rd B 2 ⎯⎯ 02 ROTXR.B Rd B 2 ⎯⎯ 02 b7 b0 C b7 b0 b7 b0 b7 b0 C b7 b0 Cb7 b0 #xx: 8/16 Rn @Rn @(d:16, Rn) @−Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied No. of States Addressing Mode/ Instruction Length (bytes) Condition Code Operand Size

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 535 of 658 REJ09B0042-0800 Mnemonic Operation I H N Z V C ROTL.B Rd B 2 ⎯⎯ ROTR.B Rd B 2 ⎯⎯ 02 BSET Rn, Rd B (Rn8 of Rd8) ←12 ⎯⎯⎯⎯⎯⎯ 2 BCLR Rn, Rd B (Rn8 of Rd8) ←02 ⎯⎯⎯⎯⎯⎯ 2 (#xx:3 of Rd8) (#xx:3 of @Rd16) (#xx:3 of @aa:8) BNOT Rn, Rd B (Rn8 of Rd8) ← 2 ⎯⎯⎯⎯⎯⎯ 2 (Rn8 of Rd8) (Rn8 of @Rd16) (Rn8 of @aa:8) #xx: 8/16 Rn @Rn @(d:16, Rn) @−Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied No. of States Addressing Mode/ Instruction Length (bytes) Condition Code Operand Size C b7 b0 C b7 b0

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 536 of 658 REJ09B0042-0800 Mnemonic Operation I H N Z V C BTST #xx:3, Rd B ( #xx:3 of Rd8) →Z2 ⎯⎯⎯ ⎯⎯ 2 BTST #xx:3, @aa:8 B ( #xx:3 of @aa:8) →Z4 ⎯⎯⎯ ⎯⎯ 6 BTST Rn, Rd B ( Rn8 of Rd8) →Z2 ⎯⎯⎯ ⎯⎯ 2 BTST Rn, @Rd B ( Rn8 of @Rd16) →Z4 ⎯⎯⎯ ⎯⎯ 6 BTST Rn, @aa:8 B ( Rn8 of @aa:8) →Z4 ⎯⎯⎯ ⎯⎯ 6 BLD #xx:3, Rd B (#xx:3 of Rd8) →C2 ⎯⎯⎯⎯⎯ 2 BILD #xx:3, Rd B ( #xx:3 of Rd8) →C2 ⎯⎯⎯⎯⎯ 2 BIST #xx:3, Rd B C →(#xx:3 of Rd8) 2 ⎯⎯⎯⎯⎯⎯ 2 BAND #xx:3, Rd B C ∧(#xx:3 of Rd8) →C2 ⎯⎯⎯⎯⎯ 2 BIAND #xx:3, Rd B C ∧(#xx:3 of Rd8) →C2 ⎯⎯⎯⎯⎯ 2 BOR #xx:3, Rd B C ∨(#xx:3 of Rd8) →C2 ⎯⎯⎯⎯⎯ 2 BIOR #xx:3, Rd B C ∨(#xx:3 of Rd8) →C2 ⎯⎯⎯⎯⎯ 2 #xx: 8/16 Rn @Rn @(d:16, Rn) @−Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied No. of States Addressing Mode/ Instruction Length (bytes) Condition Code Operand Size

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 537 of 658 REJ09B0042-0800 Mnemonic Operation I H N Z V C BXOR #xx:3, Rd B C ⊕(#xx:3 of Rd8) →C2 2 BXOR #xx:3, @Rd B C ⊕(#xx:3 of @Rd16) →C4 6 BXOR #xx:3, @aa:8 B C ⊕(#xx:3 of @aa:8) →C4 6 BIXOR #xx:3, Rd B C ⊕(#xx:3 of Rd8) →C2 2 BIXOR #xx:3, @Rd B C ⊕(#xx:3 of @Rd16) →C4 6 BIXOR #xx:3, @aa:8 B C ⊕(#xx:3 of @aa:8) →C4 6 BRA d:8 (BT d:8) ⎯ PC ←PC+d:8 2 4 BRN d:8 (BF d:8) ⎯ PC ←PC+2 2 4 BHI d:8 ⎯ C ∨Z = 0 2 4 BLS d:8 ⎯ C ∨Z = 1 2 4 BCC d:8 (BHS d:8) ⎯ C = 0 2 4 BCS d:8 (BLO d:8) ⎯ C = 1 2 4 BNE d:8 ⎯ Z = 0 2 4 BEQ d:8 ⎯ Z = 1 2 4 BVC d:8 ⎯ V = 0 2 4 BVS d:8 ⎯ V = 1 2 4 BPL d:8 ⎯ N = 0 2 4 BMI d:8 ⎯ N = 1 2 4 BGE d:8 ⎯ N⊕V = 0 2 4 BLT d:8 ⎯ N⊕V = 1 2 4 BGT d:8 ⎯ Z ∨(N⊕V) = 0 24 BLE d:8 ⎯ Z ∨(N⊕V) = 1 24 JMP @Rn ⎯ PC ←Rn16 2 4 JMP @aa:16 ⎯ PC ←aa:16 4 6 JMP @@aa:8 ⎯ PC ←@aa:8 2 8 BSR d:8 ⎯ SP−2 →SP 2 6 PC →@SP PC ←PC+d:8 #xx: 8/16 Rn @Rn @(d:16, Rn) @−Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied No. of States Addressing Mode/ Instruction Length (bytes) Condition Code Operand Size If condition is true then PC ← PC+d:8 else next; Branching Condition

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 538 of 658 REJ09B0042-0800 Mnemonic Operation I H N Z V C PC →@SP PC ←Rn16 PC →@SP PC ←aa:16 PC →@SP PC ←@aa:8 RTS ⎯ SP+2 →SP RTE ⎯ CCR ←@SP 2 SP+2 →SP PC ←@SP SP+2 →SP SLEEP ⎯ Transit to sleep mode. 2 ⎯⎯⎯⎯⎯⎯ 2 LDC #xx:8, CCR B #xx:8 →CCR 2 2 LDC Rs, CCR B Rs8 →CCR 2 2 ANDC #xx:8, CCR B CCR ∧#xx:8 →CCR 2 2 ORC #xx:8, CCR B CCR ∨#xx:8 →CCR 2 2 XORC #xx:8, CCR B CCR ⊕#xx:8 →CCR 2 2 Repeat @R5 →@R6 R5+1 →R5 R6+1 →R6 R4L−1 →R4L Until R4L=0 else next; Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. (4) The number of states required for execution is 4n + 9 (n = value of R4L). 4n + 8 for HD64F38024, H8/38024S Group, and H8/38124 Group. (5) Set to 1 if the divisor is negative; otherwise cleared to 0. (6) Set to 1 if the divisor is zero; otherwise cleared to 0. #xx: 8/16 Rn @Rn @(d:16, Rn) @−Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied No. of States Addressing Mode/ Instruction Length (bytes) Condition Code Operand Size

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 539 of 658 REJ09B0042-0800 A.2 Operation Code Map Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 540 of 658 REJ09B0042-0800 Table A.2 Operation Code Map High Low 0123 4 56789A BC D EF A B C D E F NOP BRA MULXU BSET SHLL SHAL SLEEP BRN DIVXU BNOT SHLR SHAR STC BHI BCLR ROTXL ROTL LDC BLS BTST ROTXR ROTR ORC OR BCC RTS XORC XOR BCS BSR BOR BIOR BXOR BIXOR BAND BIAND ANDC AND BNE RTE LDC BEQ NOT NEG BLD BILD BST BIST ADD SUB BVC BVS MOV INC DEC BPL JMP ADDS SUBS BMI EEPMOV MOV CMP BGE BLT ADDX SUBX BGT JSR DAA DAS BLE MOV ADD ADDX CMP SUBX OR XOR AND MOV MOV* Note: * The PUSH and POP instructions are identical in machine language to MOV instructions. Bit-manipulation instructions

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 541 of 658 REJ09B0042-0800 A.3 Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A.4 indicates the number of states required for each cycle (instruction fetch, read/write, etc.), and table A.3 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I × S I + J × SJ + K × SK + L × SL + M × SM + N × SN Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. BSET #0, @FF00 From table A.4: From table A.3: S I = 2, SL = 2 Number of states required for execution = 2 × 2 + 2 × 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. JSR @@ 30 From table A.4: From table A.3: S I = SJ = SK = 2 Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8 Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (instruction cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch S I 2 — Branch address read S J Stack operation S K Byte data access S L 2 or 3 * Word data access S M — Internal operation S N 1 Note: * Depends on which on-chip module is accessed. See section 2.9.1, Notes on Data Access for details.

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 542 of 658 REJ09B0042-0800 Table A.4 Number of Cycles in Each Instruction Instruction Mnemonic Instruction Fetch I Branch Addr. Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W Rs, Rd 1 ADDS ADDS.W #1, Rd 1 ADDS.W #2, Rd 1 ADDX ADDX.B #xx:8, Rd 1 ADDX.B Rs, Rd 1 AND AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 ANDC ANDC #xx:8, CCR 1 BAND BAND #xx:3, Rd 1 BAND #xx:3, @Rd 2 1 BAND #xx:3, @aa:8 2 1 Bcc BRA d:8 (BT d:8) 2 BRN d:8 (BF d:8) 2 BHI d:8 2 BLS d:8 2 BCC d:8 (BHS d:8) 2 BCS d:8 (BLO d:8) 2 BNE d:8 2 BEQ d:8 2 BVC d:8 2 BVS d:8 2 BPL d:8 2 BMI d:8 2 BGE d:8 2 BLT d:8 2 BGT d:8 2 BLE d:8 2 BCLR BCLR #xx:3, Rd 1 BCLR #xx:3, @Rd 2 2 BCLR #xx:3, @aa:8 2 2 BCLR Rn, Rd 1 BCLR Rn, @Rd 2 2 BCLR Rn, @aa:8 2 2 BIAND BIAND #xx:3, Rd 1 BIAND #xx:3, @Rd 2 1 BIAND #xx:3, @aa:8 2 1

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 543 of 658 REJ09B0042-0800 Instruction Mnemonic Instruction Fetch I Branch Addr. Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N BILD BILD #xx:3, Rd 1 BILD #xx:3, @Rd 2 1 BILD #xx:3, @aa:8 2 1 BIOR BIOR #xx:3, Rd 1 BIOR #xx:3, @Rd 2 1 BIOR #xx:3, @aa:8 2 1 BIST BIST #xx:3, Rd 1 BIST #xx:3, @Rd 2 2 BIST #xx:3, @aa:8 2 2 BIXOR BIXOR #xx:3, Rd 1 BIXOR #xx:3, @Rd 2 1 BIXOR #xx:3, @aa:8 2 1 BLD BLD #xx:3, Rd 1 BLD #xx:3, @Rd 2 1 BLD #xx:3, @aa:8 2 1 BNOT BNOT #xx:3, Rd 1 BNOT #xx:3, @Rd 2 2 BNOT #xx:3, @aa:8 2 2 BNOT Rn, Rd 1 BNOT Rn, @Rd 2 2 BNOT Rn, @aa:8 2 2 BOR BOR #xx:3, Rd 1 BOR #xx:3, @Rd 2 1 BOR #xx:3, @aa:8 2 1 BSET BSET #xx:3, Rd 1 BSET #xx:3, @Rd 2 2 BSET #xx:3, @aa:8 2 2 BSET Rn, Rd 1 BSET Rn, @Rd 2 2 BSET Rn, @aa:8 2 2 BSR BSR d:8 2 1 BST BST #xx:3, Rd 1 BST #xx:3, @Rd 2 2 BST #xx:3, @aa:8 2 2 BTST BTST #xx:3, Rd 1 BTST #xx:3, @Rd 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @Rd 2 1

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 544 of 658 REJ09B0042-0800 Instruction Mnemonic Instruction Fetch I Branch Addr. Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N BTST BTST Rn, @aa:8 2 1 BXOR BXOR #xx:3, Rd 1 BXOR #xx:3, @Rd 2 1 BXOR #xx:3, @aa:8 2 1 CMP CMP. B #xx:8, Rd 1 CMP. B Rs, Rd 1 CMP.W Rs, Rd 1 DAA DAA.B Rd 1 DAS DAS.B Rd 1 DEC DEC.B Rd 1 DIVXU DIVXU.B Rs, Rd 1 12 EEPMOV EEPMOV 2 2n+2 * 1 * INC INC.B Rd 1 JMP JMP @Rn 2 JMP @aa:16 2 2 JMP @@aa:8 2 1 2 JSR JSR @Rn 2 1 JSR @aa:16 2 1 2 JSR @@aa:8 2 1 1 LDC LDC #xx:8, CCR 1 LDC Rs, CCR 1 MOV MOV.B #xx:8, Rd 1 MOV.B Rs, Rd 1 MOV.B @Rs, Rd 1 1 MOV.B @(d:16, Rs), Rd 2 1 MOV.B @Rs+, Rd 1 1 2 MOV.B @aa:8, Rd 1 1 MOV.B @aa:16, Rd 2 1 MOV.B Rs, @Rd 1 1 MOV.B Rs, @(d:16, Rd) 2 1 MOV.B Rs, @–Rd 1 1 2 MOV.B Rs, @aa:8 1 1 MOV.B Rs, @aa:16 2 1 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 MOV.W @Rs, Rd 1 1 MOV.W @(d:16, Rs), Rd 2 1 MOV.W @Rs+, Rd 1 1 2 MOV.W @aa:16, Rd 2 1 Note: * n: Initial value in R4L. The source and destination operands are accessed n + 1 times each. Internal operation N is 0 for HD64F38024, HD64F38024F, H8/38024S Group and H8/38124 Group.

Appendix A CPU Instruction Set Rev. 8.00 Mar. 09, 2010 Page 545 of 658 REJ09B0042-0800 Instruction Mnemonic Instruction Fetch I Branch Addr. Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N MOV MOV.W Rs, @Rd 1 1 MOV.W Rs, @(d:16, Rd) 2 1 MOV.W Rs, @–Rd 1 1 2 MOV.W Rs, @aa:16 2 1 MULXU MULXU.B Rs, Rd 1 12 NEG NEG.B Rd 1 NOP NOP 1 NOT NOT.B Rd 1 OR OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 ORC ORC #xx:8, CCR 1 ROTL ROTL.B Rd 1 ROTR ROTR.B Rd 1 ROTXL ROTXL.B Rd 1 ROTXR ROTXR.B Rd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL.B Rd 1 SHAR SHAR.B Rd 1 SHLL SHLL.B Rd 1 SHLR SHLR.B Rd 1 SLEEP SLEEP 1 STC STC CCR, Rd 1 SUB SUB.B Rs, Rd 1 SUB.W Rs, Rd 1 SUBS SUBS.W #1, Rd 1 SUBS.W #2, Rd 1 POP POP Rd 1 1 2 PUSH PUSH Rs 1 1 2 SUBX SUBX.B #xx:8, Rd 1 SUBX.B Rs, Rd 1 XOR XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XORC XORC #xx:8, CCR 1

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 546 of 658 REJ09B0042-0800 Appendix B Internal I/O Registers B.1 Addresses Upper Address: H'F0 Bit Names Lower Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'20 FLMCR1 — SWE ESU PSU EV PV E P ROM H'23 EBR — — — EB4 EB3 EB2 EB1 EB0 H ' 2 4 H ' 2 5 H ' 2 6 H ' 2 7 H ' 2 8 H ' 2 9 H ' 2 A H ' 2 C H ' 2 D H ' 2 E H ' 2 F

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 547 of 658 REJ09B0042-0800 Upper Address: H'FF Bit Names Lower Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H ' 8 0 H ' 8 1 H ' 8 2 H ' 8 3 H ' 8 4 H ' 8 5 H'86 LVDCR LVDE — VINTDSEL VINTUSEL LVDSL LVDRE LVDDE LVDUE H'87 LVDSR OVF — — — VREFSEL — LVDDF LVDUF Low-voltage detect circuit* H ' 8 8 H ' 8 9 H ' 8 A H ' 8 B H'8C ECPWCRH ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 Asynchronous H'8D ECPWCRL ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0 event counter H'8E ECPWDRH ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0 H'8F ECPWDRL ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0 H'90 WEGR WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 System control H'91 SPCR — — SPC32 — SCINV3 SCINV2 — — SCI3 H'92 AEGSR AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 AIEGS0 ECPWME — Asynchronous H'93 event counter H'94 ECCR ACKH1 ACKH0 ACKL1 ACKL0 PWCK2 PWCK1 PWCK0 — H'95 ECCSR OVH OVL — CH2 CUEH CUEL CRCH CRCL H'96 ECH ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 H'97 ECL ECL7 ECL6 ECL5 ECL4 ECL3 ECL2 ECL1 ECL0 H ' 9 8 H ' 9 9 H ' 9 A H ' 9 B H ' 9 C H ' 9 D H ' 9 E H ' 9 F

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 548 of 658 REJ09B0042-0800 Upper Address: H'FF Bit Names Lower Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H ' A 0 H ' A 1 H ' A 2 H ' A 3 H ' A 4 H ' A 5 H ' A 6 H ' A 7 H'A8 SMR COM CHR PE PM STOP MP CKS1 CKS0 SCI3 H'A9 BRR BRR7 BRR6 BRR5 B RR4 BRR3 BRR2 BRR1 BRR0 H'AA SCR3 TIE RIE TE RE — TEIE CKE1 CKE0 H'AB TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 H'AC SSR TDRE RDRF OER FER PER TEND — — H''AD RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 H ' A E H ' A F H'B0 TMA — — — — TMA3 TMA2 TMA1 TMA0 Timer A H'B1 TCA TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 H'B2 TCSRW B6WI TCWE B4WI TCSRWE B2WI WDON BOWI WRST Watchdog H'B3 TCW TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 timer H'B4 TMC TMC7 TMC6 TMC5 — — TMC2 TMC1 TMC0 Timer C H'B5 TCC/TLC TCC7/TLC7 TCC6/TLC6 TCC5/TLC5 TCC4/TLC4 TCC3/TLC3 TCC2/TLC2 TCC1/TLC1 TCC0/TLC0 H'B6 TCRF TOLH CKSH2 CKSH1 CKSH 0 TOLL CKSL2 CKSL1 CKSL0 Timer F H'B7 TCSRF OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL H'B8 TCFH TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0 H'B9 TCFL TCFL7 TCFL6 TCFL5 TCFL4 TCFL3 TCFL2 TCFL1 TCFL0 H'BA OCRFH OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 O CRFH2 OCRFH1 OCRFH0 H'BB OCRFL OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 H'BC TMG OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Timer G H'BD ICRGF ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 H'BE ICRGR ICRGR7 I CRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 H ' B F

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 549 of 658 REJ09B0042-0800 Upper Address: H'FF Bit Names Lower Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'C0 LPCR DTS1 DTS0 CMX — SGS3 SGS2 SGS1 SGS0 H'C1 LCR — PSW ACT DISP CKS3 CKS2 CKS1 CKS0 H'C2 LCR2 LCDAB — — — CDS3 * CDS2 * CDS1 * CDS0 * LCD controller/ driver H'C3 LVDCNT CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 Low-voltage detect circuit* H'C4 ADRRH ADR9 ADR8 ADR7 ADR6 A DR5 ADR4 ADR3 ADR2 A/D converter H'C5 ADRRL ADR1 ADR0 — — — — — — H'C6 AMR CKS TRGE — — CH3 CH2 CH1 CH0 H'C8 PMR1 IRQ3 — — IRQ4 TMIG — — — I/O port H'C9 PMR2 — — POF1 — — WDCKS NCS IRQ0 H'CA PMR3 AEVL AEVH — — — TMOFH TMOFL UD H ' C B H'CC PMR5 WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 H'CD PWCR2 — — — — — PWCR22 * PWCR21 PWCR20 10 bit PWM2 H'CE PWDRU2 — — — — — — PWDRU21 PWDRU20 H'CF PWDRL2 PWDRL27 PWDRL26 PWDRL25 PWDRL24 PWDRL23 PWDRL22 PWDRL21 PWDRL20 H'D0 PWCR1 — — — — — PWCR12 * PWCR11 PWCR10 10 bit PWM1 H'D1 PWDRU1 — — — — — — PWDRU11 PWDRU10 H'D2 PWDRL1 PWDRL17 PWDRL16 PWDRL15 PWDRL14 PWDRL13 PWDRL12 PWDRL11 PWDRL10 H ' D 3 H'D4 PDR1 P17 P16 — P14 P13 — — — I/O port H ' D 5 H'D6 PDR3 P37 P36 P35 P34 P33 P32 P31 P30 H'D7 PDR4 — — — — P43 P42 P41 P40 H'D8 PDR5 P57 P56 P55 P54 P53 P52 P51 P50 H'D9 PDR6 P67 P66 P65 P64 P63 P62 P61 P60 H'DA PDR7 P77 P76 P75 P74 P73 P72 P71 P70 H'DB PDR8 P87 P86 P85 P84 P83 P82 P81 P80 H'DC PDR9 — — P95 P94 P93 P92 P91 P90 H'DD PDRA — — — — PA3 PA2 PA1 PA0 H'DE PDRB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 H ' D F

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 550 of 658 REJ09B0042-0800 Upper Address: H'FF Bit Names Lower Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'E0 PUCR1 PUCR17 PUCR16 — PUCR14 PUCR13 — — — I/O port H'E1 PUCR3 PUCR37 PUCR36 PUCR35 P UCR34 PUCR33 PUCR32 PUCR31 PUCR30 H'E2 PUCR5 PUCR57 PUCR56 PUCR55 P UCR54 PUCR53 PUCR52 PUCR51 PUCR50 H'E3 PUCR6 PUCR67 PUCR66 PUCR65 P UCR64 PUCR63 PUCR62 PUCR61 PUCR60 H'E4 PCR1 PCR17 PCR16 — PCR14 PCR13 — — — H ' E 5 H'E6 PCR3 PCR37 PCR36 PCR35 P CR34 PCR33 PCR32 PCR31 PCR30 H'E7 PCR4 — — — — — PCR42 PCR41 PCR40 H'E8 PCR5 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 H'E9 PCR6 PCR67 PCR66 PCR65 P CR64 PCR63 PCR62 PCR61 PCR60 H'EA PCR7 PCR77 PCR76 PCR75 P CR74 PCR73 PCR72 PCR71 PCR70 H'EB PCR8 PCR87 PCR86 PCR85 P CR84 PCR83 PCR82 PCR81 PCR80 H'EC PMR9 — — — — PIOFF — PWM2 PWM1 H'ED PCRA — — — — PCRA 3 PCRA2 PCRA1 PCRA0 H ' E F H'F0 SYSCR1 SSBY STS2 STS1 STS0 LSON — MA1 MA0 System control H'F1 SYSCR2 — — — NESEL DTON MSON SA1 SA0 H'F2 IEGR — — — IEG4 IEG3 — IEG1 IEG0 H'F3 IENR1 IENTA — IENWP IEN4 IEN3 IENEC2 IEN1 IEN0 H'F4 IENR2 IENDT IENA D — IENTG IENTFH IE NTFL IENTC IENEC H'F5 OSCCR * SUBSTP — — — — IRQAECF OSCF — H'F6 IRR1 IRRTA — — IRRI4 IRRI3 IRREC2 IRRI1 IRRI0 H'F7 IRR2 IRRDT IRRAD — IRRTG IRRTFH IRRTFL IRRTC IRREC H'F8 TMW * — — — — CKS3 CKS2 CKS1 CKS0 Watchdog timer H'F9 IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 System control H'FA CKSTPR1 — — S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP H'FB CKSTPR2 — — — PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP H ' F C H ' F D H ' F E H ' F F [Legend] SCI: Serial Communication Interface Note: * H8/38124 only

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 551 of 658 REJ09B0042-0800 B.2 Functions Bit Initial value R/W W W W W W W W TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 W TCRF⎯Timer Control Register F H'B6 Timer F Toggle output level L Set to low level Set to high level 16-bit mode, counts on TCFL overflow signal Internal clock: φ/32 Internal clock: φ/16 Internal clock: φ/4 Internal clock: φw/4 Toggle output level H Set to low level Set to high level Clock select H Counts on external event (TMIF) rising/ falling edge Clock select L Internal clock: φ/32 Internal clock: φ/16 Internal clock: φ/4 Internal clock: φw/4 0 ** * Don't care R W R/W Read only Write only Read and write See relevant register Dashes (⎯) indicate undefined bits. Bit numbers Register acronym Register name Address to which the register is mapped. When displayed with two-digit number, this indicates the lower address, and the upper address is HFF. Name of on-chip supporting module Names of the bits. Dashes (⎯) indicate reserved bits. Full name of bit Descriptions of bit settings

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 552 of 658 REJ09B0042-0800 FLMCR1—Flash Memory Control Re gister 1 H'F020 Flash Memory Bit Initial value Read/Write SWE R/W ESU R/W P R/W PV R/W E R/W PSU R/W Program

0 Program mode cleared (initial value)

1 Transition to program mode

[Setting condition] When SWE = 1 and PSU = 1 Erase

0 Erase mode cleared (initial value)

1 Transition to erase mode

[Setting condition] When SWE = 1 and ESU = 1 Program-Verify

0 Program-verify mode cleared (initial value)

1 Transition to program-verify mode

[Setting condition] When SWE = 1 Erase-Verify

0 Erase-verify mode cleared (initial value)

1 Transition to erase-verify mode

[Setting condition] When SWE = 1 Program-Setup

0 Program-setup cleared (initial value)

1 Program setup

[Setting condition] When SWE = 1 Erase-Setup

0 Erase-setup cleared (initial value)

1 Erase setup

[Setting condition] When SWE = 1 Software write enable bit

0 Writing/erasing disabled (initial value)

1 Writing/erasing enabled

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 553 of 658 REJ09B0042-0800 FLMCR2—Flash Memory Control Re gister 2 H'F021 Flash Memory Bit Initial value Read/Write Note: A write to FLMCR2 is prohibited. FLER R Flash memory error FLPWCR—Flash Memory Power Control Register H'F022 Flash Memory Bit Initial value Read/Write PDWND R/W Power-down Disable

0 When the system transits to sub-active mode,

the flash memory changes to low-power mode

1 When the system transits to sub-active mode,

the flash memory changes to normal mode

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 554 of 658 REJ09B0042-0800 EBR—Erase Block Register H'F023 Flash Memory Bit Initial value Read/Write Note: Set the bit of EBR to H'00 when erasing. EB0 R/W EB2 R/W EB1 R/W EB4 R/W Blocks 4 to 0

0 When a block of EB4 to EB0 is not selected (initial value)

1 When a block of EB4 to EB0 is selected

FENR—Flash Memory Enable Register H'F02B Flash Memory Bit Initial value Read/Write FLSHE R/W Flash Memory Control Register Enable

0 The flash memory control register cannot be accessed

1 The flash memory control register can be accessed

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 555 of 658 REJ09B0042-0800 LVDCR—Low-Voltage Detection Control Register H'86 LVDC Note: This register is implemented on the H8/38124 Group only. Bit Initial value Read/Write Note: * These bits are not initialized by resets trigged by LVDR. They are initialized by power-on resets and watchdog timer resets. LVDE R/W R/W VINTDSEL R/W LVDUE R/W LVDRE R/W LVDDE R/W VINTUSEL R/W Voltage Rise Interrupt Enable Voltage Drop Interrupt Enable LVDR Detection Level Select 0 Reset detection voltage 2.3 V (typ.) (initial value) 1 Reset detection voltage 3.3 V (typ.) Power Supply Rise (LVDU) Detection Level External Input Select Power Supply Drop (LVDD) Detection Level External Input Select

1 Low-voltage detection circuit use

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 556 of 658 REJ09B0042-0800 LVDSR—Low-Voltage Detection Status Register H'87 LVDC Note: This register is implemented on the H8/38124 Group only. Bit Initial value Read/Write Note: * These bits initialized by resets trigged by LVDR. OVF R/W R/W R/W LVDUF R/W R/W LVDDF R/W R/W LVD Power Supply Voltage Rise Flag 0 [Clearing condition] (initial v alue) When 0 is written after reading 1 1 [Setting condition] When the power supply voltage drops below Vint(D) while the LVDUE bit in LVDCR is set to 1, and it rises above Vint(U) before dropping below Vreset1 LVD Power Supply Voltage Drop Flag 0 [Clearing condition] (initial value) When 0 is written after reading 1 1 [Setting condition] When the power supply voltage drops below Vint(D) Reference Voltage External Input Select

0 The on-chip circuit is used to generate the reference

voltage (initial value)

1 The reference voltage is input to the Vref pin from

LVD Reference Voltage Stabilized Flag 0 [Clearing condition] (initial value) When 0 is written after reading 1 1 [Setting condition] When the low-voltage detection counter (LVDCNT) overflows VREFSEL R/W

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 557 of 658 REJ09B0042-0800 ECPWCRH—Event Counter PWM Compare Register H H'8C AEC Bit Initial value R/W R/W R/W R/W R/W R/W R/W R/W ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 R/W Sets event counter PWM waveform conversion period ECPWCRL—Event Counter PWM Compare Register L H'8D AEC ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0 11111111 Bit Initial value R/W R/W R/W R/W R/W R/W R/W R/W R/W Sets event counter PWM waveform conversion period ECPWDRH—Event Counter PWM Data Register H H'8E AEC ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0 Bit Initial value R/W W W W W W W W W Controls event counter PWM waveform generator data ECPWDRL—Event Counter PWM Data Register L H'8F AEC Bit Initial value R/W 76543210 ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0 W W W W W W W W Controls event counter PWM waveform generator data

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 558 of 658 REJ09B0042-0800 WEGR—Wakeup Edge Select Register H'90 System Control Bit Initial value Read/Write WKEGS7 R/W WKEGS6 R/W WKEGS5 R/W WKEGS0 R/W WKEGS2 R/W WKEGS1 R/W WKEGS4 R/W WKPn Edge Selected

0 WKPn pin falling edge detected

(n = 7 to 0)

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 559 of 658 REJ09B0042-0800 SPCR—Serial Port Control Register H'91 SCI3 Bit Initial value Read/Write SPC32 R/W W SCINV2 R/W W W RXD32 Pin Input Data Inversion Switch

0 RXD32 input data is not inverted

TXD32 Pin Output Data Inversion Switch

0 TXD32 output data is not inverted

P42/TXD32 Pin Function Switch

0 Function as P42 I/O pin

1 Function as TXD 32 output pin

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 560 of 658 REJ09B0042-0800 AEGSR—Input Pin Edge Select Register H'92 AEC Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 AIEGS0 ECPWME ⎯ R/W Event Counter PWM Enable/Disable, IRQAEC Select/Deselect AEC PWM halted, IRQAEC selected AEC PWM operation enabled, IRQAEC deselected IRQAEC Edge Select Bit 2 AIEGS0 Bit 3 AIEGS1 Falling edge on IRQAEC pin is sensed Rising edge on IRQAEC pin is sensed Both edges on IRQAEC pin are sensed Use prohibited Falling edge on AEVL pin is sensed Rising edge on AEVL pin is sensed Both edges on AEVL pin are sensed Use prohibited Falling edge on AEVH pin is sensed Rising edge on AEVH pin is sensed Both edges on AEVH pin are sensed Use prohibited

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 561 of 658 REJ09B0042-0800 ECCR—Event Counter Control Register H'94 AEC Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W ACKH1 ACKH0 ACKL1 ACKL0 PWCK2 PWCK1 PWCK0 ⎯ R/W Event Counter PWM Clock Select Bit 2 PWCK1 Bit 3 PWCK2 φ/2 φ/4 φ/8 φ/16 φ/32 φ/64 *: Don't care Bit 1 PWCK0 AEC Clock Select L Bit 4 ACKL0 Bit 5 ACKL1 AEVL pin input φ/2 φ/4 φ/8 φ/2 φ/4 φ/8

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 562 of 658 REJ09B0042-0800 ECCSR—Event Counter Contro l/Status Register H'95 AEC Bit Initial value Read/Write OVH R/W OVL R/W R/W CRCL R/W CUEL R/W CRCH R/W CH2 R/W Counter Reset Control L ECL is reset ECL reset is cleared and count-up function is enabled Counter Reset Control H ECH is reset

1 ECH reset is cleared and

count-up function is enabled Count-up Enable L 0 ECL event clock input is disabled. ECL value is held 0 ECH event clock input is disabled. ECH value is held

0 ECH and ECL are used together as a single-

channel 16-bit event counter

1 ECH and ECL are used as two independent

8-bit event counter channels Counter Overflow L

0 ECL has not overflowed

0 ECH has not overflowed

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 563 of 658 REJ09B0042-0800 ECH—Event Counter H H'96 AEC Bit Initial value Read/Write ECH7 R ECH6 R ECH5 R ECH0 R ECH2 R ECH1 R ECH4 R Count value ECH3 R Note: ECH and ECL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (EC). ECL—Event Counter L H'97 AEC Bit Initial value Read/Write ECL7 R ECL6 R ECL5 R ECL0 R ECL2 R ECL1 R ECL4 R ECL3 R Count value Note: ECH and ECL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (EC).

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 564 of 658 REJ09B0042-0800 SMR—Serial Mode Register H'A8 SCI3 Bit Initial value Read/Write COM R/W CHR R/W PE R/W CKS0 R/W MP R/W CKS1 R/W PM R/W Clock Select φ clock φw/2 clock 0 φ/16 clock φ/64 clock

5 Bit Communication

05 bits communication disabled 1 5 bits communication enabled Stop Bit Length 0 1 stop bit 1 2 stop bits Parity Mode

0 Even parity

1 Odd parity

0 Par ity bit addition and checking disabled

1 Parity bit addition and checking enabled

0 Asynchronous mode

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 565 of 658 REJ09B0042-0800 BRR—Bit Rate Register H'A9 SCI3 Bit Initial value Read/Write BRR7 R/W BRR6 R/W BRR5 R/W BRR4 R/W BRR3 R/W BRR0 R/W BRR2 R/W BRR1 R/W Serial transmit/receive bit rate

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 566 of 658 REJ09B0042-0800 SCR3—Serial Control Register 3 H'AA SCI3 Bit Initial value Read/Write TIE R/W RIE R/W TE R/W CKE0 R/W TEIE R/W CKE1 R/W RE R/W Receive Interrupt Enable 0R e c eive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled

1 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled

0 Transmit operation disabled (TXD32 pin is I/O port)

1 Transmit operation enabled (TXD32 pin is transmit data pin)

0R e c eive operation disabled (RXD32 pin is I/O port)

1 Receive operation enabled (RXD32 pin is receive data pin)

Transmit End Interrupt Enable Clock Enable Bit 1 CKE1 Bit 0 CKE0 Communication Mode Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Internal clock Internal clock Internal clock Reserved (Do not specify this combination) External clock External clock Reserved (Do not specify this combination) Reserved (Do not specify this combination) I/O port Serial clock output Clock output Clock input Serial clock input Clock Source SC K32 Pin Function Transmit end interrupt request (TEI) disabled

1 Transmit end interrupt request (TEI) enabled

0 Transmit data empty interrupt request (TXI) disabled

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 567 of 658 REJ09B0042-0800 TDR—Transmit Data Register H'AB SCI3 Bit Initial value Read/Write TDR7 R/W TDR6 R/W TDR5 R/W TDR4 R/W TDR3 R/W TDR0 R/W TDR2 R/W TDR1 R/W Data for transfer to TSR

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 568 of 658 REJ09B0042-0800 SSR—Serial Status Register H'AC SCI3 Bit Initial value Read/Write Note: * Only a write of 0 for flag clearing is possible. TDRE R/(W)* RDRF R/(W)* OER R/(W)* R/W TEND R R FER R/(W)* Receive Data Register Full

0 There is no receive data in RDR

[Clearing conditions] · After reading RDRF = 1, cleared by writing 0 to RDRF

• When RDR data is read by an instruction

[Setting condition] When reception ends normally and receive data is transferred from RSR to RDR Transmit Data Register Empty [Clearing conditions] · After reading TDRE = 1, cleared by writing 0 to TDRE

• When data is written to TDR by an instruction 1 Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR [Setting conditions] · When bit TE in serial control register3 (SCR3) is cleared to 0
• When data is transferred from TDR to TSR Transmit End

[Clearing conditions]

1 Transmission ended

[Setting conditions] Parity Error

0 Recept ion in progress or completed normally

[Clearing condition] After reading PER = 1, cleared by writing 0 to PER

1 A parity error has occurred during reception

[Setting condition] Framing Error

0 Reception in progress or completed normally

[Clearing condition] After reading FER = 1, cleared by writing 0 to FER [Setting condition] When the stop bit at the end of the receive data is checked for a value of 1 at completion of reception, and the stop bit is 0 Overrun Error

0 Reception in progress or completed

[Clearing condition] After reading OER = 1, cleared by writing 0 to OER

1 An overrun error has occurred during reception

[Setting condition] When the next serial reception is completed with RDRF set to 1 PER R/(W)*

• After reading TDRE = 1, cleared by writing 0 to TDRE
• When data is written to TDR by an instruction
• When bit TE in serial control register3 (SCR3) is cleared to 0
• When bit TDRE is set to 1 when the last bit of a transmit character is sent When the number of 1 bits in the receive data plus parity bit does not match the parity designated by the parity mode bit (PM) in the serial mode register (SMR)

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 569 of 658 REJ09B0042-0800 RDR—Receive Data Register H'AD SCI3 Bit Initial value Read/Write RDR7 R RDR6 R RDR5 R RDR4 R RDR3 R RDR0 R RDR2 R RDR1 R Serial receiving data are stored TMA—Timer Mode Register A H'B0 Timer A Bit Initial value Read/Write W W W TMA0 R/W TMA2 R/W TMA1 R/W Internal Clock Select TMA3 TMA2

0 PSS

1 PSW

Prescaler and Divider Ratio or Overflow Period φ/8192 φ/4096 φ/2048 φ/512 φ/256 φ/128 φ/32 φ/8 1 s 0.5 s 0.25 s 0.03125 s Interval timer Clock time base (when using 32.768 kHz) Function TMA3 R/W

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 570 of 658 REJ09B0042-0800 TCA—Timer Counter A H'B1 Timer A Bit Initial value Read/Write TCA7 R TCA6 R TCA5 R TCA4 R TCA3 R TCA0 R TCA2 R TCA1 R Count value

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 571 of 658 REJ09B0042-0800 TCSRW—Timer Control/Status Register W H'B2 Watchdog Timer Bit Initial value Read/Write B6WI R TCWE R/(W)*1 B4WI R B2WI R WRST R/(W)*1 WDON 0*2 R/(W)*1 BOWI R TCSRWE R/(W)*1 Watchdog Timer Reset When TCSRWE = 1, and 0 is written in both B0WI and WRST When TCW overflows and an internal reset signal is generatedWatchdog Timer On

0 Watchdog timer operation is disabled

Clearing conditions: Reset* 2, or 0 is written in both B2WI and WDON while TCSRWE = 1 Setting condition: 0 is written in B2WI and 1 is written in WDON while TCSRWE = 1 Bit 0 Write Inhibit

1 Bit 0 is write-disabled

1 Bit 2 is write-disabled

Timer Control/Status Register W Write Enable

0 Data cannot be written to bits 2 and 0

1 Bit 4 is write-disabled

Timer Counter W Write Enable 0 8-bit data cannot be written to TCW 1 8-bit data can be written to TCW Bit 6 Write Inhibit

1 Bit 6 is write-disabled

Notes: 1. Write is permitted only under certain conditions. 2. 1 on the H8/38124 Group.

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 572 of 658 REJ09B0042-0800 TCW—Timer Counter W H'B3 Watchdog Timer Bit Initial value Read/Write TCW7 R/W TCW6 R/W TCW5 R/W TCW3 R/W TCW0 R/W TCW2 R/W TCW1 R/W TCW4 R/W Count value TMC—Timer Mode Register C H'B4 Timer C Bit Initial value Read/Write TMC7 R/W TMC6 R/W TMC5 R/W TMC0 R/W TMC2 R/W TMC1 R/W Clock Select 000 100 Internal clock: φ/8192 Internal clock: φ/2048 Internal clock: φ/512 Internal clock: φ/64 Internal clock: φ/16 Internal clock: φ/4 Internal clock: φW/4 External event (TMIC): rising or falling edge Counter Up/Down Control

0 TCC is an up-counter

1 TCC is a down-counter

1 * Hardware control of TCC up/down operation by UD pin input UD pin input high: Down-counter UD pin input low: Up-counter Auto-Reload Function Select

0 Interval timer function selected

*: Don't care

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 573 of 658 REJ09B0042-0800 TCC—Timer Counter C H'B5 Timer C Bit Initial value Read/Write Note: TCC is allocated to the same address as TLC. In a read, the TCC value is returned. TCC7 R TCC6 R TCC5 R TCC3 R TCC0 R TCC2 R TCC1 R TCC4 R Count value TLC—Timer Load Register C H'B5 Timer C Bit Initial value Read/Write Note: TLC is allocated to the same address as TCC. In a write, the value is written to TLC. TLC7 W TLC6 W TLC5 W TLC3 W TLC0 W TLC2 W TLC1 W TLC4 W Reload value

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 574 of 658 REJ09B0042-0800 TCRF—Timer Control Register F H'B6 Timer F Bit Initial value Read/Write TOLH W CKSH2 W CKSH1 W CKSL0 W CKSL2 W CKSL1 W CKSH0 W Clock Select L Do not specify this combination Internal clock φ/32 Internal clock φ/16 Internal clock φ/4 Internal clock φw/4 Counting on external event (TMIF) rising/falling edge Toggle Output Level L

0 Low level

W Clock Select H

0 Except

Do not specify this combination Internal clock φ/32 Internal clock φ/16 Internal clock φ/4 Internal clock φw/4 16-bit mode, counting on TCFL overflow signal 011 Except for 11

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 575 of 658 REJ09B0042-0800 TCSRF—Timer Control/Status Register F H'B7 Timer F Bit Initial value Read/Write Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. OVFH R/(W)* CMFH R/(W)* OVIEH R/W CCLRL R/W CMFL R/(W)* OVIEL R/W CCLRH R/W Compare Match Flag H After reading CMFH = 1, cleared by writing 0 to CMFH Set when the TCFH value matches the OCRFH value Timer Overflow Flag H After reading OVFH = 1, cleared by writing 0 to OVFH Set when TCFH overflows from H'FF to H'00 Compare Match Flag L After reading CMFL = 1, cleared by writing 0 to CMFL Set when the TCFL value matches the OCRFL value Timer Overflow Flag L After reading OVFL = 1, cleared by writing 0 to OVFL Set when TCFL overflows from H'FF to H'00 Counter Clear H 0 16-bit mode: TCF clearing by compare match is disabled 8-bit mode: TCFH clearing by compare match is disabled 1 16-bit mode: TCF clearing by compare match is enabled 8-bit mode: TCFH clearing by compare match is enabled Timer Overflow Interrupt Enable H

0 TCFH overflow interrupt request is disabled

Timer Overflow Interrupt Enable L Counter Clear L

0 TCFL overflow interrupt request is disabled

0 TCFL clearing by compare match is disabled

R/(W)*

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 576 of 658 REJ09B0042-0800 TCFH—8-Bit Timer Counter FH H'B8 Timer F Bit Initial value Read/Write TCFH7 R/W TCFH6 R/W TCFH5 R/W TCFH4 R/W TCFH3 R/W TCFH0 R/W TCFH2 R/W TCFH1 R/W Count value Note: TCFH and TCFL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (TCF). TCFL—8-Bit Timer Counter FL H'B9 Timer F Bit Initial value Read/Write TCFL7 R/W TCFL6 R/W TCFL5 R/W TCFL4 R/W TCFL3 R/W TCFL0 R/W TCFL2 R/W TCFL1 R/W Count value Note: TCFH and TCFL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (TCF). OCRFH—Output Compare Register FH H'BA Timer F Bit Initial value Read/Write OCRFH7 R/W OCRFH6 R/W OCRFH5 R/W OCRFH4 R/W OCRFH3 R/W OCRFH0 R/W OCRFH2 R/W OCRFH1 R/W Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (OCRF).

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 577 of 658 REJ09B0042-0800 OCRFL—Output Compare Register FL H'BB Timer F Bit Initial value Read/Write OCRFL7 R/W OCRFL6 R/W OCRFL5 R/W OCRFL4 R/W OCRFL3 R/W OCRFL0 R/W OCRFL2 R/W OCRFL1 R/W Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (OCRF).

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 578 of 658 REJ09B0042-0800 TMG—Timer Mode Register G H'BC Timer G Bit Initial value Read/Write OVFH R/(W)* OVFL R/(W)* OVIE R/W CCLR1 R/W CKS0 R/W CCLR0 R/W CKS1 R/W IIEGS R/W Timer Overflow Flag L After reading OVFL = 1, cleared by writing 0 to OVFL Set when TCG overflows from H'FF to H'00 Timer Overflow Flag H After reading OVFH = 1, cleared by writing 0 to OVFH Set when TCG overflows from H'FF to H'00 Input Capture Interrupt Edge Select

0 Interrupt generated on rising edge of input capture

1 Interrupt generated on falling edge of input capture

Timer Overflow Interrupt Enable

0 TCG overflow interrupt request is disabled

0 Internal clock: counting on φ/640

1 Internal clock: counting on φ/32

1 0 Internal clock: counting on φ/2

1 Internal clock: counting on φW/4

0 TCG clearing is disabled0

1 TCG cleared by falling edge of input capture

1 0 TCG cleared by rising edge of input capture input signal

1 TCG cleared by both edges of input capture

Note: * Bits 7 and 6 can only be written with 0, for flag clearing.

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 579 of 658 REJ09B0042-0800 ICRGF—Input Capture Register GF H'BD Timer G Bit Initial value Read/Write ICRGF7 R ICRGF6 R ICRGF5 R ICRGF3 R ICRGF0 R ICRGF2 R ICRGF1 R ICRGF4 R Stores TCG value at falling edge of input capture signal ICRGR—Input Capture Register GR H'BE Timer G Bit Initial value Read/Write ICRGR7 R ICRGR6 R ICRGR5 R ICRGR3 R ICRGR0 R ICRGR2 R ICRGR1 R ICRGR4 R Stores TCG value at rising edge of input capture signal

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 580 of 658 REJ09B0042-0800 LPCR—LCD Port Control Register H'C0 LCD Controller/Driver Duty Select, Common Function Select Bit 7 DTS1 Bit 6 DTS0 Bit 5 CMX Duty Cycle Static 1/2 duty 1/3 duty 1/4 duty Common Drivers COM COM4 to COM1 COM2 to COM1 COM4 to COM1 COM3 to COM1 COM4 to COM1 COM4 to COM1 Do not use COM4 to COM2 COM4 to COM2 output the same waveform as COM1 Do not use COM4 and COM3 COM4 outputs the same waveform as COM3 and COM2 outputs the same waveform as COM1 Do not use COM4 Do not use COM4 Notes Bit Initial value Read/Write DTS1 R/W DTS0 R/W CMX R/W SGS0 R/W SGS2 R/W SGS1 R/W W Segment Driver Select SGS3 R/W Port Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port Bit 3 SGS3 Bit 2 SGS2 Bit 1 SGS1 Bit 0 SGS0 SEG32 to SEG29 SEG28 to SEG25 SEG24 to SEG21 SEG20 to SEG17 SEG16 to SEG13 SEG12 to SEG9 SEG8 to SEG5 Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port Port SEG4 to SEG1 Function of Pins SEG32 to SEG1 Note (Initial value)

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 581 of 658 REJ09B0042-0800 LCR—LCD Control Register H'C1 LCD Controller/Driver Bit Initial value Read/Write PSW R/W ACT R/W CKS3 R/W CKS0 R/W CKS2 R/W CKS1 R/W DISP R/W LCD Drive Power Supply On/Off Control Frame Frequency Select Operating ClockBit 1Bit 2Bit 3 Bit 1 CKS1CKS2CKS3 CKS0 φw φw/2 φw/4 φ/2 φ/4 φ/8 φ/16 φ/32 φ/64 φ/128 φ/256 Display Function Activate LCD controller/driver operation halted LCD controller/driver operates *: Don't care

0 LCD drive power supply off

0 Blank data is displayed

1 LCD RAM data is displayed

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 582 of 658 REJ09B0042-0800 LCR2—LCD Control Register 2 H'C2 LCD Bit Initial value Read/Write LCDAB R/W CDS3 R/W CDS0 R/W CDS2 R/W CDS1 R/W W A Waveform/B Waveform Switching Control

0 Drive using A waveform

Removal of Split-Resistance Control CDS3 Split-resistance condition Other than the above CDS2 CDS1 CDS0 Split-resistance connected Note: The removal of split-resistance control is only implemented on the H8/38124 Group. LVDCNT—Low-Voltage Detect Counter H' C3 Low-Voltage Detect Circuit Note: This register is implemented on the H8/38124 Group only. Bit Initial value Read/Write CNT7 R CNT6 R CNT5 R CNT3 R CNT0 R CNT2 R CNT1 R CNT4 R Count value

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 583 of 658 REJ09B0042-0800 AMR—A/D Mode Register H'C6 A/D Converter Bit Initial value Read/Write CKS R/W TRGE R/W CH3 R/W CH0 R/W CH2 R/W CH1 R/W Channel Select No channel selected Bit 3 Bit 2 Analog Input Channel *: Don't care CH3 CH2 CH1 CH0 Bit 1 Bit 0 0A N 1 00 External Trigger Select

0 Disables start of A/D conversion by external trigger

1 Enables start of A/D conversion by rising or falling edge

of external trigger at pin ADTRG AN5 AN6 AN **1 1 Do not specify this combination 100 AN0 AN1 AN2 AN3 Clock Select 62/φ Bit 7 Conversion PeriodCKS 31/φ1 62 μs φ = 1 MHz 31 μs 12.4 μs φ = 5 MHz ⎯*1 6.2 μs φ = 10 MHz*2 ⎯*1 Conversion Time Notes: 1. Except for the H8/38124 Group, operation cannot be guaranteed if the conversion time is less than 12.4 µs. Make sure to select a setting that gives a conversion time of 12.4 µs or more in such cases. For the H8/38124 Group select a setting that gives a conversion time of 6.2 µs or more. 2. H8/38124 Group only.

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 584 of 658 REJ09B0042-0800 ADRRH—A/D Result Register H H'C4 A/D Converter ADRRL—A/D Result Register L H'C5 Bit Initial value Read/Write ADRRH ADR9 Undefined R ADR8 Undefined R ADR7 Undefined R ADR5 Undefined R ADR2 Undefined R ADR4 Undefined R ADR3 Undefined R ADR6 Undefined R A/D conversion result Bit Initial value Read/Write ADRRL ADR1 Undefined R ADR0 Undefined R A/D conversion result ADSR—A/D Start Register H'C7 A/D Converter Bit Initial value Read/Write ADSF R/W A/D Start Flag Read Write Read Write Indicates completion of A/D conversion Stops A/D conversion Indicates A/D conversion in progress Starts A/D conversion

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 585 of 658 REJ09B0042-0800 PMR1—Port Mode Register 1 H'C8 I/O Port Bit Initial value Read/Write IRQ3 R/W W TMIG R/W W W IRQ4 R/W P13/TMIG Pin Function Switch

0 Functions as P1 3 I/O pin

P14/IRQ4/ADTRG Pin Function Switch

0 Functions as P1 4 I/O pin

P17/IRQ3/TMIF Pin Function Switch

0 Functions as P1 7 I/O pin

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 586 of 658 REJ09B0042-0800 PMR2—Port Mode Register 2 H'C9 I/O Port Bit Initial value Read/Write Note: * On the H8/38124 Group the clock source can be selected using the TMW register. POF1 R/W IRQ0 R/W WDCKS R/W NCS R/W P43/IRQ0 Pin Function Switch

0 Functions as P4 3 I/O pin

TMIG Noise Canceller Select

0 Noise cancellation function not used

1 Noise cancellation function used

0 Selects φ8192*

P35 Pin Output Buffer PMOS On/Off Control

0 CMOS output

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 587 of 658 REJ09B0042-0800 PMR3—Port Mode Register 3 H'CA I/O Port Bit Initial value Read/Write AEVL R/W AEVH R/W W W UD R/W TMOFH R/W TMOFL R/W W P32/TMOFH Pin Function Switch

0 Functions as P3 2 I/O pin

P31/TMOFL Pin Function Switch

0 Functions as P3 1 I/O pin

P30/UD Pin Function Switch

0 Functions as P3 0 I/O pin

P36/AEVH Pin Function Switch

0 Functions as P3 6 I/O pin

Functions as AEVH input pin1 P37/AEVL Pin Function Switch

0 Functions as P3 7 I/O pin

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 588 of 658 REJ09B0042-0800 PMR5—Port Mode Register 5 H'CC I/O Port Bit Initial value Read/Write WKP7 R/W WKP6 R/W WKP5 R/W WKP3 R/W WKP0 R/W WKP2 R/W WKP1 R/W WKP4 R/W

0 Functions as P5 n I/O pin

(n = 7 to 0) P5n/WKPn/SEGn+1 Pin Function Switch PWCR2—PWM2 Control Register H'CD 10-Bit PWM Clock Select The input clock is φ (tφ* 1 = 1/φ) The conversion period is 512/φ, with a minimum modulation width of 1/2φ The input clock is φ/2 (tφ*1 = 2/φ) The conversion period is 1,024/φ, with a minimum modulation width of 1/φ The input clock is φ/4 (tφ*1 = 4/φ) The conversion period is 2,048/φ, with a minimum modulation width of 2/φ The input clock is φ/8 (tφ*1 = 8/φ) The conversion period is 4,096/φ, with a minimum modulation width of 4/φ Notes: 1. t φ: Period of PWM2 input clock 2. 1 on products other than the H8/38124 Group Bit Initial value Read/Write PWCR20 W PWCR22 0*2 R/W PWCR21 W 0 10-bit PWM PWH Output Select (H8/38124 Group only)

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 589 of 658 REJ09B0042-0800 PWDRU2—PWM2 Data Register U H'CE 10-Bit PWM Bit Initial value Read/Write W ⎯⎯⎯⎯ PWDRU21 PWDRU20 W Upper 2 bits of PWM2 waveform generation data PWDRL2—PWM2 Data Register L H'CF 10-Bit PWM Lower 8 bits of PWM2 waveform generation data Bit Initial value Read/Write PWDRL27 W PWDRL26 W PWDRL25 W PWDRL23 W PWDRL20 W PWDRL22 W PWDRL21 W PWDRL24 W

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 590 of 658 REJ09B0042-0800 PWCR1—PWM1 Control Register H'D0 10-Bit PWM Bit Initial value Read/Write PWCR10 W PWCR12 0*2 R/W PWCR11 W Clock Select

0 The input clock is φ (tφ*1 = 1/φ)

The conversion period is 512/φ, with a minimum modulation width of 1/2φ The input clock is φ/2 (tφ*1 = 2/φ) The conversion period is 1,024/φ, with a minimum modulation width of 1/φ

1 The input clock is φ/4 (tφ*1 = 4/φ)

The conversion period is 2,048/φ, with a minimum modulation width of 2/φ The input clock is φ/8 (tφ*1 = 8/φ) The conversion period is 4,096/φ, with a minimum modulation width of 4/φ Notes: 1. t φ: Period of PWM1 input clock 2. 1 on products other than the H8/38124 Group 0 10-bit PWM PWH Output Select (H8/38124 Group only)

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 591 of 658 REJ09B0042-0800 PWDRU1—PWM1 Data Register U H'D1 10-Bit PWM Bit Initial value Read/Write W W Upper 2 bits of data for generating PWM1 waveform ⎯⎯⎯ PWDRU10⎯ PWDRU11 PWDRL1—PWM1 Data Register L H'D2 10-Bit PWM Bit Initial value Read/Write W W W W W W W W Lower 8 bits of data for generating PWM1 waveform PWDRL15 PWDRL14 PWDRL13 PWDRL10PWDRL12 PWDRL11PWDRL16PWDRL17 PDR1—Port Data Register 1 H'D4 I/O Ports Bit Initial value Read/Write P17 R/W Data for port 1 pins Note: * P16 is not equipped with H8/38124 Group. P16* R/W R/W R/W PDR3—Port Data Register 3 H'D6 I/O Ports Bit Initial value Read/Write R/W R/W R/W R/W R/W P30 R/W R/W R/W 234567 1 Data for port 3 pins

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 592 of 658 REJ09B0042-0800 PDR4—Port Data Register 4 H'D7 I/O Ports Bit Initial value Read/Write R R/W R/W R/W 30 21 Data for port 4 pins Reads P43 state PDR5—Port Data Register 5 H'D8 I/O Ports Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 30 214567 Data for port 5 pins PDR6—Port Data Register 6 H'D9 I/O Ports Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 30 214567 Data for port 6 pins PDR7—Port Data Register 7 H'DA I/O Ports Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 32 1 04567 Data for port 7 pins

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 593 of 658 REJ09B0042-0800 PDR8—Port Data Register 8 H'DB I/O Ports Bit Initial value Read/Write P87 R/W P86 R/W P85 R/W P84 R/W P83 R/W P80 R/W P82 R/W P81 R/W Data for port 8 pins PDR9—Port Data Register 9 H'DC I/O Ports Bit Initial value Read/Write P95 R/W P94 R/W P93 R/W P90 R/W P92 R/W P91 R/W Data for port 9 pins PDRA—Port Data Register A H'DD I/O Ports Bit Initial value Read/Write PA R/W PA R/W PA R/W PA R/W 30 21 Data for port A pins PDRB—Port Data Register B H'DE I/O Ports Bit Read/Write PB7 R PB6 R PB5 R PB4 R PB3 R PB0 R PB2 R PB1 R Read port B pin states

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 594 of 658 REJ09B0042-0800 PUCR1—Port Pull-Up Control Register 1 H'E0 I/O Ports Bit Initial value Read/Write PUCR17 R/W PUCR16* R/W Input pull-up MOS is off Input pull-up MOS is on W PUCR1 R/W W W W PUCR1 R/W Port 1 Input Pull-up MOS Control Note: When the PCR1 specification is 0. (Input port specification) Note: * PUCR16 is not equipped with H8/38124 Group. PUCR3—Port Pull-Up Control Register 3 H'E1 I/O Ports Bit Initial value Read/Write PUCR3 R/W PUCR3 R/W PUCR3 R/W PUCR3 R/W PUCR3 R/W PUCR3 R/W PUCR3 R/W PUCR3 R/W 234567 10 Input pull-up MOS is off Input pull-up MOS is on Port 3 Input Pull-up MOS Control Note: When the PCR3 specification is 0. (Input port specification)

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 595 of 658 REJ09B0042-0800 PUCR5—Port Pull-Up Control Register 5 H'E2 I/O Ports Bit Initial value Read/Write PUCR5 R/W PUCR5 R/W PUCR5 R/W PUCR5 R/W PUCR5 R/W PUCR5 R/W PUCR5 R/W PUCR5 R/W 30 214567 Input pull-up MOS is off Input pull-up MOS is on Port 5 Input Pull-up MOS Control Note: When the PCR5 specification is 0. (Input port specification) PUCR6—Port Pull-Up Control Register 6 H'E3 I/O Ports Bit Initial value Read/Write PUCR6 R/W PUCR6 R/W PUCR6 R/W PUCR6 R/W PUCR6 R/W PUCR6 R/W PUCR6 R/W PUCR6 R/W 30 214567 Input pull-up MOS is off Input pull-up MOS is on Port 6 Input Pull-up MOS Control Note: When the PCR6 specification is 0. (Input port specification)

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 596 of 658 REJ09B0042-0800 PCR1—Port Control Register 1 H'E4 I/O Ports Bit Initial value Read/Write PCR17 W PCR16* W W PCR1 W W W W PCR1 W Port 1 Input/Output Select

0 Input pin

1 Output pin

Note: * PCR16 is not equipped with H8/38124 Group. PCR3—Port Control Register 3 H'E6 I/O Ports Bit Initial value Read/Write PCR3 W PCR3 W PCR3 W PCR3 W PCR3 W PCR3 W PCR3 W PCR3 W Port 3 Input/Output Select PCR4—Port Control Register 4 H'E7 I/O Ports Bit Initial value Read/Write PCR4 W PCR4 W PCR4 W Port 4 Input/Output Select

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 597 of 658 REJ09B0042-0800 PCR5—Port Control Register 5 H'E8 I/O Ports Bit Initial value Read/Write PCR5 W PCR5 W PCR5 W PCR5 W PCR5 W PCR5 W PCR5 W PCR5 W Port 5 Input/Output Select PCR6—Port Control Register 6 H'E9 I/O Ports Bit Initial value Read/Write PCR6 W PCR6 W PCR6 W PCR6 W PCR6 W PCR6 W PCR6 W PCR6 W Port 6 Input/Output Select PCR7—Port Control Register 7 H'EA I/O Ports Bit Initial value Read/Write PCR7 W PCR7 W PCR7 W PCR7 W PCR7 W PCR7 W PCR7 W PCR7 W Port 7 Input/Output Select

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 598 of 658 REJ09B0042-0800 PCR8—Port Control Register 8 H'EB I/O Ports Bit Initial value Read/Write PCR87 W PCR86 W PCR85 W PCR84 W PCR83 W PCR8 W PCR82 W PCR81 W Port 8 Input/Output Select PMR9—Port Mode Register 9 H'EC I/O Ports P90/PWM1 Pin Function Switch Functions as P90 output pin Functions as PWM1 output pin P91/PWM2 Pin Function Switch Functions as P91 output pin Functions as PWM2 output pin P92 to P90 Step-up Circuit Control Large-current port step-up circuit is turned on Large-current port step-up circuit is turned off Bit Initial value Read/Write Note: * Readable/writable reserved bit in the H8/38024S Group and H8/38124 Group. PIOFF/⎯* R/W PWM1 R/W W PWM2 R/W

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 599 of 658 REJ09B0042-0800 PCRA—Port Control Register A H'ED I/O Ports Bit Initial value Read/Write PCRA W PCRA W PCRA W PCRA W 0123 Port A Input/Output Select PMRB—Port Mode Register B H'EE I/O Ports Bit Initial value Read/Write IRQ1 R/W

0 Functions as PB 3/AN3 input pin

1 Functions as IRQ1 input pin

PB3/AN3/IRQ1 Pin Function Switch

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 600 of 658 REJ09B0042-0800 SYSCR1—System Control Register 1 H'F0 System Control Bit Initial value Read/Write Notes: 1. Applies to products other than the H8/38124 Group. 2. Applies to the H8/38124 Group. SSBY R/W STS2 R/W STS1 R/W LSON R/W MA0 R/W MA1 R/W STS0 R/W Software Standby 0  When a SLEEP instruction is executed in active mode, a transition is made to sleep mode Standby Timer Select 2 to 0

0 Wait time = 8,192 states *1

Wait time = 16,384 states*1 0 0 Wait time = 1,024 states*1 Wait time = 2,048 states*1 Active (medium-speed) Mode Clock Select φosc/16 φosc/32 1 φosc/64 φosc/128 Wait time = 4,096 states*1 Wait time = 2 states*1 Wait time = 8 states*1 Wait time = 16 states*1 Wait time = 8,192 states*2 Wait time = 16,384 states*2 Wait time = 32,768 states*2 Wait time = 65,536 states*2 Wait time = 131,072 states*2 Wait time = 2 states*2 Wait time = 8 states*2 Wait time = 16 states*2 Low Speed on Flag

0 The CPU operates on the system clock ( φ)

1 The CPU operates on the subclock ( φ )SUB

 When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode  When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode  When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 601 of 658 REJ09B0042-0800 SYSCR2—System Control Register 2 H'F1 System Control Bit Initial value Read/Write DTON R/W SA0 R/W MSON R/W SA1 R/W NESEL R/W Subactive Mode Clock Select 0 φW/8 φW/4 1 φW/2* Direct Transfer on Flag 0  When a SLEEP instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode  When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode  When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1  When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1  When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1 Medium Speed on Flag

0 Operates in active (high-speed) mode

1 Operates in active (medium-speed) mode

Noise Elimination Sampling Frequency Select

1 Sampling rate is φOSC/4

*: Don't care

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 602 of 658 REJ09B0042-0800 IEGR—IRQ Edge Select Register H'F2 System Control Bit Initial value Read/Write IEG4 R/W IEG3 R/W IEG0 R/W W IEG1 R/W IRQ0 Edge Select

0 Falling edge of IRQ0 pin input is detected

Rising edge of IRQ0 pin input is detected1 IRQ1 Edge Select

0 Falling edge of IRQ1, TMIC pin input is detected

Rising edge of IRQ1, TMIC pin input is detected1 IRQ3 Edge Select

0 Falling edge of IRQ3, TMIF pin input is detected

Rising edge of IRQ3, TMIF pin input is detected1 IRQ4 Edge Select

0 Falling edge of IRQ4, ADTRG pin input is detected

Rising edge of IRQ4, ADTRG pin input is detected1

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 603 of 658 REJ09B0042-0800 IENR1—Interrupt Enable Regist er 1 H'F3 System Control Bit Initial value Read/Write IENTA R/W W IEN4 R/W IEN3 R/W IEN0 R/W IENEC2 R/W IEN1 R/W IENWP R/W IRQAEC Interrupt Enable

0 Disables IRQAEC interrupt requests

Enables IRQAEC interrupt requests1 IRQ4 and IRQ3 Interrupt Enable

0 Disables IRQ4 and IRQ3 interrupt requests

Enables IRQ4 and IRQ3 interrupt requests1 Timer A Interrupt Enable

0 Disables timer A interrupt requests

Enables timer A interrupt requests1 Wakeup Interrupt Enable

0 Disables WKP7 to WKP0 interrupt requests

Enables WKP7 to WKP0 interrupt requests1 IRQ1 to IRQ0 Interrupt Enable

0 Disables IRQ1 to IRQ0 interrupt, requests

Enables IRQ1 to IRQ0 interrupt requests1

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 604 of 658 REJ09B0042-0800 IENR2—Interrupt Enable Regist er 2 H'F4 System Control Bit Initial value Read/Write IENDT R/W IENAD R/W W IENTFH R/W IENEC R/W IENTFL R/W IENTC R/W IENTG R/W Asynchronous Event Counter Interrupt Enable

0 Disables asynchronous event

counter interrupt requests

1 Enables asynchronous event

counter interrupt requests Timer FL Interrupt Enable

0 Disables timer FL interrupt requests

0 Disables timer FH interrupt requests

0 Disables timer C interrupt requests

0 Disables timer G interrupt requests

A/D Converter Interrupt Enable

0 Disables A/D converter interrupt requests

Direct Transition Interrupt Enable

0 Disables direct transition interrupt requests

1 Enables direct transition interrupt requests

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 605 of 658 REJ09B0042-0800 OSCCR—Clock Pulse Generator Control Re gister H'F5 Clock Pulse Generator Note: This register is implemented on the H8/38124 Group only. Bit Initial value Read/Write SUBSTP R/W R R/W R/W IRQAECF R OSCF R R/W OSC Flag

0 Operation using system clock oscillator (on-chip oscillator stopped)

1 Operation using on-chip oscillator (system clock oscillator stopped)

1 IRQAEC pin set to VCC during resets

Subclock Oscillator Stop Control

0 Subclock oscillator operating (initial value)

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 606 of 658 REJ09B0042-0800 IRR1—Interrupt Request Register 1 H'F6 System Control Bit Initial value Read/Write IRRTA R/(W)* W IRRI3 R/(W)* IRRI0 R/(W)* IRREC2 R/(W)* IRRI1 R/(W)* IRRI4 R/(W)* IRQ1 and IRQ0 Interrupt Request Flags When IRRIn = 1, it is cleared by writing 0 (n = 1 or 0) Note: * Bits 7 and 4 to 0 can only be written with 0, for flag clearing. When pin IRQn is designated for interrupt input and the designated signal edge is input IRQ4 and IRQ3 Interrupt Request Flags When IRRIm = 1, it is cleared by writting 0 (m = 4 or 3) When pin IRQm is designated for interrupt input and the designated signal edge is input Timer A Interrupt Request Flag When IRRTA = 1, it is cleared by writing 0 When the timer A counter value overflows (from H'FF to H'00) IRQAEC Interrupt Request Flag When IRREC2 = 1, it is cleared by writing 0 When pin IRQAEC is designated for interrupt input and the designated signal edge is input

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 607 of 658 REJ09B0042-0800 IRR2—Interrupt Request Register 2 H'F7 System Control Bit Initial value Read/Write IRRDT R/(W)* IRRAD R/(W)* W IRRTFH R/(W)* IRREC R/(W)* IRRTFL R/(W)* IRRTC R/(W)* IRRTG R/(W)* Note: * Bits 7, 6, and 4 to 0 can only be written with 0, for flag clearing. A/D Converter Interrupt Request Flag When IRRAD = 1, it is cleared by writing 0 When the A/D converter completes conversion and ADSF is reset Direct Transition Interrupt Request Flag When IRRDT = 1, it is cleared by writing 0 When a SLEEP instruction is executed while DTON is set to 1, and a direct transition is made Timer FH Interrupt Request Flag When IRRTFH = 1, it is cleared by writing 0

1 Setting conditions:

When counter FH and output compare register FH match in 8-bit timer mode, or when 16-bit counters FL and FH and output compare registers FL and FH match in 16-bit timer mode Timer FL Interrupt Request Flag When IRRTFL = 1, it is cleared by writing 0 When counter FL and output compare register FL match in 8-bit timer mode Timer G Interrupt Request Flag When IRRTG = 1, it is cleared by writing 0 When the TMIG pin is designated for TMIG input and the designated signal edge is input, and when TCG overflows while OVIE is set to 1 in TMG Timer C Interrupt Request Flag When IRRTC = 1, it is cleared by writing 0 When the timer C counter value overflows (from H'FF to H'00) or underflows (from H'00 to H'FF) Asynchronous Event Counter Interrupt Request Flag When IRREC = 1, it is cleared by writing 0 When the asynchronous event counter value overflows

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 608 of 658 REJ09B0042-0800 TMW—Timer Mode Register W H'F8 Watchdog Timer Note: This register is implemented on the H8/38124 Group only. Bit Initial value Read/Write CKS3 R/W CKS0 R/W CKS2 R/W CKS1 R/W Internal Clock Select CDS3 Clock source CDS2 CDS1 CDS0 0 φ/64 1001 φ/128 1010 φ/256 1011 φ/512 1100 φ/1024 1101 φ/2048 1110 φ/4096 1111 φ/8192 0 *** On-chip oscillator Note: Valid when WDCKS bit in PMR2 register is cleared to 0.

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 609 of 658 REJ09B0042-0800 IWPR—Wakeup Interrupt Request Register H'F9 System Control Bit Initial value Read/Write IWPF7 R/(W)* IWPF6 R/(W)* IWPF5 R/(W)* IWPF3 R/(W)* IWPF0 R/(W)* IWPF2 R/(W)* IWPF1 R/(W)* IWPF4 R/(W)* When IWPFn = 1, it is cleared by writing 0 (n = 7 to 0) Note: * All bits can only be written with 0, for flag clearing. Wakeup Interrupt Request Register When pin WKPn is designated for wakeup input and a falling edge is input at that pin

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 610 of 658 REJ09B0042-0800 CKSTPR1—Clock Stop Register 1 H'FA System Control Bit Initial value Read/Write S32CKSTP R/W TGCKSTP R/W TACKSTP R/W TFCKSTP R/W TCCKSTP R/W ADCKSTP R/W Timer A Module Standby Mode Control Timer F Module Standby Mode Control Timer F module standby mode is cleared1 A/D Converter Module Standby Mode Control A/D converter module standby mode is cleared1 Timer A module standby mode is cleared1 Timer C Module Standby Mode Control Timer C module standby mode is cleared1 Timer G Module Standby Mode Control Timer G module standby mode is cleared1 SCI3 Module Standby Mode Control SCI3 module standby mode is cleared1

Appendix B Internal I/O Registers Rev. 8.00 Mar. 09, 2010 Page 611 of 658 REJ09B0042-0800 CKSTPR2—Clock Stop Register 2 H'FB System Control Bit Initial value Read/Write LVDCKSTP* R/W AECKSTP R/W LDCKSTP R/W WDCKSTP R/W PW1CKSTP R/W PW2CKSTP R/W LCD Module Standby Mode Control PWM2 Module Standby Mode Control PWM2 module standby mode is cleared1 LVD Module Standby Mode Control LVD module standby mode is cleared Note: * Control using the LVDCKST bit is implemented on the H8/38124 Group only. Asynchronous Event Counter Module Standby Mode Control Asynchronous event counter module standby mode is cleared1 PWM1 Module Standby Mode Control PWM1 module standby mode is cleared1 WDT Module Standby Mode Control

0 WDT is set to module standby mode

WDT module standby mode is cleared1 LCD module standby mode is cleared1

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 612 of 658 REJ09B0042-0800 Appendix C I/O Port Block Diagrams C.1 Block Diagrams of Port 1 P1n VCC VCC PUCR1n PMR1n PDR1n PCR1n Internal data bus SBY (low level during reset and in standby mode) V SS IRQm PDR1: PCR1: PMR1: PUCR1: n = 7 and 4 m = 4 and 3 Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C.1(a) Port 1 Block Diagram (Pins P17 and P14)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 613 of 658 REJ09B0042-0800 VCC VCC SBY (low level during reset and in standby mode) VSS PUCR16 PMR16 PDR16 PCR16 Internal data bus P16 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C.1(b) Port 1 Block Diagram (Pin P16, Products other than H8/38124 Group)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 614 of 658 REJ09B0042-0800 VCC VCC SBY VSS PUCR13 PMR13 PDR13 PCR13 Timer G module TMIG Internal data bus P13 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C.1(c) Port 1 Block Diagram (Pin P13)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 615 of 658 REJ09B0042-0800 C.2 Block Diagrams of Port 3 P3n VCC VCC PUCR3n PMR3n PDR3n PCR3n AEC module Internal data bus SBY VSS AEVH(P36) AEVL(P37) PDR3: PCR3: PMR3: PUCR3: Port data register 3 Port control register 3 Port mode register 3 Port pull-up control register 3 n = 7 and 6 Figure C.2(a) Port 3 Block Diagram (Pins P37 and P36)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 616 of 658 REJ09B0042-0800 P35 VCC VCC PUCR35 PMR25 PDR35 PCR35 SBY VSS Internal data bus PDR3: PCR3: PUCR3: PMR2 Port data register 3 Port control register 3 Port pull-up control register 3 Port mode register 2 Figure C.2(b) Port 3 Block Diagram (Pin P35)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 617 of 658 REJ09B0042-0800 P3n PDR3n PUCR3n PCR3n SBY VSS PDR3: Port data register 3 PCR3: Port control register 3 n = 4 and 3 Internal data bus VCCVCC Figure C.2(c) Port 3 Block Diagram (Pins P34 and P33)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 618 of 658 REJ09B0042-0800 P3n VCC VCC PUCR3n Internal data bus PMR3n PDR3n PCR3n SBY VSS PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 n = 2 and 1 TMOFH (P32) TMOFL (P31) Figure C.2(d) Port 3 Block Diagram (Pins P32 and P31)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 619 of 658 REJ09B0042-0800 VCC VCC VSS PUCR30 PDR30 PCR30 UD SBY Internal data bus PDR3: PCR3: PMR3: PUCR3: Port data register 3 Port control register 3 Port mode register 3 Port pull-up control register 3 Timer C module PMR30 Figure C.2(e) Port 3 Block Diagram (Pin P30)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 620 of 658 REJ09B0042-0800 C.3 Block Diagrams of Port 4 P43 PMR20 Internal data bus IRQ0 PMR2: Port mode register 2 Figure C.3(a) Port 4 Block Diagram (Pin P43)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 621 of 658 REJ09B0042-0800 P42 SCI3 module Internal data bus PDR42 SCINV3 PCR42 SBY VSS PDR4: Port data register 4 PCR4: Port control register 4 TXD32 VCC SPC32 Figure C.3(b) Port 4 Block Diagram (Pin P42)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 622 of 658 REJ09B0042-0800 P41 VCC SCI3 module PDR41 PCR41 SBY VSS PDR4: Port data register 4 PCR4: Port control register 4 RE32 RXD32 Internal data bus SCINV2 Figure C.3(c) Port 4 Block Diagram (Pin P41)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 623 of 658 REJ09B0042-0800 P40 VCC SCI3 module PDR40 PCR40 SBY VSS PDR4: Port data register 4 PCR4: Port control register 4 SCKIE32 SCKOE32 SCKO32 Internal data bus SCKI32 Figure C.3(d) Port 4 Block Diagram (Pin P40)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 624 of 658 REJ09B0042-0800 C.4 Block Diagram of Port 5 P5n VCC VCC PUCR5n Internal data bus PMR5n PDR5n PCR5n SBY* VSS WKPn PDR5: Port data register 5 PCR5: Port control register 5 PMR5: Port mode register 5 PUCR5: Port pull-up control register 5 n = 7 to 0 Note: * The value of SBY is fixed at 1 in the HD64F38024. Figure C.4 Port 5 Block Diagram

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 625 of 658 REJ09B0042-0800 C.5 Block Diagram of Port 6 P6n VCC VCC PUCR6n PDR6n Internal data bus PCR6n SBY VSS PDR6: Port data register 6 PCR6: Port control register 6 PUCR6: Port pull-up control register 6 n = 7 to 0 Figure C.5 Port 6 Block Diagram

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 626 of 658 REJ09B0042-0800 C.6 Block Diagram of Port 7 P7n VCC PDR7n Internal data bus PCR7n SBY VSS PDR7: Port data register 7 PCR7: Port control register 7 n = 7 to 0 Figure C.6 Port 7 Block Diagram

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 627 of 658 REJ09B0042-0800 C.7 Block Diagram of Port 8 P8n VCC PDR8n Internal data bus PCR8n SBY VSS PDR8: PCR8: n = 7 to 0 Port data register 8 Port control register 8 Figure C.7 Port 8 Block Diagram

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 628 of 658 REJ09B0042-0800 C.8 Block Diagrams of Port 9 P9n PDR9n PMR9n SBY VSS PDR9: n = 1 and 0 Port data register 9 PWM module PWMn+1 Internal data bus Figure C.8(a) Port 9 Block Diagram (Pins P91 and P90) P9n PDR9n SBY VSS PDR9: n = 5 to 2 Port data register 9 Internal data bus Figure C.8(b) Port 9 Block Diagram (Pins P95 to P92)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 629 of 658 REJ09B0042-0800 P93 PDR93 LVD module VREFSEL Vref SBY VSS PDR9: Port data register 9 Internal data bus Figure C.8(c) Port 9 Block Diagram (Pins P93, H8/38124 Group only)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 630 of 658 REJ09B0042-0800 C.9 Block Diagram of Port A PAn VCC PDRAn Internal data bus PCRAn SBY VSS PDRA: Port data register A PCRA: Port control register A n = 3 to 0 Figure C.9 Port A Block Diagram

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 631 of 658 REJ09B0042-0800 C.10 Block Diagrams of Port B PBn Internal data bus AMR3 to AMR0 A/D module VIN n = 7 to 0 DEC Figure C.10(a) Port B Block Diagram

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 632 of 658 REJ09B0042-0800 PB0 Internal data bus AMR3 to AMR0 A/D module VIN VINTDSEL LVD module extD DEC Figure C.10(b) Port B Block Diagram (Pin PB0, H8/38124 Group only)

Appendix C I/O Port Block Diagrams Rev. 8.00 Mar. 09, 2010 Page 633 of 658 REJ09B0042-0800 PB1 Internal data bus AMR3 to AMR0 A/D module VIN VINTUSEL LVD module extU DEC Figure C.10(c) Port B Block Diagram (Pin PB1, H8/38124 Group only)

Appendix D Port States in the Different Processing States Rev. 8.00 Mar. 09, 2010 Page 634 of 658 REJ09B0042-0800 Appendix D Port States in the Different Processing States Table D.1 Port States Overview Port Reset Sleep Subsleep Standby Watch Subactive Active P17, P16*3, P14, P13 High impedance Retained Retained High impedance*1 Retained Functions Functions P37 to P30 High impedance Retained Retained High impedance*1 Retained Functions Functions P43 to P40 High impedance Retained Retained High impedance Retained Functions Functions P57 to P50 High impedance Retained Retained High impedance*1 *2 Retained Functions Functions P67 to P60 High impedance Retained Retained High impedance*1 Retained Functions Functions P77 to P70 High impedance Retained Retained High impedance Retained Functions Functions P87 to P80 High impedance Retained Retained High impedance Retained Functions Functions P95 to P90 High impedance Retained Retained High impedance*1 Retained Functions Functions PA3 to PA0 High impedance Retained Retained High impedance Retained Functions Functions PB7 to PB0 High impedance High impedance High impedance High impedance High impedance High impedance High impedance Notes: 1. High level output when MOS pull-up is in on state. 2. In the HD64F38024 the previous pin state is retained. 3. Not implemented on H8/38124 Group.

Appendix E List of Product Codes Rev. 8.00 Mar. 09, 2010 Page 635 of 658 REJ09B0042-0800 Appendix E List of Product Codes Table E.1 H8/38024 Group Product Code Lineup Product Type Part No. Mark Code Package (Package Code) H8/38024 HD64338024H HD64338024( *)H 80-pin QFP (FP-80A) H8/38024 Group Mask ROM versions Regular specifications HD64338024F HD64338024( *)F 80-pin QFP (FP-80B) HD64338024W HD64338024( *)W 80-pin TQFP (TFP-80C) HCD64338024 — Die HD64338024D HD64338024( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338024E HD64338024( *)F 80-pin QFP (FP-80B) HD64338024WI HD64338024( *)W 80-pin TQFP (TFP-80C) HD64738024H HD64738024H 80-pin QFP (FP-80A) ZTAT versions Regular specifications HD64738024F HD64738024F 80-pin QFP (FP-80B) HD64738024W HD64738024W 80-pin TQFP (TFP-80C) HD64738024D HD64738024H 80-pin QFP (FP-80A) Wide-range specifications HD64738024E HD64738024F 80-pin QFP (FP-80B) HD64738024WI HD64738024W 80-pin TQFP (TFP-80C) HD64F38024H HD64F38024H 80-pin QFP (FP-80A) F-ZTAT versions Regular specifications HD64F38024RH HD64F38024H HD64F38024F HD64F38024F 80-pin QFP (FP-80B) HD64F38024RF HD64F38024F HD64F38024W HD64F38024W 80-pin TQFP (TFP-80C) HD64F38024RW HD64F38024W HD64F38024RLPV F38024RLPV 85-pin TFLGA (TLP-85V) HCD64F38024 — Die HCD64F38024R — HD64F38024D HD64F38024H 80-pin QFP (FP-80A) Wide-range specifications HD64F38024RD HD64F38024H HD64F38024E HD64F38024F 80-pin QFP (FP-80B) HD64F38024RE HD64F38024F HD64F38024WI HD64F38024W 80-pin TQFP (TFP-80C) HD64F38024RWI HD64F38024W HD64F38024RLPIV F38024RLPIV 85-pin TFLGA (TLP-85V)

Appendix E List of Product Codes Rev. 8.00 Mar. 09, 2010 Page 636 of 658 REJ09B0042-0800 Product Type Part No. Mark Code Package (Package Code) H8/38023 HD64338023H HD64338023( *)H 80-pin QFP (FP-80A) H8/38024 Group Mask ROM versions Regular specifications HD64338023F HD64338023( *)F 80-pin QFP (FP-80B) HD64338023W HD64338023( *)W 80-pin TQFP (TFP-80C) HCD64338023 — Die HD64338023D HD64338023( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338023E HD64338023( *)F 80-pin QFP (FP-80B) HD64338023WI HD64338023( *)W 80-pin TQFP (TFP-80C) H8/38022 HD64338022H HD64338022( *)H 80-pin QFP (FP-80A) Mask ROM versions Regular specifications HD64338022F HD64338022( *)F 80-pin QFP (FP-80B) HD64338022W HD64338022( *)W 80-pin TQFP (TFP-80C) HCD64338022 — Die HD64338022D HD64338022( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338022E HD64338022( *)F 80-pin QFP (FP-80B) HD64338022WI HD64338022( *)W 80-pin TQFP (TFP-80C) H8/38021 HD64338021H HD64338021( *)H 80-pin QFP (FP-80A) Mask ROM versions Regular specifications HD64338021F HD64338021( *)F 80-pin QFP (FP-80B) HD64338021W HD64338021( *)W 80-pin TQFP (TFP-80C) HCD64338021 — Die HD64338021D HD64338021( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338021E HD64338021( *)F 80-pin QFP (FP-80B) HD64338021WI HD64338021( *)W 80-pin TQFP (TFP-80C) H8/38020 HD64338020H HD64338020( *)H 80-pin QFP (FP-80A) Mask ROM versions Regular specifications HD64338020F HD64338020( *)F 80-pin QFP (FP-80B) HD64338020W HD64338020( *)W 80-pin TQFP (TFP-80C) HCD64338020 — Die HD64338020D HD64338020( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338020E HD64338020( *)F 80-pin QFP (FP-80B) HD64338020WI HD64338020( *)W 80-pin TQFP (TFP-80C)

Appendix E List of Product Codes Rev. 8.00 Mar. 09, 2010 Page 637 of 658 REJ09B0042-0800 Product Type Part No. Mark Code Package (Package Code) H8/38024S HD64338024SH HD64338024( *)H 80-pin QFP (FP-80A) H8/38024S Group Mask ROM versions Regular specifications HD64338024SW HD64338024( *)W 80-pin TQFP (TFP-80C) HD64338024SLPV 338024S( *)LPV 85-pin TFLGA (TLP-85V) HCD64338024S — Die HD64338024SD HD64338024( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338024SWI HD64338024( *)W 80-pin TQFP (TFP-80C) HD64338024SLPIV 338024S( *)LPIV 85-pin TFLGA (TLP-85V) H8/38023S HD64338023SH HD64338023( *)H 80-pin QFP (FP-80A) Mask ROM versions Regular specifications HD64338023SW HD64338023( *)W 80-pin TQFP (TFP-80C) HD64338023SLPV 338023S( *)LPV 85-pin TFLGA (TLP-85V) HCD64338023S — Die HD64338023SD HD64338023( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338023SWI HD64338023( *)W 80-pin TQFP (TFP-80C) HD64338023SLPIV 338023S( *)LPIV 85-pin TFLGA (TLP-85V) H8/38022S HD64338022SH HD64338022( *)H 80-pin QFP (FP-80A) Mask ROM versions Regular specifications HD64338022SW HD64338022( *)W 80-pin TQFP (TFP-80C) HD64338022SLPV 338022S( *)LPV 85-pin TFLGA (TLP-85V) HCD64338022S — Die HD64338022SD HD64338022( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338022SWI HD64338022( *)W 80-pin TQFP (TFP-80C) HD64338022SLPIV 338022S( *)LPIV 85-pin TFLGA (TLP-85V) H8/38021S HD64338021SH HD64338021( *)H 80-pin QFP (FP-80A) Mask ROM versions Regular specifications HD64338021SW HD64338021( *)W 80-pin TQFP (TFP-80C) HD64338021SLPV 338021S( *)LPV 85-pin TFLGA (TLP-85V) HCD64338021S — Die HD64338021SD HD64338021( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338021SWI HD64338021( *)W 80-pin TQFP (TFP-80C) HD64338021SLPIV 338021S( *)LPIV 85-pin TFLGA (TLP-85V) H8/38020S HD64338020SH HD64338020( *)H 80-pin QFP (FP-80A) Mask ROM versions Regular specifications HD64338020SW HD64338020( *)W 80-pin TQFP (TFP-80C) HD64338020SLPV 338020S( *)LPV 85-pin TFLGA (TLP-85V) HCD64338020S — Die HD64338020SD HD64338020( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338020SWI HD64338020( *)W 80-pin TQFP (TFP-80C) HD64338020SLPIV 338020S( *)LPIV 85-pin TFLGA (TLP-85V)

Appendix E List of Product Codes Rev. 8.00 Mar. 09, 2010 Page 638 of 658 REJ09B0042-0800 Product Type Part No. Mark Code Package (Package Code) H8/38124 HD64F38124H F38124H 80-pin QFP (FP-80A) H8/38124 Group F-ZTAT versions Regular specifications HD64F38124W F38124W 80-pin TQFP (TFP-80C) HD64F38124HW F38124H 80-pin QFP (FP-80A) Wide-range specifications HD64F38124WW F38124W 80-pin TQFP (TFP-80C) HD64338124H 38124( *)H 80-pin QFP (FP-80A) Mask ROM versions Regular specifications HD64338124W 38124( *)W 80-pin TQFP (TFP-80C) HD64338124HW 38124( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338124WW 38124( *)W 80-pin TQFP (TFP-80C) H8/38123 HD64338123H 38123( *)H 80-pin QFP (FP-80A) Mask ROM versions Regular specifications HD64338123W 38123( *)W 80-pin TQFP (TFP-80C) HD64338123HW 38123( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338123WW 38123( *)W 80-pin TQFP (TFP-80C) H8/38122 HD64F38122H F38122H 80-pin QFP (FP-80A) F-ZTAT versions Regular specifications HD64F38122W F38122W 80-pin TQFP (TFP-80C) HD64F38122HW F38122H 80-pin QFP (FP-80A) Wide-range specifications HD64F38122WW F38122W 80-pin TQFP (TFP-80C) HD64338122H 38122( *)H 80-pin QFP (FP-80A) Mask ROM versions Regular specifications HD64338122W 38122( *)W 80-pin TQFP (TFP-80C) HD64338122HW 38122( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338122WW 38122( *)W 80-pin TQFP (TFP-80C) H8/38121 HD64338121H 38121( *)H 80-pin QFP (FP-80A) Mask ROM versions Regular specifications HD64338121W 38121( *)W 80-pin TQFP (TFP-80C) HD64338121HW 38121( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338121WW 38121( *)W 80-pin TQFP (TFP-80C) H8/38120 HD64338120H 38120( *)H 80-pin QFP (FP-80A) Mask ROM versions Regular specifications HD64338120W 38120( *)W 80-pin TQFP (TFP-80C) HD64338120HW 38120( *)H 80-pin QFP (FP-80A) Wide-range specifications HD64338120WW 38120( *)W 80-pin TQFP (TFP-80C) Note: ( ***) is the ROM code.

Appendix F Package Dimensions Rev. 8.00 Mar. 09, 2010 Page 639 of 658 REJ09B0042-0800 Appendix F Package Dimensions Dimensional drawings of the H8/38024 Group, H8/38024S Group, and H8/38124 Group packages FP-80A, FP-80B, and TFP-80C are shown in figures F.1, F.2, and F.3 below. NOTE) DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 1.10.80.5 MaxNomMin Dimension in Millimeters Symbol Reference 2.70 17.517.216.9 1.6 HD ZD bp HE ZE e HE L D E HD A bp c x y ZD ZE θ 16.9 17.2 17.5 0.250.10 0.15 0.30 0.00 0.400.320.24 0.220.170.12 3.05 8°0° 0.65 0.12 0.10 0.83 0.83 Previous CodeJEITA Package Code RENESAS Code PRQP0080JB-A FP-80A/FP-80AV MASS[Typ.] 1.2gP-QFP80-14x14-0.65 Detail F c A L Terminal cross section c Mx 4160 F S S y e D E θ bp A1 A2 Figure F.1 FP-80A Package Dimensions

Appendix F Package Dimensions Rev. 8.00 Mar. 09, 2010 Page 640 of 658 REJ09B0042-0800 NOTE) DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 2.4 24.4 24.8 25.2 2.70 Reference Symbol Dimension in Millimeters Min Nom Max 1.0 1.2 1.4 e HE L D E HD A bp c x y ZD ZE θ 18.818.4 19.2 3.10 0.12 0.17 0.22 0.29 0.37 0.45 0.00 0.35 0.15 0.20 0.30 0° 10° 0.8 0.15 0.15 0.8 1.0 θ bp A1 A2 Previous CodeJEITA Package Code RENESAS Code PRQP0080GD-B FP-80B/FP-80BV MASS[Typ.] 1.7gP-QFP80-14x20-0.80 Detail F c A L Terminal cross section c xM F S S y D E e HD ZD bp HE ZE Figure F.2 FP-80B Package Dimensions

Appendix F Package Dimensions Rev. 8.00 Mar. 09, 2010 Page 641 of 658 REJ09B0042-0800 NOTE) DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 0.60.50.4 MaxNomMin Dimension in Millimeters Symbol Reference 1.00 14.214.013.8 1.0 e HE L D E HD A bp c x y ZD ZE θ 13.8 14.0 14.2 1.20 0.00 0.10 0.20 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0° 8° 0.5 0.10 0.10 1.25 1.25 Previous CodeJEITA Package Code RENESAS Code PTQP0080KC-A TFP-80C/TFP-80CV MASS[Typ.] 0.4gP-TQFP80-12x12-0.50 Detail F c A L Terminal cross section c S S y Index mark F Mx 60 41 e E D HD ZD bp HE ZE θ bp A1 A2 Figure F.3 TFP-80C Package Dimensions

Appendix F Package Dimensions Rev. 8.00 Mar. 09, 2010 Page 642 of 658 REJ09B0042-0800 B A Bw SAw S S yS 1yS v 123 4 56789 1 0 A B C D E F G H J K A PTLG0085JA-AP-TFLGA85-7x7-0.65 D E D E SD SE ZD ZE Z D Z E MASS[Typ.] 0.1gTLP-85V RENESAS CodeJEITA Package Code Prev ious Code 0.15 0.20 0.2y1 0.575 0.575 w v 0.08 7.0 1.20 0.400.350.30 0.65 0.10 7.0 y x b A Reference Symbol Dimension in Millimeters Min Nom Max e e e BASφ × bφ M Figure F.4 TLP-85V Package Dimensions

Appendix G Specifications of Chip Form Rev. 8.00 Mar. 09, 2010 Page 643 of 658 REJ09B0042-0800 Appendix G Specifications of Chip Form The specifications of the chip form of the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 are shown in figure G.1. The specifications of the chip form of the HCD64F38024 and HCD64F38024R are shown in figure G.2. The specifications of the chip form of the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S are shown in figure G.3. X-direction: 3.99 ± 0.05 Y-direction: 3.99 ± 0.05 Maximum plain X-direction: 3.99 ± 0.25 Y-direction: 3.99 ± 0.25 0.28 ± 0.02 Max 0.03 Unit: mm Figure G.1 Chip Sectional Figure of the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 X-direction: 3.84 ± 0.05 Y-direction: 4.24 ± 0.05 Maximum plain X-direction: 3.84 ± 0.25 Y-direction: 4.24 ± 0.25 0.28 ± 0.02 Max 0.03 Unit: mm Figure G.2 Chip Sectional Figure of the HCD64F38024 and HCD64F38024R

Appendix G Specifications of Chip Form Rev. 8.00 Mar. 09, 2010 Page 644 of 658 REJ09B0042-0800 X-direction: 2.91 ± 0.05 Y-direction: 2.91 ± 0.05 Maximum plain X-direction: 2.91 ± 0.25 Y-direction: 2.91 ± 0.25 0.28 ± 0.02 Max 0.03 Unit: mm Figure G.3 Chip Sectional Figure of the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S

Appendix H Form of Bonding Pads Rev. 8.00 Mar. 09, 2010 Page 645 of 658 REJ09B0042-0800 Appendix H Form of Bonding Pads The form of the bonding pads for the HCD64338024, HCD64338023, HCD64338022, HCD64338021, HCD64338020, HCD64F38024, HCD64F38024R, HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S is shown in figure H.1. Bonding area Metal layer 5 mm72 mm 5 mm 72 mm Figure H.1 Bonding Pad Form

Appendix I Specifications of Chip Tray Rev. 8.00 Mar. 09, 2010 Page 646 of 658 REJ09B0042-0800 Appendix I Specifications of Chip Tray The specifications of the chip tray for the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 are shown in figure I.1. The specifications of the chip tray for the HCD64F38024 and HCD64F38024R are shown in figure I.2. The specifications of the chip tray for the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S are shown in figure I.3. Chip direction Chip Type name Chip tray name DAINIPPON-INK-&-CHEMICALS-INC. Type: CT015 Carved code: TCT45-060P X-X' cross section Unit: mm 0.6 ± 0.1 XX ' 3.99 3.99 4.5 ± 0.05 Figure I.1 Specifications of Chip Tray for the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020

Appendix I Specifications of Chip Tray Rev. 8.00 Mar. 09, 2010 Page 647 of 658 REJ09B0042-0800 Chip direction Chip Type name Chip tray name DAINIPPON-INK-&-CHEMICALS-INC. Type: CT015 Carved code: TCT45-060P X-X' cross section Unit: mm 0.6 ± 0.1 XX ' 4.24 3.84 4.5 ± 0.05 Figure I.2 Specifications of Chip Tray for the HCD64F38024 and HCD64F38024R

Appendix I Specifications of Chip Tray Rev. 8.00 Mar. 09, 2010 Page 648 of 658 REJ09B0042-0800 Chip tray name Chip Type name Y X Chip direction Type: CT290 Carved code:TCT036036-060T 3.6 ± 0.05 4.48 ± 0.1 5.34 ± 0.1 0.2 ± 0.1 4.48 ± 0.1 5.34 ± 0.1 unit: mmX-X‘ Cross section Back of chip tray 0.8 ± 0.05 3.6 ± 0.05 XX ‘ 4.0 1.5 1.8 Figure I.3 Specifications of Chip Tray for the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S

Rev. 8.00 Mar. 09, 2010 Page 649 of 658 REJ09B0042-0800 Main Revisions for This Edition Item Page Revision (See Manual for Details) Table 1.1 Features

5 Table amended

• SCI3: 8-bit synchronous/asynchronous serial interface

4.3 Subclock

Figure 4.8 Typical Connection to 32.768 kHz/38.4 kHz Crystal Oscillator (Subclock)

111 Figure amended

X X C = C = 7 pF (typ.)1 2 Frequency 32.768 kHz* Crystal oscillator EPSON TOYOCOM. Products Name C-001R Motion Resistance 35 kΩ max Notes: Circuit constants should be detemined in consultation with the resonator manufacture. * H8/38124 Group only. C = C = 15 pF (typ.) 1 2 Frequency 38.4 kHz 32.768 kHz Crystal oscillator Seiko Instruments Inc. Nihon Denpa Kogyo Products Name VTC-200 MX73P

5.10 Usage Note 144 Newly added

6.10.6 Status Read

Figure 6.19 Status Read Mode Timing Waveforms

188 Figure amended

I/O7−I/O0 tdftdstds tdhtdh H'71 H'71

10.1 Overview 333 Description deleted

Serial communication interface 3 (SCI3) can carry out serial data communication in either asynchronous or synchronous mode. .

10.1.1 Features 333 Description amended

• Choice of asynchronous or synchronous mode for serial data communication In this mode, serial data can be exchanged with standard asynchronous communication LSIs such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). There is a choice of 12 data transfer formats.

Rev. 8.00 Mar. 09, 2010 Page 650 of 658 REJ09B0042-0800 Item Page Revision (See Manual for Details)

10.1.1 Features 333 Table amended

7, 8, 5 bits 1 or 2 bits Even, odd, or none Parity, overrun, and framing errors Break detected by reading the RXD 32 pin level directly when a framing error occurs

10.2.5 Serial Mode

Register (SMR)

341 Description amended

Bit 2—5 Bit Communication (MP) When this bit is one, the format of 5 bits communication becomes possible. In the case of writing 1 to this bit, bit 5 (PE) should be written with 1 all at once. Table amended 5 bit communication disabled 5 bit communication enabled Bit 2 MP Description (initial value)

10.2.6 Serial Control

Register 3 (SCR3)

344 Description amended

Bit 3—Reserved (MPIE) It’s a reserved bit. Table deleted

10.2.7 Serial Status

Register (SSR)

346 Description amended

SSR is an 8-bit register containing status flags that indicate the operational status of SCI3 .

349 Description amended

Bit 1—Reserved (MPBR) It’s a reserved read-only bit. Table deleted Description amended Bit 0—Reserved (MPBT) The write value should always be 0. Table deleted

Rev. 8.00 Mar. 09, 2010 Page 651 of 658 REJ09B0042-0800 Item Page Revision (See Manual for Details)

358 Description amended

• Choice of parity addition, and addition of 1 or 2 stop bits. (The combination of these parameters determines the data transfer format and the character length.) Table 10.8 SMR Settings and Corresponding Data Transfer Formats

359 Table amended

STOP Data Length Parity Bit Stop Bit LengthMode SMR Data Transfer Format 0 8-bit data 7-bit data Setting prohibited Setting prohibited No Yes No Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits Asynchronous mode 5-bit data No Yes 1 bit 2 bits 1 bit 2 bits Asynchronous mode 5-bit data Asynchronous mode

10.3.2 Operation in

Table 10.11 Data Transfer Formats (Asynchronous Mode)

363 Table amended

Serial Data Transfer Format and Frame LengthSMR 6789 1 0 1 1 Setting prohibited Setting prohibited Setting prohibited Setting prohibited

10.3.3 Operation in

372 Description amended

Parity bit cannot be added. 10.3.4 Multiprocessor Communication Function ⎯ Description deleted

Rev. 8.00 Mar. 09, 2010 Page 652 of 658 REJ09B0042-0800 Item Page Revision (See Manual for Details) 16.2.2 DC Characteristics Table 16.2 DC Characteristics

453 Table amended

Item Symbol Applicable Pins Min Typ Max Values Unit Test Condition Notes VIH V0.8 VCC

0.9 VCC

VCC + 0.3 VCC + 0.3 VCC = 4.0 V to 5.5 V Except the above RES, WKP0 to WKP7, IRQ0, IRQ3, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK V0.8 VCC AVCC + 0.3 AVCC + 0.3 VCC = 4.0 V to 5.5 V Except the above IRQ1 16.4.2 DC Characteristics Table 16.8 DC Characteristics

469 Table amended

Item Symbol Applicable Pins Min Typ Max Values Unit Test Condition Notes VIH V0.9 VCC VCC + 0.3—RES, WKP0 to WKP7, IRQ0, IRQ3, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK V0.9 VCC AVCC + 0.3—IRQ1

473 Table amended

V CC = 2.7 V, LCD on 32 kHz crystal resonator SUB=φw/8) Reference value ISUB VCC —— 10 μA Subsleep mode current dissipation V CC = 2.7 V, LCD on 32 kHz External Clock SUB=φw/2) ISUBSP VCC — 16.0 4.8 μA VCC = 2.7 V, LCD on 32 kHz External Clock SUB=φw/2) —4 0 20 μA VCC = 2.7 V, LCD on 32 kHz crystal resonator SUB=φw/2) —4 0 17 μA VCC = 2.7 V, LCD on 32 kHz crystal resonator SUB=φw/2) — 16.0 5.4 μA Item Symbol Applicable Pins Min Typ Max Values Unit Test Condition Notes

Rev. 8.00 Mar. 09, 2010 Page 653 of 658 REJ09B0042-0800 Item Page Revision (See Manual for Details) 16.4.2 DC Characteristics Table 16.8 DC Characteristics

474 Table amended

V CC = 2.7 V, Ta = 25°C 32 kHz External Clock LCD not used Reference value I WATCH VCC —— 2.0 μA VCC = 2.7 V, Ta = 25°C 32 kHz crystal resonator LCD not used —— 2.6 μA VCC = 2.7 V, 32 kHz External Clock LCD not used —6 . 0 2.0 μA VCC = 2.7 V, 32 kHz crystal resonator LCD not used —6 . 0 2.6 μA Item Symbol Applicable Pins Min Typ Max Values Unit Test Condition Notes

16.4.7 Power Supply

482 Newly added

16.6.2 DC Characteristics Table 16.16 DC Characteristics

487 Table amended

Item Symbol Applicable Pins Min Typ Max Values Unit Test Condition Notes VIH V0.9 VCC VCC + 0.3—RES, WKP0 to WKP7, IRQ0, IRQ3, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK V0.9 VCC AVCC + 0.3—IRQ1

Rev. 8.00 Mar. 09, 2010 Page 654 of 658 REJ09B0042-0800 Item Page Revision (See Manual for Details) 16.6.2 DC Characteristics Table 16.16 DC Characteristics

492 Table amended

V CC = 1.8 V, LCD on 32 kHz External Clock SUB=φw/2) Reference value ISUB VCC —— 6.2 μA VCC = 1.8 V, LCD on 32 kHz crystal resonator SUB=φw/2) —— 5.7 μA VCC = 2.7 V, LCD on 32 kHz External Clock SUB=φw/2) VCC = 2.7 V, LCD on 32 kHz crystal resonator SUB=φw/2) 4011 μA— 4010 μA VCC = 2.7 V, LCD on 32 kHz crystal resonator SUB=φw/8) —— 4.4 μA Item Symbol Applicable Pins Min Typ Max Values Unit Test Condition Notes Subsleep mode current dissipation V CC = 2.7 V, LCD on 32 kHz External Clock SUB=φw/2) ISUBSP VCC —1 6 . 0 4.8 μA VCC = 2.7 V, LCD on 32 kHz crystal resonator SUB=φw/2) —1 6 . 0 5.1 μA Watch mode current dissipation V CC = 1.8 V, Ta = 25°C 32 kHz crystal oscillator LCD not used Reference value IWATCH VCC —— 1.2 μA VCC = 2.7 V, Ta = 25°C 32 kHz External Clock LCD not used —— 2.0 μA

493 Table amended

Item Symbol Applicable Pins Min Typ Max Values Unit Test Condition Notes Watch mode current dissipation I WATCH VCC VCC = 2.7 V, 32 kHz External Clock LCD not used —6 . 0 2.0 μA VCC = 2.7 V, 32 kHz crystal resonator LCD not used —6 . 0 2.3 μA VCC = 2.7 V, Ta = 25°C 32 kHz crystal resonator LCD not used —— 2.3 μA * Reference value

Rev. 8.00 Mar. 09, 2010 Page 655 of 658 REJ09B0042-0800 Item Page Revision (See Manual for Details) 16.8.2 DC Characteristics Table 16.22 DC Characteristics

506 Table amended

Item Symbol Applicable Pins Min Typ Max Values Unit Test Condition Notes VIH VVCC × 0.8 VCC × 0.9 VCC + 0.3 VCC + 0.3 VCC = 4.0 V to 5.5 V Other than above RES, WKP0 to WKP7, IRQ0, IRQ3, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK VVCC × 0.8 VCC × 0.9 AVCC + 0.3 AVCC + 0.3 VCC = 4.0 V to 5.5 V Other than above IRQ1

16.8.10 Power

525 Newly added

B.1 Addresses 548 Table amended Lower Address Register Name Bit 7 Bit 6 Bit Names Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TIE TDRE SCR3 SSR H'AA H'AC RIE RDRF TE OER RE FER PER TEIE TEND CKE1 CKE0 SCI3 B.2 Functions 564 Figure amended SMR—Serial Mode Register H'A8 SCI3 Bit Initial value Read/Write COM R/W CHR R/W PE R/W CKS0 R/W MP R/W CKS1 R/W PM R/W Clock Select φ clock φw/2 clock 0 φ/16 clock φ/64 clock 0 5 bits communication disabled 1 5 bits communication enabled STOP R/W

Rev. 8.00 Mar. 09, 2010 Page 656 of 658 REJ09B0042-0800 Item Page Revision (See Manual for Details) B.2 Functions 566 Figure amended SCR3—Serial Control Register 3 H'AA SCI3 Bit Initial value Read/Write TIE R/W RIE R/W TE R/W CKE0 R/W TEIE R/W CKE1 R/W RE R/W Transmit End Interrupt Enable Clock Enable Bit 1 CKE1 Bit 0 CKE0 Communication Mode Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Internal clock Internal clock Internal clock Reserved (Do not specify this combination) External clock External clock Reserved (Do not specify this combination) Reserved (Do not specify this combination) I/O port Serial clock output Clock output Clock input Serial clock input Clock Source SCK

32 Pin Function

Transmit end interrupt request (TEI) disabled

568 Figure amended

SSR—Serial Status Register H'AC SCI3 Bit Initial value Read/Write TDRE R/(W)* RDRF R/(W)* OER R/(W)* R/W TEND R R FER R/(W)* PER R/(W)* Appendix F Package Dimensions Figure F.1 FP-80A Package Dimensions

639 Figure replaced

Figure F.2 FP-80B Package Dimensions

640 Figure replaced

Figure F.3 TFP-80C Package Dimensions

641 Figure replaced

Rev. 8.00 Mar. 09, 2010 Page 657 of 658 REJ09B0042-0800 Item Page Revision (See Manual for Details) Appendix F Package Dimensions Figure F.4 TLP-85V Package Dimensions

642 Figure replaced

Figure I.3 Specifications of Chip Tray for the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S

648 Figure replaced

Rev. 8.00 Mar. 09, 2010 Page 658 of 658 REJ09B0042-0800

Renesas 8-Bit Single-Chip Microcomputer Hardware Manual H8/38024, H8/38024S, H8/38024R, H8/38124 Group Publication Date: 1st Edition, November, 2000 Rev.8.00, March 9, 2010 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2010. Renesas Technology Corp., All rights reserved. Printed in Japan.

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Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 RENESAS SALES OFFICES Colophon 6.2

H8/38024, H8/38024S, H8/38024R, H8/38124 Group Hardware Manual REJ09B0042-0800