HA-5127_05 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

  • High Speed Signal Conditioners
  • Wide Bandwidth Instrumentation Amplifiers
  • Low Level Transducer Amplifiers
  • Fast, Low Level Voltage Comparators
  • Highest Quality Audio Preamplifiers
  • Pulse/RF Amplifiers OUT BAL BAL NC -IN +IN

Ordering Information

(BRAND) TEMP. RANGE (oC) PACKAGE PKG. DWG. # HA7-5127A-5 0 to 75 8 Ld CERDIP F8.3A HA9P5127-5 (H51275) 0 to 75 8 Ld SOIC M8.15 HA9P5127-5Z (H51275Z) (Note) 0 to 75 8 Ld SOIC (Pb-free) M8.15 HA9P5127-5ZX96 (H51275Z) (Note)

8 Ld SOIC Tape and Reel

(Pb-free) M8.15 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet July 27, 2005 FN2906.6 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN2906.6 July 27, 2005 Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) Maximum Junction Temperature (Ceramic Package, Note 1). . .175oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including ou tput load must be designed to maintain the maximum junction temperature below 175oC for Hermetic packages, and below 150oC for the plastic packages. 2. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. For differential input voltages greater than 0.7V, the input cu rrent must be limited to 25mA to protect the back-to-back input diodes. Electrical Specifications VSUPPLY = ±15V, CL < 50pF, RS < 100Ω PARAMETER TEST CONDITIONS TEMP. (oC) HA-5127A HA-5127 UNITSMIN TYP MAX MIN TYP MAX INPUT CHARACTERISTICS Offset Voltage 25 - 10 25 - 30 100 µV Full - 30 60 - 70 300 µV Average Offset Voltage Drift Full - 0.2 0.6 - 0.4 1.8 µV/oC Bias Current 25 - ±10 ±40 - ±15 ±80 nA Full - ±20 ±60 - ±35 ±150 nA Offset Current 25 - 7 35 - 12 75 nA Full - 15 50 - 30 135 nA Common Mode Range Full ±10.3 ±11.5 - ±10.3 ±11.5 - V Differential Input Resistance (Note 4) 25 1.5 6 - 0.8 4 - M Ω Input Noise Voltage Density (Note 6) f = 10Hz 25 - 3.5 8.0 - 3.8 8.0 nV/ √Hz f = 100Hz - 3.1 4.5 - 3.3 4.5 nV/ √Hz f = 1000Hz - 3.0 3.8 - 3.2 3.8 nV/ √Hz Input Noise Current Density (Note 6) f = 10Hz 25 - 1.7 4.0 - 1.7 - pA/ √Hz f = 1000Hz - 0.4 0.6 - 0.4 0.6 pA/ √Hz TRANSFER CHARACTERISTICS Large Signal Voltage Gain V OUT = ±10V, RL = 2kΩ 25 1000 1800 - 700 1500 - V/mV Full 600 1200 - 300 800 - V/mV Common Mode Rejection Ratio V CM = ±10V Full 114 126 - 100 120 - dB Minimum Stable Gain 25 1 - - 1 - - V/V Unity-Gain-Bandwidth 25 5 8.5 - 5 8.5 - MHz OUTPUT CHARACTERISTICS Output Voltage Swing R L = 600Ω 25 ±10.0 ±11.5 - ±10.0 ±11.5 - V Full Power Bandwidth (Note 7) 25 111 160 - 111 160 - kHz Output Resistance Open Loop 25 - 70 - - 70 - Ω Output Current 25 16.5 25 - 16.5 25 - mA TRANSIENT RESPONSE (Note 8) Rise Time 25 - - 150 - - 150 ns HA-5127, HA-5127A

4 FN2906.6 July 27, 2005 Schematic Diagram BALANCE17 QN20 QN50 OUT QP21 QN4 C6 D9 R15 R25 R1 QP37 QN45 QP32 QP55 QP56 QN19 R14 QN12 Z58 D59 QN24 QN25 D60 QN57 R24 R5 R6 SUBSTRATE 4V- +INPUT -INPUT QN10 QN11 QN39 QN42 QN42A D22 D31 QN2 QN2A D53 QP27 D41 QP36A QP36 QP26 QP40 QN1A QN1 R18 D54 QN52 QN51 R1A QN3 R2A C1 QN47 QN46 QN13 QN14 QN15 R7 R3 QN48 QN49 R10 C2 R22 R23 R11 R19 QN7 QN6 QN5 QP30 QN18 QP17 QP16 QP26 QN29 R12 R13 D33 D34 R17R21R20R2R16 QP35 QP43 QP44 QP38 HA-5127, HA-5127A

FIGURE 7. NOISE vs SUPPLY VOLTAGE FIGURE 8. CMRR vs FREQUENCY FIGURE 9. OFFSET VOLTAGE DRIFT vs TIME FI GURE 10. OFFSET VOLTAGE WARM UP DRIFT FIGURE 11. PSRR vs FREQUENCY FIGURE 12. CLOSED LOOP GAIN AND PHASE vs FREQUENCY

5 TYPICAL UNITS

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2906.6 July 27, 2005 Die Characteristics DIE DIMENSIONS: 104 mils x 65 mils x 19 mils 2650µm x 1650µm x 483µm METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ SUBSTRATE POTENTIAL (Powered Up): PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ TRANSISTOR COUNT: PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-5127 BAL BAL V+ OUT NC V-+IN-IN HA-5127, HA-5127A