H3LIS100DL STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Block diagram and pin description
- 1.1 Block diagram
- 1.2 Pin description
- 2 Mechanical and electrical specifications
- 2.1 Mechanical characteristics
- 2.2 Electrical characteristics
- 2.3 Communication interface characteristics
- 2.3.1 SPI - serial peripheral interface
- 2.3.2 I 2C - inter-IC control interface
- 2.4 Absolute maximum ratings
- 2.5 Terminology
- 2.5.1 Sensitivity
- 2.5.2 Zero-g level
- 2.5.3 Sleep-to-wakeup
- 3 Functionality
- 3.1 Sensing element
- 3.2 IC interface
- 3.3 Factory calibration
- 4 Application hints
- 4.1 Soldering information
- 5 Digital interfaces
- 5.1 I 2C serial interface
- 5.1.1 I 2C operation
- 5.2 SPI bus interface
- 5.2.1 SPI read
- 5.2.2 SPI write
- 5.2.3 SPI read in 3-wire mode
- 6 Register mapping
Features
Wide supply voltage, 2.16 V to 3.6 V Low-voltage compatible IOs, 1.8 V Ultra-low power consumption down to 10 μA in low-power mode ±100 g full scale I2C/SPI digital output interface 8-bit data output Sleep-to-wakeup function 10000 g high shock survivability ECOPACK®, RoHS and “Green” compliant
Applications
Shock detection Impact recognition and logging
Description
The H3LIS100DL is a low-power high- performance 3-axis linear accelerometer belonging to the “nano” family, with digital I 2C/SPI serial interface standard output. The device features ultra-low-power operational modes that allow advanced power saving and smart sleep-to-wakeup functions. The H3LIS100DL has a full scale of ±100 g and is capable of measuring accelerations with output data rates from 0.5 Hz to 400 Hz. The H3LIS100DL is available in a small thin plastic land grid array package (LGA) and is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. TFLGA 3x3x1.0 mm3 16L Table 1. Device summary
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connections
Table 2. Pin description
1 Vdd_IO Power supply for I/O pins
2 NC Not connected
3 NC Not connected
4 SCL
5 GND 0 V supply
7 SDO
9 INT 2 Inertial interrupt 2
10 Reserved Connect to GND
11 INT 1 Inertial interrupt 1
12 GND 0 V supply
13 GND 0 V supply
14 Vdd Power supply
15 Reserved Connect to Vdd
16 GND 0 V supply
2 Mechanical and electrical specifications
2.1 Mechanical characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted (a). product calibration is done at ±1 g. Table 3. Mechanical characteristics TCOff Zero-g level change vs.
- Typical specifications are not guaranteed.
- Verified by wafer level test and measurement of initial offset and sensitivity.
- Factory calibrated at ±1 g
- Offset can be eliminated by enabling the built-in high-pass filter.
2.2 Electrical characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted (b). Table 4. Electrical characteristics
- Typical specifications are not guaranteed.
- It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses; in this condition the
measurement chain is powered off.
- Refer to Table 20 for filter cutoff frequency.
- Time to obtain valid data after exiting power-down mode.
2.3 Communication interface characteristics
2.3.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 3. SPI slave timing diagram (2)
- Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
- When no communication is ongoing, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors.
Table 5. SPI slave timing values
- Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
2.3.2 I 2C - inter-IC control interface
Subject to general operating conditions for Vdd and Top. Figure 4. I2C slave timing diagram Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. Table 6. I2C slave timing values
- Data based on standard I 2C protocol requirement, not tested in production.
- C b = total capacitance of one bus line, in pF.
2.4 Absolute maximum ratings
Note: Supply voltage on any pin should never exceed 4.8 V. Table 7. Absolute maximum ratings permanent damage to the part. permanent damage to the part.
Mechanical and electrical specifications H3LIS100DL
2.5 Terminology
2.5.1 Sensitivity
Sensitivity describes the gain of the sensor and can be determined by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors.
2.5.2 Zero- g level
The zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady-state on a horizontal surface measures 0 g for the X-axis and 0 g for the Y-axis whereas the Z-axis measures 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from the ideal value in this case is called zero-g offset. Offset is, to some extent, a result of stress to the MEMS sensor and therefore can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, refer to “Zero-g level change vs. temperature” (see TCOff in Table 3). The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a population of sensors.
2.5.3 Sleep-to-wakeup
The “sleep-to-wakeup” function, in conjunction with low-power mode, allows further reducing the system power consumption and develop new smart applications. The H3LIS100DL may be set in a low-power operating mode, characterized by lower data rate refreshes. In this way the device, even if sleeping, continues to sense acceleration and generate interrupt requests. When the “sleep-to-wakeup” function is activated, the H3LIS100DL is able to automatically wake up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. With this feature the system may be efficiently switched from low-power mode to full performance, depending on user-selectable positioning and acceleration events, therefore ensuring power saving and flexibility.
3 Functionality
The H3LIS100DL is a “nano”, low-power, digital output 3-axis linear accelerometer housed in an LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I 2C/SPI serial interface.
3.1 Sensing element
A proprietary process is used to create a surface micromachined accelerometer. The technology allows processing suspended silicon structures, which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with traditional packaging techniques, a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase of the plastic encapsulation. When an acceleration is applied to the sensor, the proof mass displaces from its nominal position, causing an imbalance in the capacitive half bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. At steady-state the nominal value of the capacitors are a few pF and when an acceleration is applied, the maximum variation of the capacitive load is in the fF range.
3.2 IC interface
The complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage that will be available to the user through an analog-to-digital converter. The acceleration data may be accessed through an I 2C/SPI interface, making the device particularly suitable for direct interfacing with a microcontroller. The H3LIS100DL features a data-ready signal (RDY) which indicates when a new set of measured acceleration data is available, therefore simplifying data synchronization in the digital system that uses the device.
3.3 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and zero-g level (TyOff). The trim values are stored inside the device in non-volatile memory. Any time the device is turned on, the trim parameters are downloaded into the registers to be used during active operation. This allows the device to be used without further calibration.
4 Application hints
Figure 5. H3LIS100DL electrical connections be placed as near as possible to pin 14 of the device (common design practice). 2C or SPI interfaces. When using the I2C, CS must be tied high. completely programmed by the user through the I2C/SPI interface.
4.1 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standards. It is qualified for soldering heat resistance according to JEDEC J-STD-020C. Leave “pin 1 indicator” unconnected during soldering.
5 Digital interfaces
CS line must be tied high (i.e. connected to Vdd_IO).
5.1 I 2C serial interface
content can also be read back. The relevant I2C terminology is given in the table below. embedded inside the H3LIS100DL. When the bus is free both lines are high. Table 8. Serial interface pin description Table 9. I2C terminology
5.1.1 I 2C operation
7 LSB represent the actual register address while the MSB enables address auto increment. allow multiple data read/write. SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 10. SAD+Read/Write patterns Table 11. Transfer when master is writing one byte to slave
terminated by the generation of a STOP (SP) condition. address of first register to be read. Table 12. Transfer when master is writing multiple bytes to slave Table 13. Transfer when master is receiving (reading) one byte of data from slave Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave
5.2 SPI bus interface
The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Figure 6. Read and write protocol falling edge of SPC and should be captured at the rising edge of SPC. before the rising edge of CS. from the device is read. In the latter case, the chip drives SDO at the start of bit 8. bit 1: MS bit. When 0, the address remains unchanged in multiple read/write commands. When 1, the address is auto-incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSB first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSB first). S bit is ‘1’ the address used to read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged.
5.2.1 SPI read
Figure 7. SPI read protocol performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSB first). Figure 8. Multiple byte SPI read protocol (2-byte example)
5.2.2 SPI write
Figure 9. SPI write protocol is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 2 -7: address AD(5:0). This is the address field of the indexed register. Figure 10. Multiple byte SPI write protocol (2-byte example)
5.2.3 SPI read in 3-wire mode
Figure 11. SPI read protocol in 3-wire mode bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSB first). The multiple read command is also available in 3-wire mode.
6 Register mapping
Table 15. Register address map
7 Register description
write the data through the serial interface.
7.1 WHO_AM_I (0Fh)
Device identification register. This register contains the device identifier that for the H3LIS100DL is set to 32h.
7.2 CTRL_REG1 (20h)
The PM bits allow the user to select between power-down and two operating active modes. frequency defined by the DR1, DR0 bits. all the possible configurations for the DR1 and DR0 bits. Table 16. WHO_AM_I register Table 17. CTRL_REG1 register Table 18. CTRL_REG1 description
7.3 CTRL_REG2 (21h)
Table 19. Power mode and low-power output data rate configurations Table 20. Normal mode output data rate configurations and low-pass cutoff
- “11” bit configuration is not allowed and may cause incorrect device functionality
Table 21. CTRL_REG2 register Table 22. CTRL_REG2 description
be changed. At the end of the boot process the BOOT bit is set again to ‘0’. Table 23. High-pass filter mode configuration Table 24. High-pass filter cutoff frequency configuration
7.4 CTRL_REG3 [interrupt CTRL register] (22h)
7.5 CTRL_REG4 (23h)
Table 25. CTRL_REG3 register Table 26. CTRL_REG3 description PP_OD Push-pull/open drain selection on interrupt pad. Default value 0. reading INT2_SRC itself. Default value: 0. Data signal on INT 2 pad control bits. Default value: 00. cleared by reading the INT1_SRC register. Default value: 0. Data signal on INT 1 pad control bits. Default value: 00. Table 27. Data signal on INT 1 and INT 2 pad Table 28. CTRL_REG4 register
0000000 S I M
Table 29. CTRL_REG4 description SIM SPI serial interface mode selection. Default value: 0.
7.6 CTRL_REG5 (24h)
The turn-on bits are used for turning on the sleep-to-wake function. automatically changed to “normal mode” configuration.
7.7 HP_FILTER_RESET (25h)
0 g. This allows the settling time of the high-pass filter to be overcome.
7.8 REFERENCE (26h)
This register sets the acceleration value taken as a reference for the high-pass filter output. and the HPM bits are set to “01”, filter-out is generated, taking this value as a reference. Table 30. CTRL_REG5 register Table 31. CTRL_REG5 description TurnOn0 Turn-on mode selection for sleep-to-wake function. Default value: 00. Table 32. Sleep-to-wake configuration
11 Turned on: The device is in low-power mode (ODR is defined in
Table 33. REFERENCE register Table 34. REFERENCE description Ref7 - Ref0 Reference value for high-pass filter. Default value: 00h.
7.9 STATUS_REG (27h)
7.10 OUT_X (29h)
X-axis acceleration data. The value is expressed as two’s complement.
7.11 OUT_Y (2Bh)
Y-axis acceleration data. The value is expressed as two’s complement.
7.12 OUT_Z (2Dh)
Z-axis acceleration data. The value is expressed as two’s complement. Table 35. STATUS_REG register Table 36. STATUS_REG description
7.13 INT1_CFG (30h)
Configuration register for interrupt 1 source. Table 37. INT1_CFG register Table 38. INT1_CFG description AOI AND/OR combination of interrupt events. Default value: 0. Table 39. Interrupt 1 source configurations
0 OR combination of interrupt events
1 AND combination of interrupt events
7.14 INT1_SRC (31h)
Interrupt 1 source register. Read-only register. pin) and allows the refresh of data in the INT1_SRC register if the latched option is chosen.
7.15 INT1_THS (32h)
7.16 INT1_DURATION (33h)
Table 40. INT1_SRC register
0 I A Z HZ LY HY LX HX L
Table 41. INT1_SRC description Table 42. INT1_THS register
0 THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 43. INT1_THS description Table 44. INT1_DURATION register
0 D 6D 5D 4D 3D 2D 1D 0
The D6 - D0 bits set the minimum duration of the interrupt 1 event to be recognized. Duration steps and maximum values depend on the ODR chosen.
7.17 INT2_CFG (34h)
Configuration register for interrupt 2 source. Table 45. INT1_DURATION description Table 46. INT2_CFG register Table 47. INT2_CFG description AOI AND/OR combination of interrupt events. Default value: 0. Table 48. Interrupt mode configuration
7.18 INT2_SRC (35h)
Interrupt 2 source register. Read-only register. pin) and allows the refresh of data in the INT2_SRC register if the latched option is chosen.
7.19 INT2_THS (36h)
7.20 INT2_DURATION (37h)
The D6 - D0 bits set the minimum duration of the interrupt 2 event to be recognized. Duration time steps and maximum values depend on the ODR chosen. Table 49. INT2_SRC register Table 50. INT2_SRC description Table 51. INT2_THS register Table 52. INT2_THS description Table 53. INT2_DURATION register Table 54. INT2_DURATION description
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
Figure 12. TFLGA 3x3x1.0 mm3 16L mechanical drawing Table 55. TFLGA 3x3x1.0 mm3 16L mechanical data
9 Revision history
Table 56. Document revision history