HFA3101 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

 Pb-free Available as an Option  Excellent hFE and VBE Matching  Pin to Pin Compatible to UPA101

Applications

 Balanced Mixers  Multipliers  Demodulators/Modulators  Automatic Gain Control Circuits  Phase Detectors  Fiber Optic Signal Processing  Wireless Communication Systems  Wide Band Amplification Stages  Radio and Satellite Communications  High Performance Instrumentation

Ordering Information

(BRAND) TEMP. RANGE (°C) PACKAGE PKG. DWG. # HFA3101B (H3101B) -40 to 85 8 Ld SOIC M8.15 HFA3101BZ (H3101B) (Note) -40 to 85 8 Ld SOIC (Pb-free) M8.15 HFA3101B96 (H3101B) -40 to 85 8 Ld SOIC Tape and Reel M8.15 HFA3101BZ96 (H3101B) (Note) -40 to 85 8 Ld SOIC Tape and Reel (Pb-free) M8.15 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. Q 5 Q 6 Q 1 Q 2 Q 3 Q 4 NOTE: Q 5 and Q6 - 2 Paralleled 3µm x 50µm Transistors Q 1, Q2, Q3, Q4 - Single 3µm x 50µm Transistors Data Sheet September 2004 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 1998, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) θJA (oC/W) (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsTA = 25oC PARAMETER TEST CONDITIONS (NOTE 2) TEST LEVEL MIN TYP MAX UNITS Collector to Base Breakdown Voltage, V(BR)CBO , Q1 thru Q6 IC = 100µA, IE = 0 A 12 18 - V Collector to Emitter Breakdown Voltage, V(BR)CEO , Q 5 and Q6 IC = 100µA, IB = 0 A 8 12 - V Emitter to Base Breakdown Voltage, V(BR)EBO , Q1 thru Q6 IE = 10µA, IC = 0 A 5.5 6 - V Collector Cutoff Current, ICBO , Q1 thru Q4 VCB = 8V, IE = 0 A - 0.1 10 nA Emitter Cutoff Current, IEBO , Q5 and Q6 VEB = 1V, IC = 0 A - - 200 nA DC Current Gain, hFE , Q1 thru Q6 IC = 10mA, VCE = 3V A 40 70 - Collector to Base Capacitance, CCB Q 1 thru Q4 VCB = 5V, f = 1MHz C - 0.300 - pF Q 5 and Q6 - 0.600 - pF Emitter to Base Capacitance, CEB Q 1 thru Q4 VEB = 0, f = 1MHz B - 0.200 - pF Q 5 and Q6 - 0.400 - pF Current Gain-Bandwidth Product, fT Q 1 thru Q4 IC = 10mA, VCE = 5V C - 10 - GHz Q 5 and Q6 IC = 20mA, VCE = 5V C - 10 - GHz Power Gain-Bandwidth Product, fMAX Q 1 thru Q4 IC = 10mA, VCE = 5V C - 5 - GHz Q 5 and Q6 IC = 20mA, VCE = 5V C - 5 - GHz Available Gain at Minimum Noise Figure, GNFMIN , Q 5 and Q6 IC = 5mA, VCE = 3V f = 0.5GHz C - 17.5 - dB f = 1.0GHz C - 11.9 - dB Minimum Noise Figure, NFMIN , Q5 and Q6 IC = 5mA, VCE = 3V f = 0.5GHz C - 1.7 - dB f = 1.0GHz C - 2.0 - dB 50Ω Noise Figure, NF50Ω, Q5 and Q6 IC = 5mA, VCE = 3V f = 0.5GHz C - 2.25 - dB f = 1.0GHz C - 2.5 - dB DC Current Gain Matching, hFE1 /hFE2 , Q1 and Q2, Q 3 and Q4, and Q5 and Q6 IC = 10mA, VCE = 3V A 0.9 1.0 1.1 Input Offset Voltage, VOS , (Q1 and Q2), (Q3 and Q4), (Q5 and Q6) IC = 10mA, VCE = 3V A - 1.5 5 mV Input Offset Current, IC , (Q1 and Q2), (Q3 and Q4), (Q5 and Q6) IC = 10mA, VCE = 3V A - 5 25 µA Input Offset Voltage TC, dVOS /dT, (Q1 and Q2, Q3 and Q4, Q 5 and Q6) IC = 10mA, VCE = 3V C - 0.5 - µV/oC Collector to Collector Leakage, ITRENCH-LEAKAGE ∆VTEST = 5V B - 0.01 - nA NOTE: HFA3101

PSPICE Model for a 3 µm x 50 µm Transistor .Model NUHFARRY NPN + (IS = 1.840E-16 XTI = 3.000E+00 EG = 1.110E+00 VAF = 7.200E+01 + VAR = 4.500E+00 BF = 1.036E+02 ISE = 1.686E-19 NE = 1.400E+00 + IKF = 5.400E-02 XTB = 0.000E+00 BR = 1.000E+01 ISC = 1.605E-14 + NC = 1.800E+00 IKR = 5.400E-02 RC = 1.140E+01 CJC = 3.980E-13 + MJC = 2.400E-01 VJC = 9.700E-01 FC = 5.000E-01 CJE = 2.400E-13 + MJE = 5.100E-01 VJE = 8.690E-01 TR = 4.000E-09 TF = 10.51E-12 + ITF = 3.500E-02 XTF = 2.300E+00 VTF = 3.500E+00 PTF = 0.000E+00 + XCJC = 9.000E-01 CJS = 1.689E-13 VJS = 9.982E-01 MJS = 0.000E+00 + RE = 1.848E+00 RB = 5.007E+01 RBM = 1.974E+00 KF = 0.000E+00 + AF = 1.000E+00) Common Emitter S-Parameters of 3 µm x 50 µm Transistor FREQ. (Hz) |S11| PHASE(S 11) |S12| PHASE(S 12) |S21| PHASE(S 21) |S22| PHASE(S 22) VCE = 5V and IC = 5mA HFA3101

VCE = 5V and IC = 10mA Common Emitter S-Parameters of 3 µm x 50 µm Transistor (Continued) FREQ. (Hz) |S 11| PHASE(S 11)| S 12| PHASE(S 12)| S 21| PHASE(S 21)| S 22|P H A S E ( S22) HFA3101

The use of the HFA3101 as modulators has several advantages when compared to its counterpart, the diode doublebalanced mixer, in which it is required to receive enough energy to drive the diodes into a switching mode and has also some requirements depending on the frequency range desired, of different transformers to suit specific frequency responses. The HFA3101 requires very low driving capabilities for its carrier input and its frequency response is limited by the f T of the devices, the design and the layout techniques being utilized. Up conversion uses, for UHF transmitters for example, can be performed by injecting a modulating input in the range of 45MHz to 130MHz that carries the information often called IF (Intermediate frequency) for up conversion (The IF signal has been previously modulated by some modulation scheme from a baseband signal of audio or digital information) and by injecting the signal of a local oscillator of a much higher frequency range from 600MHz to 1.2GHz into the carrier input. Using the example of a 850MHz carrier input and a 70MHz IF , the output spectrum will contain a upper side band of 920MHz, a lower side band of 780MHz and some of the carrier (850MHz) and IF (70MHz) feedthrough. A Band pass filter at the output can attenuate the undesirable signals and the 920MHz signal can be routed to a transmitter RF power amplifier. Down conversion, as the name implies, is the process used to translate a higher frequency signal to a lower frequency range conserving the modulation information contained in the higher frequency signal. One very common typical down conversion use for example, is for superheterodyne radio receivers where a translated lower frequency often referred as intermediate frequency (IF) is used for detection or demodulation of the baseband signal. Other application uses include down conversion for special filtering using frequency translation methods. An oscillator referred as the local oscillator (LO) drives the upper quad transistors of the cell with a frequency called ωC . The lower pair is driven by the RF signal of frequency ωM to be translated to a lower frequency IF . The spectrum of the IF output will contain the sum and difference of the frequencies ωC and ωM . Notice that the difference can become negative when the frequency of the local oscillator is lower than the incoming frequency and the signal is folded back as in Figure 2. NOTE: The acronyms R F , IF and LO are often interchanged in the industry depending on the application of the cell as mixers or modulators. The output of the cell also contains multiples of the frequency of the signal being fed to the upper quad pair of transistors because of the switching action equivalent to a square wave multiplication. In practice, however, not only the odd multiples in the case of a symmetrical square wave but some of the even multiples will also appear at the output spectrum due to the nature of the actual switching waveform and high frequency performance. By-products of the form M* ωC + N*ωM with M and N being positive or negative integers are also expected to be present at the output and their levels are carefully examined and minimized by the design. This distortion is considered one of the figures of merit for a mixer application. The process of frequency doubling is also understood by having the same signal being fed to both modulating and carrier ports. The output frequency will be the sum of ωC and ωM which is equivalent to the product of the input frequency by 2 and a zero Hz or DC frequency equivalent to the difference of ωC and ωM . Figure 2 also shows one technique in use today where a process of down conversion named zero IF is made by using a local oscillator with a very pure signal frequency equal to the incoming RF frequency signal that contains a baseband (audio or digital signal) modulation. Although complex, the extraction or detection of the signal is straightforward. Another useful application of the HFA3101 is its use as a high frequency phase detector where the two signals are fed to the carrier and modulation ports and the DC information is extracted from its output. In this case, both ports are utilized in a switching mode or overdrive, such that the process of multiplication takes place in a quasi digital form (2 square waves). One application of a phase detector is frequency or phase demodulation where the FM signal is split before the modulating and carrier ports. The lower input port is always 90 degrees apart from the carrier input signal through a high Q tuned phase shift network. The network, being tuned for a precise 90 degrees shift at a nominal frequency, will set the two signals 90 degrees apart and a quiescent output DC level will be present at the output. When the input signal is frequency modulated, the phase shift of the signal coming from the network will deviate from 90 degrees proportional to the frequency deviation of the FM signal and a DC variation at the output will take place, resembling the demodulated FM signal. The HFA3101 could also be used for quadrature detection, (I/Q demodulation), AGC control with limited range, low level multiplication to name a few other applications. Biasing Various biasing schemes can be employed for use with the HFA3101. Figure 3 shows the most common schemes. The biasing method is a choice of the designer when cost, thermal dependence, voltage overheads and DC balancing properties are taken into consideration. Figure 3A shows the simplest form of biasing the HFA3101. The current source required for the lower pair is set by the voltage across the resistor R BIAS less a VBE drop of the lower transistor. To increase the overhead, collector resistors are substituted by an RF choke as the upper pair functions as a current source for AC signals. The bases of the upper and lower transistors are biased by R B1 and RB2 respectively. The voltage drop across the resistor R2 must be higher than a VBE with an increase sufficient to assure that the collector to base junctions of the lower pair are always reverse biased. Notice that this same voltage also sets the V CE of operation of the lower pair which is important for the optimization of gain. Resistors REE are nominally zero for applications where the input signals are well below 25mV peak. Resistors R EE are used to increase the linearity HFA3101

well as with tuned medium Q matching networks (L, T etc.). good RF techniques shall suffice the stability requirements. FIGURE 5. UP/DOWN CONVERTER LAYOUT, 400%; TABLE 1. S22 PARAMETERS FOR DOWN CONVERSION, TABLE 2. TYPICAL PARAMETERS FOR DOWN TABLE 3. TYPICAL VALUES OF S 22 FOR THE OUTPUT PORT. TABLE 4. TYPICAL VALUES OF S22. LCH = 390nH, IBIAS = 18mA

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli- able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Die Characteristics PROCESS UHF-1 DIE DIMENSIONS: 53 mils x 52 mils x 14 mils 1340µm x 1320µm x 355.6µm METALLIZATION: Type: Metal 1: AlCu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.5kÅ Type: Metal 2: AlCu(2%) Thickness: Metal 2: 16kÅ ±0.8kÅ PASSIVATION: Type: Nitride Thickness: 4kÅ ±0.5kÅ SUBSTRATE POTENTIAL (Powered Up): Floating Metallization Mask Layout HFA3101 2233 6677 HFA3101