EN25S80 EON | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 37
Technical content
This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. EN25S80 Rev. D, Issue Date: 2009/05/15
FEATURES
- Single power supply operation - Full voltage range: 1.65-1.95 volt
- Serial Interface Architecture - SPI Compatible: Mode 0 and Mode 3
- 8 M-bit Serial Flash - 8 M-bit/1024 K-byte/4096 pages - 256 bytes per programmable page
- Standard or Dual SPI - Standard SPI: CLK, CS#, DI, DO, WP#, HOLD# - Dual SPI: CLK, CS#, DQ0, DQ1, WP#, HOLD#
- High performance - 75MHz clock rate for one data bit - 50MHz clock rate for two data bits
- Low power consumption - 7 mA typical active current - 1 μA typical power down current
- Uniform Sector Architecture: - 256 sectors of 4-Kbyte - 16 blocks of 64-Kbyte - Any sector or block can be erased individually
- Software and Hardware Write Protection: - Write Protect all or portion of memory via software - Enable/Disable protection with WP# pin
- High performance program/erase speed - Page program time: 1.3ms typical - Sector erase time: 90ms typical - Block erase time 500ms typical - Chip erase time: 5 Seconds typical
- Lockable 256 byte OTP security sector
- Minimum 100K endurance cycle
- Package Options - 8 pins SOP 150mil body width - 8 pins SOP 200mil body width - 8 contact VDFN - All Pb-free packages are RoHS compliant
- Industrial temperature Range GENERAL DESCRIPTION The EN25S80 is an 8 Megabit (1024K-byte) Serial Flash memory, with advanced write protection mechanisms. The EN25S80 supports the standard Serial Peripheral Interface (SPI), and a high performance Dual output as well as Dual I/O using SPI pins: Serial Clock, Chip Select, Serial DQ 0(DI) and DQ1(DO). SPI clock frequencies of up to 50MHz are supported allowing equivalent clock rates of 100MHz for Dual Output when using the Dual Output Fast Read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The EN25S80 also offers a sophisticated method for protecting individual blocks against erroneous or malicious program and erase operatio ns. By providing the ability to in dividually protect and unprotect blocks, a system can unprotect a specific block to modify its contents while keeping the remaining blocks of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. The EN25S80 is designed to allow either single Sector/Block at a time or full chip erase operation. The EN25S80 can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector or block. EN25S80 8 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector
or modifications due to changes in technical specifications. Table 1. Pin Names *1. DQ0 and DQ1 are used for Dual instructions.
or modifications due to changes in technical specifications. Figure 2. BLOCK DIAGRAM
- DQ0 and DQ1 are used for Dual instructions.
This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. EN25S80 Rev. D, Issue Date: 2009/05/15 SIGNAL DESCRIPTION Serial Data Input, Output and IOs (DI, DO and DQ0, DQ1) The EN25S80 support standard SPI and Dual SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to seri ally write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge CLK. Dual SPI instruction use the bidirectional IO pins to serially write instruction, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Mode") Chip Select (CS#) The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is deselected and the Serial Data Output (DO, or DQ 0 and DQ 1) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When C S# is brought low the devi ce will be selected, power consumption will increase to active levels and instru ctions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new instruction will be accepted. HOLD (HOLD#) The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signal s on the DI and CLK pins will be ignored (don’t care). The HOLD# function can be useful when multiple devices are sharing the same SPI signals. Write Protect (WP#) The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected.
or modifications due to changes in technical specifications. Block or Chip Erasable but not Page Erasable. Table 2. Uniform Block Sector Architecture
This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. EN25S80 Rev. D, Issue Date: 2009/05/15 Active Power, Stand-by Power and Deep Power-Down Modes When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes into the Stand- by Power mode. The device consumption drops to I CC1. The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to I CC2. The device remains in this mode until another specif ic instruction (the Release from Deep Power-down Mode and Read Device ID (RDI) instruction) is executed. All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. Status Register. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whethe r the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRP, BP2, BP1, BP0) become read-only bits. In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only be programmed once. Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1, user must clear the protect bits before entering OTP mode and program the OTP code, then execute WRSR command to lock the OTP sector before leaving OTP mode. Write Protection Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern the EN25S80 provides the following data protection mechanisms: z Power-On Reset and an internal timer (t PUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. z Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events: – Power-up – Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction completion z The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). z The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
or modifications due to changes in technical specifications. ignored except one particular instruction (the Release from Deep Power-down instruction). Table 3. Protected Area Sizes Sector Organization Program or Erase cycle that is currently in progress. Clock (CLK) being Low (as shown in Figure 4.). with Serial Clock (CLK) being Low. being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.). and Serial Clock (CLK) are Don’t Care. ment of entering the Hold condition. Figure 4. Hold Condition Waveform
This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. EN25S80 Rev. D, Issue Date: 2009/05/15 INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK). The instruction set is listed in Tabl e 4. Every instruction sequence st arts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in in struction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down (RES ) minimum number of bytes specified has to be given, without which, the command will be ignored. In the case of Page Program, if the number of byte after the command is less than 4 (at least 1 data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any less or more will cause the command to be ignored. All attempts to access the memory array during a Writ e Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected.
This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. EN25S80 Rev. D, Issue Date: 2009/05/15 Table 4A. Instruction Set Instruction Name Byte 1 Code Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes Write Enable 06h Write Disable / Exit OTP mode 04h Read Status Register 05h (S7-S0)(3) continuous(4) Write Status Register 01h S7-S0 Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 Next byte continuous Sector Erase / OTP erase 20h A23-A16 A15-A8 A7-A0 Block Erase D8h A23-A16 A15-A8 A7-A0 Chip Erase C7h/ 60h Deep Power-down B9h Release from Deep Power-down, and read Device ID dummy dummy dummy (ID7-ID0) (5) Release from Deep Power-down ABh 00h (M7-M0) (ID7-ID0) Manufacturer/ Device ID 90h dummy dummy 01h (ID7-ID0) (M7-M0) (6) Read Identification 9Fh (M7-M0) (ID15-ID8) (ID7-ID0) (7) Enter OTP mode 3Ah Notes: 1. (BR7-BR0) : The output data of block protection register. 2. The Block Protection Registers contents will repeat continuously until CS# terminates the instruction. 3. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the device on the DO pin. 4. The Status Register contents will repeat continuously until CS# terminate the instruction. 5. The Device ID will repeat continuously until CS# terminates the instruction. 6. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminates the instruction. 00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID. 7. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity.
or modifications due to changes in technical specifications. Table 5. Manufacturer and Device Identification
or modifications due to changes in technical specifications. continuously, as shown in Figure 7. Figure 7. Read Status Register Instruction Sequence Diagram Table 6. Status Register Bit Locations
- In OTP mode, SRP bit is served as OTP_LOCK bit.
- See the table 3 “Protected Area Sizes Sector Organization”.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. reset and no Write Status Register, Program or Erase instruction is accepted. (CE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0.
or modifications due to changes in technical specifications. Register. Doing this will ensure compatibility with future devices. instruction is no longer accepted for execution. WRSR command to lock the OTP sector before leaving OTP mode. The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. the instruction code and the data byte on Serial Data Input (DI). 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. Table 3. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Protected Mode (HPM) is entered. NOTE : In the OTP mode, WRSR command will ignore input data and program OTP_LOCK bit to 1.
or modifications due to changes in technical specifications. Figure 8. Write Status Register Instruction Sequence Diagram address is automatically incremented to the next higher address after each byte of data is shifted out. to be continued indefinitely.
or modifications due to changes in technical specifications. maximum frequency FR, during the falling edge of Serial Clock (CLK). address is automatically incremented to the next higher address after each byte of data is shifted out. 000000h, allowing the read sequence to be continued indefinitely. rejected without having any effects on the cycle that is in progress. Figure 10. Fast Read Instruction Sequence Diagram
or modifications due to changes in technical specifications. segments to RAM for execution. Figure 11. Dual Output Fast Read Instruction Sequence Diagram
or modifications due to changes in technical specifications. execution (XIP) directly from the Dual SPI in some applications. address/dummy/data out will perform as 2-bit instead of previous 1-bit, as shown in Figure 12. Figure 12. Dual Input / Output Fast Read Instruction Sequence Diagram
or modifications due to changes in technical specifications. Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). grammed at the requested addresses without having any effects on the other bytes of the same page. otherwise the Page Program (PP) instruction is not executed. the Write Enable Latch (WEL) bit is reset. BP0) bits (see Table 3) is not executed. Figure 13. Page Program Instruction Sequence Diagram
or modifications due to changes in technical specifications. Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). for the entire duration of the sequence. is completed, the Write Enable Latch (WEL) bit is reset. BP0) bits (see Table 3) is not executed. Figure 14. Sector Erase Instruction Sequence Diagram Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). for the entire duration of the sequence. completed, the Write Enable Latch (WEL) bit is reset. BP0) bits (see Table 3) is not executed.
or modifications due to changes in technical specifications. Program and Erase instructions. Device ID of the device to be output on Serial Data Output (DO). entire duration of the sequence. CC2 and the Deep Power-down mode is entered. rejected without having any effects on the cycle that is in progress. Figure 17. Deep Power-down Instruction Sequence Diagram the device out of the Deep Power-down mode. instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction.
or modifications due to changes in technical specifications. Figure 20. Read Manufacturer / Device ID Diagram first byte , and the memory capacity of the device in the second byte . should not be issued while the device is in Deep Power down mode. shifted out on Serial Data Output , each bit being shifted out during the falling edge of Serial Clock . terminated by driving Chip Select High at any time during data output.
or modifications due to changes in technical specifications. Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Figure 21. Read Identification (RDID) WRSR command will ignore the input data and program OTP_LOCK bit to 1. User must clear the protect bits before enter OTP mode. User can use WRDI (04h) command to exit OTP mode. User can use Sector Erase (20h) command only to erase OTP data. Table 7. OTP Sector Address
or modifications due to changes in technical specifications. Table 9. DC Characteristics Table 10. AC Measurement Conditions Figure 24. AC Measurement I/O Waveform
or modifications due to changes in technical specifications. Table 11. AC Characteristics
75 MHz
50 MHz
1 Serial Clock High Time 6 ns
1 Serial Clock Low Time 6 ns
3 Write Protect Setup Time before CS# Low 20 ns
3 Write Protect Hold Time after CS# High 100 ns
2 CS# High to Deep Power-down Mode 3 µs
2 CS# High to Standby Mode without Electronic
2 CS# High to Standby Mode with Electronic
- Value guaranteed by characterization, not 100% tested in production.
- Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.
This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. EN25S80 Rev. D, Issue Date: 2009/05/15 ABSOLUTE MAXIMUM RATINGS Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. Parameter Value Unit Storage Temperature -65 to +150 °C Plastic Packages -65 to +125 °C Output Short Circuit Current1 200 mA Input and Output Voltage (with respect to ground) 2 -0.5 to Vcc+0.5 V Vcc -0.5 to Vcc+0.5 V Notes: 1. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. 2. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot V ss to –1.0V for periods of During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods up to 20ns. See figure below. RECOMMENDED OPERATING RANGES 1 Parameter Value Unit Ambient Operating Temperature Industrial Devices -40 to 85 °C Operating Supply Voltage Vcc Full: 1.65 to 1.95 V Notes: 1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed. Vcc +1.5V Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform
or modifications due to changes in technical specifications. Table 12. DATA RETENTION and ENDURANCE Table 13. CAPACITANCE Note : Sampled only, not 100% tested, at TA = 25°C and a frequency of 20MHz.
or modifications due to changes in technical specifications. Figure 28. SOP 8 ( 150 mil )
- Max. allowable mold flash is 0.15 mm
at the pkg ends, 0.25 mm between leads.
or modifications due to changes in technical specifications. Figure 29. SOP 200 mil ( Official name = 208 mil )
- Max. allowable mold flash is 0.15 mm
g ends, 0.25 mm between leads.
or modifications due to changes in technical specifications. Figure 30. VDFN8 ( 5x6mm )
This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. EN25S80 Rev. D, Issue Date: 2009/05/15 Purpose Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the compositions of the ICs. Eon is still keeping the promise of quality for all the products with the same as that of Eon delivered before. Please be advised with the change and appreciate your kindly cooperation and fully support Eon’s product family. Eon products’ New Top Marking cFeon Top Marking Example: For More Information Please contact your local sales office for additional information about Eon memory solutions. cFeon Part Number: XXXX-XXX Lot Number: XXXXX Date Code: XXXXX
This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. EN25S80 Rev. D, Issue Date: 2009/05/15
ORDERING INFORMATION
(Blank) = Conventional P = RoHS compliant TEMPERATURE RANGE I = Industrial (-40 °C to +85°C) PACKAGE G = 8-pin 150mil SOP H = 8-pin 200mil SOP W = 8-pin VDFN SPEED 7 5 = 7 5 M H z BASE PART NUMBER EN = Eon Silicon Solution Inc. 25S = 1.8V Serial Flash with 4KB Uniform-Sector 80 = 8 Megabit (1024K x 8)
This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. EN25S80 Rev. D, Issue Date: 2009/05/15 Revisions List Revision No Description Date A Preliminary version 2008/10/03 B 1. Modify device ID in Table 5 on Page 11 2. Modify tCLQV in Table 11 on Page28 3. Add cFeon new top marking notice on Page 35 2008/12/31 C 1. Remove Quad mode spec. 2. Correction word OTP 512 to 256 byte on page 24 3. Update page program, Sector erase, Block erase time and Chip erase time on page1 and 27 4. Modify fR from 50 to 33MHz 5. Correction word tCH and tCL on page 27 6. Modify tW from Typ 10ms and Max 15ms to Typ 20ms and Max to 50ms 7. Add package 8 pins SOP 150mil body width 8. Modify VOL test condition and Max value to 0.3V in table 9 2009/02/18 D 1. Update Block erase: from 0.4s to 0.5s on page 1 and 28. 2. Add the description of OTP erase command on page 10 and page 25. 3. Recover the Dual Input / Output FAST_READ (BBh) spec. on page 4. Correction typo for mapping to sector from 1023 to 255 on page 25. 2009/05/15