GTLPH1612

SN74GTLPH1612 TI | Alldatasheet

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(TOP VIEW) OEAB LEAB GND V CC GND GND V CC A10 GND A11 A12 GND A13 A14 GND A15 V CC A16 ERC A17 A18 OEBA LEBA CEAB CLKAB GND BIAS V CC GND GND V CC B10 GND B11 B12 GND B13 B14 GND B15 V REF B16 GND B17 B18 CLKBA CEBA

DESCRIPTION

Transparent, Latched, Clocked, or Clock-Enabled Modes TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant High-Drive GTLP Outputs (100 mA) LVTTL Outputs mA/24 mA) Variable Edge-Rate Control ERC Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads I off Power-Up 3-State, and BIAS V CC Support Live Insertion Bus Hold on A-Port Data Inputs Distributed V CC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) The SN74GTLPH1612 is a high-drive, 18-bit UBT transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or clock-enabled modes of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing V), reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to Ω GTLP is the Texas Instruments TI derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH1612 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL TT 1.2 V and V REF 0.8 or GTLP TT 1.5 V and V REF signal levels. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. Widebus, UBT, TI-OPC, OEC, TI are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 1999 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com (CONTINUED) SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D OCTOBER 1999 REVISED MAY 2005 Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V REF is the B-port differential input reference voltage. This device is fully specified for live-insertion I off power-up 3-state, and BIAS V CC The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS V CC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. This GTLP device circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies. High-drive GTLP backplane interface devices feature adjustable edge-rate control ERC Changing the ERC input voltage between GND and V CC adjusts the B-port output rise and fall times. This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load. Active bus-hold circuitry is provided to hold unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When V CC is between and 1.5 the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 the output-enable OE input should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING C to C TSSOP DGG Tape and reel SN74GTLPH1612DGGR GTLPH1612 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

www.ti.com FUNCTIONAL a high-drive (100 mA), 18-bit UBT transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent, latched, clocked, or clock-enabled modes and can replace any of the functions shown in Table Data polarity is noninverting. Table SN74GTLPH1612 UBT Transceiver Replacement Functions FUNCTION BIT BIT BIT BIT BIT Transceiver '245, '623, '645 '863 '861 '16245, '16623 '16863 Buffer/driver '241, '244, '541 '827 '16241, '16244, '16541 '16825 Latched transceiver '543 '16543 '16472 Latch '373, '573 '843 '841 '16373 '16843 Registered transceiver '646, '652 '16646, '16652 '16474 Flip-flop '374, '574 '821 '16374 Standard UBT '16500, '16501 Universal bus driver '16835 Registered transceiver with clock enable '2952 '16470, '16952 Flip-flop with clock enable '377 '823 '16823 Standard UBT with clock enable '16600, '16601 SN74GTLPH1612 UBT transceiver replaces all above functions xxx Data flow in each direction is controlled by the clock enables CEAB and CEBA latch enables (LEAB and LEBA), clock (CLKAB and CLKBA), and output enables OEAB and OEBA). CEAB and CEBA and OEAB and OEBA control the bits of data for the A-to-B and B-to-A directions, respectively. For A-to-B data flow, when CEAB is low, the device operates on the low-to-high transition of CLKAB for the flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB and LEAB are low, the A data is latched, regardless of the state of CLKAB (high or low) and if LEAB is high, the device is in transparent mode. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. The data flow for B to A is similar to that of A to except that CEBA OEBA LEBA, and CLKBA are used. FUNCTION TABLES SPACE HOLDER OUTPUT ENABLE (1) INPUTS OUTPUT MODE B CEAB OEAB LEAB CLKAB A X H X X X Z Isolation L L L H X B (2) Latched storage of A data L L L L X B (3) X L H X L L True transparent X L H X H H L L L L L Clocked storage of A data L L L H H H L L X X B (3) Clock inhibit (1) A-to-B data flow is shown: B-to-A data flow is similar, but uses CEBA OEBA LEBA, and CLKBA. The condition when OEAB and OEBA are both low at the same time is not recommended. (2) Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low (3) Output level before the indicated steady-state input conditions were established

www.ti.com CLK CLK OEAB CEAB CLKAB LEAB LEBA CLKBA CEBA OEBA CE CE 3 62 ERC VREF To 17 Other Channels SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D OCTOBER 1999 REVISED MAY 2005 B-PORT EDGE-RATE CONTROL ERC INPUT ERC OUTPUT B-PORT LOGIC NOMINAL EDGE RATE LEVEL VOLTAGE L GND Slow H V CC Fast LOGIC DIAGRAM (POSITIVE LOGIC)

www.ti.com Absolute Maximum Ratings (1) SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D OCTOBER 1999 REVISED MAY 2005 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.5 4.6 V BIAS V CC A-port, ERC and control inputs 0.5 V I Input voltage range (2) V B port and V REF 0.5 4.6 A port 0.5 Voltage range applied to any output in the V O V high-impedance or power-off state (2) B port 0.5 4.6 A port I O Current into any output in the low state mA B port 200 I O Current into any A-port output in the high state (3) mA Continuous current through each V CC or GND 100 mA I IK Input clamp current V I mA I OK Output clamp current V O mA θ JA Package thermal impedance (4) C/W T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) This current flows only when the output is in the high state and V O V CC (4) The package thermal impedance is calculated in accordance with JESD 51-7.

www.ti.com Recommended Operating Conditions (1) (2) (3) (4) SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D OCTOBER 1999 REVISED MAY 2005 MIN NOM MAX UNIT V CC Supply voltage 3.15 3.3 3.45 V BIAS V CC GTL 1.14 1.2 1.26 V TT Termination voltage V GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 V REF Reference voltage V GTLP 0.87 1.1 B port V TT V I Input voltage V Except B port V CC 5.5 B port V REF 0.05 V IH High-level input voltage ERC V CC 0.6 V CC 5.5 V Except B port and ERC B port V REF 0.05 V IL Low-level input voltage ERC GND 0.6 V Except B port and ERC 0.8 I IK Input clamp current mA I OH High-level output current A port mA A port I OL Low-level output current mA B port 100 Δ Δ v Input transition rise or fall rate Outputs enabled ns/V Δ Δ V CC Power-up ramp rate µ s/V T A Operating free-air temperature C (1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004. (2) Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V CC 3.3 V first, I/O second, and V CC 3.3 V last, because the BIAS V CC precharge circuitry is disabled when any V CC pin is connected. The control and V REF inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable, but generally, GND is connected first. (3) V TT and R TT can be adjusted to accommodate backplane impedances if the dc recommended I OL ratings are not exceeded. (4) V REF can be adjusted to optimize noise margins, but normally is two-thirds V TT TI-OPC circuitry is enabled in the A-to-B direction and is activated when V TT 0.7 V above V REF If operated in the A-to-B direction, V REF should be set to within 0.6 V of V TT to minimize current drain.

www.ti.com Electrical Characteristics Hot-Insertion Specifications for A Port SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D OCTOBER 1999 REVISED MAY 2005 over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT V IK V CC 3.15 I I mA 1.2 V V CC 3.15 V to 3.45 I OH 100 µ A V CC 0.2 V OH A port I OH mA 2.4 V V CC 3.15 V I OH mA V CC 3.15 V to 3.45 I OL 100 µ A 0.2 A port I OL mA 0.4 V CC 3.15 V I OL mA 0.5 V OL V I OL mA 0.2 B port V CC 3.15 V I OL mA 0.4 I OL 100 mA 0.55 I I Control inputs V CC 3.45 V I or 5.5 V µ A A port V O V CC I OZH (2) V CC 3.45 V µ A B port V O 1.5 V I OZL (2) A and B ports V CC 3.45 V O GND µ A I BHL (3) A port V CC 3.15 V I 0.8 V µ A I BHH (4) A port V CC 3.15 V I V µ A I BHLO (5) A port V CC 3.45 V I to V CC 500 µ A I BHHO (6) A port V CC 3.45 V I to V CC 500 µ A Outputs high V CC 3.45 I O I CC A or B port V I (A-port or control input) V CC or GND, Outputs low mA V I port) V TT or GND Outputs disabled V CC 3.45 One A-port or control input at V CC 0.6 Δ I CC (7) 1.5 mA Other A-port or control inputs at V CC or GND C i Control inputs V I 3.15 V or 5.5 pF A port V O 3.15 V or 6.5 C io pF B port V O 1.5 V or 9.5 11.5 (1) All typical values are at V CC 3.3 T A (2) For I/O ports, the parameters I OZH and I OZL include the input leakage current. (3) The bus-hold circuit can sink at least the minimum low sustaining current at V IL max. I BHL should be measured after lowering V IN to GND and then raising it to V IL max. (4) The bus-hold circuit can source at least the minimum high sustaining current at V IH min. I BHH should be measured after raising V IN to V CC and then lowering it to V IH min. (5) An external driver must source at least I BHLO to switch this node from low to high. (6) An external driver must sink at least I BHHO to switch this node from high to low. (7) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V CC or GND. over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT I off V CC BIAS V CC V I or V O to 5.5 V µ A I OZPU V CC to 1.5 V O 0.5 V to OE µ A I OZPD V CC 1.5 V to V O 0.5 V to OE µ A

www.ti.com Live-Insertion Specifications for B Port Timing Requirements SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D OCTOBER 1999 REVISED MAY 2005 over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT I off V CC BIAS V CC V I or V O to 1.5 V µ A I OZPU V CC to 1.5 BIAS V CC V O 0.5 V to 1.5 OE µ A I OZPD V CC 1.5 V to BIAS V CC V O 0.5 V to 1.5 OE µ A V CC to 3.15 V mA I CC (BIAS V CC BIAS V CC 3.15 V to 3.45 V O port) to 1.5 V V CC 3.15 V to 3.45 V µ A V O V CC BIAS V CC 3.3 I O 0.95 1.05 V I O V CC BIAS V CC 3.15 V to 3.45 V O port) 0.6 V µ A over recommended ranges of supply voltage and operating free-air temperature, V TT 1.5 V and V REF V for GTLP (normal mode) (unless otherwise noted) MIN MAX UNIT f clock Clock frequency 175 MHz LEAB or LEBA high t w Pulse duration ns CLKAB or CLKBA high or low A before CLKAB 2.2 B before CLKBA 2.4 A before LEAB CLK Don't care 1.8 t su Setup time ns B before LEBA CLK Don't care 2.1 CEAB before CLKAB 1.5 CEBA before CLKBA 1.5 A after CLKAB 0.7 B after CLKBA 0.5 A after LEAB CLK Don't care 1.2 t h Hold time ns B after LEBA CLK Don't care 0.9 CEAB after CLKAB 1.5 CEBA after CLKBA 1.5

www.ti.com Switching Characteristics SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D OCTOBER 1999 REVISED MAY 2005 over recommended ranges of supply voltage and operating free-air temperature, V TT 1.5 V and V REF V for GTLP (normal mode) (see Figure FROM TO PARAMETER EDGE RATE (1) MIN TYP (2) MAX UNIT (INPUT) (OUTPUT) f max 175 MHz t PLH 4.2 5.6 7.1 A B Slow ns t PHL 4.4 6.3 t PLH 4.3 5.7 A B Fast ns t PHL 2.6 3.8 5.3 t PLH 4.6 6.1 7.7 LEAB B Slow ns t PHL 3.3 4.7 6.5 t PLH 3.4 4.8 6.2 LEAB B Fast ns t PHL 4.2 5.7 t PLH 4.7 6.2 7.7 CLKAB B Slow ns t PHL 3.2 4.7 6.4 t PLH 3.5 4.9 6.2 CLKAB B Fast ns t PHL 2.9 4.2 5.6 t en 4.6 6.5 OEAB B Slow ns t dis 4.6 7.5 t en 2.7 4.1 5.6 OEAB B Fast ns t dis 3.4 4.8 6.2 Slow 2.5 t r Rise time, B outputs (20% to 80%) ns Fast 1.3 Slow 3.3 t f Fall time, B outputs (80% to 20%) ns Fast 2.5 t PLH 1.3 2.9 4.6 B A ns t PHL 1.6 4.2 t PLH 1.5 3.2 4.6 LEBA A ns t PHL 1.5 3.9 t PLH 1.5 3.3 4.8 CLKBA A ns t PHL 1.5 4.2 t en 1.2 2.5 OEBA A ns t dis 2.3 3.8 5.5 (1) Slow ERC GND) and Fast ERC V CC (2) All typical values are at V CC 3.3 T A

www.ti.com PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT FOR A OUTPUTS S1 Open GND 500 Ω 500 Ω TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6 V GND tPLH tPHL Output Control Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ 3 V 0 V VOH VOL 0 V VOL + 0.3 V VOH − 0.3 V ≈ 0 V 3 V 0 V tw Input 3 V 3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES (VM = 1.5 V for A port and 1 V for B port) (VOH = 3 V for A port and 1.5 V for B port) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) Output Input 1.5 V Test Point CL = 30 pF (see Note A) From Output Under Test 12.5 Ω LOAD CIRCUIT FOR B OUTPUTS 0 V VOH VOL Input VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) Output 1.5 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω , tr ≈ 2 ns, tf ≈ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. 6 V tPLH tPHL VOH 0 V VM VM Data Input 3 V 0 V tsu th Timing Input1.5 V 1.5 V 1.5 V 1.5 V

1 V 1 V

1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D OCTOBER 1999 REVISED MAY 2005 Figure Load Circuits and Voltage Waveforms

www.ti.com Distributed-Load Backplane Switching Characteristics 0.25 º Drvr 1.5 V 0.25º 1º 1º 1º 1.5 V 1º1º Rcvr Rcvr Rcvr Slot 1 Slot 2 Slot 19 Slot 20 Conn. Conn. Conn. Conn. ZO = 50 Ω 22 Ω 22 Ω From Output Under Test Test Point 1.5 V CL = 18 pF 11 Ω LL = 14 nH SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D OCTOBER 1999 REVISED MAY 2005 The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical representation is shown in Figure This backplane, or distributed load, can be approximated closely to a resistor inductance capacitance (RLC) circuit, as shown in Figure This device has been designed for optimum performance in this RLC circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC load, to help the designer better understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more information. Figure High-Drive Test Backplane Figure High-Drive RLC Network

www.ti.com Switching Characteristics SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D OCTOBER 1999 REVISED MAY 2005 over recommended ranges of supply voltage and operating free-air temperature, V TT 1.5 V and V REF V for GTLP (see Figure FROM TO PARAMETER EDGE RATE (1) TYP (2) UNIT (INPUT) (OUTPUT) t PLH 5.3 A B Slow ns t PHL 5.3 t PLH A B Fast ns t PHL t PLH 5.2 LEAB B Slow ns t PHL 5.2 t PLH 3.9 LEAB B Fast ns t PHL 3.9 t PLH 5.5 CLK B Slow ns t PHL 5.5 t PLH 4.3 CLK B Fast ns t PHL 4.3 t en 5.7 OEAB B Slow ns t dis 4.3 t en 4.3 OEAB B Fast ns t dis 3.8 Slow t r Rise time, B outputs (20% to 80%) ns Fast 1.2 Slow 2.5 t f Fall time, B outputs (80% to 20%) ns Fast 1.8 (1) Slow ERC GND) and Fast ERC V CC (2) All typical values are at V CC 3.3 T A All values are derived from TI-SPICE models.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74GTLPH1612DGGRE4 ACTIVE TSSOP DGG 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH1612DGGR ACTIVE TSSOP DGG 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97

48 PINS SHOWN

0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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