GTLP2034

SN74GTLP2034 TI | Alldatasheet

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8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Member of the Texas Instruments Widebus  Family /C0068 TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes /C0068 OEC  Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference /C0068 Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels /C0068 Split LVTTL Port Provides a Feedback Path for Control and Diagnostics Monitoring /C0068 LVTTL Interfaces Are 5-V Tolerant /C0068 High-Drive GTLP Open-Drain Outputs (100 mA) /C0068 LVTTL Outputs (–24 mA/24 mA) /C0068 Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads /C0068 Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion /C0068 Distributed VCC and GND Pins Minimize High-Speed Switching Noise /C0068 Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II /C0068 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)

description

The SN74GTLP2034 is a high-drive, 8-bit, three-wire registered transceiver that provides true LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and flip-flop modes of data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback path for control and diagnostics monitoring, the same functionality as the SN74FB2033, but with true logic. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 11 Ω . Copyright  2001, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OEC, TI-OPC, and Widebus are trademarks of Texas Instruments. DGG OR DGV PACKAGE (TOP VIEW) IMODE1 AI1 AO1 GND AI2 AO2 VCC AI3 AO3 GND AI4 AO4 AO5 AI5 GND AO6 AI6 V CC AO7 AI7 GND AO8 AI8 OMODE0 IMODE0 BIAS VCC GND OEAB ERC OEAB GND CLKAB/LEAB CLKBA/LEBA GND OEBA V CC LOOPBACK GND V REF OMODE1 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001

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description (continued) GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP2034 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (V TT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLP in BTL Applications, literature number SCEA017. Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and can be directly driven by TTL or 5-V CMOS devices. VREF is the B-port differential input reference voltage. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC . The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS V CC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies. High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between low and high adjusts the B-port output rise and fall times. This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load. When V CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OEAB should be tied to VCC through a pullup resistor and OEAB and OEBA should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. terminal assignments 1234 5 6 A IMODE1 NC NC NC NC IMODE0 B AO1 AI1 GND GND BIAS VCC B1 C AO2 AI2 VCC ERC OEAB B2 D AO3 AI3 GND GND OEAB B3 E AO4 AI4 CLKAB/LEAB B4 F AO5 AI5 CLKBA/LEBA B5 G AO6 AI6 GND GND OEBA B6 H AO7 AI7 VCC VCC LOOPBACK B7 J AO8 AI8 GND GND VREF B8 K OMODE0 NC NC NC NC OMODE1 NC = No internal connection GQL PACKAGE (TOP VIEW) A B C D E F G H J K 123456

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP – DGG Tape and reel SN74GTLP2034DGGR GTLP2034 –40°C to 85°C TVSOP – DGV Tape and reel SN74GTLP2034DGVR GT2034 VFBGA – GQL Tape and reel SN74GTLP2034GQLR GR034 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. functional description The SN74GTLP2034 is a high-drive (100 mA), 8-bit, three-wire registered transceiver containing D-type latches and D-type flip-flops for data-path operation in the transparent, latched, or flip-flop modes. Data transmission is true, with AI data going to the B port and B data going to AO. The split LVTTL AI and AO provides a feedback path for control and diagnostics monitoring. The logic element for data flow in each direction is configured by two mode (IMODE1 and IMODE0 for B to A, OMODE1 and OMODE0 for A to B) inputs as a buffer, D-type flip-flop, or D-type latch. When configured in the buffer mode, the input data appears at the output port. In the flip-flop mode, data is stored on the rising edge of the appropriate clock (CLKAB/LEAB or CLKBA/LEBA) input. In the latch mode, the clock inputs serve as active-high transparent latch enables. Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the output of the selected A-to-B logic element is the B-to-A input. The AO enable/disable control is provided by OEBA. When OEBA is low or when V CC is less than 1.5 V, AO is in the high-impedance state. When OEBA is high, AO is active (high or low logic levels). The B port is controlled by OEAB and OEAB. If OEAB is low, OEAB is high, or VCC is less than 1.5 V, the B port is inactive. If OEAB is high and OEAB is low, the B port is active. The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logic elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated outputs are in the high-impedance (AO) or inactive (B port) states.

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001

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OEBA OEAB OEAB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK OUTPUT MODE L L X X X X X X Z Isolation L XH X X X X X Z Isolation X H L L L X X X Buffer X HL L H X X X AI to B Flip-flop X HL H X X X X Latch H L X X X L L L Bt A O Bf fH XH X X L L L B to AO Buffer H L X X X L H L Bt A O Fli flH XH X X L H L B to AO Flip-flop H L X X X H X L Bt A O LthH XH X X H X L B to AO Latch H L X X X L L H AI to AO Buffer H XH X X L L H AI to AO Buffer H L X X X L H H AI to AO Flip flop H XH X X L H H AI to AO Flip-flop H L X X X H X H AI to AO Latch H XH X X H X H AI to AO Latch H H L X X X X L AI to B, B to AO Transparent with feedback path ENABLE/DISABLE INPUTS OUTPUTS OEBA OEAB OEAB AO B L X X Z H X X Active X LL Z X LH Z X HL Active X H H Z BUFFER INPUT OUTPUT L L H H LATCH INPUTS OUTPUT CLK/LE DATA OUTPUT H L L H HH L X Q 0

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Function Tables (Continued) LOOPBACK LOOPBACK Q † L B port H Point P‡ † Q is the input to the B-to-A logic element. ‡ P is the output of the A-to-B logic element (see functional block diagram). SELECT INPUTS SELECTED LOGIC MODE1 MODE0 ELEMENT L L Buffer L H Flip-flop H X Latch FLIP-FLOP INPUTS OUTPUT CLK/LE DATA OUTPUT L X Q 0 ↑ LL ↑ H H B-PORT EDGE-RATE CONTROL (ERC) INPUT ERC OUTPUT B-PORT LOGIC LEVEL EDGE RATE H Slow L Fast

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001

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P Q VREF ERC Pin numbers shown are for the DGG and DGV packages.

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Voltage range applied to any output in the high-impedance or power-off state, VO † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC . 3. The package thermal impedance is calculated in accordance with JESD 51-7.

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001

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recommended operating conditions (see Notes 4 through 7) MIN NOM MAX UNIT VCC , BIAS VCC Supply voltage 3.15 3.3 3.45 V VTT Termination voltage GTL 1.14 1.2 1.26 VVTT Termination voltage GTLP 1.35 1.5 1.65 V VREF Reference voltage GTL 0.74 0.8 0.87 VVREF Reference voltage GTLP 0.87 1 1.1 V VI Input voltage B port VTT VVI Input voltage Except B port and VREF VCC 5.5 V VIH High level input voltage B port VREF +0.05 VVIH High-level input voltage Except B port 2 V VIL Low level input voltage B port VREF –0.05 VVIL Low -level input voltage Except B port 0.8 V IIK Input clamp current –18 mA IOH High-level output current AO –24 mA IOL Low level output current AO 24 mAIOL Low -level output current B port 100 mA ∆t/∆v Input transition rise or fall rate Outputs enabled 10 ns/V ∆t/∆VCC Power-up ramp rate 20 µs/V TA Operating free-air temperature –40 85 °C NOTES: 4. All unused control and B-port inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable but, generally, GND is connected first. 6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. 7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is activated when VTT > 0.7 V above VREF . If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current drain.

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK VCC = 3.15 V, II = –18 mA –1.2 V VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC –0.2 VOH AO VCC = 3 15 V IOH = –12 mA 2.4 V VCC = 3.15 V IOH = –24 mA 2 VCC = 3.15 V to 3.45 V, IOL = 100 µA 0.2 AO VCC = 3 15 V IOL = 12 mA 0.4 VOL VCC = 3.15 V IOL = 24 mA 0.5 VVOL IOL = 10 mA 0.2 V B port VCC = 3.15 V IOL = 64 mA 0.4 IOL = 100 mA 0.55 II‡ AI and control inputs VCC = 3.45 V, VI = 0 or 5.5 V ±10 µA I ‡ AO VCC = 3.45 V, VO = 0 to 5.5 V ±10 µAIOZ ‡ B port VCC = 3.45 V, VREF within 0.6 V of VTT, VO = 0 to 2.3 V ±10 µA VCC = 3.45 V, IO = 0, Outputs high 40 ICC AO or B port VCC = 3.45 V, IO = 0, VI (A-port or control input) = VCC or GND, Outputs low 40 mA VI (B port) = VTT or GND Outputs disabled 40 ∆ICC § VCC = 3.45 V, One AI or control input at VCC – 0.6 V, Other AI or control inputs at VCC or GND 1.5 mA C i AI VI=31 5Vo r0 3.5 4.5 pFC i Control inputs VI = 3.15 V or 0 3.5 5.5 pF C o AO VO = 3.15 V or 0 5 6 pF C io B port VO = 1.5 V or 0 8.5 10 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. hot-insertion specifications for A port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff VCC = 0, VI or VO = 0 to 5.5 V 10 µA IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OEBA = VCC ±30 µA IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OEBA = VCC ±30 µA live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff VCC = 0, BIAS VCC = 0, VI or VO = 0 to 1.5 V 10 µA IOZPU VCC = 0 to 1.5 V, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OEAB = 0 and OEAB = VCC ±30 µA IOZPD VCC = 1.5 V to 0, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OEAB = 0 and OEAB = VCC ±30 ±30 µA ICC VCC = 0 to 3.15 V BIAS VCC =31 5Vt o34 5V VO (B po r t )=0t o15V 5 mACC (BIAS VCC ) VCC = 3.15 V to 3.45 V BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0 to 1.5 V 10 µA VO VCC = 0, BIAS VCC = 3.3 V, IO = 0 0.95 1.05 V IO VCC = 0, BIAS VCC = 3.15 V to 3.45 V,VO (B port) = 0.6 V –1 µA

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001

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timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted) MIN MAX UNIT fclock Clock frequency 175 MHz tw Pulse duration CLKAB/LEAB or CLKBA/LEBA 2.8 ns AI before CLKAB↑ 1.1 AI before CLKBA↑ 1.4 t Setup time B before CLKBA↑ 1.3 nstsu Setup time AI before LEAB↓ 1.3 ns AI before LEBA↓ 2.1 B before LEBA↓ 2.2 AI after CLKAB↑ 0.3 AI after CLKBA↑ 0.2 th Hold time B after CLKBA↑ 0.2 nsth Hold time AI after LEAB↓ 0.3 ns AI after LEBA↓ 0 B after LEBA↓ 0

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE † MIN TYP ‡ MAX UNIT fmax 175 MHz tPLH AI B Sl 3 7.1 nstPHL (buffer) B Slow 3 7 ns tPLH AI B Ft 2 5.6 ns tPHL (buffer) B Fast 2 5.7 ns tPLH B AO 1 5.4 ns tPHL B (buffer) AO – 1 4.8 ns tPLH LEAB B Slo 4.2 8.5 ns tPHL (latch mode) B Slow 3.2 7.3 ns tPLH LEAB B Ft 3.2 7.1 ns tPHL (latch mode) B Fast 2.8 6.3 ns tPLH LEAB AO 2 6.6 ns tPHL (latch mode) AO – 1.8 5.8 ns tPLH LEBA AO 1 5.3 ns tPHL LEBA (latch mode) AO – 1 4.5 ns tPLH OEAB B Sl 3.8 7.5 ns tPHL OEAB B Slow 3.1 7 ns tPLH OEAB B Fast 2.5 6 ns tPHL OEAB B Fast 2.5 6 ns tPLH OEAB B Sl 3.5 7.5 ns tPHL OEAB B Slow 3 7.2 ns tPLH OEAB B Ft 2.5 6 ns tPHL OEAB B Fast 2.5 6 ns tPZH OEBA AO 1 4.7 ns tPZL OEBA AO – 1 3.4 ns tPHZ OEBA AO 1 5.2 ns tPLZ OEBA AO – 1 4.9 ns tPLH CLKAB B Sl 4.4 8.6 ns tPHL (flip-flop mode) B Slow 3.6 8 ns tPLH CLKAB B Ft 3.2 7.1 ns tPHL (flip-flop mode) B Fast 3.1 6.8 ns tPLH CLKAB AO 2 6.9 ns tPHL (flip-flop mode) AO – 1.8 6.4 ns tPLH CLKBA AO 1 5.6 ns tPHL (flip-flop mode) AO – 1 4.9 ns tPLH OMODE B Sl 3.8 8.7 ns tPHL OMODE B Slow 3.2 8.2 ns tPLH OMODE B Ft 2.7 7 ns tPHL OMODE B Fast 2.7 7 ns tPLH IMODE AO 1 5.6 ns tPHL IMODE AO – 1 4.6 ns † Slow (ERC = H) and Fast (ERC = L) ‡ All typical values are at VCC = 3.3 V, TA = 25°C.

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001

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switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) (continued) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE † MIN TYP ‡ MAX UNIT tPLH LOOPBACK AO 2.5 5.5 nstPHL LOOPBACK AO – 2 4.7 ns tPLH AI AO 1 5.3 ns tPHL (loopback high) AO – 1 4.9 ns Rise time Bport outputs (20% to 80%) Slow 2.8 tr Rise time, B-port outputs (20% to 80%) Fast 1.5 ns Rise time, AO (10% to 90%) 3.5 Fall time Bport outputs (80% to 20%) Slow 3 tf Fall time, B-port outputs (80% to 20%) Fast 1.8 ns Fall time, AO (90% to 10%) 1.5 † Slow (ERC = H) and Fast (ERC = L) ‡ All typical values are at VCC = 3.3 V, TA = 25°C. skew characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 1)§ PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE † MIN TYP ‡ MAX UNIT tsk(LH)¶ AI B Slow 0.5 1 ns tsk(HL)¶ AI B Slow 0.5 1 ns tsk(LH)¶ AI B Fast 0.4 0.9 ns tsk(HL)¶ AI B Fast 0.4 0.9 ns tsk(LH)¶ CLKAB/LEAB B Slow 0.5 1 ns tsk(HL)¶ CLKAB/LEAB B Slow 0.5 1 ns tsk(LH)¶ CLKAB/LEAB B Fast 0.4 0.9 ns tsk(HL)¶ CLKAB/LEAB B Fast 0.4 0.9 ns AI B Slow 1.4 2 t k(t)¶ AI B Fast 0.6 1.4 nstsk(t)¶ CLKAB/LEAB B Slow 1.8 2.5 ns CLKAB/LEAB B Fast 0.9 1.8 † Slow (ERC = L) and Fast (ERC = H) ‡ All typical values are at VCC = 3.3 V, TA = 25°C. § Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. ¶ tsk(LH)/tsk(HL) and tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in the same direction either high to low [tsk(HL)] or low to high [tsk(LH)] or in opposite directions, both low to high and high to low [tsk(t)].

NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω , tr ≈ 2 ns, tf ≈ 2 ns. D. The outputs are measured one at a time with one transition per measurement.

1 V 1 V

Figure 1. Load Circuits and Voltage Waveforms

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www.ti.com/sc/gtlp for more information. Figure 2. High-Drive Test Backplane Figure 3. High-Drive RLC Network

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating conditions for the bus transceiver function (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE † TYP ‡ UNIT tPLH AI B Sl 5.7 nstPHL (buffer) B Slow 5.2 ns tPLH AI B Ft 3.7 ns tPHL (buffer) B Fast 4.1 ns tPLH LEAB B Sl 5.9 ns tPHL (latch mode) B Slow 5.7 ns tPLH LEAB B Fast 4.8 ns tPHL (latch mode) B Fast 4.8 ns tPLH CLKAB B Sl 5.7 ns tPHL (flip-flop mode) B Slow 6.4 ns tPLH CLKAB B Ft 4.7 ns tPHL (flip-flop mode) B Fast 5.2 ns tPLH OMODE B Sl 5.4 ns tPHL OMODE B Slow 6 ns tPLH OMODE B Ft 4.5 ns tPHL OMODE B Fast 4.9 ns t Rise time Bport outputs (20% to 80%) Slow 2 nstr Rise time, B-port outputs (20% to 80%) Fast 1.1 ns tf Fall time Bport outputs (80% to 20%) Slow 3.3 nstf Fall time, B-port outputs (80% to 20%) Fast 2.3 ns † Slow (ERC = H) and Fast (ERC = L) ‡ All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74GTLP2034DGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74GTLP2034DGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP2034DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP2034DGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP2034GQLR ACTIVE BGA MI CROSTA R JUNI OR GQL 56 1000 TBD SNPB Level-1-240C-UNLIM SN74GTLP2034ZQLR ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97

48 PINS SHOWN

0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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