GTLP1B151 FAIRCHILD | Alldatasheet

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I Separate LVTTL inputs and outputs I A feedback path for control and diagnostics monitoring I Bidirectional interface between GTLP and LVTTL logic levels I Designed with edge rate control circuitry to reduce out- put noise on the GTLP port I VREF pin provides external supply reference voltage for receiver threshold adjustibility I Special PVT compensation circuitry to provide consis- tent performance over variations of process, supply volt- age and temperature I TTL compatible driver and control inputs I Designed using Fairchild advanced BiCMOS technology I Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs I Power up/down and power off high impedance for live insertion I Open drain on GTLP to support wired-or connection I Flow through pinout optimizes PCB layout I A Port source/sink −24mA / +24mA I B Port sink +50mA Ordering Code: Order Number Package Number Package Description GTLP1B151M M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TUBE] GTLP1B151MX M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TAPE and REEL] GTLP1B151K8X MAB08A (Preliminary) 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide [TAPE and REEL]

www.fairchildsemi.com 2 GTLP1B151 Pin Descriptions Connection Diagrams US8 SOIC Functional Description The GTLP1B151 is a 1-bit transceiver that supports GTLP and LVTTL signal levels. Data polarity is non-inverting with sep- arate LVTTL inputs and outputs and there are individual GTLP and LVTTL output enable controls. Functional Tables Logic Diagram Pin Names Description OEB, OEC LVTTL Individual Output Enable Controls (OEC is Active LOW) VCC , GND, VREF Device Supplies A A Port LVTTL Input B B Port GTLP Input/Output C C Port LVTTL Output Inputs Outputs

Description

H L L Output L L B Bus Enabled, C Bus Enabled H L H Output H H B Bus Enabled, C Bus Enabled H H L Output L Z B Bus Enabled, C Bus Disabled H H H Output H Z B Bus Enabled, C Bus Disabled L H L L Z Z B Bus Disabled, C Bus Disabled L H H H Z Z B Bus Disabled, C Bus Disabled L L N/A L Z L B Bus Disabled, C Bus Enabled L L N/A H Z H B Bus Disabled, C Bus Enabled

3 www.fairchildsemi.com GTLP1B151 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be oper- ated at these limits. The parametric values defined in the “Electrical Char- acteristics” table are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Supply Voltage (VCC ) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V DC Output Voltage (VO ) Outputs 3-STATE −0.5V to +4.6V Outputs Active (Note 2) −0.5V to +4.6V DC Output Sink Current into C Port IOL 48 mA DC Output Source Current from C Port IOH −48 mA DC Output Sink Current into B Port in the LOW State, IOL 100 mA DC Input Diode Current (IIK) VI < 0V −50 mA DC Output Diode Current (IOK ) VO < 0V −50 mA ESD Rating >2000V Storage Temperature (TSTG ) −65°C to +150°C Supply Voltage VCC 3.15V to 3.45V Bus Termination Voltage (VTT) GTLP 1.47V to 1.53V VREF 0.98V to 1.02V Input Voltage (VI) on A Port and Control Pins 0.0V to V CC HIGH Level Output Current (IOH ) C Port −24 mA LOW Level Output Current (IOL ) C Port +24 mA B Port +50 mA Operating Temperature (TA) −40°C to +85°C Symbol Test Conditions Min Typ Max Units (Note 3) VIH B Port V REF + 0.05 V TT V Others 2.0 VIL B Port 0.0 V REF − 0.05 V Others 0.8 VREF B Port 0.7V 1.0 1.3V V VTT B Port V REF + 50 mV 1.5 V CC V VIK VCC = 3.15V I I = −18 mA −1.2 V VOH C Port V CC = Min to Max (Note 4) I OH = −100 µAV CC –0.2 VVCC = 3.15V I OH = −8 mA 2.4 IOH = -24mA 2.2 VOL C Port V CC = Min to Max (Note 4) I OL = 100 µA0 . 2 VVCC = 3.15V I OL = 8 mA 0.4 VCC = 3.15V I OL = 24mA 0.5 B Port V CC = 3.15V I OL = 40 mA 0.4 V IOL = 50 mA 0.55 II Control Pins VCC = 3.45V V I = 3.45V 5 µA VI = 0V −5 A Port V CC = 3.45V V I = 3.45V 10 µA VI = 0V −10 B Port V CC = 3.45V V I = 3.45 5 µA VI = 0 −5 IOFF A or C Ports, VCC = 0V I or VO = 0 to 3.45V 30 µA Control Pins B Port V CC = 0V I or VO = 0 to 3.45V 30 µA II (HOLD) A Port V CC = 3.15V V I = 0.8V 75 µA VI = 2.0V −75 IOZH C Port V CC = 3.45V V O = 3.45V 10 µA B Port V O = 3.45V 5 IOZL C Port V CC = 3.45V V O = 0V −10 µA B Port V O = 0.0V −5

www.fairchildsemi.com 4 GTLP1B151 Note 3: All typical values are at VCC = 3.3V and TA = 25°C. Note 4: For conditions shown as Min, use the appropriate value specified under recommended operating conditions. Note 5: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Note: GTLP V REF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In addition, VTT and RTERM can be adjusted beyond the recommended operating to accommodate backplane impedances other than 50Ω , but must remain within the boundaries of the DC Absolute Maximum Ratings. Similarly, VREF can be adjusted to optimize noise margin. Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). C L = 30 pF for B Port and CL = 50 pF for C Port. Note 6: All typical values are at VCC = 3.3V, and TA = 25°C. Symbol Test Conditions Min Typ Max Units (Note 3) IPU/PD All Ports V CC = 0 to 1.5V V I = 0 to 3.45V 30 µA ICC A or B Ports V CC = 3.45V Outputs HIGH 11 mAor C Port I O = 0 Outputs LOW 11 VI = VCC /VTT or GND Outputs Disabled 11 ∆ICC A Port and V CC = 3.45V, One Input at V CC 2m A (Note 5) Control Pins A or Control Inputs at VCC or GND −0.6V C i Control Pins V I = VCC or 0 3 pF and A Port C O C Port V I = VCC or 0 5 pF C I/O B Port V I = VTT or 0 5.5 pF Symbol From To Min Typ Max Unit (Input) (Output) (Note 6) tPLH AB 1.2 3.2 7.3 ns tPHL 0.8 2.3 4.5 tPLH BC 1.4 2.8 4.4 ns tPHL 1.6 2.9 5.0 tPLH AC 1.6 6.0 8.1 ns tPHL 2.0 5.1 7.5 tRISE Transition Time, B Outputs (20% to 80%) 1.4 ns tFALL Transition Time, B Outputs (80% to 20%) 2.0 ns tRISE Transition Time, C Outputs (10% to 90%) 2.8 ns tFALL Transition Time, C Outputs (90% to 10%) 2.5 ns tPZH , tPZL OEC C 1.2 2.7 5.3 ns tPHZ , tPLZ 1.4 2.8 4.9 tPLH OEB B 1.7 3.5 5.9 ns tPHL 0.5 2.2 4.7

5 www.fairchildsemi.com GTLP1B151 Test Circuits and Timing Waveforms Test Circuit for C Outputs Note: CL includes probes and Jig capacitance. Test Circuit for B Outputs Note: CL includes probes and Jig capacitance. Note: For B Port, CL = 30 pF is used for worst case. Voltage Waveforms Propagation Delay Voltage Waveform Enable and Disable Times Note: Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. Note: All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), ZO = 50Ω . The outputs are measured one at a time with one transition per measurement. Test S tPLH /tPHL OPEN tPLZ /tPZL 6V tPHZ /tPZH GND A or LVTTL Pins B or GTLP Pins VINHIGH VCC 1.5 VINLOW 0.0 0.0 VM VCC /2 1.0 VX VOL + 0.3V N/A VY VOH − 0.3V N/A

www.fairchildsemi.com 6 GTLP1B151 Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M08A

7 www.fairchildsemi.com GTLP1B151 1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide Preliminary Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com