GTLP10B320

GTLP10B320 FAIRCHILD | Alldatasheet

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I Bidirectional interface between GTLP and LVTTL logic levels I Variable edge rate control pin to select desired edge rate on GTLP port (VERC ) I VREF pin provides external supply reference voltage for receiver threshold adjustibility I Split LVTTL inputs and outputs I Special PVT compensation circuitry to provide consis- tent performance over variations of process, supply volt- age and temperature I A feedback path for control and diagnostics monitoring I TTL compatible driver and control inputs I Designed using Fairchild advanced BiCMOS technology I Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs I Power up/down and power off high impedance for live insertion I Open drain on GTLP to support wired-or connection I Flow through pinout optimizes PCB layout I A Port source/sink −24mA/+24mA I B Port sink +50mA Ordering Code: Device is also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Order Number Package Number Package Description GTLP10B320MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

www.fairchildsemi.com 2 GTLP10B320 Pin Descriptions Connection Diagram Functional Description The GTLP10B320 is a 10-bit Universal driver and receiver containing D-Type flip-flop, latch, and transparent modes of operation for the data paths. In addition there is an internal feedback path that can be used for diagnostic monitoring or caching schemes. Data flow in each direction is controlled by the clock signals (LECLKAB and LECLKBC) and output enables (OEB and OEC ). The internal feedback path is controlled by the SEL pin and allows data transfer from Port A to Port C without requiring data to be output to the backplane. The internal feedback path is selected with SEL LOW and the B Port pin is selected with SEL HIGH. The data paths can also be configured for latch/transparent or register mode for each direction with the SAB and SBC pins. Data polarity is non-inverting with the GTLP outputs enabled via the OEB pin and the LVTTL outputs being enabled via the OEC pin. For A-to-B data flow the device is configured into a latch/ transparent or register mode by pin SAB. If SAB is LOW then the register mode is selected and the device operates on the LOW-to-HIGH transition of LECLKAB. If SAB is HIGH then the latch/transparent configuration is selected and a HIGH-to-LOW transition of LECLKAB stores data in the latch. If LECLKAB is HIGH the device is in transparent mode. When OEB is LOW the outputs are active and when OEB is HIGH the outputs are high impedance. Pin Names Description OEB , OEC B Port, C Port Output Enable respectively (Active LOW) VCC , GND, VREF Device Supplies LECLKAB, LECLKBC A-to-B, B-to-C Latch CLK respectively (Transparent Active HIGH) SEL Selects Internal Feedback Path SAB, SBC Selects Register or Latch/Transparent Path for A-to-B and B-to-C respectively B0-B9 B Port GTLP I/O A0-A9 A Port LVTTL Inputs C 0-C9 C Port LVTTL Outputs VERC Edge Rate Control Pin (GND = Slow Edge Rate) (VCC = Fast Edge Rate)

3 www.fairchildsemi.com GTLP10B320 Functional Tables Note 1: Output level before the indicated steady state input conditions were established. Note 2: The data flow of B-to-C is similar except that OEC, SBC and LECLKBC are used. Note 3: Function identical for SEL = 1 if timing requirements for propagation delay to output and set-up to LECLKBC are met at B Port. Note 4: Output level before the indicated steady state input conditions were established. I/O Path: SEL = 1 (External Feedback Path) (Note 2) Inputs Outputs OEB OEC SAB SBC LECLKAB LECLKBC Mode (AB) A n C n B n 010X ↑ XR e g i s t e r L X L 010X ↑ XR e g i s t e r H X H 010X L X R e g i s t e r L X B 0 (Note 1) 010X L X R e g i s t e r H X B 0 (Note 1) 011X ↓ X Latch L X L 011X H X B u f f e r L X L 011X ↓ X Latch H X H 011X H X B u f f e r H X H 1 1 X X X X High Impedance X X Z Internal Feedback Path: SEL = 0 (Internal Feedback Path) (Note 3) Inputs Outputs OEB OEC SAB SBC LECLKAB LECLKBC Mode (AB/BC) A n B n C n 0000 ↑↑ Register/Register L L L 0000 ↑↑ Register/Register H H H

0000 L ↑ Register/Register X B 0 (Note 4) B0 (Note 4)

0000 ↑ L Register/Register L L B 0 (Note 4) 0000 ↑ L Register/Register H H B 0 (Note 4)

0000 L L R e g i s t e r / R e g i s t e r X B 0 (Note 4) B0 (Note 4)

0001 ↑↓ Register/Latch L L L 0001 ↑ H Register/Buffer L L L 0001 ↑↓ Register/Latch H H H 0001 ↑ H Register/Buffer H H H

0001 L ↓ Register/Latch X B 0 (Note 4) B0 (Note 4)

0001 L H R e g i s t e r / B u f f e r X B 0 (Note 4) B0 (Note 4)

0001 L L R e g i s t e r / L a t c h X B 0 (Note 4) B0 (Note 4)

0010 ↓↑ Latch/Register L L L 0010 ↓↑ Latch/Register H H H 0010 ↓ L Latch/Register L L B 0 (Note 4) 0010 ↓ L Latch/Register H H B 0 (Note 4)

0010 H ↑ Buffer/Register L L L

0010 H ↑ Buffer/Register H H H

0010 L L L a t c h / R e g i s t e r X B 0 (Note 4) B0 (Note 4)

0011 ↓↓ Latch/Latch L L L 0011 ↓↓ Latch/Latch H H H

0011 H HB u f f e r / B u f f e r L L L

0011 H HB u f f e r / B u f f e r H H H

1 1 X X X X High Impedance X Z Z

www.fairchildsemi.com 4 GTLP10B320 Logic Diagram

5 www.fairchildsemi.com GTLP10B320 Absolute Maximum Ratings(Note 5) Recommended Operating Conditions Note 5: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be oper- ated at these limits. The parametric values defined in the “Electrical Char- acteristics” table are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 6: IO Absolute Maximum Rating must be observed. Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Supply Voltage (VCC ) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V DC Output Voltage (VO ) Outputs 3-STATE −0.5V to +4.6V Outputs Active (Note 6) −0.5V to +4.6V DC Output Sink Current into C Port IOL 48 mA DC Output Source Current from C Port IOH −48 mA DC Output Sink Current into B Port in the LOW State, IOL 100 mA DC Input Diode Current (IIK) VI < 0V −50 mA DC Output Diode Current (IOK ) VO < 0V −50 mA ESD Rating >2000V Storage Temperature (TSTG ) −65°C to +150°C Supply Voltage VCC 3.15V to 3.45V Bus Termination Voltage (VTT) GTLP 1.47V to 1.53V VREF 0.98V to 1.02V Input Voltage (VI) on A Port and Control Pins 0.0V to V CC HIGH Level Output Current (IOH ) C Port −24 mA LOW Level Output Current (IOL ) C Port +24 mA B Port +50 mA Operating Temperature (TA) −40°C to +85°C Symbol Test Conditions Min Typ Max Units (Note 7) VIH B Port V REF + 0.05 V TT V Others 2.0 VIL B Port 0.0 V REF − 0.05 V Others 0.8 VREF B Port 0.7 1.0 1.3 V VTT B Port V REF + 50 mV 1.5 V CC V VIK VCC = 3.15V I I = −18 mA −1.2 V VOH C Port V CC = Min to Max (Note 8) I OH = −100 µAV CC –0.2 VVCC = 3.15V I OH = −8 mA 2.4 IOH = -24mA 2.2 VOL C Port V CC = Min to Max (Note 8) I OL = 100 µA0 . 2 VVCC = 3.15V I OL = 8 mA 0.4 IOL = 24 mA 0.5 B Port V CC = 3.15V I OL = 40 mA 0.4 V IOL = 50 mA 0.5 II Control Pins VCC = 3.45V V I = 3.45V 10 µA and A Port V I = 0V −10 B Port V CC = 3.45V V I = VTT 5 µA VI = 0 −5 IOFF A or C Ports, VCC = 0V I or VO = 0 to 3.45V 30 µA Control Pins B Port V CC = 0V I or VO = 0 to 1.5V 30 µA II (HOLD) A Port V CC = 3.15V V I = 0.8V 75 µA VI = 2.0V −75 IOZH C Port V CC = 3.45V V O = 3.45V 10 µA B Port V O = 1.5V 5 IOZL C Port V CC = 3.45V V O = 0V −10 µA B Port V O = 0.55V −5 IPU/PD All Ports V CC = 0 to 1.5V V I = 0 to 3.45V 30 µA

www.fairchildsemi.com 6 GTLP10B320 Note 7: All typical values are at VCC = 3.3V and TA = 25°C. Note 8: For conditions shown as Min, use the appropriate value specified under recommended operating conditions. Note 9: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Note: GTLP V REF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In addition, VTT and RTERM can be adjusted beyond the recommended operating to accommodate backplane impedances other than 50Ω , but must remain within the boundaries of the DC Absolute Maximum Ratings. Similarly, VREF can be adjusted to optimize noise margin. AC Operating Requirements Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). Symbol Test Conditions Min Typ Max Units (Note 7) ICC A or B Ports V CC = 3.45V Outputs HIGH 27 45 mAor C Port I O = 0 Outputs LOW 27 45 VI = VCC /VTT or GND Outputs Disabled 27 45 ∆ICC A Port and V CC = 3.45V, One Input at V CC 2m A (Note 9) Control Pins A or Control Inputs at VCC or GND −0.6V C i Control Pins V I = VCC or 0 4.5 pF and A Port C Port V I = VCC or 0 6 B Port V I = VCC or 0 9 Symbol Test Conditions Min Max Unit fMAX Maximum Clock Frequency 150 MHz tWIDTH Pulse Duration LECLKAB, LECLKBC HIGH or LOW 3.0 ns tSET Setup Time SAB = 0 A before LECLKAB ↑ 2.1 ns SBC = 0 B before LECLKBC ↑ 2.6 SAB = 1, SEL = 1, SBC = 0 A before LECLKBC ↑ 6.8 SAB = 1, SEL = 0, SBC = 0 A before LECLKBC ↑ 3.0 SAB = 1 A before LECLKAB ↓ 1.7 SBC = 1 B before LECLKBC ↓ 2.2 SAB = 1, SEL = 1, SBC = 1 A before LECLKBC ↓ 6.4 SAB = 1, SEL = 0, SBC = 1 A before LECLKBC ↓ 2.8 tHOLD Hold Time SAB = 0 A after LECLKAB↑ 2.0 ns SBC = 0 B after LECLKBC↑ 1.6 SAB = 1, SEL = 1, SBC = 0 A after LECLKBC↑− 1.4 SAB = 1, SEL = 0, SBC = 0 A after LECLKBC↑ 1.4 SAB = 1 A after LECLKAB↓ 2.5 SBC = 1 B after LECLKBC↓ 2.1 SAB = 1, SEL = 1, SBC = 1 A after LECLKBC↓− 1.0 SAB = 1, SEL = 0, SBC = 1 A after LECLKBC↓ 1.6

7 www.fairchildsemi.com GTLP10B320 Over recommended range of supply voltage and operating free air temperature, VREF = 1.0V (unless otherwise noted). VERC = GND. CL = 30 pF for B Port and CL = 50 pF for C Port. Note 10: All typical values are at VCC = 3.3V, and TA = 25°C. Symbol From To Min Typ Max Unit (Input) (Output) (Note 10) tPLH An Bn 2.0 4.2 7.5 ns tPHL SAB = 1 1.1 2.7 4.9 tPLH LECLKAB B n 2.2 4.5 6.7 ns tPHL SAB = 1 1.3 3.0 5.6 tPLH LECLKAB B n 2.5 4.8 7.1 ns tPHL SAB = 0 1.4 3.1 5.7 tPLH Bn C n 1.4 2.6 4.4 ns tPHL SBC = 1 1.6 2.9 5.0 tPLH LECLKBC C n 1.2 2.5 4.5 ns tPHL SBC = 1 1.5 2.9 5.0 tPLH LECLKBC C n 1.3 2.6 4.6 ns tPHL SBC = 0 1.5 2.9 5.0 tPLH An C n 3.3 6.1 10.3 ns tPHL SEL = 1, SAB = 1, SBC = 1 2.4 5.1 8.0 tPLH An C n 1.5 3.0 5.4 ns tPHL SEL = 0, SAB = 1, SBC = 1 1.9 3.4 5.8 tPLH LECLKAB C n 2.6 6.5 9.5 ns tPHL SEL = 1, SAB = 1, SBC = 1 3.0 5.5 8.6 tPLH LECLKAB C n 1.8 3.4 6.0 ns tPHL SEL = 0, SAB = 1, SBC = 1 1.9 3.6 6.3 tPLH LECLKAB C n 2.7 6.8 10.0 ns tPHL SEL = 1, SAB = 0, SBC = 1 2.9 5.5 8.6 tPLH LECLKAB C n 1.8 3.5 6.3 ns tPHL SEL = 0, SAB = 0, SBC = 1 2.0 3.7 6.5 tRISE Transition Time, B Outputs (20% to 80%) 2.2 ns tFALL Transition Time, B Outputs (80% to 20%) 1.8 tRISE Transition Time, C Outputs (10% to 90%) 1.5 tFALL Transition Time, C Outputs (90% to 10%) 1.6 tPLH SEL C n 1.2 2.8 4.9 ns tPHL 1.5 2.8 5.3 tPZH , tPZL OEB Bn 1.1 2.8 5.2 ns tPHZ , tPLZ 2.0 4.3 8.9 tPZH , tPZL OEC C n 1.2 2.9 5.3 ns tPHZ , tPLZ 1.4 2.8 4.9

www.fairchildsemi.com 8 GTLP10B320 Over recommended range of supply voltage and operating free air temperature, VREF = 1.0V (unless otherwise noted). VERC = GND. CL = 10 pF for B Port and CL = 10 pF for C Port. Note 11: All typical values are at VCC = 3.3V, and TA = 25°C. Symbol From To Min Typ Max Unit (Input) (Output) (Note 11) tPLH An Bn 1.6 3.9 7.2 ns tPHL SAB = 1 0.7 2.4 4.7 tPLH LECLKAB B n 1.7 4.1 6.3 ns tPHL SAB = 1 0.9 2.7 5.4 tPLH LECLKAB B n 2.0 4.4 6.7 ns tPHL SAB = 0 1.0 2.7 5.4 tPLH Bn C n 0.4 1.8 3.7 ns tPHL SBC = 1 0.6 2.2 4.3 tPLH LECLKBC C n 0.2 1.8 3.9 ns tPHL SBC = 1 0.4 2.0 4.3 tPLH LECLKBC C n 0.3 1.8 4.0 ns tPHL SBC = 0 0.4 2.1 4.3 tPLH An C n 2.1 5.1 9.3 ns tPHL SEL = 1, SAB = 1, SBC = 1 1.0 4.1 7.1 tPLH An C n 0.5 2.3 4.8 ns tPHL SEL = 0, SAB = 1, SBC = 1 0.8 2.6 5.2 tPLH LECLKAB C n 1.1 5.3 8.5 ns tPHL SEL = 1, SAB = 1, SBC = 1 1.4 4.3 7.6 tPLH LECLKAB C n 0.8 2.6 5.4 ns tPHL SEL = 0, SAB = 1, SBC = 1 0.9 2.8 5.6 tPLH LECLKAB C n 1.2 5.6 9.0 ns tPHL SEL = 1, SAB = 0, SBC = 1 1.3 4.3 7.6 tPLH LECLKAB C n 0.9 2.8 5.6 ns tPHL SEL = 0, SAB = 0, SBC = 1 0.9 2.9 5.8 tRISE Transition Time, B Outputs (20% to 80%) 2.0 ns tFALL Transition Time, B Outputs (80% to 20%) 1.8 tRISE Transition Time, C Outputs (10% to 90%) 0.6 tFALL Transition Time, C Outputs (90% to 10%) 0.7 tPLH SEL C n 0.3 1.7 4.3 ns tPHL 0.4 2.3 4.6 tPZH , tPZL OEB Bn 0.8 2.5 4.8 ns tPHZ , tPLZ 1.6 4.0 8.5 tPZH , tPZL OEC C n 0.6 2.0 4.0 ns tPHZ , tPLZ 0.6 1.9 3.7

9 www.fairchildsemi.com GTLP10B320 Over recommended range of supply voltage and operating free air temperature, VREF = 1.0V (unless otherwise noted). VERC = VCC . CL = 30 pF for B Port and CL = 50 pF for C Port. Note 12: All typical values are at VCC = 3.3V, and TA = 25°C. Over recommended range of supply voltage and operating free air temperature, VREF = 1.0V (unless otherwise noted). VERC = VCC . CL = 10 pF for B Port and CL = 10 pF for C Port. Note 13: All typical values are at VCC = 3.3V, and TA = 25°C. Symbol From To Min Typ Max Unit (Input) (Output) (Note 12) tPLH An Bn 1.2 3.3 7.3 ns tPHL SAB = 1 0.8 2.3 4.5 tPLH LECLKAB B n 1.4 3.7 6.0 ns tPHL SAB = 1 1.0 2.6 5.1 tPLH LECLKAB B n 1.6 3.9 6.3 ns tPHL SAB = 0 1.1 2.7 5.2 tPLH An C n 1.6 5.3 8.1 ns tPHL SEL = 1, SAB = 1, SBC = 1 2.0 4.7 7.5 tPLH LECLKAB C n 1.7 5.7 8.8 ns tPHL SEL = 1, SAB = 1, SBC = 1 2.2 5.1 8.1 tPLH LECLKAB C n 1.8 5.9 9.1 ns tPHL SEL = 1, SAB = 0, SBC = 1 2.3 5.1 8.2 tRISE Transition Time, B Outputs (20% to 80%) 1.8 ns tFALL Transition Time, B Outputs (80% to 20%) 1.4 tPZH , tPZL OEB Bn 0.5 2.4 4.7 ns tPHZ , tPLZ 1.7 3.4 5.9 Symbol From To Min Typ Max Unit (Input) (Output) (Note 13) tPLH An Bn 0.8 3.0 7.0 ns tPHL SAB = 1 0.5 2.1 4.3 tPLH LECLKAB B n 0.6 3.2 5.7 ns tPHL SAB = 1 0.6 2.3 4.8 tPLH LECLKAB B n 0.8 3.5 6.0 ns tPHL SAB = 0 0.7 2.4 4.9 tPLH An C n 0.2 4.2 8.1 ns tPHL SEL = 1, SAB = 1, SBC = 1 0.6 3.7 6.6 tPLH LECLKAB C n 0.2 4.5 7.7 ns tPHL SEL = 1, SAB = 1, SBC = 1 0.7 3.9 7.2 tPLH LECLKAB C n 0.3 4.8 8.0 ns tPHL SEL = 1, SAB = 0, SBC = 1 0.8 3.9 7.2 tRISE Transition Time, B Outputs (20% to 80%) 1.4 ns tFALL Transition Time, B Outputs (80% to 20%) 1.2 tPZH , tPZL OEB Bn 0.2 2.1 4.4 ns tPHZ , tPLZ 1.3 3.0 5.5

www.fairchildsemi.com 10 GTLP10B320 AC Extended Electrical Characteristics Over recommended ranges of supply voltage and operating free air temperature VREF = 1.0V (unless otherwise noted). C L = 30 pF for B Port and CL = 50 pF for C Port. Note 14: tOSHL /tOSLH and tOST - Output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL ) or LOW-to-HIGH (tOSLH ) or in opposite directions both HL and LH (tOST ). This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 15: tPV - Part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device. The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 16: Due to the open drain structure on GTLP outputs tOST and tPV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the VTT and RT values on the backplane. Symbol Path From To Mode Max Unit tOSLH (Note 14) A B n B(n+1) SAB = 1 0.5 ns tOSHL (Note 14) 0.4 tPVHL (Note 15)(Note 16) A B n B(n+1) SAB = 1 2.0 ns tOSLH (Note 14) LECLKAB B n B(n+1) SAB = 1 0.5 ns tOSHL (Note 14) 0.4 tPVHL (Note 15)(Note 16) LECLKAB B n B(n+1) SAB = 1 2.0 ns tOSLH (Note 14) LECLKAB B n B(n+1) SAB = 0 0.5 ns tOSHL (Note 14) 0.4 tPVHL (Note 14)(Note 15) LECLKAB B n B(n+1) SAB = 0 2.0 ns tOSLH (Note 14) B C n C (n+1) SBC = 1 0.4 ns tOSHL (Note 14) 0.4 tOST (Note 14) B C n C (n+1) SBC = 1 1.0 ns tPV (Note 15) B C n C (n+1) SBC = 1 1.5 ns tOSLH (Note 14) LECLKBC C n C (n+1) SBC = 1 0.4 ns tOSHL (Note 14) 0.4 tOST (Note 14) LECLKBC C n C (n+1) SBC = 1 1.0 ns tPV (Note 15) LECLKBC C n C (n+1) SBC = 1 1.5 ns tOSLH (Note 14) LECLKBC C n C (n+1) SBC = 0 0.4 ns tOSHL (Note 14) 0.4 tOST (Note 14) LECLKBC C n C (n+1) SBC = 0 1.0 ns tPV (Note 15) LECLKBC C n C (n+1) SBC = 0 1.5 ns tOSLH (Note 14) SEL C n C (n+1) 0.4 ns tOSHL (Note 14) 0.4 tOST (Note 14) SEL C n C (n+1) 1.0 ns tPV (Note 15) SEL C n C (n+1) 1.2 ns

11 www.fairchildsemi.com GTLP10B320 Test Circuits and Timing Waveforms Test Circuit for A Outputs Note A: CL includes probes and Jig capacitance. Test Circuit for B Outputs Note B: For B Port, CL = 30 pF or 10 pF. Voltage Waveform - Propagation Delay Times Voltage Waveform - Setup and Hold Times Voltage Waveform - Pulse Width Voltage Waveform - Enable and Disable times Output Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the control output. Output Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the control output. Input and Measure Conditions All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), ZO = 50Ω The outputs are measured one at a time with one transition per measurement. Test S tPLH /tPHL Open tPLZ /tPZL 6V tPHZ /tPZH GND A or LVTTL Pins B or GTLP Pins VinHIGH VCC 1.5 VinLOW 0.0 0.0 VM VCC /2 1.0 VX VOL + 0.3V N/A VY VOH − 0.3V N/A

www.fairchildsemi.com 12 GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com