GTL2002 PHILIPS | Alldatasheet
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2-bit bi-directional low voltage translator Product data sheet Supersedes data of 2003 Apr 01
2004 Sep 29
Philips Semiconductors Product data sheet GTL20022-bit bi-directional low voltage translator
22004 Sep 29
FEATURES
- 2-bit bi-directional low voltage translator
- Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V buses which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
- Provides bi-directional voltage translation with no direction pin
- Low 6.5 Ω RDS ON resistance between input and output pins (Sn/Dn)
- Supports hot insertion
- No power supply required - Will not latch up
- 5 V tolerant inputs
- Low stand-by current
- Flow-through pinout for ease of printed circuit board trace routing
- ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V per JESD22-C101
- Packages offered: SO8, TSSOP8 (MSOP8), VSSOP8
APPLICATIONS
- Any application that requires bi-directional or unidirectional voltage level translation from any voltage between 1.0 V and 5.0 V to any voltage between 1.0 V and 5.0 V
- The open drain construction with no direction pin is ideal for processor I2C port translation to the normal 3.3 V or 5.0 V I2C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels.
DESCRIPTION
The Gunning Transceiver Logic — Transceiver Voltage Clamps (GTL–TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2002 provides 2 NMOS pass transistors (Sn and Dn) with a common gate REF ) and a reference transistor (SREF and DREF ). The device allows bi-directional voltage translations between 1.0 V and 5.0 V without use of a direction pin. When the Sn or Dn port is LOW the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is high, the voltage on the Sn port is limited to the voltage set by the reference transistor (S REF ). When the Sn port is high, the Dn port is pulled to VCC by the pull up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user, without the need for directional control. All transistors have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the transistors is symmetrical. Because all transistors in the device are identical, S REF and DREF can be located on any of the other two matched Sn/Dn transistors, allowing for easier board layout. The translator’s transistors provides excellent ESD protection to lower voltage devices and at the same time protect less ESD resistant devices.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DWG NUMBER 8-Pin Plastic SO –40 °C to +85 °C GTL2002D GTL2002 SOT96–1 8-Pin Plastic TSSOP (MSOP) –40 °C to +85 °C GTL2002DP 2002 SOT505–1 8-Pin Plastic VSSOP –40 °C to +85 °C GTL2002DC 2002 SOT765–1 Standard packing quantities and other packaging data is available at www.standardproducts.philips.com/packaging.
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Figure 1. SO8 and TSSOP8 pinning Figure 2. VSSOP8 pinning
- Sn is not pulled up or pulled down.
- Sn follows the Dn input LOW.
- VTT is equal to the SREF voltage.
- Dn is pulled up to VCC through an external resistor.
- Dn follows the Sn input LOW.
- VTT is equal to the SREF voltage.
Figure 3. Clamp schematic
Philips Semiconductors Product data sheet GTL20022-bit bi-directional low voltage translator
2004 Sep 29 4
Bi-directional translation For the bi-directional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the GREF input must be connected to DREF and both pins pulled to HIGH side VCC through a pull-up resistor (typically 200 kΩ ). A filter capacitor on DREF is recommended. The processor output can be totem pole or open drain (pull-up resistors may be required) and the chipset output can be totem pole or open drain (pull-up resistors are required to pull the Dn outputs to VCC ). However, if either output is totem pole, data must be uni-directional or the outputs must be 3-statable and the outputs must be controlled by some direction control mechanism to prevent HIGH-to-LOW contentions in either direction. If both outputs are open drain, no direction control is needed. The opposite side of the reference transistor (SREF ) is connected to the processor core power supply voltage. When DREF is connected through a 200 kΩ resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V to VCC – 1.5 V, the output of each Sn has a maximum output voltage equal to SREF and the output of each Dn has a maximum output voltage equal to VCC . 1.8 V GND G REF SREF 1.5 V 1.2 V 1.0 V SA00642 GTL2002 VCORE CPU I/O CHIPSET I/O TOTEM POLE OR OPEN DRAIN I/O TYPICAL BI-DIRECTIONAL VOLTAGE TRANSLATION 5 V VCC Sn Dn CHIPSET I/O 3.3 V VCC INCREASE BIT SIZE BY USING
10 BIT GTL2010 OR
22 BIT GTL2000
200 kΩ Figure 4. Bi-directional translation to multiple higher voltage levels such as an I2C-bus application
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output voltage equal to SREF . Figure 5. Uni-directional down translation, to protect low voltage processor pins For uni-directional up translation, lower voltage to higher voltage, the reference transistor is connected the same as for a down translation. Figure 6. Uni-directional up translation, to higher voltage chip sets
Philips Semiconductors Product data sheet GTL20022-bit bi-directional low voltage translator
2004 Sep 29 6
The pull-up resistor value needs to limit the current through the pass transistor when it is in the “on” state to about 15 mA. This will guarantee a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage will also be higher in the “on” state. To set the current through each pass transistor at 15 mA, the pull-up resistor value is calculated as follows: Resistor value (/C0087) Pull–up voltage (V)/C00420.35 V 0.015 A The table below summarizes resistor values for various reference voltages and currents at 15 mA and also at 10 mA and 3 mA. The resistor value shown in the +10 % column or a larger value should be used to ensure that the pass voltage of the transistor would be 350 mV or less. The external driver must be able to sink the total current from the resistors on both sides of the GTL–TVC device at 0.175 V, although the 15 mA only applies to current flowing through the GTL–TVC device. See Application Note AN10145-01 Bi-Directional Voltage Translators for more information. PULL-UP RESISTOR VALUES PULL-UP RESISTOR VALUE ( Ω ) VOLTAGE 15 mA 10 mA 3 mA VOLTAGE NOMINAL + 10 % NOMINAL + 10 % NOMINAL + 10 %
5.0 V 310 341 465 512 1550 1705
3.3 V 197 217 295 325 983 1082
2.5 V 143 158 215 237 717 788
1.8 V 97 106 145 160 483 532
1.5 V 77 85 115 127 383 422
1.2 V 57 63 85 94 283 312
NOTES: 1. Calculated for VOL = 0.35 V 2. Assumes output driver VOL = 0.175 V at stated current 3. +10 % to compensate for VDD range and resistor tolerance. ABSOLUTE MAXIMUM RATINGS 1, 2, 3 SYMBOL PARAMETER CONDITIONS RATING UNIT VSREF DC source reference voltage –0.5 to +7.0 V VDREF DC drain reference voltage –0.5 to +7.0 V VGREF DC gate reference voltage –0.5 to +7.0 V VSn DC voltage Port Sn –0.5 to +7.0 V VDn DC voltage Port Dn –0.5 to +7.0 V IREFK DC diode current on reference pins VI < 0 V –50 mA ISK DC diode current Port Sn VI < 0 V –50 mA IDK DC diode current Port Dn VI < 0 V –50 mA IMAX DC clamp current per channel Channel in ON-state ±128 mA Tstg Storage temperature range –65 to +150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Philips Semiconductors Product data sheet GTL20022-bit bi-directional low voltage translator
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RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS LIMITS UNITSYMBOL PARAMETER CONDITIONS Min Max UNIT VI/O Input/output voltage (Sn, Dn) 0 5.5 V VSREF DC source reference voltage1 0 5.5 V VDREF DC drain reference voltage 0 5.5 V VGREF DC gate reference voltage 0 5.5 V IPASS Pass transistor current — 64 mA Tamb Operating ambient temperature rangeIn free air –40 +85 °C NOTE: 1. VSREF ≤ VDREF – 1.5 V for best results in level shifting applications.
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted) SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT VOL LOW-level output voltageVDD = 3.0 V; VSREF = 1.365 V; VSn or VDn = 0.175 V; Iclamp = 15.2 mA — 260 350 mV VIK Input clamp voltage II = –18 mA VGREF = 0 V — — –1.2 V IIH Gate input leakage VI = 5 V VGREF = 0 V — — 5 µA C I(GREF) Gate capacitance VI = 3 V or 0 V — 19.4 — pF C IO(OFF) Off capacitance VO = 3 V or 0 VVGREF = 0 V — 7.4 — pF C IO(ON) On capacitance VO = 3 V or 0 VVGREF = 3 V — 18.6 — pF VGREF = 4.5 V — 3.5 5 VGREF = 3 V IO =6 4m A — 4.4 7 Ω VI = 0 V VGREF = 2.3 V IO = 64 mA — 5.5 9 Ω r 2 On resistance VGREF = 1.5 V — 67 105 ron2 On -resistance VGREF = 1.5 V IO = 30 mA — 9 15 Ω V =24V VGREF = 4.5 V — 7 10 VI = 2.4 V VGREF = 3 V IO = 15 mA — 58 80 Ω VI = 1.7 V VGREF = 2.3 V — 50 70 NOTES: 1. All typical values are measured at Tamb = 25 °C 2. Measured by the voltage drop between the Sn and the Dn terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (Sn or Dn) terminals.
Philips Semiconductors Product data sheet GTL20022-bit bi-directional low voltage translator
2004 Sep 29 8
AC CHARACTERISTICS FOR TRANSLATOR TYPE APPLICATIONS LIMITS SYMBOL PARAMETER WAVEFORM Tamb = –40 °C to +85 °C UNIT MIN TYP 1 MAX tPLH 2 Propagation delay Sn to Dn; Dn to Sn 0.5 1.5 5.5 ns NOTES: 2. Propagation delay guaranteed by characterization. 3. C ON(max) of 30 pF and a COFF(max) of 15 pF is guaranteed by design. AC WAVEFORMS VM = 1.5 V; VIN = GND to 3.0 V INPUT tPHL tPLH VM VM VM VM TEST JIG OUTPUT HIGH-to-LOW LOW-to-HIGH VM VM DUT OUTPUT HIGH-to-LOW LOW-to-HIGH VI GND VDD2 VOL VDD2 VOL tPHL 1 tPLH 1 tPHL tPLH SA00659 Waveform 1. The Input (Sn) to Output (Dn) propagation delays TEST CIRCUIT VREF S1 S2 D REF D 1 D 2G REF SA00646 PULSE GENERATOR DUT SREF VDD1 VDD2 VDD2 VDD2 200 kΩ 150 Ω TEST JIG 150 Ω 150 Ω Waveform 2. Load circuit
Philips Semiconductors Product data sheet GTL20022-bit bi-directional low voltage translator
2004 Sep 29 9
AC CHARACTERISTICS FOR CBT TYPE APPLICATION GND = 0 V; tR; CL = 50 pF SYMBOL PARAMETER DESCRIPTION LIMITS Tamb = –40 °C to +85 °C G REF = 5 V ± 0.5 V UNITS Min Mean Max tpd Propagation delay1 — — 250 ps NOTES: 1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance). AC WAVEFORMS VM = 1.5 V; VIN = GND to 3.0 V INPUT 1.5 V OUTPUT tPLH tPHL SA00639 1.5 V 1.5 V 1.5 V 3 V 0 V VOH VOL Waveform 3. Input (Sn) to Output (Dn) Propagation Delays TEST CIRCUIT AND WAVEFORMS C L = 50 pF 500 Ω Load Circuit DEFINITIONS C L = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. TEST S1 tpd open tPLZ /tPZL 7 V tPHZ /tPZH open SA00012 500 ΩFrom Output Under Test 7 V Open GND Waveform 4. Load circuit
Philips Semiconductors Product data sheet GTL20022-bit bi-directional low voltage translator
2004 Sep 29 10
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
Philips Semiconductors Product data sheet GTL20022-bit bi-directional low voltage translator
2004 Sep 29 11
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
Philips Semiconductors Product data sheet GTL20022-bit bi-directional low voltage translator
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VSSOP8: plastic very thin shrink small outline package; body width 2.3 mm SOT765-1
Philips Semiconductors Product data sheet GTL20022-bit bi-directional low voltage translator
2004 Sep 29 13
REVISION HISTORY
_3 20040929 Product data (9397 750 13058). Supersedes data of 2003 Apr 01 (9397 750 11349). Modifications:
- “Features” section on page 2, last bullet: add “(MSOP8)”
- “Ordering information” table on page 2: add “(MSOP)” to cell 8-Pin Plastic TSSOP in Packages column.
- Add VSSOP8 package offering. _2 20030401 Product data (9397 750 11349); ECN 853-2214 29603 Dated 28 February 2003. Supersedes data dated 2000 Aug 16 (9397 750 07417). _1 20000816 Product data (9397 750 07417); ECN 853-2214 24367 dated 2000 Aug 16.
Philips Semiconductors Product data sheet GTL20022-bit bi-directional low voltage translator
2004 Sep 29 14
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 09-04 Document order number: 9397 750 13058 Philips Semiconductors Data sheet status[1] Objective data sheet Preliminary data sheet Product data sheet Product status[2] [3] Development Qualification Production Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Level I II III