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GMS87C7216LQ

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8-BIT SINGLE-CHIP MICROCONTROLLERS

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MAGNACHIP SEMICONDUCTOR LTD. 8-BIT SINGLE-CHIP MICROCONTROLLERS GMS81C7208 GMS81C7216 User’s Manual (Ver. 1.04)

Version 1.04 Published by 2004 MagnaChip Semiconductor Ltd. All right reserved. Additional information of this manual may be served by MagnaChip Semiconductor offices in Korea or Distributors and Representatives listed at address directory. MagnaChip Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable ; however, MagnaChip Semiconductor is in no way re- sponsible for any violations of patents or other rights of the third party generated by the use of this manual.

REVISION HISTORY

VERSION 1.04 (FEB. 2005) This book Fixed some errata at page32 (Port Mode Register). VERSION 1.03 (SEP. 2004) This book The company name, Hynix Semiconductor Inc. changed to MagnaChip Semiconductor Ltd. VERSION 1.02 (AUG. 2003) Delete I DD3 and the following sentence at page11. The bit7(SUBM) of LCR register must be set to “1” by software because of reduction current consumption(reset value=”0”). VERSION 1.01 (AUG. 2003) Fixed some errata. VERSION 1.00 (AUG. 2003) First Edition 44MQFP/LQFP package.

FEB. 2005 Ver 1.04 1 6. PORT STRUCTURES 7

2 FEB. 2005 Ver 1.04

FEB. 2005 Ver 1.04 1 GMS81C7208/16 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH LCD DRIVER & A/D CONVERTER 1. OVERVIEW

1.1 Description

The GMS81C7208/7216 is advanced CM OS 8-bit microcontrollers with 8K/16K bytes of ROM. Ther e are a powerful microcontroller which provides a highly flexible and cost effective solution to many LCD applications. These provide the following standard features:8K/ 16K bytes of mask type ROM or 16K bytes OTP ROM, 448 bytes of RAM, 8-bit Timer/Counter, 8-bit A/D converter, programmable buzz- er driving port, 8-bit basic interval timer, watch dog timer, serial peripheral interface, on chip oscillator and clock circuitry. They also come with 4com/17seg LCD driver. In addition, it support power saving mode to reduce power consumption.

1.2 Features

8K/16K Bytes On-chip Programmable ROM
448 Bytes of On-chip Data RAM (Included Stack Area and 27 Nibbles LCD Display RAM)
Minimum Instruction Execution Time 1µs at 4MHz (2cycle NOP Instruction)
One 8-bit Basic Interval Timer
One Watch Timer
One Watchdog Timer
Four 8-bit Timer/Event Counter (or Two 16-bit Timer/Event Counter)
Three External Interrupt Input Ports
One Programmable 6-bit Buzzer Driving Port - 500Hz ~ 250kHz@4MHz
29 I/O Ports
Three Channel 8-bit A/D Converter
One 8-bit Serial Communication Interface
LCD Display/ Controller - Static Mode (20SEG x 1COM, Static) - 1/2 Duty Mode (19SEG x 2COM, 1/2 or 1/3 Bias) - 1/3 Duty Mode (18SEG x 3COM, 1/3 Bias) - 1/4 Duty Mode (17SEG x 4COM, 1/3 Bias) - Internal Built-in Resistor Circuit for Bias
Twelve Interrupt Sources - Basic Interval Timer: 1 - External Input: 3 - Timer/Event Counter: 4 - ADC: 1 - Serial Interface: 1 - WT:1 - WDT: 1
Main Clock Oscillation (1.0~4.5MHz) - Crystal - Ceramic Resonator - External R Oscillator (Built-in Capacitor)
Power Saving Operation Mode - 2/8/16/64 Divided System Clock Selectable
Power Down Mode - STOP Mode - SLEEP Mode
Wide Temperature Range - Industrial : -40°C ~ + 85°C
2.7V to 5.5V Wide Operating Voltage Range
Noise Immunity Circuit for EMS - Power Fail Processor - Built-in Noise Filter
44MQFP, 44LQFP Package Types
Available 16K Bytes OTP Version Device Name ROM Size RAM Size I/O OTP Package GMS81C7208 8K bytes 448 bytes 29 GMS87C7216 44MQFP, 44LQFP GMS81C7216 16K bytes 448 bytes 29

2 FEB. 2005 Ver 1.04

1.3 Development Tools

Note: There are several setting sw itches in the Emulator. User should read carefully and do setting properly before developing the program refer to "24.2 Emulator EVA. Board Setting" on page 86. Otherwise, the Emulator may not work properly. The GMS81C7208/16 is supported by a full-featured macro as- sembler, an in-circu it emulator CHOICE-Dr. TM and OTP pro- grammers. There are two differe nt type programmers, one is single type, another is gang type. For more detail, refer to OTP Programming chapter. Macro assembler operates under the MS- Windows 95/98/2000/XPTM. Please contact sales part of MagnaChip Semiconductor.

1.4 Ordering Information

Software - MS- Window base assembler - Linker / Editor / Debugger Hardware (Emulator) - CHOICE-Dr. - CHOICE-Dr. EVA81C7X B/D OTP program- mer - PGM-Plus - CHOICE-SIGMA (Single type) - CHOICE-GANG4 (4-gang type) Device name ROM Size (bytes) RAM size Package Mask ROM version GMS81C7208 Q GMS81C7216 Q GMS81C7208 LQ GMS81C7216 LQ 8K bytes 16K bytes 8K bytes 16K bytes 448 bytes 448 bytes 448 bytes 448 bytes 44MQFP 44MQFP 44LQFP 44LQFP OTP ROM version GMS87C7216 Q GMS87C7216 LQ 16K bytes OTP 16K bytes OTP 448 bytes 448 bytes 44MQFP 44LQFP

FEB. 2005 Ver 1.04 3 2. BLOCK DIAGRAM GMS81C7208/7216 ALU LCD Controller / Driver (LCDC) Accumulator Stack Pointer Interrupt Controller Data Memory LCD Display Memory Program Memory Data Table PC 8-bit Basic Interval Timer PC R0R3 Buzzer Driver PSW System controller Timing generator System Clock Controller Clock Generator frequency RESET XIN XOUT Common Drive Output COM0 R00 / INT0 R01 / INT1 R02 / INT2 R03 / EC0 R04 / EC2 R05 / SCK R06 / SO R07 / SI R30 / BUZ VDD VSS Power Supply VCL0 VCL1 VCL2 COM1/SEG26 COM2/SEG25 COM3/SEG24LCD Power Control Circuit AVDD AVSS Power Supply Circuit BIAS R21 / AN1 R22 / AN2 R23 / AN3 8-bit A/D Converter 8-bit Timer/CounterSIO R4 R5 R6 Watch/ Timer Segment Drive Output SEG0 ~ SEG11 R40-R47 Watchdog R50-R53 R60-R64 LCD Power Supply SEG16 ~ SEG20

4 FEB. 2005 Ver 1.04 3. PIN ASSIGNMENT 44MQFP (Top View) 3122 GMS81C7208/16 R63 / SEG19 R47 / SEG7 R50 / SEG8 R51 / SEG9 R52 / SEG10 R53 / SEG11 R60 / SEG16 R61 / SEG17 R62 / SEG18 R46 / SEG6 R45 / SEG5 SEG20 / R64 SEG26 / COM1 SEG25 / COM2 SEG24 / COM3 VCL0 VCL1 VCL2 AVDD COM0 VDD AN1 / R21 AVSS SI / R07 VSS RESET XOUT XIN BIAS SCK / R05 SO / R06 AN3 / R23 AN2 / R22 R44 / SEG4 R43 / SEG3 R42 / SEG2 R41 / SEG1 R40 / SEG0 R30 / BUZO R00 / INT0 R01 / INT1 R02 / INT2 R03 / EC0 R04 / EC2 44LQFP (Top View) 3122 GMS81C7208/16 R63 / SEG19 R47 / SEG7 R50 / SEG8 R51 / SEG9 R52 / SEG10 R53 / SEG11 R60 / SEG16 R61 / SEG17 R62 / SEG18 R46 / SEG6 R45 / SEG5 SEG20 / R64 SEG26 / COM1 SEG25 / COM2 SEG24 / COM3 VCL0 VCL1 VCL2 AVDD COM0 VDD AN1 / R21 AVSS SI / R07 VSS RESET XOUT XIN BIAS SCK / R05 SO / R06 AN3 / R23 AN2 / R22 R44 / SEG4 R43 / SEG3 R42 / SEG2 R41 / SEG1 R40 / SEG0 R30 / BUZO R00 / INT0 R01 / INT1 R02 / INT2 R03 / EC0 R04 / EC2

FEB. 2005 Ver 1.04 5 4. PACKAGE DIMENSION 44LQFP 1.60 max. SEE DETAIL “A” 0.75 0.45 0-7° 0.15 0.05 1.00 BSC DETAIL “A” UNIT: MM 0.45 0.30

0.80 BSC

1.45 1.35 0.20 0.09 10.10 9.90 12.20 11.80 10.10 9.90 12.20 11.80 44MQFP 2.35 max. SEE DETAIL “A” 1.03 0.73 0-7° 0.25 0.10 1.60 BSC DETAIL “A” UNIT: MM 0.45 0.30 2.10 1.95 0.23 0.13 10.10 9.90 13.45 12.95 10.10 9.90 13.45 12.95

6 FEB. 2005 Ver 1.04 5. PIN FUNCTION VDD: Supply voltage. VSS: Circuit ground. RESET: Reset the MCU. AVDD: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use inde- pendent power source as well as possible, other than digital pow- er source. AVSS: ADC circuit ground. XIN: Input to the inverting oscillator amplifier and input to the in- ternal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. BIAS: LCD bias voltage input pin. VCL0~VCL2: LCD driver power supply pins. The voltage on each pin is VCL2> VCL1> VCL0. For details, Refer to “18. LCD DRIVER” on page 65. COM0~COM3: LCD common signal output pins. Also, the pins of COM1,COM2 and COM3 are sh ared with LCD segment sig- nal outputs of SEG26, SEG25, SEG24 as application require- ment. R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or schmitt trigger inputs. Also, pull-up resistors and open-drain outputs are software assignable. In addition, R0 serves the functions of the various following spe- cial features. R21~R23: R2 is an 3-bit CMOS bidirectional I/O port. R2 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. Also, pull-up resistors and open-drain outputs are soft- ware assignable. In addition, R2 is shared with the ADC input. R30: R3 is a 1-bit CMOS bidirect ional I/O port. R30 pin 1 or 0 written to the Port Direction Register can be used as output or in- put. Also, pull-up resistor and ope n-drain output is software as- signable. In addition, R30 serves the function of the following spe- cial feature. SEG0~SEG7: These pins generate LCD segment signal output. Every LCD segment pins are shared with normal R4 input/output port. R4 is an 8-bit CMOS bidire ctional I/O port. R4 pins 1 or 0 written to the Port Direction Register can be used as outputs or in- puts. SEG8~SEG11: These pins generate LCD segment signal output. Every LCD segment pins are shared with normal R5 input/output port. R5 is an 4-bit CMOS bidire ctional I/O port. R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or in- puts. SEG16~SEG20: These pins generate LCD segment signal out- put. Every LCD segment pins are shared with normal R6 input/output port. R6 is an 5-bit CMOS bidire ctional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or in- puts. Port Pin Alternate Function R00 R01 R02 R03 R04 R05 R06 R07 INT0 (External Interrupt 0) INT1 (External Interrupt 1) INT2 (External Interrupt 2) EC0 (Event Counter Input 0) EC2 (Event Counter Input 2) SCK (Serial Clock) SO (Serial Data Output) SI (Serial Data Input) Port Pin Alternate Function R21 R22 R23 AN1 (Analog Input 1) AN2 (Analog Input 2) AN3 (Analog Input 3) Port Pin Alternate Function R30 BUZ (Buzzer driving output) LCD Pin Function Port Pin SEG0 (LCD Segment 0 Signal Output) SEG1 (LCD Segment 1 Signal Output) SEG2 (LCD Segment 2 Signal Output) SEG3 (LCD Segment 3 Signal Output) SEG4 (LCD Segment 4 Signal Output) SEG5 (LCD Segment 5 Signal Output) SEG6 (LCD Segment 6 Signal Output) SEG7 (LCD Segment 7 Signal Output) R40 R41 R42 R43 R44 R45 R46 R47 LCD Pin Function Port Pin SEG8 (LCD Segment 8 Signal Output) SEG9 (LCD Segment 9 Signal Output) SEG10 (LCD Segment 10 Signal Output) SEG11 (LCD Segment 11 Signal Output) R50 R51 R52 R53 LCD Pin Function Port Pin SEG16 (LCD Segment 16 Signal Output) SEG17 (LCD Segment 17 Signal Output) SEG18 (LCD Segment 18 Signal Output) SEG19 (LCD Segment 19 Signal Output) SEG20 (LCD Segment 20 Signal Output) R60 R61 R62 R63 R64

FEB. 2005 Ver 1.04 7 6. PORT STRUCTURES PIN NAME (Alternate) In/Out (Alternate) Function Basic Alternate VDD - Supply Voltage VSS - Circuit Ground RESET I Reset Signal Input AVDD - Supply Voltage Input Pin for ADC AVSS - Ground Level Input Pin for ADC XIN I Oscillation Input XOUT O Oscillation Output BIAS I LCD Bias Voltage Input VCL0~VCL2 I LCD Driver Power Supply COM0 O LCD Common Signal Output COM1(SEG26) O(O) LCD Common Signal Output LCD Segment Signal outputCOM2(SEG25) O(O) COM3(SEG24) O(O) R00 (INT0) I/O (I) 8-bit General I/O Ports External Interrupt 0 Input R01 (INT1) I/O (I) External Interrupt 1 Input R02 (INT2) I/O (I) External Interrupt 2 Input R03 (EC0) I/O (I) Timer/Counter 0 External Input R04 (EC2) I/O (I) Timer/Counter 1 External Input R05 (SCK) I/O (I/O) Serial Clock I/O R06 (SO) I/O (O) Serial Data Output R07 (SI) I/O (I) Serial Data Input R21~R23(AN1~AN3) I/O(I) 3-bit General I/O Ports Analog Voltage Input R30(BUZO) I/O(O) 1-bit General I/O Ports Buzzer Driving Output SEG0 ~ SEG7 (R40~R47) O (I/O) LCD Segment Signal Output 8-bit General I/O Ports SEG8 ~ SEG11 (R50~R53) O (I/O) LCD Segment Signal Output 4-bit General I/O Ports SEG16 ~ SEG20 (R60~R64) O (I/O) LCD Segment Signal Output 5-bit General I/O Ports Table 6-1 Port Function Description

8 FEB. 2005 Ver 1.04 R00/INT0, R01/INT1, R02/INT2, R03/EC0, R04/EC2, R05/SCK, R07/SI R30/BUZ, R06/SO R21/AN1~R23/AN3 RESET R40~R47, R50~R53, R60~R64 / SEG0~SEG11, SEG16~SEG20 Pin Data Reg. Dir. Reg. Noise Canceller INT0 ~ INT2 Pull up Reg. MUX RD VDD VSS Pull-up Tr. EC0,EC2 Open Drain Reg. Data Bus SI,SCK Tr.: Transistor Reg.: Register Pin Data Reg. Dir. Reg. Pull up Reg. MUX VDD VSS Pull-up Tr. Open Drain Reg. BUZ,SO Data Bus RD Pin Data Reg. Dir. Reg. Analog SwitchAN1 ~ AN3 Pull up Reg. MUX RD VDD VSS Pull-up Tr. Open Drain Reg. Data Bus RESET VSS Noise Canceller Internal RESET VSS VDD High Voltage On(OTP) VDD OTP MCU :disconnected Mask MCU :connected OTP MCU :connected Mask MCU :disconnected Enable OTP Program Mode Pin Data Reg. Dir. Reg. MUX RD VDD VSS Data Bus VCL2 VCL1 VSS VCL0 LCD Data VCL2 Enable LCD Data VCL1 Enable LCD Data VCL0 Enable LCD Data GND Enable

FEB. 2005 Ver 1.04 9 COM0~COM3 / SEG26~SEG24 XIN, XOUT Pin VCL2 VCL1 VSS VCL0 LCD Data VCL2 Enable LCD Data VCL1 Enable LCD Data VCL0 Enable LCD Data GND Enable XOUT VDD VSS Main Clock XIN STOP & Main Clock OFF

10 FEB. 2005 Ver 1.04 7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Voltage on any pin with respect to Ground (VSS) Maximum output current sourced by (IOH per I/O Pin) Note: Stresses above thos e listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the de- vice. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability.

7.2 Recommended Operating Conditions

7.3 DC Electrical Characteristics

(TA=-40~85°C, VDD=2.7~5.5V), Parameter Symbol Condition Specifications Unit Min. Max. Supply Voltage VDD fXIN=4.19MHz 2.7 5.5 V Operating Frequency fXIN VDD=2.7~5.5V 14 . 5 M H z Operating Temperature TOPR -40 +85 °C Parameter Symbol Condition Specifications Unit Min. Typ. Max. Input High Voltage VIH1 RESET, R0 (except R06) 0.8 VDD - VDD V VIH2 Other pins 0.7 VDD - VDD V Input Low Voltage VIL1 RESET, R0 (except R06) 0 - 0.2 VDD V VIL2 Other pins 0 - 0.3 VDD V Output High Voltage VOH1 R0,R2,R3 IOH1=-0.5mA VDD-0.1 -- V VOH2 SEG, COM IOH2=-30µA- - 0 . 4 V Output Low Voltage VOL1 R0,R2,R3 IOL1=0.4mA - - 0.2 V VOL2 SEG, COM IOL2=30µA VDD-0.2 -- V Input High Leakage Current IIH1 VIN=VDD, All Input Pins except XIN --1 µA IIH2 VIN=VDD, XIN -- 2 0 µA Input Low Leakage Current IIL1 VIN=0, All Input Pins except XIN -- - 1 µA IIL2 VIN=0, XIN -- - 2 0 µA Pull-up Resistor RPORT VIN=0V, VDD=5.5V, R0, R2 60 160 350 k Ω

FEB. 2005 Ver 1.04 11 LCD Voltage Dividing Resistor RLCD VDD= 5 . 5 V 4 56 58 5 k Ω Voltage Drop |VDD-COMn| , n=0~3 VDC VDD=2.7 ~ 5.5V -15µA per Common Pin - - 120 mV Voltage Drop |VDD-SEGn| , n=0~26 VDS VDD=2.7 ~ 5.5V -15µA per Segment Pin - - 120 mV VCL2 Output Voltage VCL2 VDD=2.7 ~ 5.5V, 1/3 Bias BIAS pin and VCL2 pin are shorted VDD-0.3 V DD VDD+0.3 VVCL1 Output Voltage VCL1 0.66VDD -0.2 0.66VDD 0.66VDD +0.3 VCL0 Output Voltage VCL0 0.33VDD -0.3 0.33VDD 0.33VDD +0.3 RC Oscillation Fre- quency fRC R=60kΩ, VDD= 5 V 123 M H z Supply Current 1 ( ) means at 3V opera- tion IDD1 Main Clock Operation Mode 2 VDD=5.5V±10%, XIN=4MHz - 2.9 (1.3) 7.0 (3.0) mA IDD2 Sleep Mode 3 VDD=5.5V±10%, XIN=4MHz - 0.4 (0.1) 1.7 (1.0) mA IDD6 Stop Mode 4 VDD=5V±10%, XIN= 0Hz When the bit7 of LCR register is “1”. - 1.0 (0.5) (5) µA 1. Supply current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, comparator volt- age divide resistor, LVD circuit and output port drive currents. 2. This mode set System Clock Mode Register(SCMR) to xxxx0000 B that is fXIN/2 3. This mode set SCMR to xxxx0000 B (fXIN/2) and set SMR to “1” 4. Main frequency clock stops and set SCMR to xxxx0011 B and set SMR to “1”. Parameter Symbol Condition Specifications Unit Min. Typ. Max. ** Caution : The bit7(SUBM) of LCR register must be set to “1” by software because of reduction current consumption (reset value =”0”).

12 FEB. 2005 Ver 1.04

7.4 A/D Converter Characteristics

(TA=25°C, VSS=0V, VDD=5.0V, AVDD=5.0V @fXIN=4MHz)

7.5 AC Characteristics

(TA=-40~+85°C, VDD=5V±10%, VSS=0V) Parameter Symbol T est Condition Specifications Unit Min. Typ.1 1. Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Max. Analog Input Voltage Range VAIN VDD=AVDD=5.0V VSS-0.3 - AVDD+0.3 V Non-linearity Error NNLE - ±1.0 ±1.5 LSB Differential Non-linearity Error NDNLE - ±1.0 ±1.5 LSB Zero Offset Error NZOE - ±0.5 ±1.5 LSB Full Scale Error NFSE - ±0.25 ±0.5 LSB Gain Error NGE - ±1.0 ±1.5 LSB Overall Accuracy NACC - ±1.0 ±1.5 LSB AVDD Input Current IREF -- 2 0 0 µA Conversion Time TCONV -- 2 0 µs Analog Power Supply Input Range AVDD VDD=5.0V VDD=3.0V 3.0 2.7 - VDD V Parameter Symbol Pins Specifications Unit Min. Typ. Max. Operating Frequency fMAIN XIN 0.455 - 4.2 MHz External Clock Pulse Width tMCPW XIN 80 - - ns External Clock Transition Time tMRCP,tMFCP XIN - - 20 ns Main oscillation Stabilizing Time tMST XIN, XOUT at 4MHz -- 2 0 m s Interrupt Pulse Width tIW INT0, INT1, INT2 2 - - tSYS1 RESET Input Width tRST RESET 8-- tSYS1 Event Counter Input Pulse Width tECW EC0, EC2 2 - - tSYS1 1. t SYS is one of 2/fMAIN or 8/fMAIN or 16/fMAIN or 64/fMAIN in the main clock operation mode.

FEB. 2005 Ver 1.04 13 Figure 7-1 Timing Chart tMRCP tMFCP XIN INT0, INT1 INT2 0.5V VDD-0.5V 0.2VDD 0.8VDD 0.2VDD RESET 0.2VDD 0.8VDDEC0, EC2 tIWtIW tRST tECWtECW 1/fMAIN tMCPW tMCPW tSYS

14 FEB. 2005 Ver 1.04

7.6 Serial Interface Timing Characteristics

(TA=-40~+85°C, VDD=2.7~5.5V, VSS=0V, fXIN=4MHz) Figure 7-2 Serial I/O Timing Chart Parameter Symbol Pins Specifications Unit Min. Typ. Max. Serial Input Clock Pulse tSCYC SCK 2tSYS+200 -8 n s Serial Input Clock Pulse Width tSCKW SCK tSYS+70 -8 n s SIN Input Setup Time (External SCK) tSUS SIN 100 - - ns SIN Input Setup Time (Internal SCK) tSUS SIN 200 - - ns SIN Input Hold Time tHS SIN tSYS+70 -- n s Serial Output Clock Cycle Time tSCYC SCK 4tSYS - 16tSYS ns Serial Output Clock Pulse Width tSCKW SCK tSYS-30 -- n s Serial Output Clock Pulse Transition Time tFSCK tRSCK SCK - - 30 ns Serial Output Delay Time sOUT SO - - 100 ns SCLK SIN 0.2VDD SOUT 0.2VDD 0.8VDD tSCYC tSCKW tSCKW tRSCKtFSCK 0.8VDD tSUS tHS tDS 0.2VDD 0.8VDD

FEB. 2005 Ver 1.04 15

7.7 Typical Characteristics

This graphs and tables provided in this section are for de- sign guidance only and are not tested or guaranteed. In some graphs or tables the data presented are out- side specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean − 3σ) respectively where σ is standard deviation IOL−VOL, VDD=5.5V (mA) IOL VOL (V) IOL−VOL, VDD=3.0V (mA) IOL VOL (V) IOH−VOH, VDD=5.0V -20 -15 -10 (mA) IOH 12 34 5 VOH (V) IOH−VOH, VDD=3.0V (mA) IOH VOH (V) Ta=25°C R0,R1,R2,R3 pin 200 100 (kΩ) -20 04 08 0 Ta (°C) R 12 34 5 fXIN=4MHz VDD−VIH1 (V) VIH1 23 45 6 VDD (V) VDD−VIH2 (V) VIH2 23 45 6 VDD (V) Ta=25°C fXIN=4MHz Ta=25°C R0 (except R06) R2~R6 pin (include R06) fXIN=4MHz VDD−VIH3 (V) VIH1 23 45 6 VDD (V) Ta=25°C XIN R = 6.2kΩ4 (MHz) fXIN 2345 6 VDD (V) Ta=25°C R = 20kΩ R = 180kΩ R = 60kΩ fXIN−VDD Ta=25°C Ta=25°CTa=25°C RPU−Ta, VDD=5.0V

16 FEB. 2005 Ver 1.04 ISTOP(IDD6)−VDD STOP Mode IDD1−VDD (mA) IDD VDD (V) Normal Operation (Main opr.) ISLEEP(IDD2)−VDD fXIN=4MHz VDD−VIL1 (V) VIH1 23 45 6 VDD (V) VDD−VIL2 (V) VIH2 23 45 6 VDD (V) Ta=25°C fXIN=4MHz Ta=25°C R0 (except R06) R2~R6 pin (include R06) fXIN=4MHz VDD−VIL3 (V) VIH1 23 45 6 VDD (V) Ta=25°C XIN 23 45 SLEEP Mode (Main opr.) 400 300 200 100 (µA) IDD 23 45 6 VDD (V) ISTOP(IDD3)−VDD STOP Mode (µA) IDD 23 45 6 VDD (V) fXIN=0Hz Ta=25°C fXIN=4MHz Ta=25°C fXIN=4MHz Ta=25°C (µA) I DD 23 45 6 VDD (V) fSXIN=0Hz Ta=25°C

FEB. 2005 Ver 1.04 17 8. MEMORY ORGANIZATION The GMS81C7208/16 has separate address spaces for Program memory and Data Memory. Progr am memory can only be read, not written to. It can be up to 8K/16K bytes of Program memory. Data memory can be read and written to up to 448 bytes including the stack area and the LCD display RAM area.

8.1 Registers

This device has six registers th at are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. Figure 8-1 Configuration of Registers Accumulator: The Accumulator is the 8-bit general purpose reg- ister, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. Figure 8-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely ef- fective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumula- tors. Stack Pointer: The Stack Pointer is an 8-bit register used for oc- currence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be access (save or restore). Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in ex- cess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 011B H to 01FFH of the internal data memory. The SP is not initialized by hard- ware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Nor- mally, the initial value of “FFH” is used. Note: The Stack Pointer must be initialized by software be- cause its value is undefined after RESET. Example: To initialize the SP LDX #0FFH TXSP ; SP ← FFH Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indi- cates the address of the next inst ruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) con- tains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD opera- tion), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or not borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift In- struction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is “0” and is cleared by any other result. ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD X A SP Y PCL PSW PCH Two 8-bit Registers can be used as a “YA” 16-bit Register Y A Y A SP01H Stack Area (100H ~ 1FFH) Bit 15 Bit 0 87 Hardware Fixed 00H~FFH LCD display RAM area is located in 100H~11AH, SP (Stack Pointer) could be in 00H~FFH. User must have concerning that Stack data does not cross over LCD RAM area.

18 FEB. 2005 Ver 1.04 Figure 8-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Direct page flag G] This flag assigns RAM page for direct addressing mode. In the di- rect addressing mode, addressi ng area is from zero page 00 H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned by RPR regi ster (address 0F3H). It is set by SETG in- struction and cleared by CLRG. When content of RPR is above 2, malfunction will be occurred. [Overflow flag V] This flag is set to “1” when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7F H) or - 128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BI T instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is exe- cuted, bit 7 of memory is copied to this flag. N NEGATIVE FLAG V G B H I Z C MSB LSB RESET VALUE: 00HPSW OVERFLOW FLAG BRK FLAG CARRY FLAG RECEIVES ZERO FLAG INTERRUPT ENABLE FLAG CARRY OUT HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 3 OF ADDITION OPERLANDS SELECT DIRECT PAGE when G=1, page is selected to “page 1” RAM Page Instruction Bit1 of RPR Bit0 of RPR 0 page CLRG X X 0 page SETG 0 0 1 page SETG 0 1 Reserved SETG 1 0 Reserved SETG 1 1

FEB. 2005 Ver 1.04 19 Figure 8-4 Stack Operation At execution of a CALL/TCALL/PCALL PCL PCH 01FC SP after execution SP before execution 01FD 01FD 01FE 01FF 01FF Push down At acceptance of interrupt PCL PCH 01FC 01FC 01FD 01FE 01FF 01FF Push down PSW At execution of RET instruction PCL PCH 01FC 01FF 01FD 01FE 01FF 01FD Pop up At execution of RET instruction PCL PCH 01FC 01FF 01FE 01FE 01FF 01FC Pop up PSW 0100H 01FFH Stack depth At execution of PUSH instruction A 01FC 01FE 01FD 01FE 01FF 01FF Push down SP after execution SP before execution PUSH A (X,Y,PSW) At execution of POP instruction A 01FC 01FF 01FD 01FE 01FF 01FE Pop up POP A (X,Y,PSW)

20 FEB. 2005 Ver 1.04

8.2 Program Memory

A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 8K/ 16K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-5, shows a map of Program Memory. After reset, the CPU begins execution from reset v ector which is stored in ad- dress FFFEH and FFFFH as shown in Figure 8-6. As shown in Figure 8-5, each area is assigned a fixed location in Program Memory. Program Memory area contains the user pro- gram. Figure 8-5 Program Memory Map Page Call (PCALL) area contai ns subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequen tly called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL ad- dress, where it commences the execution of the service routine. The Table Call service area sp aces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 8-7. Example: Usage of TCALL The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFA H. The in- terrupt service locations sp aces 2-byte interval: 0FFF8 H and 0FFF9H for External Interrupt 1, 0FFFAH and 0FFFBH for Exter- nal Interrupt 0, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Mem- ory. Figure 8-6 Interrupt Vector Area Interrupt Vector Area C000H FEFFH FF00H FFC0H FFDFH FFE0H FFFFH PCALL area E000H TCALL area GMS81C7208 8K ROM GMS81C7216 16K ROM 0FFE0H Address Vector Area Memory EA EC EE FA FC FE Timer/Counter 3 Timer/Counter 2 Watch Timer A/D Converter External Interrupt 0 Timer/Counter 1 Basic Interval Timer Key Scan RESET Watchdog Timer Serial Peripheral Interface “-” means reserved area. NOTE: External Interrupt 2 External Interrupt 1 Timer/Counter 0

FEB. 2005 Ver 1.04 21 Figure 8-7 PCALL and TCALL Memory Area PCALL→ rel 4F35 PCALL 35H TCALL→ n 4A TCALL 4 0FFC0H Address Program Memory 0FF00H Address PCALL Area Memory 0FFFFH PCALL Area (256 Bytes) * means that the BRK software interrupt is using same address with TCALL0. NOTE: TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * CA CB CC CD CE CF DA DB DC DD DE DF ~~ ~ NEXT 0FF35H 0FF00H 0FFFFH 11111111 11010110 01001010 PC: FH FH DH 6H ~~ ~ 250FFD6H 0FF00H 0FFFFH NEXT 0FFD7H 0D125H Reverse

22 FEB. 2005 Ver 1.04 Example: The usage software example of Vector address for GMS81C7216. ORG 0FFE0H DW TIMER3 ; Timer-3 DW TIMER2 ; Timer-2 DW WATCH_TIMER ; Watch Timer DW ADC ; ADC DW SIO ; Serial Interface DW NOT_USED ; - DW NOT_USED ; - DW INT2 ; Int.2 DW TIMER1 ; Timer-1 DW TIMER0 ; Timer-0 DW INT1 ; Int.1 DW INT0 ; Int.0 DW WD_TIMER ; Watchdog Timer DW BIT_TIMER ; Basic Interval Timer DW NOT_USED ; - DW RESET ; Reset ORG 0C000H ; in case of 16K ROM Start address ; ORG 0E000H ; in case of 8K ROM Start address ; MAIN PROGRAM * RESET: LDM SCMR,#0 ;When main clock mode DI ;Disable All Interrupts LDM WDTR,#0 ;Disable Watch Dog Timer LDM RPR,#1 CLRG LDX #0 RAM_CLR:LDA #0 ;RAM Clear(!0000H ~ !00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR SETG LDX #0 RAM_CLR1: LDA #0 STA {X}+ CMPX #1BH ;DISPLAY RAM Clear(!0100H ~ !011AH) BNE RAM_CLR1 CLRG LDX #0FFH ;Stack Pointer Initialize TXSP LDM R0, #0 ;Normal Port 0 LDM R0DD,#82H ;Normal Port Direction LDM R0PU,#0 ;Normal Pull Up LDM TDR0,#250 ;8us x 250 = 2000us LDM TM0,#0000_1111B ;Start Timer0, 8us at 4MHz LDM IRQH,#0 LDM IRQL,#0 LDM IENH,#0000_1110B ;Enable INT0, INT1, Timer0 LDM IENL,#0 LDM IEDS,#15H ;Select falling edge detect on INT pin LDM PMR,#3H ;Set external interrupt pin(INT0, INT1) EI ;Enable master interrupt

FEB. 2005 Ver 1.04 23

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into four gr oups, a user RAM, control regis- ters, Stack, and LCD memory. Figure 8-8 Data Memory Map User Memory The both GMS81C7208/16 has 448 × 8 bits for the user memory (RAM). There are two page internal RAM. Page is selected by G-flag and RAM page selection register RPR. When G-flag is cleared to “0”, always page 0 is selected regardless of RPR value. If G-flag is set to “1”, page will be selected according to RPR value. Figure 8-9 RAM Page Configuration Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. There- fore these registers contain control and status bits for the interrupt system, the Timer/Counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0 H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return ran- dom data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit ma- nipulation instruction (SET1, CLR1). Do not use read-mod- ify-write instruction. Use byte manipulation instruction, for example “LDM”. Example; To write at CKCTLR LDM CKCTLR,#09H ;Divide ratio(÷16) Stack Area The stack provides the area where the return address is saved be- fore a jump is performed during the processing routine at the ex- ecution of a subroutine call in struction or the acceptance of an interrupt. When returning from the processi ng routine, executing the sub- routine return instruction [RET] restores the contents of the pro- gram counter from the stack; executing the interrupt return instruction [RETI] restores the c ontents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is au tomatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack lo cation number for the next save. Refer to Figure 8-4 on page 19. User Memory Control Registers or Stack Area 0000H 00BFH 00C0H 00FFH 0100H 01FFH PAGE0 User Memory PAGE1 LCD display RAM (27 Nibbles)011AH 011BH (192 Bytes) (229 Bytes) Page 0 Page 0: 00~FFH Page 1 Page 1: 100~1FFH RPR=1, G=1 G=0

24 FEB. 2005 Ver 1.04

8.4 List of Control Registers

Address Register Name Symbol R/W Initial Value Page 76543210 0 0 C 0 R 0 P o r t D a t a R e g i s t e r R 0 R / W 00000000 p a g e3 2 00C2 R2 Port Data Register R2 R/W - - - - 0 0 0 - page 32 0 0 C 4 R 4 P o r t D a t a R e g i s t e r R 4 R / W 00000000 p a g e3 2 0 0 C 5 R 5 P o r t D a t a R e g i s t e r R 5 R / W - - - -0000 p a g e3 2 0 0 C 6 R 6 P o r t D a t a R e g i s t e r R 6 R / W - - -00000 p a g e3 2 0 0 C 8 R 0 P o r t I / O D i r e c t i o n R e g i s t e r R 0 D D W 00000000 p a g e3 2 00CA R2 Port I/O Direction Register R2DD W - - - - 0 0 0 - page 32 0 0 C C R 4 P o r t I / O D i r e c t i o n R e g i s t e r R 4 D D W 00000000 p a g e3 2 0 0 C D R 5 P o r t I / O D i r e c t i o n R e g i s t e r R 5 D D W - - - -0000 p a g e3 2 0 0 C E R 6 P o r t I / O D i r e c t i o n R e g i s t e r R 6 D D W - - -00000 p a g e3 2 0 0 D 0 R 0 P o r t P u l l - u p R e g i s t e r R 0 P U W 00000000 p a g e3 2 00D2 R2 Port Pull-up Register R2PU W - - - - 0 0 0 - page 32 0 0 D 4 R 0 P o r t O p e n D r a i n C o n t r o l R e g i s t e r R 0 C R W 00000000 p a g e3 2 00D6 R2 Port Open Drain Control Register R2CR W - - - - 0 0 0 - page 32 0 0 D 8 E x t . I n t e r r u p t E d g e S e l e c t i o n R e g i s t e r I E D S R / W - -000000 p a g e3 2 0 0 D 9 P o r t M o d e R e g i s t e r P M R R / W - -000000p a g e3 2 , page 57 00DA Interrupt Enable Lower Byte Register IENL R/W 0 - - 0 0000 p a g e6 0 00DB Interrupt Enable Upper Byte Register IENH R/W - - 0 0 0000 p a g e6 0 0 0 D C I n t e r r u p t R e q u e s t F l a g L o w e r B y t e R e g i s t e r I R Q L R / W 0- -00000 p a g e5 9 0 0 D D I n t e r r u p t R e q u e s t F l a g U p p e r B y t e R e g i s t e r I R Q H R / W - -000000 p a g e5 9 0 0 D F W a t c h D o g T i m e r R e g i s t e r W D T R R / W - - -10010 p a g e7 4 0 0 E 0 T i m e r 0 M o d e R e g i s t e r T M 0 R / W - -000000 p a g e4 3 00E1 T i m e r 0 C o u n t e r R e g i s t e r T 0 R 00000000 p a g e4 3 T i m e r 0 D a t a R e g i s t e r T D R 0 W 11111111 p a g e4 3 Timer0 Input Capture Register CDR0 R 00000000 p a g e4 3 0 0 E 2 T i m e r 1 M o d e R e g i s t e r T M 1 R / W - - -00000 p a g e4 3 0 0 E 3 T i m e r 1 D a t a R e g i s t e r T D R 1 W 11111111 p a g e4 3 00E4 T i m e r 1 C o u n t e r R e g i s t e r T 1 R 00000000 p a g e4 3 Timer1 Input Capture Register CDR1 R 00000000 p a g e4 3 0 0 E 6 T i m e r 2 M o d e R e g i s t e r T M 2 R / W - -000000 p a g e4 4 Table 8-1 Control Registers

FEB. 2005 Ver 1.04 25 00E7 T i m e r 2 C o u n t e r R e g i s t e r T 2 R 00000000 p a g e4 4 T i m e r 2 D a t a R e g i s t e r T D R 2 W 11111111 p a g e4 4 Timer2 Input Capture Register CDR2 R 00000000 p a g e4 4 0 0 E 8 T i m e r 3 M o d e R e g i s t e r T M 3 R / W - - -00000 p a g e4 4 0 0 E 9 T i m e r 3 D a t a R e g i s t e r T D R 3 W 11111111 p a g e4 4 00EA T i m e r 3 C o u n t e r R e g i s t e r T 3 R 00000000 p a g e4 4 Timer3 Input Capture Register CDR3 R 00000000 p a g e4 4 00EC A/D Converter Mode Register ADCM R/W - 0 0 0 0001 p a g e5 3 00ED A/D Converter Data Register ADR R Undefined page 53 00EF Watch Timer Mode Register WTMR R/W - 0 - - 0000 p a g e7 4 0 0 F 1 L C D C o n t r o l R e g i s t e r L C R R / W -0000000 p a g e6 6 00F2 LCD Port Mode Register High LPMR R/W - - 0 0 0000 p a g e6 6 00F3 RAM Paging Register RPR R/W - - - - - - 0 0 page 23, page 66 00F4 B a s i c I n t e r v a l T i m e r R e g i s t e r B I T R R 00000000 p a g e4 1 C l o c k C o n t r o l R e g i s t e r C K C T L R W - - -00111 p a g e4 1 0 0 F 5 S y s t e m C l o c k M o d e R e g i s t e r S C M R R / W 00000000 p a g e3 7 0 0 F B L V D R e g i s t e r L V D R R / W 00000- - - p a g e8 2 0 0 F D B u z z e r D a t a R e g i s t e r B U R W 00000000 p a g e5 7 0 0 F E S e r i a l I / O M o d e R e g i s t e r S I O M R / W 00000001 p a g e5 4 00FF Serial I/O Data Register SIOR R/W Undefined page 54 Address Register Name Symbol R/W Initial Value Page 76543210 Table 8-1 Control Registers Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation W Registers are controlled by both bit and byte manipulation instruction.R/W instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. - : this bit location is reserved.

26 FEB. 2005 Ver 1.04 Three registers are mapped on same address. Two registers are mapped on same address. Address Timer/Counter Mode Capture Mode E1H T0 [R], TDR0 [W] CDR0 [R], TDR0 [W] E3H TDR1 [W] TDR1 [W] E4H T1 [R] CDR1 [R] E7H T2 [R], TDR2 [W] CDR2 [R], TDR2 [W] E9H TDR3 [W] TDR3 [W] EAH T3 [R] CDR3 [R] Address Basic Interval Timer F4H BITR [R], CKCTLR [W]

FEB. 2005 Ver 1.04 27

8.5 Addressing Mode

The G(H)MS800 series MCU uses six addressing modes;

Register Addressing
Immediate Addressing
Direct Page Addressing
Absolute Addressing
Indexed Addressing
Register Indirect Addressing (1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing → #imm In this mode, second byte (operand) is accessed as a data imme- diately. Example:

0435 ADC #35H

When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. Example: G=1, RPR=01 E45535 LDM 35H,#55H (3) Direct Page Addressing → dp In this mode, a address is specified within direct page. Example; G=0 C535 LDA 35H ;A ←RAM[35H] A+35H+C → A04 MEMORY E40F100H data← 55H ~~ ~ data0135H 350F102H 550F101H data 35H 0E551H data → A ➊~~ ~ ~C50E550H

28 FEB. 2005 Ver 1.04 (4) Absolute Addressing → !abs Absolute addressing sets corresponding memory data to Data, i.e. second byte (Operand I) of comm and becomes lower level ad- dress and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example; 0735F0 ADC !0F035H ;A ←ROM[0F035H] The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135 H regardless of G-flag. 983501 INC !0135H ;A ←ROM[135H] (5) Indexed Addressing X Indexed Direct Page (No Offset) → {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1 D4 LDA {X} ;ACC ←RAM[X] X Indexed Direct Page, Auto Increment→ {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H DB LDA {X}+ X Indexed Direct Page (8 Bit Offset) → dp+X This address value is the second byte (Operand) of command plus the data of X-register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H 070F100H ~~ ~ data0F035H F00F102H 350F101H A+data+C → A address: 0F035 980F100H ~~ ~ data135H 010F102H 350F101H data+1 → data address: 0135 data 115H 0E550H data → A ~~ ~ data DB 35H data → A ~~ ~ 36H → X

FEB. 2005 Ver 1.04 29 C645 LDA 45H+X Y Indexed Direct Page (8 Bit Offset) → dp+Y This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y Indexed Absolute → !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory.This addressing mode can specify memory in whole ar- ea. Example; Y=55H D500FA LDA !0FA00H+Y (6) Indirect Addressing Direct Page Indirect → [dp] Assigns data address to use for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example; G=0 3F35 JMP [35H] X Indexed Indirect → [dp+X] Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10 H

1625 ADC [25H+X]

Y Indexed Indirect → [dp]+Y Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Y- register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10 H data 3AH 0E551H data → A➋ ~~ ~ ~C60E550H 45H+0F5H=13AH D50F100H data → A ~~ ~ data0FA55H 0FA00H+55H=0FA55H FA0F102H 000F101H 0A35H jump to ~~ ~ 0FA00H E336H 0E30AH NEXT ~~ ~ address 0E30AH 0535H 0E005H~~ ~ 0FA00H E036H 0E005H data ~~ ~ ➌ A + data + C → A 25 + X(10) = 35H

30 FEB. 2005 Ver 1.04

1725 ADC [25H]+Y

Absolute Indirect → [!abs] The program jumps to address sp ecified by 16-bit absolute ad- dress. JMP Example; G=0 1F25E0 JMP [!0E025H] 0525H 0E005H + Y(10) ~~ ~ 0FA00H E026H 0E015H data ~~ ~ = 0E015H A + data + C → A 250E025H jump to ~~ ~ 0FA00H E70E026H 0E725H NEXT ~~ ~ ~1F PROGRAM MEMORY address 0E30AH

FEB. 2005 Ver 1.04 31 9. I/O PORTS The GMS81C7208/16 has six ports (R0, R2, R3, R4, R5 and R6), and LCD segment port SEG0~SEG11 and SEG16~SEG20 and LCD common port COM0~COM3, which are multiplexed with SEG24~SEG26. These ports pins may be multiplex ed with an alternate function for the peripheral features on the device. In general, in a initial re- set state, R0,R2,R3 ports are used as a general purpose input port and R4, R5 and R6 ports are used as LCD segment drive output port.

9.1 Port Data Registers

The Port Data Registers in I/O buffer in each six ports (R0,R2,R3,R4,R5,R6) are repres ented as a Type D flip-flop, which will clock in a value from the internal bus in response to a "write to data register" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read data register" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to "read data register" sig- nal from the CPU. Some instructions that read a port activating the "read register" signal, and others activating the "read pin" sig- nal Port Direction Registers All pins have data direction registers which can define these ports as output or input. A "1" in the port direction register configure the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd num- bered bits as input ports, write “55 H” to address 0C8H (R0 port direction register) during initial setting as shown in Figure 9-1. Figure 9-1 Example of Port I/O Assignment All the port direction registers in the MCU have 0 written to them by reset function. On the other hand, its initial status is input. Pull-up Control Registers The R0, R2 and R3 ports have internal pull-up resistors. Figure 9-2 shows a functional diagram of a typical pull-up port. It is connected or disconnec ted by pull-up control register (PURn). The value of that resistor is typically 160kΩ. When a port is used as input, input logic is firmly either low or high, therefore external pull-dow n or pull-up resisters are re- quired practically. The GMS81C7208/16 has internal pull-up, it can be logic high by pull-up that can be able to configure either connect or disconnect individually by pull-up control registers R0PU, R2PU and R3PU. When ports are configured as inputs and pull-up resistor is select- ed by software, they are pulled to high. Figure 9-2 Pull-up Port Structure Open Drain Port Registers The R0, R2 and R3 ports have open drain port resistors R0CR~R3CR. Figure 9-3 shows a open drain port configuration by control reg- ister. It is selected as either push-pull port or open-drain port by R0CR, R1CR, R2CR and R3CR. Figure 9-3 Open Drain Port Structure I : INPUT PORT WRITE “55H” TO PORT R0 DIRECTION REGISTER 0 1 0 1 0 1 0 1 I O I O I O I O R0 DATA R0 DIRECTION R1 DATA R1 DIRECTION 0C0H 0C1H 0C8H 0C9H 76543210 BIT 76543210 PORT O : OUTPUT PORT ~~ ~~ PULL-UP RESISTOR PORT PIN 1: Connect 0: Disconnect Pull-up control bit VDD GND VDD Typ. 160kΩ PORT PIN 1: Open drain 0: Push-pull Open drain port selection bit GND

32 FEB. 2005 Ver 1.04

9.2 I/O Ports Configuration

R0 and R0DD Register: R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can i ndependently used as an input or an output through the R0DD register (address 0C8 H). Each port also can be set individually as pull-up port through the R0PU (address 0D0 H), and as open drain register through the R0CR (address 0D4H). In addition, port R0 is multiplexed with various special features. The control register thro ugh the PMR (address 0D9 H) and the SIOM (address 0FEH) control the selection of alternate function. After reset, this value is “0”, port may be used as normal I/O port. To use alternate function such as external interrupt, event counter input, serial interface data input, serial interface data output or se- rial interface clock, write “1” in the corresponding bit of PMR (address 0D9 H) and SIOM (address 0FEH). Regardless of the direction register R0DD, the control registers of PMR and SIOM are selected to use as alternate functions, port pin can be used as a corresponding alternate features. R2 and R2DD Register: R2 is an 3-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an output through the R2DD register (address 0CA H). Each port also can be set individually as pull-up port through the R2PU (address 0D2 H), and as open drain register through the R2CR (address 0D6H). Port Pin Alternate Function R00 R01 R02 R03 R04 R05 R06 R07 INT0 (External interrupt 0) INT1 (External interrupt 1) INT2 (External interrupt 2) EC0 (Event counter input 0) EC2 (Event counter input 2) SCK (Serial clock) SO (Serial data output) SI (Serial data input) R0 Data Register ADDRESS: 0C0H RESET VALUE: 00H R07 R06 R05 R04 R03 R02 R01 R00 Port Direction R0 Direction Register R0DD ADDRESS: 0C8H RESET VALUE: 00H 0: Input 1: Output Input / Output data Port Pull-up R0 Pull-up Register R0PU ADDRESS: 0D0H RESET VALUE: 00H 0: Pull-up Resistor Off 1: Pull-up Resistor On Port Open drain R0 Open Drain Control Register R0CR ADDRESS: 0D4H RESET VALUE: 00H 0: Push Pull 1: Open Drain Port Mode Register PMR ADDRESS: 0D9H RESET VALUE: 00H 0: R00 1: INT0 0: R01 1: INT1 0: R02 1: INT2 0: R03 1: EC0 0: R04 1: EC2 0: R30 1: BUZ 12345-- Edge Detection Register IEDS ADDRESS: 0D8H RESET VALUE: 00H 012345-- INT0INT1INT2 External Interrupt Edge Select 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling)

FEB. 2005 Ver 1.04 33 In addition, port R2 is multiplexed with analog input port. R3 and R3DD Register: R3 is an 1-bit CMOS bidirectional I/O port (address 0C3H). Each I/O pin can independently used as an input or an output through the R3DD register (address 0CB H). Each port also can be set individually as pull-up port through the R3PU (address 0D3 H), and as open drain register through the R3CR (address 0D7H). In addition, port R3 is multiplexed with various special features. Port Pin Alternate Function R21 R22 R23 AN1 (Analog Input 1) AN2 (Analog Input 2) AN3 (Analog Input 3) R2 Data Register ADDRESS: 0C2H RESET VALUE: 00H R23 R22 R21 Port Direction R2 Direction Register R2DD ADDRESS: 0CAH RESET VALUE: 00H 0: Input 1: Output Input / Output Data Port Pull-up R2 Pull-up Register R2PU ADDRESS: 0D2H RESET VALUE: 00H 0: Pull-up Resistor Off 1: Pull-up Resistor On Port Open Drain R2 Open Drain Control Register R2CR ADDRESS: 0D6H RESET VALUE: 00H 0: Push Pull 1: Open Drain - - - - - - - - - - - - - - - - - - - - Port Pin Alternate Function R30 BUZ (Buzzer driving output) R3 Data Register ADDRESS: 0C3H RESET VALUE: 00H Port Direction R3 Direction Register R3DD ADDRESS: 0CBH RESET VALUE: 00H 0: Input 1: Output Input / Output data Port Pull-up R3 Pull-up Register R3PU ADDRESS: 0D3H RESET VALUE: 00H 0: Pull-up Resistor Off 1: Pull-up Resistor On Port Open Drain R3 Open Drain Control Register R3CR ADDRESS: 0D7H RESET VALUE: 00H 0: Push Pull 1: Open drain - R30- - - - - - - - - - - - - - - - - - - - - - - - - - -

34 FEB. 2005 Ver 1.04 R4 and R4DD Register: R4 is an 8-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently used as an input or an output through the R4DD register (address 0CCH). After Reset, R4 port is used as LCD segment output SEG0~SEG7. To use general I/O ports user should be written ap- propriate value into the LPMR (0F3H). R5 and R5DD Register: R5 is an 4-bit CMOS bidirectional I/O port (address 0C5H). Each I/O pin can independently used as an input or an output through the R4DD register (address 0CDH). After Reset, R5 port is used as LCD segment output SEG8~SEG11. To use general I/ O ports user should be written appropriate value into the LPMR (0F3H). Port Selection Register PMR ADDRESS: 0D9H RESET VALUE: 00H 0: R00 1: INT0 0: R01 1: INT1 0: R02 1: INT2 0: R03 1: EC0 0: R04 1: EC2 0: R30 1: BUZ 12345-- Watch Dog Timer Register WDTR ADDRESS: 0DFH RESET VALUE: --01_0010B WDCLRWDOMWDCK0WDCK1WDEN-- LCD Control Register LCR ADDRESS: 0F1H RESET VALUE: 00H LCK0LCK1DTY0DTY1BRCLCDENBTC SUBM ** Caution : The bit7(SUBM) of LCR register must be set to “1” by software because of reduction current consumption (reset value=”0”). LCD Pin Function Port Pin SEG0 (LCD Segment 0 Signal Output) SEG1 (LCD Segment 1 Signal Output) SEG2 (LCD Segment 2 Signal Output) SEG3 (LCD Segment 3 Signal Output) SEG4 (LCD Segment 4 Signal Output) SEG5 (LCD Segment 5 Signal Output) SEG6 (LCD Segment 6 Signal Output) SEG7 (LCD Segment 7 Signal Output) R40 R41 R42 R43 R44 R45 R46 R47 LCD Pin Function Port Pin SEG8 (LCD Segment 8 Signal Output) SEG9 (LCD Segment 9 Signal Output) SEG10 (LCD Segment 10 Signal Output) SEG11 (LCD Segment 11 Signal Output) R50 R51 R52 R53 R4 Data Register ADDRESS: 0C4H RESET VALUE: 00H R47 R46 R45 R44 R43 R42 R41 R40 Port Direction R4 Direction Register R4DD ADDRESS: 0CCH RESET VALUE: 00H 0: Input 1: Output Input / Output data

FEB. 2005 Ver 1.04 35 R6 and R6DD Register: R6 is an 5-bit CMOS bidirectional I/O port (address 0C6H). Each I/O pin can i ndependently used as an input or an output through the R6DD register (address 0CEH). After Reset, R6 port is used as LCD segment output SEG16~SEG20. To use general I/O ports user should be written appropriate value into the LPMR (0F3H). R5 Data Register ADDRESS: 0C5H RESET VALUE: 00H R53 R52 R51 R50 Port Direction R5 Direction Register R5DD ADDRESS: 0CDH RESET VALUE: 00H 0: Input 1: Output Input / Output Data -- -- -- -- LCD Pin Function Port Pin SEG16 (LCD Segment 16 Signal Output) SEG17 (LCD Segment 17 Signal Output) SEG18 (LCD Segment 18 Signal Output) SEG19 (LCD Segment 19 Signal Output) SEG20 (LCD Segment 20 Signal Output) R60 R61 R62 R63 R64 R6 Data Register ADDRESS: 0C6H RESET VALUE: 00H R64 R63 R62 R61 R60 Port Direction R6 Direction Register R6DD ADDRESS: 0CEH RESET VALUE: 00H 0: Input 1: Output Input / Output Data -- - -- -

36 FEB. 2005 Ver 1.04 10. CLOCK GENERATOR As shown in Figure 10-1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains an oscillators: a main-frequency clock oscillator. The system clock can also be obtained from the external oscillator. The clock generator produces th e system clocks forming clock pulse, which are supplied to the CPU and the peripheral hard- ware. The internal system clock can be selected by bit2, and bit3 of the system clock mode register(SCMR). The register is shown in Figure 10-2. To the peripheral block, the clock among the not-divided original clocks, divided by 2, 4,..., up to 1024 can be provided. Peripheral clock is enabled or disabled by STOP instruction. Figure 10-1 Block Diagram of Clock Generator CPU Clock Instruction Cycle Time X IN = 4MHz ÷ 2 0.5 us ÷ 8 2.0 us ÷ 16 4.0 us ÷ 64 16.0 us Internal system clock (CPU clock) PRESCALER 0XIN PIN Peripheral clock MUX ÷16 ÷64 Select clock SCS[1:0] OSC Stop SYCC<0> STOP Mode SLEEP Mode PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 CLOCK PULSE fEX(MHz) PS0 PS3 PS2 PS4PS1 PS10PS9PS5 PS6 PS7 Frequency period 4M 1M 500K 250K2M 125K 62.5K 250n 500n 1u 2u 4u 8u 16u 32u 64u 256u 128u 3.906K7.183K15.63K31.25K PS8 fEX GENERATOR 1Reserved

FEB. 2005 Ver 1.04 37 The system clock is decided by bit1 (SYCC1) of the system clock mode register(SCMR). On the initial reset, internal system clock is PS1 which is the fastest and other clock can be provided by bit2 and bit3 of SCMR. Figure 10-2 SCMR: System Clock Control Registers System (CPU) Clock Control 00: Main Clock On 01: Main Clock On 10: Reserved 11: Reserved System Clock Source Select 00: XIN÷2 01: XIN÷8 INITIAL VALUE: 00H ADDRESS: 0F5HSCMR 10: XIN÷16 11: XIN÷64 BTCL 76543210 -- SYCC1 SYCC0 R/W R/W R/W R/W SCS1 SCS0--

38 FEB. 2005 Ver 1.04 11. OPERATION MODE The system clock controller st arts or stops the main-frequency clock oscillator. The operating mode is generally divided into the main-clock mode, which is controlled by system clock mode reg- ister (SCMR). Figure 11-1shows the operating mode transition diagram. System clock control is performed by the system clock mode reg- ister, SCMR. During reset, this register is initialized to “0” so that the main-clock operating mode is selected. Main Clock Operating Mode This mode is fast-frequency operating mode. The CPU and the peripheral hardwares are operated on the high- frequency clock. At reset release, this mode is invoked. SLEEP Mode In this mode, the CPU clock stops while peripherals and the os- cillation source continue to operate normally. STOP Mode In this mode, the system opera tions are all stopped, holding the internal states valid immediately before the stop at the low power consumption level. Figure 11-1 Operating Mode Main-clock Mode STOP Mode RESET Operation Reset Reset Main: According to SCMRMain: Stopped Main: Oscillating SLEEP Mode Release Reset STOP Instruction Refer to note1 Instruction Refer to note2 Main - Oscillating NOTE1: RESET Watch Timer Int. Timer interrupt (EC0, EC2) External Int. NOTE2: RESET All Int. CPU stops, Peripherals are operate.CPU and Peripherals are stops, SIO Int. Watchdog Timer Int.

FEB. 2005 Ver 1.04 39

11.1 Operation Mode

In the main-clock operation mode, only the high-frequency clock oscillator is used. During reset, the system clock mode register is initialized at the main-clock mode. Shifting from the Normal Operation to the SLEEP Mode By setting bit 0 of SMR, the CPU clock stops and the SLEEP mode is invoked. The CPU stops while other peripherals are op- erate normally. The way of release from this mode is RESET and all available in- terrupts. For more detail, See "20.1 SLEEP Mode" on page 76 Shifting from the Normal Operation to the STOP Mode By executing STOP instruction, the main-frequency clock oscil- lation stops and the STOP mode is invoked. After the STOP op- eration is released by reset, the operation mode is to main-clock mode. The methods of release are RESET, watch timer interrupt, Timer/ Event Counter1 (EC0, EC2 pin), and external interrupt. For more details, see "20.2 STOP Mode" on page 77. Note: In the STOP, the power consumed by the oscillator and the internal hardware is reduced. However, the power for the pin interface (depending on external circuitry and program) is not directly associated with the low-power con- sumption operation. This must be considered in system de- sign as well as interface circuit design.

40 FEB. 2005 Ver 1.04 12. BASIC INTERVAL TIMER The GMS81C7208/16 has one 8-bit basic interval timer that is free-run and can not stop. Block diagram is shown in Figure 12-1. In addition, the basic tnterval timer generates the time base for watchdog timer counting. It also provides a Basic interval timer interrupt (BITIF). As the count overflow from FF H to 00 H, this overflow causes the interrupt to be generated. The basic interval timer is controlled by the cloc k control register (CKCTLR) shown in Figure 12-2. Source clock can be selected by lower 3 bits of CKCTLR. The registers BITR and CKCTLR are located at same address, and address 0F9H is read as a BITR, and written to CKCTLR. Figure 12-1 Block Diagram of Basic Interval Timer Table 12-1 Basic Interval Timer Interrupt Time MUX Basic Interval Timer Interrupt Select Input clock 3 Basic Interval Timer source clock 8-bit up-counter BTS[2:0] BTCL ÷1024 ÷512 ÷256 ÷128 ÷64 ÷32 ÷16 To Watchdog timer (WDTCK) CKCTLR clear overflow Internal bus line clock control register [0F4H] [0F9H] BITIF Read Prescaler BITR fXIN reserved SCMR[1:0] BTS[2:0] CPU Source Clock Interrupt (overflow) Period (ms) @ fXIN = 4MHz 000 001 010 011 100 101 110 111 ÷ 8 ÷16 ÷32 ÷64 ÷128 ÷256 ÷512 ÷1024 0.512 1.024 2.048 4.096 8.192 16.384 32.768 65.536

FEB. 2005 Ver 1.04 41 Figure 12-2 BITR: Basic Interval Timer Mode Register Example 1: Interrupt request flag is generated every 8.192ms at 4MHz. LDM CKCTLR,#0CH SET1 BITE EI BTCL 76543210 -- BTS1 Basic Interval Timer source clock select 000: fXIN ÷ 8 001: fXIN ÷ 16 010: fXIN ÷ 32 011: fXIN ÷ 64 100: fXIN ÷ 128 101: fXIN ÷ 256 110: fXIN ÷ 512 111: fXIN ÷ 1024 Clear bit 0: Normal operation, free-run 1: Clear 8-bit counter (BITR) to “0” and count up again. INITIAL VALUE: ---0 0111B ADDRESS: 0F4H CKCTLR INITIAL VALUE: Undefined ADDRESS: 0F4HBITR Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR. Caution: 8-BIT FREE-RUN BINARY COUNTER BTS0BTS2BTCL BTCL 76543210 R WW WW W RR R RR R R BCK- This bit becomes to “0” automatically after one machine cycle. For the test purpose. This bit must be cleared to “0” for normal operation, otherwise BIT clock source is form sub-clock.

42 FEB. 2005 Ver 1.04 13. TIMER/EVENT COUNTER The GMS81C7208/16 has four Ti mer/Event Counters. Each module can generate an interrupt to indicate that an event has oc- curred (i.e. timer match). Timer 0 and timer 1 are can be used either two 8-bit Timer/ Counter or one 16-bit Timer/Co unter with combine them. Also timer 2 and timer 3 can be joined as a 16-bit Timer/Counter. In the “timer” function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. The count rate is 1/2 to 1/2048 of the oscillator frequency. In the “counter” function, the register is incremented in response to a 0-to-1 (rising edge) transition at its corresponding external input pin, EC0 or EC2 pin. In addition the “capture” function, the register is incremented in response external or internal clock sources same with timer or counter function. When external clock edge input, the count reg- ister is captured into capture data register correspondingly. It has five operating modes: “8-bit Timer/Counter”, “16-bit Tim- er/Counter”, “8-bit capture”, “16-bit capture” which are selected by bit in timer mode register TMn. In operation of timer 2, timer 3, their operations are same with timer 0, timer 1, respectively. When programming the software, you may refer to following ex- ample. Example 1: Timer 0 = 8-bit timer mode, 8ms interval at 4MHz Timer 1 = 8-bit timer mode, 4ms interval at 4MHz Timer 2 = 16-bit event counter mode LDM SCMR,#0 ;Main clock mode LDM TDR0,#249 LDM TM0,#0001_0011B LDM TDR1,#124 LDM TM1,#0000_1111B LDM TDR2,#1FH LDM TDR3,#4CH LDM TM2,#0001_1111B LDM TM3,#0100_1100B SET1 T0E SET1 T2E EI Example 2: Timer0 = 16-bit timer mode, 0.5s at 4MHz Timer2 = 2ms 8-bit timer mode at 4MHz Timer3 = 250us 8-bit timer mode at 4MHz LDM SCMR,#0 ;Main clock mode LDM TDR0,#23H LDM TDR1,#0F4H LDM TM0,#0FH ;FXIN/32, 8us LDM TM1,#4CH LDM TDR2,#249 LDM TDR3,#124 LDM TM2,#0FH ;FXUN/32, 8us LDM TM3,#0DH ;FXIN/8, 2us SET1 T0E SET1 T2E SET1 T3E EI Example 3: Timer0 = 8-bit timer mode, 2ms interval at 4MHz Timer1 = 8-bit capture mode, 2us sampling count. LDM TDR0,#249 ;250x8=2000us LDM TM0,#0FH ;FXIN/32, 8us LDM IEDS,#XXXX_01XXB ;FALLING LDM PMR,#XXXX_XX1XB ;AS INT1 LDM TDR1,#0FFH LDM TM1,#0001_1011B ;2us SET1 T0E ;ENABLE TIMER 0 SET1 T1E ;ENABLE TIMER 1 SET1 INT1E ;ENABLE EXT. INT1 EI X: don’t care. Example 4: Timer0 = 8-bit timer mode, 2ms interval at 4MHz Timer2 = 16-bit capture mode, 8us sampling count. LDM TDR0,#249 LDM TM0,#0FH LDM IEDS,#XX11_XXXXB LDM PMR4,#XXXX_X1XXB LDM TDR2,#0FFH ;MAX LDM TDR3,#0FFH ;MAX LDM TM2,#XX10_1111B ;/32 LDM TM3,#X10X_11XXB SET1 T0E ;ENABLE TIMER 0 SET1 T2E ;ENABLE TIMER 2 SET1 INT2E ;ENABLE EXT. INT2 EI X: don’t care.

FEB. 2005 Ver 1.04 43 Figure 13-1 TM0, TM1, TDRn Registers BTCL 76543210 CAP0 T0CK1 INITIAL VALUE: 00H ADDRESS: 0E0HTM0 T0CK0 T0CN T0ST 76543210 INITIAL VALUE: 0FFH ADDRESS: 0E1H, 0E3H, 0E7H, 0E9H TDR0~TDR3 Compare data registers WWWWWWWW R/W R/W R/W R/W R/W R/W T0CK2 Timer 0 Mode Register Basic Interval Timer Source Clock Selection 000: fXIN ÷ 2 001: fXIN ÷ 4 010: fXIN ÷ 8 011: fXIN ÷ 32 100: fXIN ÷ 128 101: fXIN ÷ 512 110: fXIN ÷ 2048 111: EC0 (External Event Input 0) 0: Disable Count 1: Enable Count 0: Stop Count 1: Clearing the T0 Counter and Start Again Timer/Counter 0 Enable Flag Timer/Counter 0 Start/Stop Control Flag 0: Timer Mode 1: Capture Mode Capture Mode Enable BTCL 76543210 T1CK1 INITIAL VALUE: 00H ADDRESS: 0E2H TM1 T1CK0 T1CN T1ST R/W R/W R/W R/W R/W R/W CAP1 Timer 1 Mode Register Timer/Counter 1 Source Clock Selection 00: fXIN 01: fXIN ÷ 2 10: fXIN ÷ 8 11: Timer 0 Clock 0: Disable Count 1: Enable Count 0: Stop Count 1: Clearing the T1 Counter and Start Again Timer/Counter 1 Enable Flag Timer/Counter 1 Start/Stop Control Flag 0: Timer Mode 1: Capture Mode Capture Mode Enable - 16BIT0 R/W R/W 0: 8-bit Mode 1: 16-bit Mode Mode Selection

44 FEB. 2005 Ver 1.04 Figure 13-2 TM2, TM3 Registers BTCL 76543210 CAP2 T2CK1 INITIAL VALUE: 00H ADDRESS: 0E6HTM2 T2CK0 T2CN T2ST R/W R/W R/W R/W R/W R/W T2CK2 Timer 2 Mode Register Timer/Counter 2 Source Clock Select 000: fXIN ÷ 2 001: fXIN ÷ 4 010: fXIN ÷ 8 011: fXIN ÷ 32 100: fXIN ÷ 128 101: fXIN ÷ 512 110: fXIN ÷ 2048 111: EC2 (External Event Input 2) 0: Disable Count 1: Enable Count 0: Stop Count 1: Clearing the T0 Counter and Start again Timer/Counter 2 Enable Flag Timer/Counter 2 Start/Stop Control Flag 0: Timer Mode 1: Capture Mode Capture Mode Enable BTCL 76543210 T3CK1 INITIAL VALUE: 00H ADDRESS: 0E8HTM3 T3CK0 T3CN T3ST R/W R/W R/W R/W R/W R/W CAP3 Timer 3 Mode Register Timer/Counter 3 Source Clock Selection 0: Disable Count 1: Enable Count 0: Stop Count 1: Clearing the T3 Counter and Start Again Timer/Counter 3 Enable Flag Timer/Counter 3 Start/Stop Control Flag 0: Timer Mode 1: Capture Mode Capture Mode Enable R/W R/W 0: 8-bit Mode 1: 16-bit Mode Mode Selection 00: fXIN 01: fXIN ÷ 2 10: fXIN ÷ 8 11: Timer 2 Clock 76543210 INITIAL VALUE: 00H ADDRESS: 0E1H, 0E4H, 0E7H, 0EAH T0~T3 Count registers RRRRRRRR CDR0~CDR3 - 16BIT1 -

FEB. 2005 Ver 1.04 45 13.1 8-bit Timer / Counter Mode The GMS81C7208/16 has four 8- bit Timer/Counters, timer 0, timer 1, timer 2, timer 3 which are shown in Figure 13-3, Figure 13-4. The “timer” or “counter” function is selected by control registers TMn. To use as an 8-bit Timer/Counter mode, CAP0, CAP1 and 16BIT0 bits should be cleared to “0”. These timers have each 8- bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 2~2048 selected by control bits of register TMn (n=0,1,2,3). Figure 13-3 8-bit Timer/Counter 0, 1 EC0 PIN ÷ 2 ÷ 4 ÷ 8 MUX Prescaler T0IF clear 0: Stop 1: Clear and start 000 001 010 TIMER 0 INTERRUPT MUX T1IF clear 0: Stop 1: Clear and start TIMER 1 INTERRUPT ÷ 8 ÷ 2 ÷ 1 TDR0 (8-bit) T1 (8-bit) TDR1 (8-bit) T0 (8-bit) Comparator Comparator TIMER 0 TIMER 1 BTCL 76543210 - CAP0 T0CK1 INITIAL VALUE: 00H ADDRESS: 0E0HTM0 T0CK0 T0CN T0ST-T 0 C K 2 XX X means don’t care ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110 111 BTCL- - T1CK1 INITIAL VALUE: 00H ADDRESS: 0E2HTM1 T1CK0 T1CN T1ST16BIT0 CAP1 X0 00 Edge Detector fXIN reserved SCMR[1:0] XX X X XX X X X T0CN T0CK[2:0] T0ST T1ST T1CN T1CK[1:0] [0E1H] [0E1H] [0E4H] [0E3H]

46 FEB. 2005 Ver 1.04 Note: The contents of timer data register TDRx should be initialized with 1 H~FFH, not to 0 H, because it is not to de- fined before reset. In the timer 0, timer register T0 increments from 00 H until it matches with TDR0 and then reset to 00 H. The match output of timer 0 generates timer 0 interrupt (latched in T0IF bit) As TDRx and Tx register are in same address, when reading it as a Tx, written to TDRx. In counter function, the counter is increased every 0-to-1 (rising edge) transition of EC0 or EC2 pin. In order to use counter func- tion, the bit 3 and bit 4 of the Port mode register PMR are set to “1” by software. The Timer 0 can be used as a counter by pin EC0 input. Similarly, Timer 2 can be used by pin EC2 input. Figure 13-4 8-bit Timer/Counter 2, 3 EC2 PIN ÷ 2 ÷ 4 ÷ 8 MUX Prescaler T2IF clear 0: Stop 1: Clear and start 000 001 010 TIMER 2 INTERRUPT MUX T3IF clear 0: Stop 1: Clear and start TIMER 3 INTERRUPT ÷ 8 ÷ 2 ÷ 1 TDR2 (8-bit) T3 (8-bit) TDR3 (8-bit) T2 (8-bit) Comparator Comparator TIMER 2 TIMER 3 BTCL 76543210 - CAP2 T2CK1 INITIAL VALUE: 00H ADDRESS: 0E6HTM2 T2CK0 T2CN T2ST-T 2 C K 2 XX X means don’t care ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110 111 BTCL- - T3CK1 INITIAL VALUE: 00H ADDRESS: 0E8HTM3 T3CK0 T3CN T3ST16BIT1 CAP3 X0 00 Edge Detector fXIN reserved SCMR[1:0] XX X X XX X X X T2CN T2CK[2:0] T2ST T3ST T3CN T3CK[1:0] [0E7H] [0E7H] [0EAH] [0E9H]

FEB. 2005 Ver 1.04 49 13.2 16-bit Timer / Counter Mode The Timer register is being run with all 16 bits. A 16-bit Timer/ Counter register T0, T1 are incremented from 0000 H until it matches TDR0, TDR1 and then resets to 0000H. The match out- put generates Timer 0 interrupt. The clock source of the Timer 0 is selected either internal or ex- ternal clock by bit T0SL1, T0SL0. Even if the Timer 0 (including th e Timer 1) is used as a 16-bit timer, the Timer 2 and Timer 3 can still be used as either two 8- bit timer or one 16-bit timer by setting the TM2. Reversely, even if the Timer 2 (including the Time r 3) is used as a 16-bit timer, the Timer 0 and Timer 1 can still be used as 8-bit timer indepen- dently. Figure 13-9 16-bit Timer/Counter T0IF clear 0: Stop 1: Clear and start T0ST T0CK[2:0] TIMER 0 INTERRUPTT0CN Comparator TIMER 0 + TIMER 1 → TIMER 0 (16-bit) Higher byte Lower byte COMPARE DATA (16-bit) (Not Timer 1 interrupt) 76543210 INITIAL VALUE: 00H ADDRESS: 0E0HTM0 XX X X XX0X X means don’t care ÷ 2 ÷ 4 ÷ 8 MUX Prescaler 000 001 010 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110 111 Edge Detector EC0 PIN TM1 BTCL X10011XX - - T1CK1 INITIAL VALUE: 00H ADDRESS: 0E2HT1CK0 T1CN T1ST16BIT0 CAP1 BTCL- CAP0 T0CK1T0CK0 T0CN T0ST-T 0 C K 2 76543210 INITIAL VALUE: 00H ADDRESS: 0E6H TM2 XX X X XX0X TM3 BTCL X10011XX - - T3CK1 INITIAL VALUE: 00H ADDRESS: 0E8HT3CK0 T3CN T3ST16BIT1 CAP3 BTCL- CAP2 T2CK1T2CK0 T2CN T2ST-T 2 C K 2 TDR0TDR1 fXIN reserved SCMR[1:0] T2IF clear 0: Stop 1: Clear and start T2ST T2CK[2:0] TIMER 2 INTERRUPTT2CN Comparator TIMER 0 + TIMER 1 → TIMER 0 (16-bit) Higher byte Lower byte COMPARE DATA (16-bit) (Not Timer 3 interrupt) ÷ 2 ÷ 4 ÷ 8 MUX Prescaler 000 001 010 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110 111 Edge Detector EC2 PIN TDR2TDR3 fXIN reserved SCMR[1:0] X means don’t care

50 FEB. 2005 Ver 1.04 13.3 8-bit Capture Mode The capture mode can be used to measure the pulse width be- tween two edges. The timer 0 capture mode is set by bit CAP0 of timer mode register TM0, and the timer 1 capture mode is set by CAP1 of timer mode register TM1 as shown in Figure 13-10. Timer 2 and timer 3 have same architecture with timer 0 and timer The Timer/Counter register is incremented in response internal or external input. This counting function is same with normal timer mode, and timer interrupt is generate when timer register T0 (T1, T2, T3) increase and match TDR0 (TDR1, TDR2, TDR3). Timer/Counter still does the above, but with the added feature that a edge transition at external input INTn pin causes the current Figure 13-10 8-bit Capture Mode (Timer0/Timer1 Case) ftimer fxin T0CK[2:0] ÷ 2 ÷ 4 ÷ 8 MUX 000 001 010 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110 111 Edge Detector EC0 PIN T0CN INT0IF 0: Stop 1: Clear and start INT0 INTERRUPT CDR0 (8-bit)T0 (8-bit) capture IEDS[1:0] CDR0 (8-bit)CDR0 T0IF TIMER 0 INTERRUPTComparator COMPARE DATA CDR0 (8-bit)TDR0 (8-bit) INT0 PIN T0ST clear clear T1CK[1:0] ÷ 1 ÷ 2 ÷ 8 MUX T1CN 0: Stop 1: Clear and start CDR0 (8-bit)T1 (8-bit) CDR0 (8-bit)CDR1 T1IF TIMER 1 INTERRUPTComparator COMPARE DATA CDR0 (8-bit)TDR1 (8-bit) T1ST clear INT1IF INT1 INTERRUPT capture IEDS[3:2] INT1 PIN clear 76543210 INITIAL VALUE: 00H ADDRESS: 0E0HTM0 XX X X XX1X TM1 BTCL X001XXXX - - T1CK1 INITIAL VALUE: 00H ADDRESS: 0E2HT1CK0 T1CN T1ST16BIT0 CAP1 BTCL- CAP0 T0CK1T0CK0 T0CN T0ST-T 0 C K 2 ÷ 1 Prescaler fXIN reserved SCMR[1:0] fEX

FEB. 2005 Ver 1.04 51 value in the timer counter register (T0,T1), to be captured and stored into registers CDR n (CDR0, CDR1), respectively. After capture, the Timer counter register is cleared and restarts by hard- ware. At this time, reading the address E1 H as a CDR0, not T0. T0, TDR0, CDR0 are located at same address. The other CDR1~CDR3 are same. Refer to timer registers of page 26. It has three transition modes: “falling edge”, “rising edge”, “both edge” which are selected by inte rrupt edge selection register IEDS. Refer to “17.4 External Interrupt” on page 63. In addition, the transition at INTn pin generate an interrupt. Note: The CDRn and Tn are in same address.In the cap- ture mode, reading operation is read as CDRn, not Tn be- cause addressing path is opened to the CDRn. Figure 13-11 16-bit Capture Mode 13.4 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the timer register is being run will 16 bits. Configuration is shown in Figure 13-11. T0CK[2:0] ÷ 2 ÷ 4 ÷ 8 MUX 000 001 010 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110 111 Edge Detector EC0 PIN T0CN INT0IF 0: Stop 1: Clear and start INT0 INTERRUPT capture IEDS[1:0] T0IF TIMER 0 INTERRUPTComparator COMPARE DATA INT0 PIN T0ST clear clear Prescaler fXIN reserved SCMR[1:0] CDR1 CDR0 TDR1 TDR0 T1 T0 BTCL 76543210 - CAP0 T0CK1 INITIAL VALUE: 00H ADDRESS: 0E0HTM0 T0CK0 T0CN T0ST-T 0 C K 2 XX X means don’t care BTCL- - T1CK1 INITIAL VALUE: 00H ADDRESS: 0E2HTM1 T1CK0 T1CN T1ST16BIT0 CAP1 X 10 1 11 X X XX X X X

16 BITSMSB LSB

FEB. 2005 Ver 1.04 53 (3) AD pin sharing with normal I/O port The analog input pins AN1 to AN3 also function as input/output port (PORT R21~R23) pins. When A/D conversion is performed with any of pins AN1 to AN3 selected, be sure not to execute a PORT input instruction while conve rsion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid ap- plying pulses to pins adjacent to the pin undergoing A/D conver- sion. (4) AV DD pin input impedance A series resistor stri ng of approximately 10k Ω is connected be- tween the AVDD pin and the AVSS pin. Therefore, if the output imped ance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AV DD pin and the AVSS pin, and there will be a large reference voltage error. Figure 14-3 A/D Converter Operation Flow Figure 14-4 A/D Converter Control Register ENABLE A/D CONVERTER A/D START ( ADST = 1 ) NOP ADSF = 1 A/D INPUT CHANNEL SELECT ANALOG REFERENCE SELECT READ ADR YES NO BTCL 76543210 ADEN- ADST A/D status bit Analog input channel select INITIAL VALUE: -0-0 0001B ADDRESS: 0ECHADCM ADSF A/D converter Enable bit 0: A/D converter module turn off and current is not flow. 1: Enable A/D converter R/W R/W R/W R/W R/W R 001: Channel 1 (AN1) 010: Channel 2 (AN2) 011: Channel 3 (AN3) 0: A/D conversion is in progress 1: A/D conversion is completed A/D start bit Setting this bit starts an A/D conversion. After one cycle, bit is cleared to “0” by hardware. ADS1 ADS0-A D S 2 INITIAL VALUE: Undefined ADDRESS: 0EDHADR A/D Conversion Data BTCL 76543210 RRRR RRR R 0: - 1: A/D start

54 FEB. 2005 Ver 1.04 15. SERIAL COMMUNICATION The serial interface is used to transmit/receive 8-bit data serially. Serial communication block consists of serial I/O data register, serial I/O mode register, clock selection circuit, octal counter and control circuit as illustrated in Figure 15-1.Pi n R07/SIN, R06/ SOUT and R05/SCLK pins are controlled by the serial mode reg- ister. The contents of the Serial I/O data register can be written into or read out by software. The serial communication is acti vated by the instruction “SET1 SIOST”. The octal counter is reset to “0” by this instruction, starts counting at the falling or rising edge (by POL selection) of the transmit clock (SCLK), and it increments at the every clock. A se- rial interrupt request flag is set when the eighth transmit clock signal is input (the serial interface is reset) or when serial commu- nication is discontinued (the octal counter is reset). The data in the serial data regi ster can be shifted synchronously with the transfer clock signal. Figure 15-1 SCI Control Register SCK1 SCK0 SCLK/R05 Port Clock Source Prescaler Divide Ratio 0 0 SCLK output Internal clock ÷ 4 0 1 SCLK output Internal clock ÷ 16 1 0 SCLK output Internal clock Use clock from Timer 0 overflow 1 1 SCLK input External clock - BTCL 76543210 MSBPOL SIOST Serial transmission status bit Serial transmission clock selection INITIAL VALUE: 0000_0001B ADDRESS: 0FEHSIOM SIOSF MSB first or LSB first 0: LSB First 1: MSB First R/W R/W R/W R/W R/W R 00: fXIN ÷ 4 01: fXIN ÷ 16 10: Timer 0 Overflow 11: External Clock 0: Serial transmission is in progress 1: Serial transmission is completed Serial transmission start bit Setting this bit starts an Serial transmission. After one cycle, bit is cleared to “0” by hardware. SCK1 SCK0SIO1 SIO0 R/W Serial transmission operation Mode 00: Normal Port(R05,R06,R07) 01: Sending Mode(SCLK,SOUT,R07) 10: Receiving Mode(SCLK,R06,SIN) 11: Sending & Receiving Mode(SCLK,SOUT,SIN) INITIAL VALUE: Undefined ADDRESS: 0FFHSIOR BTCL 76543210 R/W R/W R/W R/W R/W R/WR/W R/W Sending data during sending Mode Receiving data during receiving Mode Selection polarity 0: Data in on rising edge, data out on falling edge 1: Data in on falling edge, data out on rising edge R/W

FEB. 2005 Ver 1.04 55 Serial I/O mode register(SIOM) controls serial I/O function. The POL bit control which edge. According to SCK1 and SCK0, th e internal clock or external clock can be selected. Serial I/O data register(SIOR) is an 8-bit shift register. Figure 15-2 Block Diagram of SCI

15.1 Transmission/Receiving Timing

The serial transmission is started by setting SIOST(bit1 of SIOM) to “1”. After one cycl e of SCK, SIOST is cleared automatically to “0”. The serial output data from 8-bit shift register is output at falling edge of SCLK. And input data is latched at rising edge of SCLK pin. When transmission clock is counted 8 times, serial I/O counter is cleared as ‘0”. Transmission clock is halted in “H” state and serial I/ O interrupt(SIOIF) occurred. Figure 15-3 SPI Timing Diagram at POL=0 R05/SCLK PIN CONTROL CIRCUIT R06/SOUT PINSerial IO Data Octal Counter Serial communication Interrupt SIOIF R07/SIN PIN SCK, SIO overflow SCK[1:0] MUX ÷ 16 ÷ 4 Prescaler fXIN reserved SCMR[1:0] T0OV (Timer 0 overflow) POL SIOST start SIOSF complete clock clear SIO1 SIO0 [0FFH] Edge Detector SIO[1:0] shift clock SCLK OUT D1 D2 D3 D4 D6 D7D0 D5 D1 D2 D3 D4 D6 D7D0 D5 SIOST SCLK [R05] (POL=0) SOUT [R06] SIN [R07] SIOIF (Interrupt Req.) SIOSF

56 FEB. 2005 Ver 1.04

15.2 The Method of Serial I/O

Select transmission/receiving mode When external clock is used, th e frequency should be less than 1MHz and recommended duty is 50%. 2. In case of sending mode, write data to be send to SIOR. 3. Set SIOST to “1” to start serial transmission. If both transmission mode is se lected and transmission is per- formed simultaneously it would be made error. 4. The SIO interrupt is generate d at the completion of SIO and SIOSF is set to “1”. In SIO interrupt service routine, correct trans- mission should be tested. 5. In case of receiving mode, th e received data is acquired by reading the SIOR. Figure 15-4 SPI Timing Diagram at POL=1

15.3 The Method to Test Correct Transmission

Figure 15-5 Serial Method to Test Transmission D1 D2 D3 D4 D6 D7D0 D5 D1 D2 D3 D4 D6 D7D0 D5 SIOST SCLK [R05] (POL=1) SOUT [R06] SIN [R07] SCIIF SIOSF Serial I/O Interrupt Service Routine SE = 0 Write SIOM Normal Operation Overrun Error Abnormal SIOSF - SE : Interrupt Enable Register Low IENL(Bit3) - SR : Interrupt Request Flag Register Low IRQL(Bit3) SR

58 FEB. 2005 Ver 1.04 Note that BUR is a write-only register. The 6-bit counter is cleared and starts the counting by writing sig- nal at BUR register. It is incremental from 00H until it matches 6- bit BUR value. When main-frequency is 4MHz, buzzer frequency is shown as below table. The unit is kHz. BUR [5:0] BUCK[1:0] BUR [5:0] BUCK[1:0] 00 01 10 11 00 01 10 11 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.906 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488 Table 16-1 Buzzer Frequency at 4MHz

FEB. 2005 Ver 1.04 59 17. INTERRUPTS The GMS81C7208/16 interrupt circuits consist of interrupt en- able register (IENH, IENL), in terrupt request flags of IRQH, IRQL, priority circuit, and master enable flag (“I” flag of PSW). twelve interrupt sources are provided. The configuration of inter- rupt circuit is shown in Figure 17-2. The basic interval timer interrupt is generated by BITIF which is set by an overflow in the timer register. The watchdog timer interrupt is generated by WDTIF which set by a match in watchdog timer register. The external interrupts INT0 ~ INT2 each can be transition-acti- vated (1-to-0 or 0-to-1 transition) by selection IEDS. The flags that actually generate these interrupts are bit INT0IF, INT1IF and INT2IF in register IRQH and IRQL. When an exter- nal interrupt is generated, the fl ag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. The timer 0 ~ timer 3 interrupts are generated by T0IF~T3IF which are set by a match in their respective Timer/Counter regis- ter. The serial communication interrupts are generated by SIOIF which is set by 8-bit serial data transmitting or receiving through SCK, SIN, SOUT pin. The AD converter interrupt is generated by ADIF which is set by finishing the analog to digital conversion. The watch timer interrupt is ge nerated by WTIF which is set by an 14-bit binary counter overflow. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW on page 18), the interrupt enable register (IENH, IENL), and the interrupt request flags (in IRQH and IRQL) except power-on reset and software BRK interrupt. Below table shows the Interrupt priority. Vector addresses are shown in Figure 8-6 on page 20. Interrupt enable registers are shown in Fi gure 17-3. These registers are composed of interrupt enable flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. When enable flag is “0”, a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I- flag, which disables all interrupts at once. Figure 17-1 Interrupt Request Flag Reset/Interrupt Symbol Priority Hardware Reset Reserved Basic Interval Timer Watchdog Timer External Interrupt 0 External Interrupt 1 Timer/Counter 0 Timer/Counter 1 External Interrupt 2 Serial Communication ADC Interrupt Watch Timer Interrupt Timer/Counter 2 Timer/Counter 3 RESET BIT WDT INT0 INT1 Timer 0 Timer 1 INT2 SCI ADC WT Timer 2 Timer 3 WDTIF R/W Timer/Counter 3 INITIAL VALUE: -000 0000B ADDRESS: 0DDH IRQH - MSB LSB T0IF T1IFINT0IF INT1IFBITIF R/W R/W Timer/Counter 2 Timer/Counter 1 Interrupt Request Flag External Interrupt 1 Serial Communication INITIAL VALUE: 0--0 0000B ADDRESS: 0DCH IRQL MSB LSB Timer/Counter 0 R/W R/W-R / W R / W Basic Interval Timer Watchdog Timer A/D Converter External Interrupt 0 SIOIF INT2IF - T2IF T3IFADIF WTIF- R/W R/W R/W R/WR/W - R/W Watch Timer External Interrupt 2

FEB. 2005 Ver 1.04 61

17.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” by a reset or an instruction. Inter- rupt acceptance sequence requires 8 fXIN (2 µs at fMAIN=4.19MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execu- tion of an interrupt return instruction [RETI]. Interrupt Acceptance 1. The interrupt master enable flag (I-flag) is cleared to “0” to temporarily disable the acceptance of any follow- ing maskable interrupts. When a non-maskable inter- rupt is accepted, the ac ceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to “0”. 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at th e entry address of the inter- rupt service program is executed. Figure 17-4 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction A interrupt request is not accepted until the I-flag is set to “1” even if a requested interrupt has higher priority than that of the current interrupt being serviced. When nested interrupt service is required, the I-flag should be set to “1” by “EI” instruction in the interrupt service program. In this case, acceptable interrupt source s are selectively enabled by the individual interrupt enable flags. Saving/Restoring General Purpose Register During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These regis- ters are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save/restore the general-purpose registers. V.L. System clock Address Bus PC SP SP-1 SP-2 V.H. New PC V.L.Data Bus Not used PCH PCL PSW ADL OP codeADH Instruction Fetch Internal Read Internal Write Interrupt Processing Step Interrupt Service Task ADL and ADH are start addresses of interrupt service routine as vector contents. Watch Timer 012H 0E3H 0FFE4H 0FFE5H 0EH 2EH 0E312H 0E313H Entry Address Correspondence between vector table address for Watch Timer Interrupt and the entry address of the interrupt service program. Vector Table Address

62 FEB. 2005 Ver 1.04 Example: Register save using push and pop instructions General-purpose register save/restore using push and pop instruc- tions;

17.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK inter- rupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 17-5. Figure 17-5 Execution of BRK/TCALL0

17.3 Multi Interrupt

If two requests of different prior ity levels are received simulta- neously, the request of higher prio rity level is serviced. If re- quests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hard- ware which request is serviced. However, multiple processing through software for special fea- tures is possible. Generally when an interrupt is accepted, the I- flag is cleared to disable any further interrupt. But as user sets I- flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. Example: During Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. TIMER1: PUSH A PUSH X PUSH Y LDM IENH,#08H ;Enable INT0 only LDM IENL,#00H ;Disable other EI ;Enable Interrupt LDM IENH,#0FFH ;Enable all interrupts LDM IENL,#0FFH POP Y POP X POP A RETI Figure 17-6 Execution of Multi Interrupt INTxx: PUSH A PUSH X PUSH Y ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG. interrupt processing POP Y POP X POP A RETI ;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return B-FLAG BRK INTERRUPT ROUTINE RETI TCALL0 ROUTINE RET BRK or TCALL0 enable INT0 TIMER 1 service INT0 service Main Program service Occur TIMER1 interrupt Occur INT0 EI disable other enable INT0 enable other In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable “EI” in the TIMER1 routine.

FEB. 2005 Ver 1.04 63

17.4 External Interrupt

The external interrupt on INT0, INT1 and INT3 pins are edge triggered depending on the edge selection register IEDS (address 0D8H) as shown in Figure 17-7. The edge detection of external interrupt has three transition acti- vated mode: rising edge, falling edge, and both edge. Figure 17-7 External Interrupt Block Diagram INT0 ~ INT2 are multiplexed with general I/O ports (R00~R02). To use as an external interrupt pin, the bit of Port Mode Register PMR should be set to “1” correspondingly as shown in Figure 17- Example: To use as an INT0 and INT2 ;** Set port as an input port R00,R02 LDM R0DD,#1111_1010B ; Set port as an external interrupt port LDM PMR,#05H ;** Set Falling-edge Detection LDM IEDS,#0001_0001B Response Time The INT0 ~ INT2 edge are latched into INT1IF ~ INT2IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be ex- ecuted. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and th e beginning of execution of the first instruction of the service routine. Figure 17-8 shows interrupt response timings. Figure 17-8 Interrupt Response Timing Diagram INT0IFINT0 pin INT0 INTERRUPT INT1IFINT1 pin INT1 INTERRUPT INT2IFINT2 pin INT2 INTERRUPT IEDS [0D8H] Edge selection register 2 2 2 Interrupt goes active Interrupt latched Interrupt processing Interrupt routine 8 fXIN periodmax. 12 fXIN period

64 FEB. 2005 Ver 1.04 Figure 17-9 PMR and IEDS Registers BTCLBUZ--I N T 1 S 0: R00 1: INT0 INITIAL VALUE: 00H ADDRESS: 0D9HPMR EC2S INT0S INT2SEC0S 0: R01 1: INT1 0: R02 1: INT2 0: R03 1: EC0 0: R30 1: BUZ 0: R04 1: EC2 LSBMSB BTCL - - R/W R/W R/W R/W R/W R/W IED2H--I E D 0 H INITIAL VALUE: 00H ADDRESS: 0D8HIEDS IED2L IED0L IED1LIED1H LSBMSB Edge selection register 00: Reserved 01: Falling (1-to-0 Transition) 10: Rising (0-to-1 Transition) 11: Both (Rising & Falling) INT0 INT1INT2 R/W R/W R/W R/W R/W R/W R/W R/W

66 FEB. 2005 Ver 1.04

18.1 LCD Control Registers

The LCD driver is controlled by the LCD control register LCR which is shown in Figure 18-2. LCD block input the clock from the watch timer. When LCD is operate, the watch timer much be enabled by WTEN (bit 6 of address 0EFH). Figure 18-2 LCD Control Register 76543210 Selection Frame Frequency INITIAL VALUE: 00H ADDRESS: 0F1H LCR R/W R/W R/W Duty Control 00: 1/4 Duty 01: 1/3 Duty (SEG24 Active) Bias Resistor Control 0: External 1: Internal LCD Display Control 0: LCD Display All Segment 0 Data Output 1: LCD Display Enable R/W R/W R/W Bias Transistor Control 0: Off 1: On BTCSUBM LCDEN BRC LCK1 LCK0 R/W R/W 10: 1/2 Duty (SEG24, SEG25 Active) 11: Static (SEG24, SEG25, SEG26 Active) DTY0DTY1 76543210 R4 port Selection 00:SEG0~SEG7 01:SEG4~SEG7,R40~R43 10:SEG0~SEG3,R44~R47 11:R40~R47 INITIAL VALUE:0000 0000 ADDRESS: 0F2 H LPMR R/W R/W R/W R/W R5LPMR R4LPMR R5 port Selection 00:SEG8~SEG11 01:R50~R53 10:SEG8~SEG11 11:R50~R53 R6LPMR R6 port Selection 00:SEG16~SEG20 01:SEG20,R60~R63 10:SEG16~SEG19,R64 11:R60~R64 R/W R/W R/W R/W 76543210 INITIAL VALUE: 00H ADDRESS: 0F3H RPR R/W R/W - RPR1 RPR0----- -- ---- The RPR register is used for RAM page selection. RAM page Instruction PRP1 PRR0 Page 0 CLRG X X Page 0 SETG 0 0 Page 1 SETG 0 1 Reserved SETG 1 0 Reserved SETG 1 1 No internal bias registers in the Emulator, so user must select the “0”, External mode at least during use the Emulator. OTP and Mask MCU can use both. ** Caution : The bit7(SUBM) of LCR register must be set to “1” by software because of reduction current consumption (reset value=”0”). 00: fXIN÷27÷32, 1024Hz@4.19MHz 01: fXIN÷27÷64, 512Hz@4.19MHz 10: fXIN÷27÷128, 256Hz@4.19MHz 11: fXIN÷27÷256, 128Hz@4.19MHz

FEB. 2005 Ver 1.04 67

18.2 Duty and Bias Selection of LCD Driver

5 kinds of driving methods can be selected by DTY (bits 3 and 2 of LCD Control Register and connection of VCL pin externally. Figure 18-3 shows typical driving waveforms for LCD.). Figure 18-3 LCD Drive Waveform (Voltage COM-SEG Pins)

18.3 Selecting Frame Frequency

Frame frequency is set to the main frequency as shown in the fol- lowing Table 18-1. The LCK[1:0] of LCR determines the frequency of COM signal scanning of each segment output. The watch timer must be en- abled when the LCD display is turned on. RESET clears the LCD control register LCR values to logic zero. The LCD display can continue to operate even during the SLEEP and STOP modes. VCL2 VCL1 VCL0 GND -VCL0 -VCL1 -VCL2 1/fF Data “1” (a) 1/4 duty, 1/3 bias Data “0” VCL2 VCL1 VCL0 GND -VCL0 -VCL1 -VCL2 1/fF Data “1” (b) 1/3 duty, 1/3 bias Data “0” 1/fF Data “1” Data “0” (c) 1/2 duty,1/3 bias 1/fF Data “1” Data “0” VCL2 VCL1 VCL0 GND -VCL0 -VCL1 -VCL2 (e) Static Note: fF: LCD Frame Frequency 1/fF Data “1” Data “0” VCL2 GND -VCL0 = -VCL1 -VCL2 (d) 1/2 duty, 1/2 bias VCL1 = VCL0 VCL2 VCL1 VCL0 GND -VCL0 -VCL1 -VCL2 LCK[1:0] LCD clock Frame Frequency (Hz) (When fXIN = 4.19 MHz) fXIN÷27÷32 fXIN÷27÷64 fXIN÷27÷128 fXIN÷27÷256 1024 512 256 128 Table 18-1 Setting of LCD Frame Frequency

68 FEB. 2005 Ver 1.04 LCD Port Selection Segment pins are also used for normal I/O pins. The LCD port se- lection register LPMR is used to set Rn pin for ordinary digital in- put. Refer to LPMR register as shown in Figure 18-2. Bias Resistor To operate LCD, built-in Bias resistor dividing V DD to V SS section into several stages generates necessary voltage. The BTC (Bit 6 of LCR) switches Transistor supplying voltage to serially connected Bias resistor. If it is ‘1’, it turns on, and if it is ‘0’, it turns off. The LCD drive voltage (VCL2) is given by the dif- ference in potential (V DD-VCL2) between pins V DD and V CL2. Therefore, when the MCU operating voltage is 5V and LCD drive voltage are the same, the Bias pin is connected to the VCL2 pin as shown in (a) of Figure 18-5. Figure 18-4 Application Example of 5V LCD Panel When require supply 3V output to the LCD, the voltage of VCL2 becomes 3V as shown in Figure 18-5. Because V DD is down to 3V through internal 2R resistor. The LCD light only when the difference in potential between the segment and common output is ±VCL, and turn off at all other times. During reset, the power switch of the LCD driver is turned off automatically, shutting off the VCL voltage. one frame (at 1/4 duty, 1/3 bias) COM0 pin VCL1 VCL2 BIAS BTC VDD VSS (a) Internal, Static or 1/3 Bias BTC = “1” BRC = “1” Internal Bias resistors MCU Internal VCL0 BRC R R R BTC VDD VSS (b) Internal, Static or 1/2 Bias BTC = “1” BRC = “1” Two pins are connected each other Internal Bias resistors MCU Internal BRC R R R Typ. R=65kΩ VCL1 VCL2 BIAS VCL0 Short two pins each other externally VCL2=5V VCL1=3.33V VCL0=1.67V VCL2=5V VCL1=2.5V VCL0=2.5V

70 FEB. 2005 Ver 1.04

18.4 LCD Display Memory

Display data are stored to the display data area (address 100H-11AH) in the data memory. The display data stored to the display data area are read au- tomatically and sent to the LCD driver by the hardware. The LCD driver generates the segment signals and com- mon signals in accordance with the display data and drive method. Figure 18-7 LCD Display Memory Therefore, display patterns can be changed by only over- writing the contents of the display data area with a pro- gram. The table look up instruction is mainly used for this overwriting. Figure 18-7 shows the correspondence between the display data area and the SEG/COM pins. The LCD lights when the display data is “1” and turn off when “0”. The number of segment which can be driven differs de- pending on the LCD drive me thod, therefore, the number of display data area bits used to store the data also differs (Refer to Figure 18-2). Consequently, data memory not SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM0 COM1 COM2 COM3 SEG8 SEG9 SEG10 SEG11 SEG16 SEG17 SEG18 SEG19 SEG20 SEG24 SEG25 SEG26 0123 45 67Bit 100H 101H 102H 103H 104H 105H 106H 107H 108H 109H 10AH 10BH 10CH 10DH 10EH 10FH 110H 111H 112H 113H 114H 115H 116H 117H 118H 119H 11AH Note: The bit 4 to 7 of every byte are reserved. Any read or write is not effect. -- - - ---- -- - - ---- -- - - ---- -- - - ---- -- - - ---- -- - - ---- -- - - ---- Drive Methods Bit 3 Bit 2 Bit 1 Bit 0 1/4 Duty COM3 COM2 COM1 COM0 1/3 Duty - COM2 COM1 COM0 1/2 Duty - - COM1 COM0 Static --- COM0 Table 18-2 The Duty vs. COM Port Configuration

FEB. 2005 Ver 1.04 71 used to store display data and data memory for which the address are not connected to LCD can be used to store or- dinary user’s processing data. Blanking Blanking is applied by setting LCDEN (bit 7 of LCR) to “0” and turns off the LCD by outputting the non light operation level to the COM pin. When setting Frame frequency or changing operat- ing mode, LCD display should be off before operation, to prevent display flickering.

18.5 Control Method of LCD Driver

Flow chart of initial setting is shown in Figure 18-8. Example: When operating with 1/4 duty LCD using a frame frequency of 512Hz. Figure 18-8 Initial Setting of LCD Driver Figure 18-9 Example of Connection COM & SEG Display Data Setting Normally, display data are kept permanently in the pro- gram memory and then stored at the display data area by the table look-up instruction. This can be explained using numerical display with 1/4 du ty LCD as an example. The COM and SEG connections to the LCD and display data are the same as those shown is Figure 18-9. Programming LDM LCR,#0101_0001B;1/4duty, f F=512Hz (fSUB= 32.768kHz) SETG LDM RPR,#1;Select LCD Memory ;area (Page 1 = address 1XX LDX #0 C_LCD1: LDA #0 ;RAM Clear ;RAM(100H~11AH) STA {X}+ CMPX #01BH BNE C_LCD1 CLRG SET1 LCR.5;Enable LCD display Clear LCD Display Memory Select Frame Frequency Turn on LCD Setting of LCD drive method Initialize of display memory Enable display (Release of blanking) SEG0 SEG1 COM3 COM0 COM1 COM2 Example: display “2” 11 10 01 01 100H 101H 31 20bit 7 5 64 Note: * are don’t care.

72 FEB. 2005 Ver 1.04 example for displaying character is shown below. Note: When power on RESET, an oscillation start up time is required. Enable LCD display after an oscillation is stabi- lized, or LCD may occur flicker at power on time shortly. CLRG LDX#DISPRAM GOLCD: LDA{X} TAY LDA!FONT+Y ;LOAD FONT DATA LDMRPR,#1;Set RPR = 1 to access LCD SETG ;Set Page 1 LDX#0 STA{X}+;LOWER 4 BITS OF ACC. -> M(X) XCN STA{X};UPPER 4 BITS OF ACC. -> M(X+1) CLRG ;Set Page = 0 FONT DB 1101_0111B; “0” DB 0000_0110B; “1” DB 1110_0011B; “2” DB 1010_0111B; “3” DB 0011_0110B; “4” DB 1011_0101B; “5” DB 1111_0101B; “6” DB 0000_0111B; “7” DB 1111_0111B; “8” DB 0011_0111B; “9” Font data Write into the LCD Memory

FEB. 2005 Ver 1.04 73 19. WATCH / WATCHDOG TIMER

19.1 Watch Timer

The watch timer goes the clock continuously even during the power saving mode. When MCU is in the Stop or Sleep mode, MCU can wake up itself every 2Hz or 4Hz or 16Hz. The watch timer consis ts of input clock selector, 14-bit binary counter, interval selector and watch timer mode register WTMR (address 0EF H). The WTMR is 5-bit read/write register and shown in Figure 19-2. WTMR can select the clock input by 2 bits WTCK[1:0] and interval time sele ctor by 2 bits WTIN[1:0] and enable/disable bit. The WTEN bit is set to “1” timer start count- ing. Input clocks can be selected among three different source which are divided main clock (fXIN ÷128) or main clock. Recom- mend the oscillator 4.194304MHz as a main. Because above main frequency is equal to 128 times of 32.768kHz. Generally main clock (fXIN) at WTCK=10B is not be used, it is just for test purpose in factory. In the Stop Mode, the main clock is stopped. LDM IENL,#XXXX_X1XXB EI LDM WTMR,#0100_1000B Figure 19-1 Block Diagram of Watchdog Timer

19.2 Watchdog Timer

The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for de tecting malfunction can be se- lected either a reset CPU or a interrupt request as you want. When the watchdog timer is not being used for malfunction de- tection, it can be used as a timer to generate an interrupt at fixed intervals. Watchdog Timer Control Figure 19-2 shows the watchdog tim er control register WDTR (address 0DF H). The watchdog timer is automatically enabled initially and watchdog output to reset CPU but clock input source is disabled. To enable this function, you should write bit WTEN of WTMR (address 0EFH) set to “1”. The CPU malfunction is detected during setting of the detection time, selecting of output, and cl earing of the binary counter. Clearing the 2-bit binary counter by bit WDCLR of WDTR is re- peated within the detection time. If the malfunction occurs for any cause, the watchdog timer out- put will become active from the binary counters unless the binary counter is cleared. At this time, when WDOM=1, a reset is gen- erated, which drives the RESET pin to low to reset the internal hardware. When WDOM=0, a watchdog timer interrupt (WD- TIF) is generated instead of Reset function. This interrupt can be used general timer as user want. When main clock is selected as clock input source on the STOP mode, clock input is stopped so the watchdog timer temporarily stops counting. enable Watch Timer interruptWTIF 14-bit Binary Counter MUX reserved fXIN ÷128 fXIN(test) fW fXIN = 4.194304 MHz Interval Selector 2Hz 4Hz 16Hz 2Hz 4Hz 8Hz 16Hz 2-bit Binary Counter WDCK[1:0] WTIN[1:0] WTCK[1:0] clear 0: Stop 1: Clear and start WDCLR WDTIF to RESET CPU Watchdog Timer Interrupt overflow WDEN WDOM 00 01 10 11 000110 enable WTEN MUX When

74 FEB. 2005 Ver 1.04 Figure 19-2 WTMR, WDTR: Watch Timer and Watchdog Timer Data Register Example: Sets the Watchdog Timer Detection Time to 1 SEC at 4.19MHz Enable and Disable Watchdog Watchdog timer is enabled by setting WDEN (bit 4 in CKCTLR) to “1”. WDEN is initialized to “1” during reset and it should be clear to “0” disable. Example: Enables watchdog timer for Reset LDM WTMR,#0100_XXXXB; WTEN ← 1 LDM WDTR,#00X1_XX11B; WDEN ← 1 The watchdog timer is disabled by clearing either bit 4 (WDEN) of WDTR or bit 6 (WTEN) of WTMR. The watchdog timer is halted in STOP mode and restarts automatically after STOP mode is released. Clearing 2-Bit Binary Counter of the Watchdog Timer The watchdog timer count the cl ock source as 14-bit binary INITIAL VALUE: -0--_0000B ADDRESS: 0EFHWTMR - WTEN WTIN1 WTIN0 -R / W R/W R/W-R / W R / W -- WTCK1 WTCK0 Clock Source Selection 00: Reserved 01: Main Clock (fXIN ÷ 128) 10: Main Clock (test purpose in factory) 11: - Watch Timer Interrupt Interval Selection 00: 16Hz 01: 4Hz 10: 2Hz 11: - Watch Timer Count Enable 0: Disable 1: Enable INITIAL VALUE: --01_0010B ADDRESS: 0DFHWDTR - - WDCK1 WDCK0 R/WR/W R/W-- R / W - WDEN WDOM WDCLR Watchdog Timer Interrupt Interval Selection 00: 2 sec. 01: 1 sec. 10: 0.5 sec. 11: 0.25 sec. R/W R/W Clear Bit 0: Normal operation 1: Clear and starts counting When fXIN = 4.19MHz Output Mode 0: Interrupt Request 1: Reset CPUWatchdog Timer Count Enable 0: Disable 1: Enable When fXIN = 4.19MHz LDM WTMR,#0100_1000B; Select sub clock as an input source LDM WDTR,#0001_0111B SET1 WDCLR ; Clear counter SET1 WDCLR ; Clear counter SET1 WDCLR ; Clear counter Within 0.75 sec. Within 0.75 sec.

FEB. 2005 Ver 1.04 75 counter which is free run can not be cleared. The watchdog timer has 2-bit binary counter. It is incremented by 14-bit binary counter match as shown in Figure 19-1. Interrupt request flag or Reset signal are generated by overflow 2-bit binary counter. During normal operation in the software, 2-bit binary counter should be cleared by bit WDCLR of WDTR within watchdog timer overflow. The time of clearing must be within 3 times of 14-bit binary counter interval as shown in Figure 19-3. The worst case, watchdog time is just 3 times of 14-bit counter. Figure 19-3 Watchdog Timer Timing If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin low to reset the internal hardware. The main clock oscillator also turns on when a watchdog timer re- set is generated in sub clock mode. 14-bit binary 2-bit binary WDTIF interrupt Write WDCLR = 1 at this point Counter Clear n counter 0 1 1FFE ~~~ 1FFF counter 0 23 1FFE 1FFF 1FFE 1FFF ~~~ ~ 01 1FFE 1FFF 2 222 ~~~ Even if user set to 1 sec., When WDTR = 0011_0111B worst case 0.75 second

76 FEB. 2005 Ver 1.04 20. POWER DOWN OPERATION The GMS81C7208/16 has two power-down modes. In power- down mode, power consumption is reduced considerably that in Battery operation Battery life can be extended a lot. Sleep mode is entered by setting bit 0 of sleep mode regis- ter, and STOP mode is entered by STOP instruction.

20.1 SLEEP Mode

In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operate normally but CPU stops. Movement of all Peripherals is shown in Table 20-1. Sleep mode is entered by setting bit 0 of SMR (address 0DEH). It is released by RESET or interru pt. To be release by interrupt, interrupt should be enabled before Sleep mode. Figure 20-1 SLEEP Mode Register Figure 20-2 Sleep Mode Release Timing by External Interrupt Figure 20-3 SLEEP Mode Release Timing by RESET Pin Sleep Mode Register SMR ADDRESS : 0DEH 0: Release Sleep Mode 1: Enter Sleep Mode W Oscillator Normal Operation Stand-by Mode Normal Operation Interrupt Internal CPU Clock ReleaseSet bit 0 of SMR (XIN pin) ~~ ~ Oscillator (XIN pin) 0BIT Counter 1 FE FF 0 12 tST = 62.5ms RESET Internal CPU Clock Clear & Start Normal Operation Sleep Mode Normal Operation ReleaseSet bit 0 of SMR ~~~ at 4.19MHz by hardware tST = x 256 fMAIN ÷1024

FEB. 2005 Ver 1.04 77

20.2 STOP Mode

For applications where power consumption is a critical factor, device provides reduced power of STOP. Start the Stop Operation An instruction that STOP cause s to be the last instruction is executed before going into the STOP mode. In the Stop mode, the on-chip main-frequency oscillator is stopped. With the clock frozen, all functions are stopped, but the on- chip RAM and Control registers are held. The port pins output the values held by their respective port data register, the port direction registers. The status of peripherals during Stop mode is shown below. Note: Since the XIN pin is connected internally to GND to avoid current leakage due to the crystal oscillator in STOP mode, do not use STOP instruction when an external clock is used as the main system clock. In the Stop mode of operation, VDD can be reduced to minimize power consumption. Be careful, however, that V DD is not re- duced before the Stop mode is invoked, and that VDD is restored to its normal operating level before the Stop mode is terminated. The reset should not be activated before V DD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. And after STOP instruction, at least two or more NOP instruction should be written as shown in example below. Example) LDM CKCTLR,#0EBH;32.8ms ; LDM CKCTLR,#0FBH ;65.5ms STOP NOP NOP The interval timer register CKCTLR should be initialized (0F H or 0EH) by software in order that oscillation stabilization time should be longer than 20ms before STOP mode. Release the STOP Mode The exit from STOP mode is using hardware reset or external in- terrupt, watch timer, key scan or Timer/Counter. To release STOP mode, corresponding interrupt should be enabled before STOP mode. Specially as a clock source of Timer/Event Counter, EC0 or EC2 pin can release it by Timer/Event Counter interrupt request. Reset redefines all the control re gisters but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. Start-up is performed to acquire the time for stabilizing oscilla- tion. During the start-up, the internal operations are all stopped. Peripheral STOP Mode SLEEP Mode CPU All CPU operations are disabled All CPU operations are disabled RAM Retain Retain LCD Driver LCD driver operates contin uously LCD driver operates continuously Basic Interval Timer Halted BIT operates continuously Timer/Event Counter Halted (Only when the Event counter mode is enabled, Timer operates normally) Timer/Event Counter operates continuously Watch Timer Watch Timer operates contin uously Watch Timer operates continuously Main-oscillation Stop (X IN pin = “L”, XOUT pin = ”L”) Oscillation Sub-oscillation Oscillation Oscillation I/O Ports Retain Retain Control Registers Retain Retain Release Method RESET, SIO interrupt, Watch Timer inter- rupt, Timer interrupt (EC0,2), External inter- rupt RESET, All interrupts Table 20-1 Peripheral Operation During Power Down Mode

78 FEB. 2005 Ver 1.04 Figure 20-4 STOP Mode Release Timing by External Interrupt Figure 20-5 STOP Mode Release Timing by RESET Minimizing Current Consumption The stop mode is designed to reduce power consumption. To minimize current drawn during stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. Note: In the STOP operation, the power dissipation asso- ciated with the oscillator and the internal hardware is low- ered; however, the power diss ipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level DD/VSS); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a cur- rent begins to flow. Therefore, if cutting off the output tran- sistor at an I/O port puts the pin signal into the high- impedance state, a current flow across the ports input tran- sistor, requiring it to fix the level by pull-up or other means. Before executing Stop instruction, Basic Interval Timer must be set Oscillator (XIN pin) n 0BIT Counter n+1 n+2 n+3 Normal Operation Stop Operation Normal Operation

1 FE FF 0 12

~~ ~ tST > 20ms External Interrupt Internal Clock Clear STOP Instruction Executed ~~~ properly by software to get stabilization time which is longer than 20ms. by software Oscillator (XIN pin) n 0BIT Counter n+1 n+2 n+3 Normal Operation Stop Operation Normal Operation ~~ ~ tST > 62.5ms Internal Clock Clear STOP Instruction Executed ~~~ at 4.19MHz by hardware RESET n+2 tST = x 256 fMAIN ÷1024 ~~~

80 FEB. 2005 Ver 1.04 21. OSCILLATOR CIRCUIT The GMS81C7208/16 has two oscillation circuits internally. XIN and XOUT are input and output for main frequency and SXIN and SXOUT are input and output for s ub frequency, respectively, in- verting amplifier which can be configured for being used as an on-chip oscillator, as shown in Figure 21-1. To use RC oscillation instead of crystal, user should check mark on the “MASK OR- DER & VERIFICATION SHEET” of the appendix of this man- ual. However in the OTP devi ce, when the programming RC oscillation can be selected or not into the configuration bit. For more detail, refer to "24.1 OTP Programming" on page 84. Note: When using the sub clock oscillation, connect a re- sistor in series with R which is shown as below figure. In order to reduce the power consumption, the sub clock oscillator employs a low amplification factor circuit. Be- cause of this, the sub clock oscillator is more sensitive to noise than the main system clock oscillator. Figure 21-1 Oscillation Circuit Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic res- onator have their own characteristics, the user should consult the crystal manufacturer for appropri ate values of external compo- nents. Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic res- onator have their own characteristics, the user should consult the crystal manufacturer for appropri ate values of external compo- nents. In addition, see Figure 21-2 for the layout of the crystal. Note: Minimize the wiring length. Do not allow the wiring to intersect with other signal conductors. Do not allow the wir- ing to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of V SS. Do not ground it to any ground pattern where high cur- rent is present. Do not fetch signals from the oscillator. Figure 21-2 Recommend Layout of Oscillator PCB Circuit XOUT XIN VSS Recommend C1,C2 = 20pF XOUT XINExternal Clock Open XOUT XIN External Oscillator RC Oscillator (mask option) Crystal or ceramic oscillator 4.19MHz Crystal Oscillator Ceramic Resonator C1,C2 = 30pF Refer to AC Characteristics For selection R value, REXT XOUT XIN

FEB. 2005 Ver 1.04 81 22. RESET The GMS81C7208/16 has two types of reset generation proce- dures; one is an external reset input, the other is a watch-dog tim- er reset. Table 22-1 shows on- chip hardware initialization by reset action. Figure 22-1 Simple Power-On Reset Circuit.

22.1 External Reset Input

The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initial- ized. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 22-2. Internal RAM is not affe cted by reset. When V DD is turned on, the RAM content is indeterminat e. Therefore, this RAM should be initialized before read or tested it. When the RESET pin input goes to high, the reset operation is re- leased and the program execution starts at the vector address stored at addresses FFFEH - FFFFH. A connection for simple power-on-reset is shown in Figure . Figure 22-2 Timing Diagram after RESET

22.2 Watchdog Timer Reset

Refer to “18. LCD DRIVER” on page 65. 7036P VCC 10uF 10kΩ to the RESET pin On-chip Hardware Initial Value Program Counter (PC) (FFFFH) - (FFFEH) G-Flag (G) 0 Operation Mode Main Operating Mode Peripheral Clock On Watchdog Timer Disable (Because the Watch timer is disabled) Control Registers Refer to Table 8-1 on page 24 Low Voltage Detector Enable Table 22-1 Initializing Internal Status by Reset Action MAIN PROGRAM Oscillator (XIN pin) ? ? FFFE FFFF Stabilization Time tST = 62.5mS at 4.19MHz RESET ADDRESS DATA 1 2 3 4 5 6 7 ?? Start ? ?? FE? ADL ADH OP BUS BUS RESET Process Step tST = x 256 fMAIN ÷1024

FEB. 2005 Ver 1.04 83 Figure 23-3 Power Fail Processor Situations Internal RESET Internal RESET Internal RESET VDD VDD VDD LVDVDDMAX LVDVDDMIN LVDVDDMAX LVDVDDMIN LVDVDDMAX LVDVDDMIN 64mS 64mS t <64mS 64mS When LVDM = 1

84 FEB. 2005 Ver 1.04 24. DEVELOPMENT TOOLS

24.1 OTP Programming

The GMS87C7216 is OTP (One Ti me Programmable) type mi- crocontrollers. Its internal us er memory is constructed with EPROM (Electrically programmable read only memory). The OTP microcontroller is genera lly used for chip evaluation, first production, small amount production, fast mass production, etc. Blank OTP’s internal EPROM is filled by 00H, not FFH. Note: In any case, you have to use the *.OTP file for pro- gramming, not the *.HEX file. After assemble the source program, both OTP and HEX file are generated by automat- ically. The HEX file is us ed during program emulation on the emulator. How to Program To program the OTP devices, user should use MagnaChip own programmer. Ask to MagnaChip sales part for purchasing or more detail. Programmer: CHOICE-SIGMA (Single type) PGM-Plus (Single type) StandAlone-GANG4 (4-gang type) Socket adapter:87C70XX-64SD (for 64SDIP) 87C70XX-64QF (for 64MQFP) 87C70XX-64LQ (for 64LQFP) The CHOICE-SIGMA is a MagnaChip universal single program- mer for all of MagnaChip OTP de vices, also the StandAlone- GANG4 can program four OTPs at once. Programming Procedure 1. Select device GMS87C7216 as you want. 2. Load the *.OTP file from the PC to programmer. The file is composed of Motorola-S1 format. 3. Set the programming address range as below table. 4. Mount the socket adap ter on the programmer. 5. Set the configuration bytes as your needs. 6. Start program/verify. Select the Options for Program Lock and RC Oscillation Except the user program memory C000H~FFFFH, there is config- uration byte (address 707F H) for the selection of program lock and RC oscillation. The configuration byte of OTP is shown as Figure 24-1. It could be served when user use the OTP program- 87C70XX-64SD 87C70XX-64QF 87C71XX-52SD 87C70XX-64SD 87C70XX-64QF 87C71XX-52SD

FEB. 2005 Ver 1.04 85 mer (PGM-Plus, Choice-Sigma or StandAlone-Gang4). Figure 24-1 The OTP Configuration Byte ADDRESS: 707FH 76543210 OTP Configuration Byte LOCK RC 0: Crystal or Resonator 1: External RC Oscillator 0: Allow Code Read Out 1: Not Allow Code Read Out Lock bit Oscillation Option

86 FEB. 2005 Ver 1.04 24.2 Emulator EVA. Board Setting GND VCL1 VLCDC CB GND N.C. REMOUT (TONED) GND R36 R34 R21 R23 R25 R27 R16 R14 R12 R10 R06 R04 R02 R00 R32 R30 +5V POWER RUN STOP SLEEP J_USERB RESET J_USERA V_USER X1 (OSC) X2/RESET XOUT LCD_Vdd VLCDC SEG46 SEG44 SEG42 SEG40 SEG38 VREG COM1/S36 COM3/S34 SEG32 SEG30 SEG28 SEG26 SEG24 SEG22 SEG20 SEG18 SEG16 SEG14 SEG12 SEG10 SEG8 SEG6 SEG4 SEG2 SEG0 SEG47 SEG45 SEG43 SEG41 SEG39 SEG37 COM0 COM2/S35 SEG33 SEG31 SEG29 SEG27 SEG25 SEG23 SEG21 SEG19 SEG17 SEG15 SEG13 SEG11 SEG9 SEG7 SEG5 SEG3 SEG1 GND VCL0 VCL2 CA GND /U_RST U_XOUT GND R37 R35 R20 R22 R24 R26 R17 R15 R13 R11 R07 R05 R03 R01 R33 R31 +5V J_USERBJ_USERA ONOFF SW4 SW5 SW2 2 1 ON OFF SW1 Supply +5V (max. 200mA) VR1 +5V External oscillator socket

FEB. 2005 Ver 1.04 87 DIP Switch and VR Setting Before execute the user program, keep in your mind the below configuration DIP S/W, VR Description ON/OFF Setting SW1 - Emulator Reset Switch. Reset the Emulator. Reset the Emulator. SW2 Pod RESET pin configuration Normally OFF. EVA. chip can be reset by external user target board. ON : Reset is available by either user target system board or Emula- tor RESET switch. OFF : Reset the MCU by Emulator RESET switch. Does not work from user target board. Pod XOUT pin configuration Normally OFF. MCU XOUT pin is disconnected internally in the Emulator. Some cir- cumstance user may connect this circuit. ON : Output XOUT signal OFF : Disconnect circuit SW4 External Bias Resistors Connection Must be ON position. It serves the external bias resistors. If this switches are turned off, LCD bias voltage does not supplied, floated because there are no inter- nal bias resistors and bias Tr. inside the Emulator. LCD Voltage doubling circuit. Must be OFF position. It is reserved for the GMS81C5108. 7 Select the Stack Page. Must be ON position. This switch select the Stack page 0 (off) or page 1 (on). ON : For the 81C7XXX OFF : For the GMS81C5108 81Cx detect the VDD voltage but Emulator can not do because Emulator can not operate if V DD is below normal opr. voltage (5V), This switch serves LVD environment through the applying 0V to LVD pin of EVA. chip during 5V normal operation. Position ON during normal opera- tion. ON : Normal operation OFF : Force to detect the LVD, refer to "23. POWER FAIL PROCES- SOR" on page 82. SW2-1 RESET pinEVA. Chip SW2-2 XOUT pin EVA. Chip Oscillator VCL1 VCL2 BIAS External Resistor EVA. Chip Internal VCL0 VSS VDD Adjust Contrast SW4-1 SW4-2 SW4-3 0.47uF × 3 10kΩ × 3 and Capacitor VR1 50kΩ SW4 SW4-8 VDD EVA. Chip LVD pin

88 FEB. 2005 Ver 1.04 SW5 1 Internal power supply to sub-oscillation circuit. Must be ON position. 2 Reserved for other purpose. Must be OFF position. VR1 - Adjust the LCD contrast. It supply bias voltage and adjust the VCL2 voltage. Adjust the proper position as well as LCD display good. VR2 - Reserved for other purpose. Don’t care. DIP S/W, VR Description ON/OFF Setting VCL1 VCL2 BIAS External Resistor EVA. Chip Internal VCL0 VSS VDD Adjust Contrast SW4-1 SW4-2 SW4-3 0.47uF × 3 10kΩ × 3 and Capacitor VR1 50kΩ

A. MASK ORDER SHEET 1. Customer Information Company Name 2. Device Information 3. Marking Specification 4. Delivery Schedule Customer Sample Date YYYY MM DD Risk Order YYYY MM DD Quantity MagnaChip Confirmation Application Order Date YYYY MM DD Tel: Fax: Name & Signature: Package 44MQFP 44LQFP 5. ROM Code Verification Verification Date: YYYY MM DD Approval Date: YYYY MM DD Please confirm our verification data. I agree with your verification data and confirm you to make mask set. Check Sum: Tel: Fax: Name & Signature: Tel: Fax: Name & Signature: C000H E000H FFFFH .OTP file data DFFFH Mask Data Internet File Name: ( .OTP) (Please check mark into ) pcs pcs Check Sum: ( ) Customer should write inside thick line box. This box is written after “5.Verification”. RC OSC Opt. Crystal RC GMS81C7216 (16K ROM) GMS81C7208 (8K ROM) ROM Size 8K 16K YYWW KOREA Customer’s logo Customer logo is not required. YYWW KOREA GMS81C72 Customer’s part number If the customer logo must be used in the special mark, please submit a clean original of the logo. 08 or 16 E-mail: E-mail: 01-AUG-2003 MASK ORDER & VERIFICATION SHEET GMS81C7208-LAGMS81C7216 -LA GMS81C72 -LA Lot Number MagnaChip ROM Code Number 6 ~

FEB. 2005 Ver 1.04 iii B. INSTRUCTION B.1 Terminology List Terminology Description A Accumulator X X - register Y Y - register PSW Program Status Word #imm 8-bit Immediate Data dp Direct Page Offset Address !abs Absolute Address [ ] Indirect Expression { } Register Indirect Expression { }+ Register Indirect Expression, after that, Register Auto-Increment .bit Bit Position A.bit Bit Position of Accumulator dp.bit Bit Position of Direct Page Memory M.bit Bit Position of Memory Data (000 H~0FFFH) rel Relative Addressing Data upage U-page (0FF00 H~0FFFFH) Offset Address n Table CALL Number (0~15) + Addition x Upper Nibble Expression in Opcode y Upper Nibble Expression in Opcode − Subtraction × Multiplication / Division ( ) Contents Expression ∧ AND ∨ OR ⊕ Exclusive OR ~N O T ← Assignment / Transfer / Shift Left → Shift Right ↔ Exchange = Equal ≠ Not Equal Bit Position Bit Position

iv FEB. 2005 Ver 1.04 B.2 Instruction Map LOW HIGH 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 000 - SET1 dp.bit BBS A.bit,r el BBS dp.bit, rel ADC #imm ADC dp ADC dp+X ADC !abs ASL A ASL dp TCAL L SETA .bit BIT dp POP A PUSH A BRK

001 CLRC SBC

#imm SBC dp SBC dp+X SBC !abs ROL A ROL dp TCAL L CLRA .bit COM dp POP X PUSH X BRA rel

010 CLRG CMP

#imm CMP dp CMP dp+X CMP !abs LSR A LSR dp TCAL L NOT1 M.bit TST dp POP Y PUSH Y PCAL L Upage

011 DI OR

#imm OR dp OR dp+X OR !abs ROR A ROR dp TCAL L OR1 OR1B CMPX dp POP PSW PUSH PSW RET

100 CLRV AND

#imm AND dp AND dp+X AND !abs INC A INC dp TCAL L AND1 AND1 B CMPY dp CBNE dp+X TXSP INC X

101 SETC EOR

#imm EOR dp EOR dp+X EOR !abs DEC A DEC dp TCAL L EOR1 EOR1 B DBNE dp XMA dp+X TSPX DEC X

110 SETG LDA

#imm LDA dp LDA dp+X LDA !abs TXA LDY dp TCAL L LDC LDCB LDX dp LDX dp+Y XCN DAS 111 EI LDM dp,#i mm STA dp STA dp+X STA !abs TAX STY dp TCAL L STC M.bit STX dp STX dp+Y XAX STOP LOW HIGH 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111

000 BPL

dp.bit BBC A.bit,rel BBC dp.bit,r el ADC {X} ADC !abs+ Y ADC [dp+X] ADC [dp]+Y ASL !abs ASL dp+X TCAL L JMP !abs BIT !abs ADD W dp LDX #imm JMP [!abs]

001 BVC

{X} SBC !abs+ Y SBC [dp+X] SBC [dp]+Y ROL !abs ROL dp+X TCAL L CALL !abs TEST !abs SUB W dp LDY #imm JMP [dp]

010 BCC

{X} CMP !abs+ Y CMP [dp+X] CMP [dp]+Y LSR !abs LSR dp+X TCAL L MUL TCLR !abs CMP W dp CMPX #imm CALL [dp]

011 BNE

{X} OR !abs+ Y OR [dp+X] OR [dp]+Y ROR !abs ROR dp+X TCAL L DBNE Y CMPX !abs LDYA dp CMPY #imm RETI

100 BMI

{X} AND !abs+ Y AND [dp+X] AND [dp]+Y INC !abs INC dp+X TCAL L DIV CMPY !abs INCW dp INC Y TAY

101 BVS

{X} EOR !abs+ Y EOR [dp+X] EOR [dp]+Y DEC !abs DEC dp+X TCAL L XMA {X} XMA dp DEC W dp DEC Y TYA

110 BCS

{X} LDA !abs+ Y LDA [dp+X] LDA [dp]+Y LDY !abs LDY dp+X TCAL L LDA {X}+ LDX !abs STYA dp XAY DAA

111 BEQ

{X} STA !abs+ Y STA [dp+X] STA [dp]+Y STY !abs STY dp+X TCAL L STA {X}+ STX !abs CBNE dp XYX NOP

FEB. 2005 Ver 1.04 v B.3 Instruction Set Arithmetic / Logic Operation No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC

1 ADC #imm 04 2 2

Add with carry. A ← ( A ) + ( M ) + C NV--H-ZC

2 ADC dp 05 2 3

3 ADC dp + X 06 2 4

4 ADC !abs 07 3 4 5 ADC !abs + Y 15 3 5

6 ADC [ dp + X ] 16 2 6

7 ADC [ dp ] + Y 17 2 6

8 ADC { X } 14 1 3

9 AND #imm 84 2 2

10 AND dp 85 2 3

11 AND dp + X 86 2 4

12 AND !abs 87 3 4 13 AND !abs + Y 95 3 5

14 AND [ dp + X ] 96 2 6

15 AND [ dp ] + Y 97 2 6

16 AND { X } 94 1 3

17 ASL A 08 1 2 Arithmetic shift left

18 ASL dp 09 2 4

19 ASL dp + X 19 2 5

20 ASL !abs 18 3 5

21 CMP #imm 44 2 2

Compare accumulator contents with memory contents

22 CMP dp 45 2 3

23 CMP dp + X 46 2 4

24 CMP !abs 47 3 4 25 CMP !abs + Y 55 3 5

26 CMP [ dp + X ] 56 2 6

27 CMP [ dp ] + Y 57 2 6

28 CMP { X } 54 1 3

29 CMPX #imm 5E 2 2

Compare X contents with memory contents ( X ) - ( M ) N-----ZC30 CMPX dp 6C 2 3 31 CMPX !abs 7C 3 4

32 CMPY #imm 7E 2 2

Compare Y contents with memory contents ( Y ) - ( M ) N-----ZC33 CMPY dp 8C 2 3 34 CMPY !abs 9C 3 4

35 COM dp 2C 2 4 1’S Complement : ( dp ) ← ~( dp ) N-----Z-

36 DAA DF 1 3 Decimal adjust for addition N-----ZC

37 DAS CF 1 3 Decimal adjust for subtraction N-----ZC

← “0”← C

vi FEB. 2005 Ver 1.04

38 DEC A A8 1 2

M ← ( M ) - 1 N-----Z-

39 DEC dp A9 2 4

40 DEC dp + X B9 2 5

41 DEC !abs B8 3 5

42 DEC X AF 1 2

43 DEC Y BE 1 2

44 DIV 9B 1 12 Divide : YA / X Q: A, R: Y NV--H-Z-

45 EOR #imm A4 2 2

A ← ( A ) ⊕ ( M ) N-----Z-

46 EOR dp A5 2 3

47 EOR dp + X A6 2 4

48 EOR !abs A7 3 4 49 EOR !abs + Y B5 3 5

50 EOR [ dp + X ] B6 2 6

51 EOR [ dp ] + Y B7 2 6

52 EOR { X } B4 1 3

53 INC A 88 1 2

M ← ( M ) + 1 N-----ZC

54 INC dp 89 2 4

55 INC dp + X 99 2 5

56 INC !abs 98 3 5

57 INC X 8F 1 2

58 INC Y 9E 1 2

59 LSR A 48 1 2 Logical shift right

60 LSR dp 49 2 4

61 LSR dp + X 59 2 5

62 LSR !abs 58 3 5

63 MUL 5B 1 9 Multiply : YA ← Y × A N-----Z-

64 OR #imm 64 2 2

65 OR dp 65 2 3

66 OR dp + X 66 2 4

67 OR !abs 67 3 4 68 OR !abs + Y 75 3 5

69 OR [ dp + X ] 76 2 6

70 OR [ dp ] + Y 77 2 6

71 OR { X } 74 1 3

72 ROL A 28 1 2 Rotate left through Carry

73 ROL dp 29 2 4

74 ROL dp + X 39 2 5

75 ROL !abs 38 3 5 No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC 76543210 “0” → → C 76543210C

FEB. 2005 Ver 1.04 vii

76 ROR A 68 1 2 Rotate right through Carry

77 ROR dp 69 2 4

78 ROR dp + X 79 2 5

79 ROR !abs 78 3 5

80 SBC #imm 24 2 2

A ← ( A ) - ( M ) - ~( C ) NV--HZC

81 SBC dp 25 2 3

82 SBC dp + X 26 2 4

83 SBC !abs 27 3 4 84 SBC !abs + Y 35 3 5

85 SBC [ dp + X ] 36 2 6

86 SBC [ dp ] + Y 37 2 6

87 SBC { X } 34 1 3

88 TST dp 4C 2 3 Test memory contents for negative or zero, ( dp ) - 00

89 XCN CE 1 5 Exchange nibbles within the accumulator

A7~A4 ↔ A3~A0 N-----Z- No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC 76543210 C

viii FEB. 2005 Ver 1.04 Register / Memory Operation No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC

1 LDA #imm C4 2 2

A ← ( M ) N-----Z-

2 LDA dp C5 2 3

3 LDA dp + X C6 2 4

4 LDA !abs C7 3 4 5 LDA !abs + Y D5 3 5

6 LDA [ dp + X ] D6 2 6

7 LDA [ dp ] + Y D7 2 6

8L D A { X } D 4 1 3

9 LDA { X }+ DB 1 4 X- register auto-increment : A ← ( M ) , X ← X + 1

11 LDX #imm 1E 2 2

X ← ( M ) N-----Z-

12 LDX dp CC 2 3

13 LDX dp + Y CD 2 4

14 LDX !abs DC 3 4

15 LDY #imm 3E 2 2

Y ← ( M ) N-----Z-

16 LDY dp C9 2 3

17 LDY dp + X D9 2 4

18 LDY !abs D8 3 4

19 STA dp E5 2 4

Store accumulator contents in memory

20 STA dp + X E6 2 5

21 STA !abs E7 3 5 22 STA !abs + Y F5 3 6

23 STA [ dp + X ] F6 2 7

24 STA [ dp ] + Y F7 2 7

25 STA { X } F4 1 4

26 STA { X }+ FB 1 4 X- register auto-increment : ( M ) ← A, X ← X + 1

27 STX dp EC 2 4

Store X-register contents in memory 29 STX !abs FC 3 5

30 STY dp E9 2 4

Store Y-register contents in memory 32 STY !abs F8 3 5

33 TAX E8 1 2 Transfer accumulator contents to X-register : X ← A N-----Z-

34 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y ← A N-----Z-

35 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X ← sp N-----Z-

36 TXA C8 1 2 Transfer X-register contents to accumulator: A ← X N-----Z-

37 TXSP 8E 1 2 Transfer X-register contents to stack-pointer: sp ← X N-----Z-

38 TYA BF 1 2 Transfer Y-register contents to accumulator: A ← Y N-----Z-

FEB. 2005 Ver 1.04 ix 16-BIT operation Bit Manipulation

39 XAX EE 1 4 Exchange X-register contents with accumulator :X ↔

40 XAY DE 1 4 Exchange Y-register contents with accumulator :Y ↔

41 XMA dp BC 2 5

Exchange memory contents with accumulator ( M ) ↔ A N-----Z-42 XMA dp+X AD 2 6

43 XMA {X} BB 1 5

No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC

1 ADDW dp 1D 2 5 16-Bits add without Carry

YA ← ( YA ) ( dp +1 ) ( dp ) NV--H-ZC

2 CMPW dp 5D 2 4 Compare YA contents with memory pair contents :

(YA) − (dp+1)(dp) N-----ZC

3 DECW dp BD 2 6 Decrement memory pair

4I N C W d p 9 D 2 6 Increment memory pair

5 LDYA dp 7D 2 5 Load YA

YA ← ( dp +1 ) ( dp ) N-----Z-

6 STYA dp DD 2 5 Store YA

7 SUBW dp 3D 2 5 16-Bits subtract without carry

YA ← ( YA ) - ( dp +1) ( dp) NV--H-ZC No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC

3 BIT dp 0C 2 4 Bit test A with memory :

4 BIT !abs 1C 3 5

8 CLRG 40 1 2 Clear G-flag : G ← “0” --0-----

9 CLRV 80 1 2 Clear V-flag : V ← “0” -0--0---

11 EOR1B M.bit AB 3 5 Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M

x FEB. 2005 Ver 1.04

20 SETG C0 1 2 Set G-flag : G ← “1” --1-----

22 TCLR1 !abs 5C 3 6 Test and clear bits with A : 23 TSET1 !abs 3C 3 6 Test and set bits with A :

FEB. 2005 Ver 1.04 xi Branch / Jump Operation No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC 1 BBC A.bit,rel y2 2 4/6 Branch if bit clear : 2 BBC dp.bit,rel y3 3 5/7 3 BBS A.bit,rel x2 2 4/6 Branch if bit set : 4 BBS dp.bit,rel x3 3 5/7

5 BCC rel 50 2 2/4 Branch if carry bit clear

6B C S r e l D 0 2 2 / 4 Branch if carry bit set

7 BEQ rel F0 2 2/4 Branch if equal

8B M I r e l 9 0 2 2 / 4 Branch if minus 9B N E r e l 7 0 2 2 / 4 Branch if not equal

10 BPL rel 10 2 2/4 Branch if plus

11 BRA rel 2F 2 4 Branch always

12 BVC rel 30 2 2/4 Branch if overflow bit clear

13 BVS rel B0 2 2/4 Branch if overflow bit set

14 CALL !abs 3B 3 8 Subroutine call M( sp)←( pcH ), sp←sp - 1, M(sp)← (pcL), sp ←sp - 1, if !abs, pc← abs ; if [dp], pcL← ( dp ), pcH← ( dp+1 ) .

15 CALL [dp] 5F 2 8

16 CBNE dp,rel FD 3 5/7 Compare and branch if not equal :

17 CBNE dp+X,rel 8D 3 6/8

18 DBNE dp,rel AC 3 5/7 Decrement and branch if not equal :

19 DBNE Y,rel 7B 2 4/6

20 JMP !abs 1B 3 3 Unconditional jump

22 JMP [dp] 3F 2 4

23 PCALL upage 4F 2 6

M(sp) ←( pcH ), sp ←sp - 1, M(sp) ← ( pcL ), sp ← sp - 1, pcL ← ( upage ), pcH ← ”0FFH” .

24 TCALL n nA 1 8

Table call : (sp) ←( pcH ), sp ← sp - 1, M(sp) ← ( pcL ),sp ← sp - 1, pcL ← (Table vector L), pcH ← (Table vector H)

xii FEB. 2005 Ver 1.04 Control Operation & Etc. No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC 1B R K 0 F 1 8 Software interrupt : B ← ”1”, M(sp) ← (pcH), sp ←sp-1, M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp - pcL ← ( 0FFDEH ) , pcH ← ( 0FFDFH) . ---1-0--

2 DI 60 1 3 Disable all interrupts : I ← “0” -----0--

3 EI E0 1 3 Enable all interrupt : I ← “1” -----1--

5P O P A 0 D 1 4 s p ← sp + 1, A ← M( sp ) 7P O P Y 4 D 1 4 s p ← sp + 1, Y ← M( sp ) 8P O P P S W 6 D 1 4 s p ← sp + 1, PSW ← M( sp ) restored

9 PUSH A 0E 1 4 M( sp ) ← A , sp ← sp - 1

10 PUSH X 2E 1 4 M( sp ) ← X , sp ← sp - 1

11 PUSH Y 4E 1 4 M( sp ) ← Y , sp ← sp - 1

12 PUSH PSW 6E 1 4 M( sp ) ← PSW , sp ← sp - 1

13 RET 6F 1 5 Return from subroutine

14 RETI 7F 1 6

sp ← sp +1, PSW ← M( sp ), sp ← sp + 1, pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp ) restored

FEB. 2005 Ver 1.04 xiii C. SOFTWARE EXAMPLE ; Title: GMS81C7216/7016 (GMS800 Series) Demonstration Program * ; Company: MagnaChip Semiconductor Ltd. * ; Contents: LCD DISPLAY & DUAL THERMOMETER * R0 EQU 0C0H ;port R0 register R1 EQU 0C1H ;port R1 register R2 EQU 0C2H ;port R2 register R3 EQU 0C3H ;port R3 register R4 EQU 0C4H ;port R4 register R5 EQU 0C5H ;port R5 register R0DD EQU 0C8H ;port R0 data I/O direction register R1DD EQU 0C9H ;port R1 data I/O direction register R2DD EQU 0CAH ;port R2 data I/O direction register R3DD EQU 0CBH ;port R3 data I/O direction register R4DD EQU 0CCH ;port R4 data I/O direction register R5DD EQU 0CDH ;port R5 data I/O direction register R0PU EQU 0D0H ;port R0 Pull-up selection register R1PU EQU 0D1H ;port R1 Pull-up selection register R2PU EQU 0D2H ;port R2 Pull-up selection register R3PU EQU 0D3H ;port R3 Pull-up selection register R0CR EQU 0D4H ;port R0 Type selection register R1CR EQU 0D5H ;port R1 Type selection register R2CR EQU 0D6H ;port R2 Type selection register R3CR EQU 0D7H ;port R3 Type selection register IEDS EQU 0D8H ;External interrupt edge selection register PMR EQU 0D9H ;Alternative port mode register IENL EQU 0DAH ;int. enable register low IENH EQU 0DBH ;int. enable register high IRQL EQU 0DCH ;int. request flag register low IRQH EQU 0DDH ;int. request flag register high SLPR EQU 0DEH ;sleep mode register WDTR EQU 0DFH ;Watchdog timer register TM0 EQU 0E0H ;Timer 0 mode register TDR0 EQU 0E1H ;Timer 0 data register TM1 EQU 0E2H ;Timer 1 mode register TDR1 EQU 0E3H ;Timer 1 data register T1PPR EQU 0E3H ;PWM0 period register T1PDR EQU 0E4H ;Timer 1 pulse duty register PWM0HR EQU 0E5H ;PWM0 high register TM2 EQU 0E6H ;Timer 2 mode register TDR2 EQU 0E7H ;Timer 2 data register TM3 EQU 0E8H ;Timer 3 mode register TDR3 EQU 0E9H ;Timer 3 data register T3PPR EQU 0E9H ;PWM1 period register T3PDR EQU 0EAH ;Timer 3 pulse duty register PWM1HR EQU 0EBH ;PWM1 high register ADCM EQU 0ECH ;ADC mode register ADR EQU 0EDH ;ADC result data register WTMR EQU 0EFH ;Watch timer mode register KSMR EQU 0F0H ;Key scan mode register LCDM EQU 0F1H ;LCD mode register LCDPM EQU 0F2H ;LCD port mode register RPR EQU 0F3H ;RAM paging register BITR EQU 0F4H ;Basic interval timer data register CKCTLR EQU 0F4H ;Clock control register SCMR EQU 0F5H ;System clock mode register PFDR EQU 0FBH ;Power fail detector BUR EQU 0FDH ;buzzer data register SMR EQU 0FEH ;Serial mode register SIOD EQU 0FFH ;Serial data buffer register R_SAVEMACRO ;Save Registers to Stacks

xiv FEB. 2005 Ver 1.04 PUSH A PUSH X PUSH Y ENDM R_RSTRMACRO ;Restore Register from Stacks POP Y POP X POP A ENDM ; RAM ALLOCATION * TEMP0 DS 1 TEMP1 DS 1 TEMP2 DS 1 FLAG1 DS 1 RPTEN EQU 1,FLAG1 ;SET RPTEN(REPEAT KEY ENABLE) AFTER 1 SEC. KEYONF EQU 2,FLAG1 ;KEYSCAN ACTKEY EQU 3,FLAG1 ;AT ONCE, KEY VALID TOGMO3 EQU 4,FLAG1 ;MODE 3 (PORT TOGGLE) DUAL_T EQU 5,FLAG1 ;INSIDE & OUTSIDE TEMP. DUAL DISPLAY OUTSIDE EQU 6,FLAG1 ;INSIDE TEMP or OUTSIDE TEMP. FLAG2 DS 1 F200MS EQU 0,FLAG2 F20MS EQU 1,FLAG2 F_1MIN EQU 2,FLAG2 ;WTIMER LPM EQU 3,FLAG2 ;LEFT TIME PM FLAG RPM EQU 4,FLAG2 ;RIGHT TIME PM FLAG STATUS DS 1 RPTKEY EQU 7,STATUS F_CLOCK EQU 6,STATUS F_ON EQU 0,STATUS DISPSIGN DS 1 DISPRAM DS 1 ;TEMP. DISPRAM1 DS 4 ;LEFT TIME, RIGHT TIME ONDO DS 2 LHOUR DS 1 ;LEFT WATCH COUNT LMINUTE DS 1 RHOUR DS 1 RMINUTE DS 1 ;RIGHT WATCH COUNT BUF. TIMESET DS 4 ;WATCH SET BUFFER TSFLAG DS 1 TSLPM EQU 0,TSFLAG ;TIME SET LEFT PM TSRPM EQU 1,TSFLAG ;TIME SET RIGHT PM BLINKCNT DS 1 ;BLINK COUNTER 0~250 LOOP NEWKY DS 1 OLDKY DS 1 PORTDT DS 1 KEYNM DS 1 KEYDT DS 1 TOTLKY DS 1 CHATFL DS 1 R0BUF DS 1 DGTCNT DS 1 MODE DS 1 SUBMODE DS 1 BSCTIME DS 1 TEMPCNT DS 1 HZCNT DS 1 PWMF DS 1 PERIOD EQU 0,PWMF ; INTERRUPT VECTOR TABLE *

FEB. 2005 Ver 1.04 xv ORG 0FFE0H DW NOT_USED ; Timer-3 DW NOT_USED ; Timer-2 DW WTIMER ; Watch Timer DW INT_AD ; A/D CON. DW NOT_USED ; Serial I/O DW NOT_USED ; Not used DW NOT_USED ; Not used DW NOT_USED ; Int.2 DW TIMER1 ; Timer-1 DW TIMER0 ; Timer-0 DW INT1 ; Int.1 DW INT0 ; Int.0 DW NOT_USED; Watch Dog Timer DW NOT_USED; BIT DW INT_KEY ; Key Scan(Only GMS81C7008/7016) DW RESET ; Reset ; MAIN PROGRAM * ORG 0C000H ;Program Start Address ;ORG 0E000H ; 8K ROM VERSION RESET: LDM WDTR,#0 LDM RPR,#1 CLRG LDX #0 RAMCLR: LDA #0 ;RAM Clear(!0000H->!00BFH) STA {X}+ ;M(X) <- A, then X <- X+1 CMPX #0C0H ;X = #0C0H ? BNE RAMCLR SETG LDX #0 RAMCLR1: LDA #0 ;RAM Clear(!0100H->!011AH) STA {X}+ ;M(X) <- A, then X <- X+1 CMPX #1BH ;X = #01BH ? BNE RAMCLR1 CLRG LDX #0FFH ;Stack Pointer Initial TXSP ;SP. <- #0FFH ; LDM MODE,#4 ; LDM SUBMODE,#1 SET1 LPM ;KST PM 12:00 JUST NOON LDM LHOUR,#12H LDM LMINUTE,#00H LDM RHOUR,#03H ;UTC AM 03:00 LDM RMINUTE,#00H SET1 OUTSIDE SET1 F_ON ;POWER ON LDM LCDPM,#0 ;SEG0~SEG23 are used LDM R0,#0 ;I/O Port Data Clea LDM R1,#0 ;I/O Port Data Clear LDM R2,#0 LDM R3,#0 LDM R0DD,#1111_0001B ;R05,R06,R07: output for Keyscan LDM R1DD,#0000_0000B LDM R2DD,#0000_0000B ;R20~R23: input for keyscan LDM R3DD,#0000_0100B LDM R2PU,#0000_1111B ;R20~R23 pull-up active LDM CKCTLR,#0 ;WAKE UP TIME = 0.0625 sec LDM TDR0,#249 ;8us x (249+1) = 2ms LDM TM0,#0000_1111B ;8BIT Timer,8us,Start Count-up LDM TDR1,#249 ;2us x (249+1) = 500us LDM TM1,#0000_1111B ;Timer1(8bit),32us,Start Count-up LDM TM3,#1010_1011B

xvi FEB. 2005 Ver 1.04 LDM T3PPR,#99 LDM T3PDR,#50 LDM PWM1HR,#00H LDM PMR,#80H LDM IRQH,#0 ;Clear All Interrupts Requeat Flags LDM IRQL,#0 LDM IENL,#1111_1111B ;INT2,ADC,WT,T2,T3 LDM IENH,#1111_1111B ;BIT,WDT,INT0,INT1,T0,T1 LDM IEDS,#0001_0101B ;External Int. Falling edge select LDM KSMR,#0000_0001B ;R10 KEY INTERRUPT LDM WTMR,#48H ;ENABLE WT COUNTER, 2Hz, SELECT SUBCLOCK LDM LCDM,#70H ;CLK=fsub/64, 1/4duty, internal Bias LDM SCMR,#0 ;1/2, MAIN OSC. EI ;Enable Interrupts LOOP: BBC KEYONF,EXE1 ;TEST IF KEY IS PRESSED CALL KEYDECODE CLR1 KEYONF ;CLEAR KEY FLAG EXE1: BBC F20MS,NEXT1 CLR1 F20MS CALL MODEEXE ;SETTING DISPLAY MEMORY CALL MODE1EXE ;DURING CLOCK, CALL MODE3EXE CALL LCDDGT ;7-Segments Display CALL LCDDOT ;Dot Display CALL ADCEXE ;ADC execution CALL LKEYSCAN NEXT1: BBC F200MS,ELOOP CLR1 F200MS CALL WIND ELOOP: BBS F_ON,EXE2 CLR1 R0.7 ;FOR WAKE-UP BY NEXT KEY CLR1 R0.6 ;FOR WAKE-UP BY NEXT KEY CLR1 R0.5 ;FOR WAKE-UP BY NEXT KEY CLR1 R0.4 ;FOR WAKE-UP BY NEXT KEY STOP NOP NOP IF [F_1MIN] CLR1 F_1MIN CALL MODEEXE CALL LCDDGT ;7-Segments Display CALL LCDDOT ;Dot Display ENDIF CALL LKEYSCAN EXE2: JMP LOOP ; TIMER0,INTERRUPT ROUTINE(2ms) * TIMER0: R_SAVE ;Save Registers to Stacks CLRG CALL MAKE10MS ;SET every 10ms R_RSTR ;Restore Registers from Stacks RETI ; TIMER1 * TIMER1: R_SAVE CLRG R_RSTR

FEB. 2005 Ver 1.04 xvii RETI ; WATCH TIMER 4Hz * WTIMER: R_SAVE CLRG NOT1 R0.0 INC HZCNT LDA HZCNT CMP #120 BNE WT5 LDM HZCNT,#0 SET1 F_1MIN CALL INC1MIN WT5: R_RSTR RETI ; PORT INTERRUPT * INT_KEY: R_SAVE CLRG BBS CHATFL.7,IK8 BBS F_ON,IK8 LDX #3 LDM KSMR,#0 ;MAKE R10 TO BE NORMAL INPUT WW: LDY #2 ;24ms wait WW2: LDA #8 WW3: DEC A BNE WW3 DEC Y BNE WW2 LDA R1 ;READ R10 ROR A BCS IK8 DEC X BNE WW LDM SCMR,#0 ;MAIN OSC. SET1 F_ON SET1 CHATFL.7 LDM OLDKY,#0CH IK8: LDM KSMR,#1 R_RSTR RETI ; EXTERNAL INTERRUPT 0 * INT0: R_SAVE CLRG R_RSTR RETI ; EXTERNAL INTERRUPT 1 * INT1: CLRG RETI ; ADC INTERRUPT * INT_AD: RETI

xviii FEB. 2005 Ver 1.04 ; Subject: LCDDGT ; LCD 7-SEG. DIGIT DISPLAY (TMEP,LTIME,RTIME * ; Entry: DGTCNT (DIGIT COUNTER) * ; X (START ADDRESS) * ; Output: Output SEG_PORT (SEG0~SEG23) * ; Output COM_PORT (COM0~COM3) * ; LMINUTE+1 LMINUTE * LCDDGT: LDM DGTCNT,#9 LDX #DISPRAM GOLCD: LDA {X} PUSH X if [DGTCNT.0] ;WHEN DIGIT IS EVEN NUMBER, AND #0F0H ;WHEN DIGIT IS ODD NUMBER, XCN CALL LCDDSP ;HIGHER 4 NIBBLE IS DISPLAYED POP X else AND #0FH ;LOWER 4 NIBBLE IS DISPLAYED CALL LCDDSP POP X INC X endif DEC DGTCNT BPL GOLCD RET LCDDSP: TAY BNE GOCONT ;IF A=0 THEN SURPRESS LDA DGTCNT CMP #9 BEQ BLNK CMP #7 BEQ BLNK CMP #3 BEQ BLNK BRA GOCONT BLNK: LDY #0AH GOCONT: LDA !FONT+Y ;LOAD FONT DATA STA TEMP0 ;STORE 7-SEG FONT LDM TEMP2,#7 ;SHIFT COUNTER INITIALIZE LDY DGTCNT ;GET OFFSET LCD ADDRESS FOR DGTCNT LDA #14 MUL TAY DPL1: LDA !FONTD0+Y ;GET LCD RAM ADDRESS TAX ;STORE LCD RAM ADDRESS INC Y ;INCREMENT POINTER LDA !FONTD0+Y ;GET BIT POSITION STA TEMP1 ;STORE BIT POSITION ROR TEMP0 BCS DPL3 LDA #0FFH ;CLEAR BIT DISPLAY RAM ROL A DEC TEMP1 BPL $-3 SETG AND {X} BRA DPL5 DPL3: LDA #00H ;SET BIT DISPLAY RAM ROL A DEC TEMP1 BPL $-3 SETG OR {X} DPL5: STA {X}

FEB. 2005 Ver 1.04 xix CLRG INC Y DBNE TEMP2,DPL1 RET FONTD0 DB 13H,1H,13H,2H,13H,0H,13H,3H,0CH,3H,0CH,2H,0CH,0H ;RMINUTE0 FONTD1 DB 12H,1H,12H,2H,12H,0H,12H,3H,05H,3H,05H,2H,05H,0H ;RMINUTE1 FONTD2 DB 06H,1H,06H,2H,06H,0H,06H,3H,01H,3H,01H,2H,01H,0H ;RHOUR0 FONTD3 DB 80H,0H,01H,1H,01H,1H,80H,0H,80H,0H,80H,0H,80H,0H ;RHOUR1 FONTD4 DB 02H,1H,02H,2H,02H,0H,02H,3H,15H,3H,15H,2H,15H,0H ;LMINUTE0 FONTD5 DB 09H,1H,15H,1H,09H,0H,09H,3H,16H,0H,16H,1H,09H,2H ;LMINUTE1 FONTD6 DB 14H,1H,14H,2H,14H,0H,14H,3H,00H,3H,00H,2H,00H,0H ;LHOUR0 FONTD7 DB 80H,0H,08H,2H,08H,2H,80H,0H,80H,0H,80H,0H,80H,0H ;LHOUR1 FONTD8 DB 0BH,2H,0BH,0H,0BH,3H,0BH,1H,17H,1H,17H,0H,17H,3H ;ONDO0 FONTD9 DB 0FH,2H,0FH,0H,0FH,3H,0FH,1H,10H,1H,10H,0H,10H,3H ;ONDO1 ; 7-SEGMENT PATTERN DATA * ; _a_ * ; f | g |b * ; |---| * ; d .h * ; Segment: hgfe dcba To be displayed Digit Number FONT DB 0011_1111B ; 0 "0" DB 0000_0110B ; 1 DB 0101_1011B ; 2 DB 0100_1111B ; 3 DB 0110_0110B ; 4 DB 0110_1101B ; 5 DB 0111_1101B ; 6 DB 0000_0111B ; 7 DB 0111_1111B ; 8 "8" DB 0110_1111B ; 9 "9" DB 0000_0000B ; A "BLANK" DB 0100_0000B ; B "BAR" _LCOLON EQU 2,116H _RCOLON EQU 2,10EH _ONDO EQU 2,107H _C EQU 0,111H _RAM EQU 1,10EH _RPM EQU 0,10EH _LAM EQU 1,108H _LPM EQU 3,108H _OUTSIDE EQU 1,104H _INSIDE EQU 0,107H _S1 EQU 2,10AH _SNOW EQU 3,10AH _SAVE EQU 3,104H LCDDOT: SETC STC _LCOLON STC _S1 STC _ONDO STC _C LDCB F_ON STC _SAVE LDCB DUAL_T STC _RCOLON LDC LPM STC _LPM LDCB LPM STC _LAM IF [DUAL_T]==0 ldc RPM ;AM,PM SETTING stc _RPM ldcb RPM stc _RAM ELSE LDCB DUAL_T ;TURN OFF THE AM, PM STC _RPM

xx FEB. 2005 Ver 1.04 STC _RAM ENDIF LDC OUTSIDE STC _OUTSIDE LDCB OUTSIDE STC _INSIDE RET ; Subject: ANY EXECUTION * ; DESCRIPTION: EVERY 20MS * ; * MODEEXE: IF [OUTSIDE] LDX #0 ELSE LDX #1 ENDIF LDA ONDO+X ;COPY ONDO DATA TO DISPRAM STA DISPRAM LDA SIGN+X STA DISPSIGN IF [DISPSIGN.0] ;IF MINUS ONDO, THEN "-" DISPLAY IF [DISPRAM] < #10 LDA #0B0H OR DISPRAM STA DISPRAM CLRC STC _SNOW ELSE SETC STC _SNOW ENDIF ELSE CLRC STC _SNOW ENDIF LDX #3 ;MOVE TIME_BUF. TO DISP_BUF. MX1: LDA LHOUR+X STA DISPRAM1+X DEC X BPL MX1 BBC DUAL_T,MX2 ;IF SINGLE TEMP. MODE, SKIP LDA #0AAH ;MAKE ERASE DISP BUF. WITCH STA DISPRAM1+2 ;WILL BE DISPLAYED TEMP. IF [OUTSIDE] ;IF DUAL TEMP. MODE LDX #1 ;IF MAIN=OUSIDE, THEN SELECT INSIDE ELSE LDX #0 ;IF MAIN=INSIDE, THEN SELECT OUTSIDE ENDIF LDA ONDO+X STA DISPRAM1+3 LDA SIGN+X ;GET BIT0 OF SIGN ROR A ;COPY SIGN TO CARRY IF C ;IF MINUS ONDO, THEN "-" DISPLAY IF [DISPRAM1+3] < #10 LDA #0B0H ;EXE) BB-4 OR DISPRAM1+3 STA DISPRAM1+3 ELSE LDM DISPRAM1+2,#0ABH ;EXE) B-14 ENDIF ELSE IF [DISPRAM1+3] < #10 LDA #0A0H ;EXE) BB-4 OR DISPRAM1+3 STA DISPRAM1+3 ENDIF

FEB. 2005 Ver 1.04 xxi ENDIF MX2: RET ; Subject: MODE 1 EXECUTION * ; DESCRIPTION: CLOCK SET * ; * MODE1EXE: LDA MODE AND #0F0H CMP #10H ;IF MODE=1x BNE MB3 LDX #3 MB1: LDA TIMESET+X ;TIMESET BUF. COPIED TO DISP BUF. STA DISPRAM1+X ;4BYTE & 2 BIT DEC X BPL MB1 LDC TSLPM STC LPM LDC TSRPM STC RPM LDA MODE CMP #10H ;TEST IF LEFT TIME SET MODE ? BEQ MO10 CMP #11H BEQ MO11 ;TEST IF RIGHT TIME SET MODE ? BRA MB3 MO10: LDA BLINKCNT CMP #125 ;IF LESS THAN 124, OFF BCS MB3 LDA #0AAH STA DISPRAM1 STA DISPRAM1+1 MB3: RET MO11: LDA BLINKCNT CMP #125 ;IF LESS THAN 124, OFF BCS MB3 LDA #0AAH STA DISPRAM1+2 STA DISPRAM1+3 BRA MB3 ; Subject: MODE 3 EXECUTION * ; DESCRIPTION: All pin goes low and high * ; repeatly every 20ms, rectangle wave output * ; * MODE3EXE: LDA MODE CMP #3 BNE MO2 LDA SUBMODE DEC A ;BECAUSE INITIAL NO.=1 ROL A ;EIGHT TIMES ROL A ROL A NOT1 TOGMO3 BBC TOGMO3,MO1 CLRC ADC #4 ;ADD OFFSET MO1: TAY LDA !PPORT+Y AND #0001_1111B OR R0BUF STA R0BUF STA R0 LDA !PPORT+1+Y STA R1 LDA !PPORT+2+Y STA R2

xxii FEB. 2005 Ver 1.04 LDA !PPORT+3+Y STA R3 MO2: RET PPORT DB 00H,00H,00H,00H DB 00H,00H,00H,00H DB 0FFH,0FFH,0FFH,0FFH DB 0FFH,0FFH,0FFH,0FFH DB 00H,00H,00H,00H DB 0FFH,0FFH,0FFH,0FFH DB 00H,00H,00H,00H DB 0FFH,00H,0FFH,00H DB 00H,0FFH,00H,0FFH DB 00H,00H,00H,00H DB 00H,0FFH,00H,0FFH DB 0FFH,00H,0FFH,00H DB 55H,55H,55H,55H DB 0AAH,0AAH,0AAH,0AAH ; Subject: Set falg at every 20ms * MAKE10MS: SETC LDA #0 ADC BSCTIME DAA STA BSCTIME BNE $+4 SET1 F200MS ;SET F200MS EVERY 200ms AND #0FH BNE $+4 SET1 F20MS ;SET F20MS EVERY 20ms INC BLINKCNT ;USED IN MODE0(CLOCK SET) LDA BLINKCNT CMP #250 BNE MZ1 LDM BLINKCNT,#0 MZ1: RET ; Subject: Analog to Digital Conversion * ; It is called in main routine every 20ms ADCNT DS 2 ADR_AVR DS 2 ADTTL DS 4 ADFLAG DS 1 AD_CH EQU 0,ADFLAG SIGN DS 2 DIVISOR EQU 250 ; :ADR_AVR: :ADR_AVR: ; : : : : ; :OUTSIDE: :INSIDE : ; :CH4 : :CH5 : ADCEXE: IF [AD_CH]== 0 LDM ADCM,#52H ;AD START CH4 LDX #0 ;SET TO 0 INDEX POINTER ELSE LDM ADCM,#56H ;AD START CH5 LDX #1 ;SET TO 1 INDEX POINTER ENDIF LDY #20 ;WAIT ADC END ADWAIT: DEC Y BBS ADCM.0,GOGET CMPY #0 BNE ADWAIT

FEB. 2005 Ver 1.04 xxiii GOGET: CLRC ;UP8 LO8 LDA ADR ;ADTTL2|ADTTL0 = CH4 DATA ADC ADTTL+X ;ADTTL3|ADTTL1 = CH5 DATA STA ADTTL+X LDA #0 ADC ADTTL+2+X STA ADTTL+2+X INC ADCNT+X LDA ADCNT+X IF A == #DIVISOR ;GET AVERAGE VALUE LDA #0 STA ADCNT+X LDY ADTTL+2+X LDA ADTTL+X PUSH X LDX #DIVISOR ;DIVIDE BY DIVISOR DIV POP X STA ADR_AVR+X LDA #0 ;CLEAR SUM BUF. STA ADTTL+X STA ADTTL+2+X LDA ADR_AVR+X IF A < #65 ;IGNORE BELOW 65 LDA #65 ENDIF IF A > #240 ;MAX. 240 LDA #240 ENDIF CMP #181 ;MAKE SIGN ROL SIGN+X ;COPY TO MINUS OR PLUS SETC SBC #65 TAY LDA !ADTABLE1+Y STA ONDO+X ENDIF NOT1 AD_CH ADCQUIT: RET ADTABLE DB 50H,49H,49H,48H,48H,47H ; 65~ 70 65->+50’C DB 47H,46H,46H,45H,45H,44H,44H,43H,43H,42H ; 71~ 80 DB 41H,41H,40H,40H,40H,39H,39H,38H,38H,37H ; 81~ 90 83->+40'C DB 37H,36H,36H,35H,35H,34H,34H,33H,33H,32H ; 91~100 DB 32H,31H,31H,30H,30H,30H,29H,29H,28H,28H ;101~110 105->+30'C DB 27H,27H,26H,26H,25H,25H,24H,24H,24H,23H ;111~120 DB 23H,22H,22H,22H,21H,21H,20H,20H,20H,20H ;121~130 129->+20'C DB 19H,19H,18H,18H,17H,17H,16H,16H,15H,15H ;131~140 DB 15H,14H,14H,14H,13H,13H,13H,12H,12H,12H ;141~150 DB 11H,11H,11H,10H,10H,10H,09H,09H,09H,08H ;151~160 154->+10'C DB 08H,07H,07H,07H,06H,05H,05H,04H,04H,04H ;161~170 DB 03H,03H,02H,02H,01H,01H,00H,00H,00H,01H ;171~180 178-> 0'C DB 01H,02H,02H,03H,03H,04H,04H,05H,05H,06H ;181~190 DB 06H,07H,07H,08H,08H,09H,09H,10H,10H,11H ;191~200 199->-10'C DB 11H,12H,12H,13H,13H,14H,15H,15H,16H,17H ;201~210 DB 17H,18H,18H,19H,19H,20H,20H,21H,21H,22H ;211~220 217->-20'C DB 23H,23H,24H,24H,25H,25H,26H,27H,28H,29H ;221~230 DB 30H,31H,32H,33H,34H,35H,36H,37H,38H,39H ;231~240 231->-30'C DB 40H,41H,42H ADTABLE1 DB 50H,50H,50H,49H,49H,48H ; 65~ 70 65->+50’C DB 48H,47H,47H,46H,46H,45H,45H,44H,44H,43H ; 71~ 80 DB 43H,42H,41H,40H,39H,38H,37H,36H,35H,34H ; 81~ 90 83->+40'C DB 35H,35H,34H,34H,33H,33H,32H,32H,31H,31H ; 91~100 DB 30H,30H,29H,29H,28H,28H,27H,27H,26H,26H ;101~110 105->+30'C DB 26H,25H,25H,25H,24H,24H,24H,23H,23H,23H ;111~120 DB 22H,22H,22H,21H,21H,21H,20H,20H,20H,20H ;121~130 129->+20'C DB 19H,18H,18H,18H,17H,17H,17H,16H,16H,16H ;131~140 DB 15H,15H,15H,14H,14H,14H,13H,13H,13H,12H ;141~150 DB 12H,11H,11H,10H,10H,09H,09H,09H,08H,08H ;151~160 154->+10'C DB 07H,07H,06H,06H,05H,05H,04H,04H,04H,03H ;161~170 DB 03H,03H,02H,02H,02H,01H,01H,01H,00H,00H ;171~180 178-> 0'C DB 01H,01h,02H,02H,03H,03H,04H,04H,05H,05H ;181~190 DB 06H,06H,07H,07H,08H,08H,09H,09H,10H,10H ;191~200 199->-10'C DB 11H,11H,12H,12H,13H,13H,14H,15H,15H,16H ;201~210 DB 16H,16H,17H,18H,18H,19H,19H,20H,20H,21H ;211~220 217->-20'C

xxiv FEB. 2005 Ver 1.04 DB 21H,22H,23H,23H,24H,24H,25H,25H,26H,27H ;221~230 DB 28H,29H,30H,31H,32H,33H,34H,35H,36H,37H ;231~240 231->-30'C DB 38H,39H,40H ; Subject: KEYDECODE * ; * REPEAT EQU #1000_0000B CLOCK EQU #0100_0000B PWRON EQU #0000_0001B KEYDECODE: LDA KEYDT LDY #3 MUL TAY LDA !KEY+Y STA TEMP0 LDA !KEY+1+Y STA TEMP1 LDA !KEY+2+Y STA TEMP2 CALL CONDICHK BCC QUIT JMP [TEMP0] KEY: DW NOKEY ;0 DB 0 DW NOKEY ;1 DB 0 DW NOKEY ;2 DB 0 DW NOKEY ;3 DB 0 DW NOKEY ;4 DB 0 DW NOKEY ;5 DB 0 DW NOKEY ;6 DB 0 DW DOWNKEY ;7 DB PWRON+REPEAT DW NOKEY ;8 DB 0 DW DUALKEY ;9 DB PWRON DW SWAPKEY ;A DB PWRON DW NOKEY ;B DB 0 DW POWERKEY ;C DB PWRON DW CLOCKKEY ;D DB PWRON+CLOCK DW HOURKEY ;E DB PWRON+REPEAT+CLOCK DW MINUTEKEY ;F DB PWRON+REPEAT+CLOCK DW NOKEY ;10 DB 0 DW UPKEY ;11 DB PWRON+REPEAT DW NOKEY ;12 DB 0 QUIT: NOKEY: RET CONDICHK: LDA TEMP2 OR STATUS SBC TEMP2 BEQ CDC9 BCS CDC10 CDC9: SETC ;PASS RET CDC10: CLRC ;SKIP RET

FEB. 2005 Ver 1.04 xxv ; DISPLAY SWAP KEY (TEMP. DISPLAY SWAP) * SWAPKEY: NOT1 OUTSIDE RET ; DUAL KEY * DUALKEY: NOT1 DUAL_T RET ; POWER KEY * POWERKEY: CLR1 F_ON IF [F_ON] ELSE LDM SCMR,#2 CLR1 DUAL_T LDM MODE,#0 SET1 F20MS ENDIF RET ; CLOCK KEY * CLOCKKEY: SET1 F_CLOCK LDM BLINKCNT,#0 LDA MODE ; 10->11 CMP #10H ; 11->00 BNE CL1 ; ETC. -> 10 LDM MODE,#11H BRA QUIT CL1: CMP #11H BNE CL2 LDM MODE,#0 CLR1 F_CLOCK CALL SETTO_CNT LDC TSLPM STC LPM LDC TSRPM STC RPM LDM HZCNT,#0 CLR1 F_1MIN BRA CLQ CL2: LDM MODE,#10H CLR1 DUAL_T CALL CNTTO_SET LDC LPM STC TSLPM LDC RPM STC TSRPM CLQ: RET SETTO_CNT: LDX #3 CL11: LDA TIMESET+X STA LHOUR+X DEC X BPL CL11 RET CNTTO_SET: LDX #3 CL3: LDA LHOUR+X STA TIMESET+X DEC X BPL CL3 RET ; HOUR/MINUTE KEY * HOURKEY: LDA MODE

xxvi FEB. 2005 Ver 1.04 AND #0F0H CMP #10H BNE HO1 LDM BLINKCNT,#125 LDA MODE CMP #10H BNE HO2 SETC ;IF MODE=10H, THEN LEFT TIME SET LDA #0 ;INC. LEFT HOUR 1UP ADC TIMESET DAA IF A==#12H NOT1 TSLPM ;ADJUST AM,PM FLAG ENDIF IF A==#13H LDA #1 ENDIF STA TIMESET HO1: RET HO2: CMP #11H BNE HO1 SETC ;INC. RIGHT HOUR 1UP LDA #0 ADC TIMESET+2 DAA IF A==#12H NOT1 TSRPM ;ADJUST AM,PM FLAG ENDIF IF A==#13H LDA #1 ENDIF STA TIMESET+2 BRA HO1 MINUTEKEY: LDA MODE AND #0F0H CMP #10H BNE MT3 LDM BLINKCNT,#125 LDX #3 LDA MODE CMP #10H BNE MT1 LDX #1 MT1: SETC LDA #0 ADC TIMESET+X DAA CMP #60H BNE MT2 LDA #0 MT2: STA TIMESET+X MT3: RET ; UP /DOWN KEY * UPKEY: BBS PERIOD,PRU LDA PWM1HR AND #0000_0011B CMP #3 BNE UPK1 LDA T3PDR CMP #0FFH BNE UPK1 UPK0: RET UPK1: INC T3PDR BNE UPK0 INC PWM1HR BRA UPK0 PRU: DOWNKEY: BBS PERIOD,PRD LDA PWM1HR AND #0000_0011B CMP #0

FEB. 2005 Ver 1.04 xxvii BNE DNK1 LDA T3PDR CMP #0 BEQ UPK0 DNK1: DEC T3PDR LDA T3PDR CMP #0FFH BNE DNK2 DEC PWM1HR DNK2: RET PRD: PWMMODE: ; PLUS KEY * ; * ; When MODE=3, PRESS PULS KEY, SUBMODE IS INCRESED * ; When MODE=3, PRESS MINUS KEY, SUBMODE IS DECRESED * ; * ; Subject: KEYSCAN * ; STROBE OUT: R05,R06,R07 * ; READ PORT : R20,R21,R22,R23 * ; * LKEYSCAN: BBS KEYONF,KS7 LDM KEYNM,#1 LDM TOTLKY,#0 LDM NEWKY,#0 LDY #3 ;INITIALIZE STROBE LINE KS1: CMPY #3 BNE $+4 CLR1 R0.4 ;OUTPUT STROBE SIGNAL CMPY #2 BNE $+4 CLR1 R0.5 ;OUTPUT STROBE SIGNAL CMPY #1 BNE $+4 CLR1 R0.6 ;OUTPUT STROBE SIGNAL CMPY #0 BNE $+4 CLR1 R0.7 ;OUTPUT STROBE SIGNAL NOP NOP LDA R2 STA PORTDT ;READ KEY IN PORT AND #0FH CMP #0FH ;IF KEY IS PRESSED ? BNE KS2 CLRC ;KEYNM + 4 -> KEYNM LDA #4 ADC KEYNM STA KEYNM BRA KS5 KS2: LDX #3 ;INITIALIZE SHIFT COUNTER KS3: ROR PORTDT BCS KS4 INC TOTLKY ;IF TOTLKY IS ABOVE 2, THEN QUIT LDA TOTLKY CMP #20 BEQ KS7 LDA KEYNM ;KEYNM -> NEWKY STA NEWKY KS4: INC KEYNM DEC X BPL KS3 KS5: SET1 R0.4 SET1 R0.5

xxviii FEB. 2005 Ver 1.04 SET1 R0.6 SET1 R0.7 DEC Y ;TEST NEXT LINE BPL KS1 LDA NEWKY CMP #0 ;WHEN NO KEY IS PRESSED, BNE KS8 ;INITIALIZE NEWKY,OLDKY,CHATFL KS6: LDA NEWKY STA OLDKY LDM CHATFL,#0 CLR1 RPTKEY CLR1 ACTKEY CLR1 RPTEN KS7: RET KS8: LDA NEWKY CMP OLDKY BNE KS6 BBS CHATFL.7,KS10 LDA CHATFL AND #0111_1111B CMP #5 BCC KS9 LDA NEWKY STA KEYDT SET1 ACTKEY KS81: LDM CHATFL,#80H ;SET1 CHATFL.7 & SET TO 0 SET1 KEYONF BRA KS7 KS9: INC CHATFL BRA KS7 KS10: LDA CHATFL ;REPEAT KEY AND #0111_1111B BBS RPTEN,KS11 CMP #25 BCC KS9 SET1 RPTEN BRA KS81 KS11: CMP #3 BCC KS9 BBC ACTKEY,KS7 SET1 RPTKEY BRA KS81 ; Subject: Increase 1 minute * INC1MIN: LDX #LMINUTE CALL MIN1UP LDX #RMINUTE CALL MIN1UP RET MIN1UP: SETC LDA #0 ; LMINUTE <- LMINUTE + 1 ADC {X} DAA IF A ==#60H SETC LDA #0 ENDIF STA {X} BCC INC1 DEC X LDA #0 ADC {X} DAA IF A==#12H IF X==#LHOUR NOT1 LPM ELSE NOT1 RPM ENDIF ENDIF IF A==#13H LDA #1 ENDIF STA {X} INC1: RET

FEB. 2005 Ver 1.04 xxix ; Subject: WIND DISPLAY * WIND: LDA TEMPCNT CLRC STC 10DH.0 STC 10DH.1 STC 10DH.2 STC 10DH.3 CMP #0 BEQ LLL3 CMP #1 BEQ LLL2 CMP #2 BEQ LLL1 CMP #3 BEQ LLL0 CMP #4 BEQ LLL1 CMP #5 BEQ LLL2 CMP #6 BEQ LLL3 CMP #7 BEQ LLL4 LLL0: STC 10DH.1 LLL1: STC 10DH.2 LLL2: STC 10DH.3 LLL3: STC 10DH.0 LLL4: STC 111H.1 INC TEMPCNT IF [TEMPCNT]==#8 LDM TEMPCNT,#0 ENDIF RET NOT_USED: nop ;Discard Unexpected Interrupts reti END ;Notice Program End

Product Information

GMS87C7216LQ specifications and overview.

Summary

8-BIT SINGLE-CHIP MICROCONTROLLERS

Description

8-BIT SINGLE-CHIP MICROCONTROLLERS

Source title GMS87C7216LQ Datasheet(PDF) - List of Unclassifed Manufacturers

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